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Comprehensive Ivy Bridge/ Processor

Training

Let MindShare Bring Intel Ivy Bridge & Sandy Bridge Processors to Life For You

Ivy Bridge and Sandy Bridge processors are two recent additions to Intel’s (Intel 64 and IA32) CPU family. Building on features introduced in the previous generation Nehalem processors, the second-generation 32nm Sandy Bridge and third-generation 22nm Ivy Bridge employ a new and bring significant enhancements in areas including CPU graphics, integrated IO, and power/thermal management.

A primary focus of the course is on CPU features and internal core hardware: instruction pipeline, caches, registers, execution units, and local APICs. CPU logic is also covered: graphics, main memory DRAM controller, system bus interfaces (DMI/QPI), and integrated IO (PCIe, etc.). An overview of the chipset (PCH) and common single-CPU and multi-CPU Ivy Bridge and Sandy Bridge platform topologies is also provided.

The course also introduces CPU operational modes, the IA32/64 instruction set, performance monitoring, processor virtualization, etc.--mainly in the context of CPU hardware required to support them. Note that other MindShare courses offer comprehensive coverage of the software architecture, platform chipsets, QPI, PCI Express, DRAM, virtualization, etc.

You Will Learn: • Place of Ivy Bridge and Sandy Bridge CPUs within the larger Intel x86 CPU family • CPU and platform variants: mobile, desktop, workstation, server • Architecture of the processor and differences between Ivy Bridge/Sandy Bridge • Integrated graphics capabilities • Power management • Thermal management features • Interrupts • Error handling • Performance monitoring • External CPU interfaces • Processor virtualization support (VT-X)

Course Length: 4 Days

Course Outline:

• Part One: Intel IA32 CPU and Platform Background o Intel 64 and IA32 lineage and Ivy Bridge/Sandy Bridge CPUs o Intel platforms before Nehalem/Sandy Bridge/Ivy Bridge • Part Two: Ivy Bridge/Sandy Bridge CPU Internal Architecture o Cache Hierarchy: . Split L1 Code and L1 Data Caches . Unified L2 Cache . Unified L3 Cache . Coherence engine . Ring Interconnect o Instruction Pipeline . Prefetch . Branch Prediction . Instruction Decode . uOp Cache . Reorder Buffer (ROB) . Execution Units . Register Set . Implications of HyperThreading o Integrated Graphics 800-633-1440 1-800-633-1440 [email protected] www.mindshare.com

. Introduction • Overview of Graphics Architecture—Hardware & Software • 2D and 3D Geometric Shapes and Transformations • 3D Fragment Processing • Rasterization • Pixel Stream Processing . Modern GPU pipeline • General Computation & Rendering Units • Display Pipeline • Intel GPU Architecture • Other GPU Architectures • Part Three: o Ivy Bridge/Sandy Bridge Platform Examples . Single-CPU Core i7 desktop system . Single-CPU Core i5 system . Single-CPU E3 workstation/server system . Dual-CPU Xeon E5 workstation/server system • Part Four: Processor Operational Modes o Legacy Modes . Real Mode . Protected Mode . . System Management Mode (SMM) o IA32e Modes . 64-bit Mode . Compatibility Mode • Part Five: Address Generation o Real Mode Segmentation o Protected Mode Segmentation and Paging o Impact of IA32e 64-bit extensions • Part Six: Interrupt Handling o Background o CPU Local APICs and Chipset IOAPICs o Message Signaled Interrupt (MSI) Delivery o Interrupt servicing • Part Seven: CPU Management Topics o Power management o Thermal management o System Management Mode (SMM) o Error handling and Machine Check Architecture (MCA) o Performance Monitoring o Microcode Update • Part Eight: Overview of External CPU Interfaces o (DMI) o QuickPath Interconnect (QPI) o Integrated (IMC) and DRAM channels o Platform Environmental Control Interface (PECI) • Part Nine: Processor Virtualization (VT-x) support

Recommended Prerequisites: None

Course materials: 1) Course presentation PDF 2) MindShare’s “x86 Instruction Set Architecture” eBook by Tom Shanley