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Home , Exception handling

8.1 8.2 What are Exceptions?

• Exceptions are rare events triggered by the hardware and forcing the processor to execute a EE 457 Unit 8 handler – – Exceptions – “What Happens When Things Go Wrong” • Similar to conditional branches/ calls – Utilize the hardware already in place for branches – Flush pipeline – Fetch from entry point of software exceptions handler

8.3 8.4 Exception Processing Exception Examples 1

• Exception = Example Stage Action – Asynchronous (non-programmed) control transfer I/O Device WB Take ASAP – Synchronous system call/ • A peripheral device requires action from the CPU (Interrupt I/O Driven) • Must save PC of offending instruction, program state, and any information needed to return afterwards Calls (“Traps”) [e.g. File Open] ____ Precise • Trap instruction causes processor to enter kernel mode • Restore upon return

User Program System Exception Instruction Tracing and ID Precise Handler ------• When TRAP is all instructions cause exceptions ------• Particular instructions are flagged for exceptions ------() ------Arithmetic Exceptions EX Precise ------• Overflow or Divide-by-0 ------Return from exception 8.5 8.6 Exception Examples 2 System Calls/Traps

Example Stage Action • A controlled-method for user application calling OS Page Faults ______Precise • Virtual memory access fault (no Page Table entry resident in services memory) Misaligned ____ Abort • Switches processor to “kernel” mode where certain • Address is not multiple of operand size Process privileges are enabled that we would not want Memory Protection Violations ____ Abort • Address is out of bounds; RWX violation Process normal user apps to access Undefined Instructions ____ Precise • Decode unit does not recognize opcode or other fields (Why not Instruction Tracing and • Could be useful to extend the instruction set abort) x86 System Call (old DOS OS call) Single-stepping & Breakpoint in x86 IN AH, 01H Hardware failure WB Take ASAP INT 20H // getchar() • Unrecoverable hardware error is detected; is compromised PSW TF Processor Trap Flag Power Failure WB Take ASAP Status Word • Power has fallen below a threshold; Trap to software to save as much state as possible

8.7 8.8 Exception Processing MIPS Coprocessor 0 Registers

• Save necessary state to be able to restart the process • Status Register – Enables and disables the handling of exceptions/ – Save ____of offending instruction – Controls user/kernel processor modes • Call an appropriate ______to deal with • Kernel mode allows access to certain regions of the address space and execution of certain instructions the error / interrupt / syscall • Cause Register: Indicates which exception/interrupt occurred – Handler identifies cause of exception and handles it • ______Register – May need to save more state – Indicates the address of the instruction causing the exception – This is also the instruction we should return to after handling the exception • Restore state and return to offending application (or • Coprocessor registers can be accessed via the ‘mtc0’ and ‘mfc0’ kill it if recovery is impossible) instructions – mfc0 $gpr,$c0_reg # R[gpr] = C0[c0_reg] – mtc0 $gpr,$c0_reg # C0[c0_reg] = R[gpr] 8.9 8.10 Status Register Cause Register

Code Cause • Register 12 in coprocessor 0 • Register 13 in coprocessor 0 0 Interrupt (HW) • Bit definitions • Bit definitions 4, 5 Load (4), Store (5) Address Error – IM[7:0] – Interrupt Mask – BD – Branch Delay 6, 7 Instruc. (6), Data (7) Bus • 1 = Ignore interrupt / 0 = Allow interrupt • The offending instruction was in the branch Error delay slot – UM – User Mode 8 Syscall • 1 = User mode / 0 = Kernel mode • EPC points at the branch but it was EPC+4 that caused the exception 9 Breakpoint ERL/EXL = Exception/Error Level – – PI[7:0] – Pending Interrupt 10 Reserved Instruc. • 1 = Already handling exception or error / 0 = Normal exec. • 1 = Interrupt Requested / 0 = No interrupt 11 CoProc. Unusable • If either bit is ‘1’ processor is also said to be in kernel mode requested 12 Arith. Overflow – IE = Interrupt Enable – Exception Code – Indicates cause of 13 Trap • 1 = Allow unmasked interrupts / 0 = Ignore all interrupts exception (see table) 15 Floating Point

31 15 8 4 2 1 0 31 15 8 7 6 2 1 0 Status Cause Exception Code

0 0 0 0 0 IE 0 0 0 BD

0000 0000 0000 0000 000 0000 0000 0000 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 UM IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 EXL Register ERL Register

8.11 8.12 EPC Register Problem of Calling a Handler

• Exception PC holds the address of the offending • We can’t use explicit ‘jal’ instructions to call instruction exception handlers since we don’t – Can be used along with ‘Cause’ register to find and correct ______some error conditions

• ______instruction used to return from exception .text Many instructions could cause MAIN: ---- an error condition. Or a handler and back to execution point in original code hardware like a keyboard ---- (unless handling the error means having the OS kill press could occur at any point in ---- the code. the process) ------– ______Operation: PC = EPC jr $ra

31 0 EPC = Exception PC Address of instruction that generated the exception 8.13 8.14 Solution for Calling a Handler Handler Calling Methods

• Since we don’t know when an exception will occur there must be a preset location where an exception handler should be Kernel 0xffffffff Kernel 0xffffffff Kernel 0xffffffff defined or some way of telling the processor in advance where Space Space Space our exception handlers will be located INT 2 Hand. x3 INT n Hand. • Method 1: ______for master handler 0x80000??? – Early MIPS architecture defines that the exception handler should be INT 2 Hand. 0x80000300 Handler 1 x1 INT 1 Hand. 0x80000200 INT 1 Hand. x2 located at 0x8000_0180. Code there should then examine CAUSE register Exception Exception 0x80000180 and then call appropriate handler routine Handler 0x80000180 Handler addr x3 addr x2 • Method 2: ______(usually for interrupts) 0x80000000 0x80000000 addr x1 0x80000000 – Each at a different address based on interrupt number (a.k.a. vector) (INT1 @ 0x80000200, INT2 @ 0x80000300) User User User Space Space Space

• Method 3: ______0x00000000 0x00000000 0x00000000 – Table in memory holding start address of exception handlers (i.e. Method 1 Method 2 Method 3 overflow exception handler pointer at 0x0004, FP exception handler pointer at 0x0008, etc.)

8.15 8.16 Precise Exceptions Why are Exceptions So Important?

• Two conditions: • Exceptions are part of the ISA (Instruction Set Architecture) – Synchronized with an instruction specification • A particular instruction caused the exception • Any implementation of an ISA must comply with its • Not an interrupt or some of failure “Exception model” – Must resume execution after handler Precise constrains what the architecture • Restart the instruction causing the exception after exception handler • returns can do • Not an exception that will cause the process to abort – Exceptions are rare yet we must functionally support them • Not difficult in a processor executing one instruction at a time – If we did not have to comply to the exception model architects would have a lot more freedom in their design • Very difficult in architectures in which multiple instruction execute concurrently (i.e. our 5-stage pipeline) When designing micro-architectures for the common case, exceptions must always be in the back of your mind! 8.17 8.18 Exceptions in the 5-Stage Pipeline Exception in EX stage FLUSH • Save EPC=PC+4 of offending instruction • Record Cause EX.RegWrite • Add 3 rd input of 0x8000_0180 to PCSrc Mux (start address of exception handler) Stall EX.RegDst PCWrite HDU

• To support precise exceptions in the 5-stage pipeline we WB WB must… IRWrite IF.Flush Mem Mem MemToReg WB – Identify the pipeline stage and instruction causing the exceptions Control Branch + Ex 4 +

• Any stage can trigger an exception (except for the WB stage) rs Sh.

Read & MemRead

Left 2 MemWrite Reg. 1 # EPC Identify the cause of the exception 5 Read 0 – data 1 Cause rt Read 1 2 – Save the process state at the faulting instruction 5 Reg. 2 # 3 0 0 . Write ALUSelA • Including registers, PC, and cause Read ALU 1 Reg. # = PC data 2 2 0 Res. Usually done by software exception handler I-Cache • Write 1 0 Data 2 8000_0180 1 – Complete the execution of instructions preceding the faulting Register Instruction 3 Register File 1 Pipeline Stage Register Stage Pipeline Pipeline Stage Register Stage Pipeline

instruction -Cache

Sign ALUSelB ALUSrc Extend Register Stage Pipeline RegDst – Flush instruction following the faulting instruction plus the faulting Reset 16 rs 32 instruction Forwarding 0 rt Unit 1 – Transfer control to exception handler rd

Use many of the same mechanisms as conditional branches.

8.19 8.20 Exception Handling Complexities More Complex Complexities?

• When the arithmetic exception is triggered in EX, we must flush __, • What happens if multiple exceptions occur in the same cycle from ___and ___ and start fetching from 0x8000_0180 different instructions in different stages • Note that the handler’s software must have access to CAUSE and EPC – Should take the ______exception in ______registers to figure out what to do – “Program/process order” = Order if only 1 instruction were executed at a time (= Fetch order) – Thus oldest instruction is the one ______into the pipeline • Realize though exceptions may occur in all but the WB stage – There is no point in dealing with all exceptions, just the oldest one – 4 possible values of ______– Let software deal with the oldest and then restart…if later instruction were going to generate an exception, then they will again upon restart and we can handle it then – Software needs to know which value is the actual cause and EPC – Depending on the stage where the exception occurs, we have to flush different stages Cycle n We can start handling illegal instruction exception. What Muxes could happen on cycle n+1?

EPC EPC EPC EPC EPC EPC EPC EPC EPC EPC Cause Cause Cause Cause Cause Cause Cause Cause Cause Cause

IM Reg ALU DM Reg IM Reg ALU DM Reg

LW But it gets worse!!! I-Fetch Illegal SW address TLB miss TLB miss / Instruction computation Page hit (no exception) 8.21 8.22 More Complex Complexities? Simplify the Process

• Remember we must complete instruction preceding the faulting • It is not practical to take an exception in the cycle when it happens instruction – Multiple exceptions in the same cycle – It is complex to take exception in various pipeline stages since we have to take them in program • Remember we are supposed to handle instruction in program order (not order and not temporal order temporal order) • Instead, we will just tag an instruction in the pipeline if it causes and exception (recording the cause and EPC) – Turn the offending instruction into a NOOP (bubble) – Let the instructions continue to flow down the pipeline and handle the offending instruction’s execution in the WB stage • The cause and status info is carried down the pipe via stage registers – Exception remains ______until it reaches the WB stage – Exceptions are then processed into the WB stage Cycle n+1 Muxes Actual EPC & Cause Register

EPC EPC EPC EPC EPC Cause Cause Cause Cause Cause IM Reg ALU DM Reg IM Reg ALU DM Reg I-Fetch Illegal LW TLB miss / Instruction Page Fault

8.23 8.24 Handling in WB Stage Simplified Processing

• Handling in WB stage helps deal with temporal vs. program • Precise exceptions are now taken in WB along with other HW interrupts order issues • Faulting instructions “carry” their cause and EPC values through the pipeline stage registers CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 • Only one set of EPC and CAUSE registers in the WB stage • When an instruction flagged as faulting reaches the WB stage 40: LW $1,0($8) IM Reg ALU DM Reg – Flush IF, ID, EX, MEM • Make sure that if a SW is in MEM stage that it is not allowed to write Load the handler address in the PC 44: AND $12,$2,$5 IM Reg ALU DM Reg – – Make sure EPC & Cause are software-readable (movable to GPR’s)

48: OR $13,$6,$2 IM Reg ALU DM Reg

52: ADD $14,$2,$2 IM Reg ALU DM Reg This is a general approach to dealing with exceptions in the processor: … Wait until the faulting instruction exits the machine to trigger the handling procedure