DOCSLIB.ORG

SIMULTANEOUS MULTITHREADING: a Platform for Next-Generation Processors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
SIMULTANEOUS MULTITHREADING: a Platform for Next-Generation Processors SIMULTANEOUS MULTITHREADING: A Platform for Next-Generation Processors Susan J. Eggers s the processor community prepares exploits both types of parallelism, SMT University of Washington for a billion transistors on a chip, processors use resources more efficiently, and Aresearchers continue to debate the both instruction throughput and speedups are Joel S. Emer most effective way to use them. One greater. Digital Equipment Corp. approach is to add more memory (either Simultaneous multithreading combines cache or primary memory) to the chip, but hardware features of wide-issue superscalars Henry M. Levy the performance gain from memory alone is and multithreaded processors. From super- University of Washington limited. Another approach is to increase the scalars, it inherits the ability to issue multi- level of systems integration, bringing sup- ple instructions each cycle; and like Jack L. Lo port functions like graphics accelerators and multithreaded processors it contains hard- University of Washington I/O controllers on chip. Although integra- ware state for several programs (or threads). tion lowers system costs and communica- The result is a processor that can issue mul- Rebecca L. Stamm tion latency, the overall performance gain to tiple instructions from multiple threads each Digital Equipment Corp. applications is again marginal. cycle, achieving better performance for a We believe the only way to significantly variety of workloads. For a mix of indepen- Dean M. Tullsen improve performance is to enhance the dent programs (multiprogramming), the University of California, processor’s computational capabilities. In overall throughput of the machine is San Diego general, this means increasing parallelism— improved. Similarly, programs that are par- in all its available forms. At present only cer- allelizable, either by a compiler or a pro- tain forms of parallelism are being exploited. grammer, reap the same throughput Current superscalars, for example, can exe- benefits, resulting in program speedup. cute four or more instructions per cycle; in Finally, a single-threaded program that must practice, however, they achieve only one or execute alone will have all machine two, because current applications have low resources available to it and will maintain instruction-level parallelism. Placing multi- roughly the same level of performance as ple superscalar processors on a chip is also when executing on a single-threaded, wide- not an effective solution, because, in addi- issue processor. Simultaneous tion to the low instruction-level parallelism, Equal in importance to its performance ben- performance suffers when there is little efits is the simplicity of SMT’s design. multithreading exploits thread-level parallelism. A better solution is Simultaneous multithreading adds minimal to design a processor that can exploit all hardware complexity to, and, in fact, is a both instruction-level types of parallelism well. straightforward extension of, conventional Simultaneous multithreading is a processor dynamically scheduled superscalars. Hardware and thread-level design that meets this goal, because it con- designers can focus on building a fast, single- sumes both thread-level and instruction-level threaded superscalar, and add SMT’s multi- parallelism by issuing parallelism. In SMT processors, thread-level thread capability on top. parallelism can come from either multi- Given the enormous transistor budget in instructions from threaded, parallel programs or individual, the next computer era, we believe simulta- independent programs in a multiprogram- neous multithreading provides an efficient different threads in the ming workload. Instruction-level parallelism base technology that can be used in many comes from each single program or thread. ways to extract improved performance. For same cycle. Because it successfully (and simultaneously) example, on a one billion transistor chip, 20 12 IEEE Micro 0272-1732/97/$10.00 © 1997 IEEE Authorized licensed use limited to: Stanford University. Downloaded on March 11,2021 at 00:29:23 UTC from IEEE Xplore. Restrictions apply. to 40 SMTs could be used side-by-side to that of achieve per- formance comparable to a much larger number of conven- tional superscalars. With IRAM technology, SMT’s high execution rate, which currently doubles memory bandwidth Thread 1 requirements, can fully exploit the increased bandwidth Thread 2 capability. In both billion-transistor scenarios, the SMT Thread 3 processor we describe here could serve as the processor Thread 4 building block. cycles) (processor Time Thread 5 How SMT works The difference between superscalar, multithreading, and (a) (b) (c) simultaneous multithreading is pictured in Figure 1, which shows sample execution sequences for the three architec- tures. Each row represents the issue slots for a single exe- Figure 1. How architectures partition issue slots (function- cution cycle: a filled box indicates that the processor found al units): a superscalar (a), a fine-grained multithreaded an instruction to execute in that issue slot on that cycle; an superscalar (b), and a simultaneous multithreaded proces- empty box denotes an unused slot. We characterize the sor (c). The rows of squares represent issue slots. The pro- unused slots as horizontal or vertical waste. Horizontal waste cessor either finds an instruction to execute (filled box) or occurs when some, but not all, of the issue slots in a cycle the slot goes unused (empty box). can be used. It typically occurs because of poor instruction- level parallelism. Vertical waste occurs when a cycle goes completely unused. This can be caused by a long latency the processor fetches eight instructions from the instruction instruction (such as a memory access) that inhibits further cache. After instruction decoding, the register-renaming logic instruction issue. maps the architectural registers to the hardware renaming Figure 1a shows a sequence from a conventional super- registers to remove false dependencies. Instructions are then scalar. As in all superscalars, it is executing a single program, fed to either the integer or floating-point dispatch queues. or thread, from which it attempts to find multiple instruc- When their operands become available, instructions are tions to issue each cycle. When it cannot, the issue slots go issued from these queues to their corresponding functional unused, and it incurs both horizontal and vertical waste. units. To support out-of-order execution, the processor tracks Figure 1b shows a sequence from a multithreaded archi- instruction and operand dependencies so that it can deter- tecture, such as the Tera.1 Multithreaded processors contain mine which instructions it can issue and which must wait for hardware state (a program counter and registers) for sever- previously issued instructions to finish. After instructions al threads. On any given cycle a processor executes instruc- complete execution, the processor retires them in order and tions from one of the threads. On the next cycle, it switches frees hardware registers that are no longer needed. to a different thread context and executes instructions from Our SMT model, which can simultaneously execute the new thread. As the figure shows, the primary advantage threads from up to eight hardware contexts, is a straightfor- of multithreaded processors is that they better tolerate long- ward extension of this conventional superscalar. We repli- latency operations, effectively eliminating vertical waste. cated some superscalar resources to support simultaneous However, they cannot remove horizontal waste. Conse- multithreading: state for the hardware contexts (registers and quently, as instruction issue width continues to increase, mul- program counters) and per-thread mechanisms for pipeline tithreaded architectures will ultimately suffer the same fate flushing, instruction retirement, trapping, precise interrupts, as superscalars: they will be limited by the instruction-level and subroutine return. We also added per-thread (address- parallelism in a single thread. space) identifiers to the branch target buffer and translation Figure 1c shows how each cycle an SMT processor selects look-aside buffer. Only two components, the instruction fetch instructions for execution from all threads. It exploits instruc- unit and the processor pipeline, were redesigned to benefit tion-level parallelism by selecting instructions from any from SMT’s multithread instruction issue. thread that can (potentially) issue. The processor then Simultaneous multithreading needs no special hardware to dynamically schedules machine resources among the instruc- schedule instructions from the different threads onto the tions, providing the greatest chance for the highest hardware functional units. Dynamic scheduling hardware in current utilization. If one thread has high instruction-level paral- out-of-order superscalars is already functionally capable of lelism, that parallelism can be satisfied; if multiple threads simultaneous multithreaded scheduling. Register renaming each have low instruction-level parallelism, they can be exe- eliminates register name conflicts both within and between cuted together to compensate. In this way, SMT can recov- threads by mapping thread-specific architectural registers er issue slots lost to both horizontal and vertical waste. onto the hardware registers; the processor then issues instruc- tions (after their operands have been calculated or loaded SMT model from memory) without regard to thread. We derived
Load more

Recommended publications
  • GPU Implementation Over IPTV Software Defined Networking
    Esmeralda Hysenbelliu. Int. Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 7, Issue 8, ( Part -1) August 2017, pp.41-45 RESEARCH ARTICLE OPEN ACCESS GPU Implementation over IPTV Software Defined Networking Esmeralda Hysenbelliu* Information Technology Faculty, Polytechnic University of Tirana, Sheshi “Nënë Tereza”, Nr.4, Tirana, Albania Corresponding author: Esmeralda Hysenbelliu ABSTRACT One of the most important issue in IPTV Software defined Network is Bandwidth Issue and Quality of Service at the client side. Decidedly, it is required high level quality of images in low bandwidth and for this reason it is needed different transcoding standards (Compression of image as much as it is possible without destroying the quality of it) as H.264, H265, VP8 and VP9. During a test performed in SMC IPTV SDN Cloud Network, it was observed that with a server HP ProLiant DL380 g6 with two physical processors there was not possible to transcode in format H.264 more than 30 channels simultaneously because CPU’s achieved 100%. This is the reason why it was immediately needed to use Graphic Processing Units called GPU’s which offer high level images processing. After GPU superscalar processor was integrated and done functional via module NVENC of FFEMPEG Program, number of channels transcoded simultaneously was tremendous increased (more than 100 channels). The aim of this paper is to real implement GPU superscalar processors in IPTV Cloud Networks by achieving improvement of performance to more than 60%. Keywords - GPU superscalar processor, Performance Improvement, NVENC, CUDA --------------------------------------------------------------------------------------------------------------------------------------- Date of Submission: 01 -05-2017 Date of acceptance: 19-08-2017 --------------------------------------------------------------------------------------------------------------------------------------- I.
    [Show full text]
  • Computer Hardware Architecture Lecture 4
    Computer Hardware Architecture Lecture 4 Manfred Liebmann Technische Universit¨atM¨unchen Chair of Optimal Control Center for Mathematical Sciences, M17 [email protected] November 10, 2015 Manfred Liebmann November 10, 2015 Reading List • Pacheco - An Introduction to Parallel Programming (Chapter 1 - 2) { Introduction to computer hardware architecture from the parallel programming angle • Hennessy-Patterson - Computer Architecture - A Quantitative Approach { Reference book for computer hardware architecture All books are available on the Moodle platform! Computer Hardware Architecture 1 Manfred Liebmann November 10, 2015 UMA Architecture Figure 1: A uniform memory access (UMA) multicore system Access times to main memory is the same for all cores in the system! Computer Hardware Architecture 2 Manfred Liebmann November 10, 2015 NUMA Architecture Figure 2: A nonuniform memory access (UMA) multicore system Access times to main memory differs form core to core depending on the proximity of the main memory. This architecture is often used in dual and quad socket servers, due to improved memory bandwidth. Computer Hardware Architecture 3 Manfred Liebmann November 10, 2015 Cache Coherence Figure 3: A shared memory system with two cores and two caches What happens if the same data element z1 is manipulated in two different caches? The hardware enforces cache coherence, i.e. consistency between the caches. Expensive! Computer Hardware Architecture 4 Manfred Liebmann November 10, 2015 False Sharing The cache coherence protocol works on the granularity of a cache line. If two threads manipulate different element within a single cache line, the cache coherency protocol is activated to ensure consistency, even if every thread is only manipulating its own data.
    [Show full text]
  • Superscalar Fall 2020
    CS232 Superscalar Fall 2020 Superscalar What is superscalar - A superscalar processor has more than one set of functional units and executes multiple independent instructions during a clock cycle by simultaneously dispatching multiple instructions to different functional units in the processor. - You can think of a superscalar processor as there are more than one washer, dryer, and person who can fold. So, it allows more throughput. - The order of instruction execution is usually assisted by the compiler. The hardware and the compiler assure that parallel execution does not violate the intent of the program. - Example: • Ordinary pipeline: four stages (Fetch, Decode, Execute, Write back), one clock cycle per stage. Executing 6 instructions take 9 clock cycles. I0: F D E W I1: F D E W I2: F D E W I3: F D E W I4: F D E W I5: F D E W cc: 1 2 3 4 5 6 7 8 9 • 2-degree superscalar: attempts to process 2 instructions simultaneously. Executing 6 instructions take 6 clock cycles. I0: F D E W I1: F D E W I2: F D E W I3: F D E W I4: F D E W I5: F D E W cc: 1 2 3 4 5 6 Limitations of Superscalar - The above example assumes that the instructions are independent of each other. So, it’s easily to push them into the pipeline and superscalar. However, instructions are usually relevant to each other. Just like the hazards in pipeline, superscalar has limitations too. - There are several fundamental limitations the system must cope, which are true data dependency, procedural dependency, resource conflict, output dependency, and anti- dependency.
    [Show full text]
  • The Multiscalar Architecture
    THE MULTISCALAR ARCHITECTURE by MANOJ FRANKLIN A thesis submitted in partial ful®llment of the requirements for the degree of DOCTOR OF PHILOSOPHY (Computer Sciences) at the UNIVERSITY OF WISCONSIN Ð MADISON 1993 THE MULTISCALAR ARCHITECTURE Manoj Franklin Under the supervision of Associate Professor Gurindar S. Sohi at the University of Wisconsin-Madison ABSTRACT The centerpiece of this thesis is a new processing paradigm for exploiting instruction level parallelism. This paradigm, called the multiscalar paradigm, splits the program into many smaller tasks, and exploits ®ne-grain parallelism by executing multiple, possibly (control and/or data) depen- dent tasks in parallel using multiple processing elements. Splitting the instruction stream at statically determined boundaries allows the compiler to pass substantial information about the tasks to the hardware. The processing paradigm can be viewed as extensions of the superscalar and multiprocess- ing paradigms, and shares a number of properties of the sequential processing model and the data¯ow processing model. The multiscalar paradigm is easily realizable, and we describe an implementation of the multis- calar paradigm, called the multiscalar processor. The central idea here is to connect multiple sequen- tial processors, in a decoupled and decentralized manner, to achieve overall multiple issue. The mul- tiscalar processor supports speculative execution, allows arbitrary dynamic code motion (facilitated by an ef®cient hardware memory disambiguation mechanism), exploits communication localities, and does all of these with hardware that is fairly straightforward to build. Other desirable aspects of the implementation include decentralization of the critical resources, absence of wide associative searches, and absence of wide interconnection/data paths.
    [Show full text]
  • Trends in Processor Architecture
    A. González Trends in Processor Architecture Trends in Processor Architecture Antonio González Universitat Politècnica de Catalunya, Barcelona, Spain 1. Past Trends Processors have undergone a tremendous evolution throughout their history. A key milestone in this evolution was the introduction of the microprocessor, term that refers to a processor that is implemented in a single chip. The first microprocessor was introduced by Intel under the name of Intel 4004 in 1971. It contained about 2,300 transistors, was clocked at 740 KHz and delivered 92,000 instructions per second while dissipating around 0.5 watts. Since then, practically every year we have witnessed the launch of a new microprocessor, delivering significant performance improvements over previous ones. Some studies have estimated this growth to be exponential, in the order of about 50% per year, which results in a cumulative growth of over three orders of magnitude in a time span of two decades [12]. These improvements have been fueled by advances in the manufacturing process and innovations in processor architecture. According to several studies [4][6], both aspects contributed in a similar amount to the global gains. The manufacturing process technology has tried to follow the scaling recipe laid down by Robert N. Dennard in the early 1970s [7]. The basics of this technology scaling consists of reducing transistor dimensions by a factor of 30% every generation (typically 2 years) while keeping electric fields constant. The 30% scaling in the dimensions results in doubling the transistor density (doubling transistor density every two years was predicted in 1975 by Gordon Moore and is normally referred to as Moore’s Law [21][22]).
    [Show full text]
  • Intro Evolution of Superscalar Processor
    Superscalar Processors Superscalar Processors vs. VLIW • 7.1 Introduction • 7.2 Parallel decoding • 7.3 Superscalar instruction issue • 7.4 Shelving • 7.5 Register renaming • 7.6 Parallel execution • 7.7 Preserving the sequential consistency of instruction execution • 7.8 Preserving the sequential consistency of exception processing • 7.9 Implementation of superscalar CISC processors using a superscalar RISC core • 7.10 Case studies of superscalar processors TECH Computer Science CH01 Superscalar Processor: Intro Emergence and spread of superscalar processors • Parallel Issue • Parallel Execution • {Hardware} Dynamic Instruction Scheduling • Currently the predominant class of processors 4Pentium 4PowerPC 4UltraSparc 4AMD K5- 4HP PA7100- 4DEC α Evolution of superscalar processor Specific tasks of superscalar processing Parallel decoding {and Dependencies check} Decoding and Pre-decoding • What need to be done • Superscalar processors tend to use 2 and sometimes even 3 or more pipeline cycles for decoding and issuing instructions • >> Pre-decoding: 4shifts a part of the decode task up into loading phase 4resulting of pre-decoding f the instruction class f the type of resources required for the execution f in some processor (e.g. UltraSparc), branch target addresses calculation as well 4the results are stored by attaching 4-7 bits • + shortens the overall cycle time or reduces the number of cycles needed The principle of perdecoding Number of perdecode bits used Specific tasks of superscalar processing: Issue 7.3 Superscalar instruction issue • How and when to send the instruction(s) to EU(s) Instruction issue policies of superscalar processors: Issue policies ---Performance, tread-----Æ Issue rate {How many instructions/cycle} Issue policies: Handing Issue Blockages • CISC about 2 • RISC: Issue stopped by True dependency Issue order of instructions • True dependency Æ (Blocked: need to wait) Aligned vs.
    [Show full text]
  • Parallel Architectures MICHAEL J
    Parallel Architectures MICHAEL J. FLYNN AND KEVIN W. RUDD Stanford University ^[email protected]&; ^[email protected]& PARALLEL ARCHITECTURES currently performing different phases of processing an instruction. This does not Parallel or concurrent operation has achieve concurrency of execution (with many different forms within a computer system. Using a model based on the multiple actions being taken on objects) different streams used in the computa- but does achieve a concurrency of pro- tion process, we represent some of the cessing—an improvement in efficiency different kinds of parallelism available. upon which almost all processors de- A stream is a sequence of objects such pend today. as data, or of actions such as instruc- Techniques that exploit concurrency tions. Each stream is independent of all of execution, often called instruction- other streams, and each element of a level parallelism (ILP), are also com- stream can consist of one or more ob- mon. Two architectures that exploit ILP jects or actions. We thus have four com- are superscalar and VLIW (very long binations that describe most familiar parallel architectures: instruction word). These techniques schedule different operations to execute (1) SISD: single instruction, single data concurrently based on analyzing the de- stream. This is the traditional uni- pendencies between the operations processor [Figure 1(a)]. within the instruction stream—dynami- (2) SIMD: single instruction, multiple cally at run time in a superscalar pro- data stream. This includes vector cessor and statically at compile time in processors as well as massively par- a VLIW processor. Both ILP approaches allel processors [Figure 1(b)].
    [Show full text]
  • Modern Processor Design: Fundamentals of Superscalar
    Fundamentals of Superscalar Processors John Paul Shen Intel Corporation Mikko H. Lipasti University of Wisconsin WAVELAND PRESS, INC. Long Grove, Illinois To Our parents: Paul and Sue Shen Tarja and Simo Lipasti Our spouses: Amy C. Shen Erica Ann Lipasti Our children: Priscilla S. Shen, Rachael S. Shen, and Valentia C. Shen Emma Kristiina Lipasti and Elias Joel Lipasti For information about this book, contact: Waveland Press, Inc. 4180 IL Route 83, Suite 101 Long Grove, IL 60047-9580 (847) 634-0081 info @ waveland.com www.waveland.com Copyright © 2005 by John Paul Shen and Mikko H. Lipasti 2013 reissued by Waveland Press, Inc. 10-digit ISBN 1-4786-0783-1 13-digit ISBN 978-1-4786-0783-0 All rights reserved. No part of this book may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without permission in writing from the publisher. Printed in the United States of America 7 6 5 4 3 2 1 Table of Contents PrefaceAbout the Authors x ix 1 Processor Design 1 1.1 The Evolution of Microprocessors 2 1.21.2.1 Instruction Digital Set Systems Processor Design Design 44 1.2.2 Architecture,Realization Implementation, and 5 1.2.3 Instruction Set Architecture 6 1.2.4 Dynamic-Static Interface 8 1.3 Principles of Processor Performance 10 1.3.1 Processor Performance Equation 10 1.3.2 Processor Performance Optimizations 11 1.3.3 Performance Evaluation Method 13 1.4 Instruction-Level Parallel Processing 16 1.4.1 From Scalar to Superscalar 16 1.4.2 Limits of Instruction-Level Parallelism 24 1.51.4.3 Machines Summary for Instruction-Level
    [Show full text]
  • Multithreading
    CS 152 Computer Architecture and Engineering CS252 Graduate Computer Architecture Lecture 14 – Multithreading Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs152 Last Time Lecture 13: VLIW § In a classic VLIW, compiler is responsible for avoiding all hazards -> simple hardware, complex compiler. § Later VLIWs added more dynamic hardware interlocks, which reduce relative hardware benefits § Use loop unrolling and software pipelining for loops, trace scheduling for more irregular code § Static scheduling difficult in presence of unpredictable branches and variable latency memory § VLIW has failed in general-purpose computing, but still used in deeply embedded processors and DSPs 2 Thread-Level Parallelism (TLP) § Difficult to continue to extract instruction-level parallelism (ILP) from a single sequential thread of control § Many workloads can make use of thread-level parallelism: – TLP from multiprogramming (run independent sequential jobs) – TLP from multithreaded applications (run one job faster using parallel threads) § Multithreading uses TLP to improve utilization of a single processor 3 Multithreading How can we guarantee no dependencies between instructions in a pipeline? One way is to interleave execution of instructions from different program threads on same pipeline Interleave 4 threads, T1-T4, on non-bypassed 5-stage pipe t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 T1:LD x1,0(x2) F D X M W Prior instruction in a T2:ADD x7,x1,x4
    [Show full text]
  • A VHDL Model of a Superscalar Implementation of the DLX Instruction Set Architcture
    Rochester Institute of Technology RIT Scholar Works Theses 10-1-1996 A VHDL model of a superscalar implementation of the DLX instruction set architcture Paul Ferno Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Ferno, Paul, "A VHDL model of a superscalar implementation of the DLX instruction set architcture" (1996). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. A VHDL MODEL OF A SUPERSCALAR IMPLEMENTATION OF THE DLX INSTRUCTION SET ARCHITECTURE by Paul A. Femo A thesis submitted in partial fulfillment ofthe requirements for the degree of Masters ofScience in Computer Engineering Department ofComputer Engineering College ofEngineering Rochester Institute ofTechnology Rochester, New York October, 1996 Approvedby _ Dr. Kevin Shank, Assistant Professor Dr. Tony Chang, Professor Dr. Roy Czemikowski, Dept. Head and Professor THESIS RELEASE PERMISSION FORM ROCHESTER INSTITUTE OF TECHNOLOGY COLLEGE OF ENGINEERING Title: A VHDL Model ofa Superscalar Implementation ofthe DLX Instruction Set Architecture I, Paul A. Femo, hereby grant permission to the Wallace Memorial Library to reproduce my thesis in whole or part. Signature: _ Date: I(t-?£ ii Abstract The complexity of today's microprocessors demands that designers have an extensive knowledge of superscalar design techniques; this knowledge is difficult to acquire outside of a professional design team. Presently, there are a limited number of adequate resources available for the student, both in textual and model form.
    [Show full text]
  • Superscalar Processors and Parallel Computer Systems Objective
    Chapter 06: Instruction Pipelining and Parallel Processing Lesson 09: Superscalar Processors and Parallel Computer Systems Objective • To understand parallel pipelines and multiple execution units • Instruction level parallelism in superscalar processors Schaum’s Outline of Theory and Problems of Computer Architecture 2 Copyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 Multiple execution Units in Superscalar Processor Schaum’s Outline of Theory and Problems of Computer Architecture 3 Copyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 Superscalar Processor • Multiple execution units to execute instructions • Each execution unit reads its operands from and writes its results to a single, centralized register file Schaum’s Outline of Theory and Problems of Computer Architecture 4 Copyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 Multiple execution Units - Superscalar Processor • When an operation writes its result back to the register file, that result becomes visible to all of the execution units on the next cycle, allowing operations to execute on different units from the operations that generate their inputs Schaum’s Outline of Theory and Problems of Computer Architecture 5 Copyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 Instruction Issue Logic and Four execution units in a superscalar Schaum’s Outline of Theory and Problems of Computer Architecture 6 Copyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 Instruction Level Parallelism (ILP) in Superscalar processors • Have complex bypassing hardware that forwards the results of each instruction to all of the execution units to reduce the delay between dependent instructions • The instructions that make up a program are handled in superscalar processors by the instruction issue logic, which issues instructions to the units in parallel Schaum’s Outline of Theory and Problems of Computer Architecture 7 Copyright © The McGraw-Hill Companies Inc.
    [Show full text]
  • Memory Data Flow, VLIW and EPIC Processors
    Advanced Computer Architectures 05 Superscalar techniques - Memory data flow, VLIW and EPIC processors Czech Technical University in Prague, Faculty of Electrical Engineering Slides authors: Michal Štepanovský, update Pavel Píša B4M35PAP Advanced Computer Architectures 1 Superscalar Techniques… • The goal is to achieve a maximum throughput of instruction processing • Instruction processing can be analyzed as instructions flow or data flow, more precisely: • register data flow – data flow between processor registers • instruction flow through the pipeline Today’s lecture • memory data flow – to/from memory topic • It roughly matches to: • Arithmetic-logic (ALU) and other computational instructions (FP, bit- field, vector) processing • Branch instruction processing • Load/store instruction processing • maximizing the throughput of these three flows (or complete flow) correspond to the minimizing penalties and latencies of above three instructions types B4M35PAP Advanced Computer Architectures 2 Superscalar pipeline – see previous lesson Fetch Instruction / decode buffer Decode Dispatch buffer Dispatch Reservation stations Issue Execute Finish Reorder / Completion buffer Complete Store buffer Retire B4M35PAP Advanced Computer Architectures 3 What you know already from other subjects ... • Load / Store instructions are responsible for moving data between the memory and the processor's own registers • The processor has a very limited number of registers • The compiler generates a so-called spill code that temporarily saves data to memory/stack to make registers available - just by using the load/store instructions Significant latency of load/store instructions caused by: • Address generation – effective address computation • Address translation (see virtual memory) – TLB hit vs. TLB miss (is the page in memory × page fault, is the address in TLB × page-table walking) • Actual memory access – see next slide B4M35PAP Advanced Computer Architectures 4 Memory access • Load instruction: • Store data read from memory to rename register or reorder buffer.
    [Show full text]