Rambleed: Reading Bits in Memory Without Accessing Them
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Reading Bits in Memory Without Accessing Them
RAMBleed: Reading Bits in Memory Without Accessing Them Andrew Kwong Daniel Genkin Daniel Gruss Yuval Yarom University of Michigan University of Michigan Graz University of Technology University of Adelaide and Data61 [email protected] [email protected] [email protected] [email protected] Abstract—The Rowhammer bug is a reliability issue in DRAM directly access the changed memory location, the change is cells that can enable an unprivileged adversary to flip the values not visible to the processor or the operating system, and is of bits in neighboring rows on the memory module. Previous not subject to any permission checks. Thus far, this ability to work has exploited this for various types of fault attacks across security boundaries, where the attacker flips inaccessible bits, reliably flip bits across security boundaries has been exploited often resulting in privilege escalation. It is widely assumed for sandbox escapes [21, 57], privilege escalation attacks on however, that bit flips within the adversary’s own private memory operating systems and hypervisors [21, 23, 53, 57, 63, 66], have no security implications, as the attacker can already modify denial-of-service attacks [23, 30], and even for fault injection its private memory via regular write operations. in cryptographic protocols [6]. We demonstrate that this assumption is incorrect by employing Rowhammer as a read side channel. More specifically, we show A common theme for all past Rowhammer attacks is how an unprivileged attacker can exploit the data dependence that they break memory integrity. Namely, the attacker uses between Rowhammer-induced bit flips and the bits in nearby Rowhammer to obtain a (limited) write primitive into oth- rows to deduce these bits, including values belonging to other erwise inaccessible memory, and subsequently modifies the processes. -
Opportunistic Memory Systems in Presence of Hardware Variability
UCLA UCLA Electronic Theses and Dissertations Title Opportunistic Memory Systems in Presence of Hardware Variability Permalink https://escholarship.org/uc/item/85c1r1q9 Author Gottscho, Mark William Publication Date 2017 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California UNIVERSITY OF CALIFORNIA Los Angeles Opportunistic Memory Systems in Presence of Hardware Variability A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering by Mark William Gottscho 2017 c Copyright by Mark William Gottscho 2017 ABSTRACT OF THE DISSERTATION Opportunistic Memory Systems in Presence of Hardware Variability by Mark William Gottscho Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 2017 Professor Puneet Gupta, Chair The memory system presents many problems in computer architecture and system design. An important challenge is worsening hardware variability that is caused by nanometer-scale manufac- turing difficulties. Variability particularly affects memory circuits and systems – which are essen- tial in all aspects of computing – by degrading their reliability and energy efficiency. To address this challenge, this dissertation proposes Opportunistic Memory Systems in Presence of Hardware Variability. It describes a suite of techniques to opportunistically exploit memory variability for energy savings and cope with memory errors when they inevitably occur. In Part 1, three complementary projects are described that exploit memory variability for im- proved energy efficiency. First, ViPZonE and DPCS study how to save energy in off-chip DRAM main memory and on-chip SRAM caches, respectively, without significantly impacting perfor- mance or manufacturing cost. ViPZonE is a novel extension to the virtual memory subsystem in Linux that leverages power variation-aware physical address zoning for energy savings. -
Large Scale Studies of Memory, Storage, and Network Failures in a Modern Data Center
Large Scale Studies of Memory, Storage, and Network Failures in a Modern Data Center Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Justin J. Meza B.S., Computer Science, University of California at Los Angeles M.S., Electrical and Computer Engineering, Carnegie Mellon University arXiv:1901.03401v1 [cs.DC] 1 Jan 2019 Carnegie Mellon University Pittsburgh, PA December 2018 © 2010–2018 Justin J. Meza. All rights reserved. iii Acknowledgements I gratefully acknowledge: My advisor, Onur Mutlu (who also chaired my doctoral committee), who had confidence in me even when I did not. My doctoral committee—Greg Ganger, James Hoe, and Kaushik Veeraraghavan— who were always there to listen to me and guide me. The SAFARI group at CMU, for lifelong friendships. My family, friends, and colleagues (of which there are too many to list!) who kept me going. I also acknowledge generous partial support throughout my PhD from: • National Science Foundation grants 0953246, 1065112, 1147397, 1212962, 1320531, 1409723, and 1423172; Gigascale Systems Research Center; Intel Corporation URO Memory Hierarchy Program; Intel Science and Technology Center for Cloud Computing; Semiconductor Research Corporation; Carnegie Mellon CyLab. • Equipment and gift support from AMD, Facebook, Google, Hewlett-Packard Labs, IBM, Intel, Qual- comm, Samsung, Oracle, and VMware. iv Abstract The workloads running in the modern data centers of large scale Internet service providers (such as Alibaba, Amazon, Baidu, Facebook, Google, and Microsoft) support billions of users and span globally distributed infrastructure. Yet, the devices used in modern data centers fail due to a variety of causes, from faulty components to bugs to misconfiguration. -
Marco Ottavi Dimitris Gizopoulos Salvatore Pontarelli Editors
Marco Ottavi Dimitris Gizopoulos Salvatore Pontarelli Editors Dependable Multicore Architectures at Nanoscale Dependable Multicore Architectures at Nanoscale Marco Ottavi • Dimitris Gizopoulos Salvatore Pontarelli Editors Dependable Multicore Architectures at Nanoscale 123 Editors Marco Ottavi Salvatore Pontarelli Department of Electronic Engineering National Inter-University Consortium University of Rome Tor Vergata for Telecommunications (CNIT) Rome Rome Italy Italy Dimitris Gizopoulos Department of Informatics and Telecommunications National and Kapodistrian University of Athens Athens Greece ISBN 978-3-319-54421-2 ISBN 978-3-319-54422-9 (eBook) DOI 10.1007/978-3-319-54422-9 Library of Congress Control Number: 2017943827 © Springer International Publishing AG 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. -
Self-Healing and Secure Low-Power Memory Systems
Self-healing and secure low-power memory systems Mădălin Neagu ADVERTIMENT La consulta d’aquesta tesi queda condicionada a l’acceptació de les següents condicions d'ús: La difusió d’aquesta tesi per mitjà del repositori institucional UPCommons (http://upcommons.upc.edu/tesis) i el repositori cooperatiu TDX ( http://www.tdx.cat/) ha estat autoritzada pels titulars dels drets de propietat intel·lectual únicament per a usos privats emmarcats en activitats d’investigació i docència. No s’autoritza la seva reproducció amb finalitats de lucre ni la seva difusió i posada a disposició des d’un lloc aliè al servei UPCommons o TDX. No s’autoritza la presentació del seu contingut en una finestra o marc aliè a UPCommons (framing). Aquesta reserva de drets afecta tant al resum de presentació de la tesi com als seus continguts. En la utilització o cita de parts de la tesi és obligat indicar el nom de la persona autora. ADVERTENCIA La consulta de esta tesis queda condicionada a la aceptación de las siguientes condiciones de uso: La difusión de esta tesis por medio del repositorio institucional UPCommons (http://upcommons.upc.edu/tesis) y el repositorio cooperativo TDR (http://www.tdx.cat/?locale- attribute=es) ha sido autorizada por los titulares de los derechos de propiedad intelectual únicamente para usos privados enmarcados en actividades de investigación y docencia. No se autoriza su reproducción con finalidades de lucro ni su difusión y puesta a disposición desde un sitio ajeno al servicio UPCommons No se autoriza la presentación de su contenido en una ventana o marco ajeno a UPCommons (framing). -
EDAC Software Implementation to Protect Small Satellites Memory
EDAC software implementation to protect small satellites memory Rita Roca Taxonera School of Electrical Engineering Final Project Espoo 21.05.2019 Supervisor Alexandre Bosser, Ph.D. Advisor Prof. Jaan Praks Copyright ⃝c 2019 Rita Roca Taxonera Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s final project Author Rita Roca Taxonera Title EDAC software implementation to protect small satellites memory Degree programme Electronics and electrical engineering Major Industrial Engineering Code of major - Supervisor Alexandre Bosser, Ph.D. Advisor Prof. Jaan Praks Date 21.05.2019 Number of pages 60+15 Language English Abstract Radiation is a well-known problem for satellites in space. It can produce different negative effects on electronic components which can provoke errors and failures. Therefore, mitigating these effects is especially important for the success of space missions. One of the techniques to increase the reliability of memory chips and reduce transient errors and permanent faults is Error Detection and Correction (EDAC). EDAC codes are characterised by the use of redundancy to detect and correct errors. This final project consists in the implementation of a software EDAC algorithm to protect the main memory of a microcontroller. The implementation requirements and the issues of software EDAC are described and the test results are commented. Keywords software EDAC, error detection and correction (EDAC), single-event upset (SEU), LEO, small satellites 4 Preface I would like to thank Alexandre Bosser for supervising this final project, for being always available and for his invaluable advice and support. I also would like to thank Jaan Praks for introducing me to the satellites world that was new to me, and also for all his great help and advice. -
System Effects of Single Event Upsets
SYSTEM EFFECTS OF SINGLE EVENT UPSETS A. M. Finn United Technologies Research Center Silver Lane East Hartford, CT 06108 Abstract At the system level, SEUs in processors are controlled by fault-tolerance techniques such as replication and Single Event Upsets (SEUs) pose a serious threat to voting, watchdog processors, and tagged data schemes computer reliability and longevity. SEU effects are found [13,16,30]. SEUs in memory subsystems are controlled at sea level, in airborne avionics, and in space. At the by use of error control codes (ECCs) [4,17,21] and a system level, SEUs in processors are controlled by process called scrubbing. The scrubbing process replication and voting, watchdog processors, and tagged periodically reads each word in the memory. If the data schemes. SEUs in memory subsystems are number of faulty digits in a word is less than or equal to controlled by periodically scrubbing words protected by the number the ECC can correct, then the digits are an Error Control Code (ECC). The rate of memory corrected and the word is written back to memory. If the scrubbing affects the performance and reliability of the number of faulty digits exceeds the ECC's capability, the entire computer system. There are tradeoffs between errors cannot be corrected and the memory has failed. using radiation hardened semiconductors, scrubbing Fault-tolerance to memory failures requires either rates, and ECC capabilities. Previous tradeoff analyses physical redundancy via replication or temporal have used simplified analytic models. redundancy via checkpoint rollback schemes. In most aerospace applications physical redundancy is The system effects of SEUs may be evaluated by Markov undesirable because mass, volume, and power are at a modeling. -
Kingston Tools Ultimate Memory Guide
UNITED STATES Kingston Tools Ultimate Memory Guide WHAT IS MEMORY? INTRODUCTION These days, no matter how much memory your computer has, it never seems to be quite enough. Not long ago, it was unheard of for a PC (Personal Computer), to have more than 1 or 2 MB (Megabytes) of memory. Today, most systems require 128MB to run basic applications. And up to 512MB or more is needed for optimal performance when using graphical and multimedia programs. As an indication of how much things have changed over the past two decades, consider this: in 1981, referring to computer memory, Bill Gates said, "640K (roughly 1/2 of a megabyte) ought to be enough for anybody." For some, the memory equation is simple: more is good; less is bad. However, for those who want to know more, this reference guide contains answers to the most common questions, plus much, much more. THE ROLE OF MEMORY IN THE COMPUTER People in the computer industry commonly use the term "memory" to refer to RAM (Random Access Memory). A computer uses Ram to hold temporary instructions and data needed to complete tasks. This enables the computer's CPU (Central Processing Unit), to access instructions and data stored in memory very quickly. A good example of this is when the CPU loads an application program - such as a word processing or page layout program - into memory, thereby allowing the application program to work as quickly and efficiently as possible. In practical terms, having the program loaded into memory means that you can get work done more quickly with less time spent waiting for the computer to perform tasks.