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Retargetable Compilers and Architecture Exploration for Embedded Processors

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Retargetable Compilers and Architecture Exploration for Embedded Processors Retargetable compilers and architecture exploration for embedded processors R. Leupers, M. Hohenauer, J. Ceng, H. Scharwaechter, H. Meyr, G. Ascheid and G. Braun Abstract: Retargetable compilers can generate assembly code for a variety of different target processor architectures. Owing to their use in the design of application-specific embedded processors, they bridge the gap between the traditionally separate disciplines of compiler construction and electronic design automation. In particular, they assist in architecture exploration for tailoring processors towards a certain application domain. The paper reviews the state-of-the-art in retargetable compilers for embedded processors. Based on some essential compiler background, several representative retargetable compiler systems are discussed, while also outlining their use in iterative, profiling-based architecture exploration. The LISATek C compiler is presented as a detailed case study, and promising areas of future work are proposed. 1 Introduction high-performance off-the-shelf processors from the desktop computer domain (together with their well developed Compilers translate high-level language source code into compiler technology) impossible for many applications. machine-specific assembly code. For this task, any compiler As a consequence, hundreds of different domain or even uses a model of the target processor. This model captures application-specific programmable processors have the compiler-relevant machine resources, including the appeared in the semiconductor market, and this trend instruction set, register files and instruction scheduling is expected to continue. Prominent examples include constraints. While in traditional target-specific compilers low-cost=low-energy microcontrollers (e.g. for wireless this model is built-in (i.e. it is hard-coded and probably sensor networks), number-crunching digital signal pro- distributed within the compiler source code), a retargetable cessors (e.g. for audio and video codecs), as well as network compiler uses an external processor model as an additional processors (e.g. for internet traffic management). input that can be edited without the need to modify the All these devices demand for their own programming compiler source code itself (Fig. 1). This concept provides environment, obviously including a high-level language retargetable compilers with high flexibility with respect to (mostly ANSI C) compiler. This requires the capability of the target processor. quickly designing compilers for new processors, or vari- Retargetable compilers have been recognised as import- ations of existing ones, without the need to start from scratch ant tools in the context of embedded system-on-chip (SoC) each time. While compiler design traditionally has been design for several years. One reason is the trend towards considered a very tedious and manpower-intensive task, increasing use of programmable processor cores as SoC contemporary retargetable compiler technology makes it platform building blocks, which provide the necessary possible to build operational (not heavily optimising) C flexibility for fast adoption, e.g. of new media encoding or compilers within a few weeks and more decent ones protocol standards and easy (software-based) product approximately within a single man-year. Naturally, the upgrading and debugging. While assembly language used exact effort heavily depends on the complexity of the target to be predominant in embedded processor programming for processor, the required code optimisation and robustness quite some time, the increasing complexity of embedded level, and the engineering skills. However, compiler application code now makes the use of high-level languages construction for new embedded processors is now certainly like C and Cþþ just as inevitable as in desktop application much more feasible than a decade ago. This permits us programming. to employ compilers not only for application code develop- In contrast to desktop computers, embedded SoCs have ment,butalsoforoptimisinganembeddedprocessor to meet very high efficiency requirements in terms of architecture itself, leading to a true ‘compiler= architecture MIPS per Watt, which makes the use of power-hungry, codesign’ technology that helps to avoid hardware–software mismatches long before silicon fabrication. This paper summarises the state-of-the-art in retargetable q IEE, 2005 compilers for embedded processors and outlines their design IEE Proceedings online no. 20045075 and use by means of examples and case studies. We provide doi: 10.1049/ip-cdt:20045075 some compiler construction background needed to under- stand the different retargeting technologies and give an Paper first received 7th July and in revised form 27th October 2004 overview of some existing retargetable compiler systems. R. Leupers, M. Hohenauer, J. Ceng, H. Scharwaechter, H. Meyr, and G. Ascheid are with the Institute for Integrated Signal Processing Systems, We describe how the above-mentioned ‘compiler=architec- RWTH Aachen University of Technology, SSS-611920, Templergraben 55, architecture codesign’ concept can be implemented in a D-52056, Aachen, Germany processor architecture exploration environment. A detailed G. Braun is with CoWare Inc., CA 95131, USA example of an industrial retargetable C compiler system is E-mail: [email protected] discussed. IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, March 2005 209 so that the parser can complete its job in linear time in the classical compiler retargetable compiler input size. However, the same also holds for LR(k) parsers source source processor which can process a broader range of context-free code code model grammars. They work bottom-up, i.e. the input token stream is reduced step-by-step until finally reaching the start symbol. Instead of making a reduction step solely based on compiler the knowledge of the k lookahead symbols, the parser processor compiler model additionally stores input symbols temporarily on a stack until enough symbols for an entire right-hand side of a grammar rule have been read. Due to this, the asm asm implementation of an LR(k) parser is less intuitive and code code requires more effort than for LL(k). Constructing LL(k) and LR(k) parsers manually provides Fig. 1 Classical against retargetable compiler some advantage in parsing speed. However, in most practical cases tools like yacc [5] (that generates a variant 2 Compiler construction background of LR(k) parsers) are employed for semi-automatic parser implementation. The general structure of retargetable compilers follows that Finally, the semantic analyser performs correctness of well proven classical compiler technology, which is checks not covered by syntax analysis, e.g. forward described in textbooks such as [1–4]. First, there is a declaration of identifiers and type compatibility of operands. language frontend for source code analysis. The frontend It also builds up a symbol table that stores identifier produces an intermediate representation by which a number information and visibility scopes. In contrast to scanners of machine-independent code optimisations are performed. and parsers, there are no widespread standard tools like lex Finally, the backend translates the intermediate represen- and yacc for generating semantic analysers. Frequently, tation into assembly code, while performing additional attribute grammars [1] are used, though, for capturing the machine-specific code optimisations. semantic actions in a syntax-directed fashion, and special tools like ox [6] can extend lex and yacc to handle attribute grammars. 2.1 Source language frontend The standard organisation of a frontend comprises a scanner, a parser and a semantic analyser (Fig. 2). The 2.2 Intermediate representation and scanner performs lexical analysis on the input source file, optimisation which is first considered just as a stream of ASCII In most cases, the output of the frontend is an intermediate characters. During lexical analysis, the scanner forms representation (IR) of the source code that represents the substrings of the input string to groups (represented by input program as assembly-like, yet machine-independent tokens), each of which corresponds to a primitive syntactic low-level code. Three-address code (Figs. 3 and 4)isa entity of the source language, e.g. identifiers, numerical common IR format. constants, keywords, or operators. These entities can be There is no standard format for three-address code, but represented by regular expressions, for which in turn finite usually all high-level control flow constructs and complex automata can be constructed and implemented that accept expressions are decomposed into simple statement the formal languages generated by the regular expressions. sequences consisting of three-operand assignments and Scanner implementation is strongly facilitated by tools gotos. The IR generator inserts temporary variables to store like lex [5]. intermediate results of computations. The scanner passes the tokenised input file to the parser, Three-address code is a suitable format for performing which performs syntax analysis with respect to the context- different types of flow analysis, i.e. control and data flow free grammar underlying the source language. The parser analysis. Control flow analysis first identifies the basic block recognises syntax errors and, in the case of a correct input, structure of the IR and detects the possible control transfers builds up a tree data structure that represents the syntactic between basic blocks. (A basic
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