The State of the Chapel Union

Total Page:16

File Type:pdf, Size:1020Kb

Load more

The State of the Chapel Union Bradford L. Chamberlain, Sung-Eun Choi, Martha Dumler Thomas Hildebrandt, David Iten, Vassily Litvinov, Greg Titus Cray Inc. Seattle, WA 98164 chapel [email protected] Abstract—Chapel is an emerging parallel programming Cray’s entry in the DARPA HPCS program concluded language that originated under the DARPA High Productivity successfully in the fall of 2012, culminating with the launch Computing Systems (HPCS) program. Although the HPCS pro- of the Cray XC30TM system. Even though the HPCS pro- gram is now complete, the Chapel language and project remain very much alive and well. Under the HCPS program, Chapel gram has completed, the Chapel project remains active and generated sufficient interest among HPC user communities to growing. This paper’s goal is to present a snapshot of Chapel warrant continuing its evolution and development over the next as it stands today at the juncture between HPCS and the several years. In this paper, we reflect on the progress that was next phase of Chapel’s development: to review the Chapel made with Chapel under the auspices of the HPCS program, project, describe its status, summarize its successes and noting key decisions made during the project’s history. We also summarize the current state of Chapel for programmers who lessons learned, and sketch out the next few years of the are interested in using it today. And finally, we describe current language’s life cycle. Generally speaking, this paper reports and ongoing work to evolve it from prototype to production- on Chapel as of version 1.7.01, released on April 18th, 2013. grade; and also to make it better suited for execution on next- The rest of this paper is organized as follows: Section II generation systems. provides a brief history of the Chapel project under HPCS Keywords-Chapel; parallel languages; project status for background. A short introduction to the language’s features is given in Section III, for those unfamiliar with I. INTRODUCTION Chapel. It is followed by a summary of Chapel’s status in Section IV. In Section V, we report on Chapel’s greatest Chapel is a parallel programming language that has been successes and lessons learned under the HPCS program. In developed by Cray Inc. under the DARPA High Productivity Section VI, we describe the next steps in Chapel’s design Computing Systems (HPCS) program over the past decade. and implementation before wrapping up in Section VII. Our primary goal for Chapel under HPCS was to improve programmer productivity on high-end parallel systems. At II. CHAPEL’S ORIGINS the same time, we have worked to make Chapel a portable This section provides a historical overview of the Chapel programming model that is attractive for commodity clus- project. For a more detailed history of Chapel, please refer ters, desktop computing, and parallel programmers outside to [1]. of the traditional High Performance Computing (HPC) com- munity. A. A Brief History of Chapel While the success of any new language can never be In 2002, at the outset of the HPCS program, the Cray guaranteed, Chapel has succeeded in making a very positive team (codenamed Cascade) began considering ways to im- impression on the parallel programming community. Most prove user productivity across the entire system stack: from programmers who have invested the time to learn about processor and memory architecture, to network technology Chapel are very interested in using it once its implementation and topology, to operating system and runtime responsi- becomes more robust and optimized. Perhaps more than any bilities, to programming environment features. As part of previous parallel language, there is a strong desire among this investigation, the team wrestled with whether or not to a broad base of users to see Chapel succeed and evolve develop a new programming language, considering the status from its current prototype status to become product-grade. quo to be far from ideal from a productivity perspective. Chapel has been downloaded over 6,000 times since its first Initially, there was concern that a language developed by public release in November of 2008, and it is also available a lone hardware vendor could not possibly be successful as a standard module on most Cray systems. It has been and was therefore not worth the effort; however, we soon experimented with by typical HPC users in government realized that many of the most successful languages had been and industry, nationally and internationally, as well as by developed in precisely this way and had simply transitioned research and educational groups within Computer Science departments. 1Available for download at https://sourceforge.net/projects/chapel/. to a consortium-based model as they grew in maturity. the broader Chapel community. At SC11, the first Chapel Having overcome that initial hesitancy, the Chapel project “swag” was developed—a USB stick bearing the Chapel was initiated during the first half of 2003. From the outset, logo. SC11 also saw the first in a series of “Chapel Lightning it was determined to be a portable, open-source effort that Talks” sessions, highlighting work being done on Chapel by would also support the ability to leverage Cray architectural a half dozen groups outside of Cray. features. In October 2012, Chapel completed its final deliverables From 2003 through 2006, Chapel existed in a reasonably for the DARPA HPCS program: a scalable execution of the molten state. The team at that time was simultaneously SSCA#2 benchmark on the prototype Cray XC30 system working to define the language and kick off the imple- and a final productivity report. In the ensuing time, the mentation effort. Much of this period was characterized team has continued working on improvements to Chapel by wrestling with different language concepts and design while simultaneously planning for the next phase in Chapel’s philosophies, striving to find a set of features that would development (described in Section VI). work well together. In early summer 2006, a turning point B. Chapel By the Numbers was reached when the current type inference semantics and compiler architecture were formulated. From that point The following list provides some numbers characterizing on, progress became much more monotonic and stable. In aspects of Chapel’s history at the time of this writing: December 2006, the first Chapel release (version 0.4) was 21,334: Commits against the Chapel public repository made available on a by-request basis and included support 6116: Downloads of Chapel releases from SourceForge for multitasking in a single-locale (shared memory) setting. 1024: Messages sent to the chapel-users mailing list In July 2007, the first multi-locale (distributed memory) 192: Unique, non-Cray subscribers to Chapel mailing Chapel programs began running, and by March 2008, this lists hosted at SourceForge support was stable enough to be included in the fourth 154: Chapel talks given by the Cray team and final request-only release of Chapel (version 0.7). From 80 at conferences and workshops there, the implementation began focusing on Chapel’s data 32 at milestone reviews parallel features, both in single- and multi-locale settings. 18 at universities That fall, Chapel was mature enough to run versions of 16 at government labs the HPCC Stream and Random Access (RA) benchmarks 8 in industry settings written with a user-defined Block distribution that scaled to 24: Notable collaborations external to the Cray team hundreds of compute nodes. This milestone earned Chapel 10 with national labs a place in the three-way tie with Matlab and UPC/X10 10 with academic groups for “most elegant” language in the 2008 HPC Challenge 4 with international teams competition. That fall also saw our first public release of 17: Number of Chapel tutorials given Chapel (version 0.8) and our first tutorial at SC08. The following several years saw Chapel increase in 6 at SCxy maturity and prominence. In April 2009, Chapel’s source 5 in Europe code repository moved from being hosted in an invite- 3 at government labs only manner at the University of Washington to an open 3 at CUG repository at SourceForge, where it continues to be hosted 14: Major releases of Chapel today. A few months later, the Chapel website was launched 10 public releases at http://chapel.cray.com. At that year’s HPC Challenge 4 by request only competition, Chapel emerged from the pack and was named 0: Language modifications due to changes in the the “most productive” language—a title that it has retained Cascade architecture during the HPCS program each year it has participated since then (2011 and 2012). This last item is notable because Chapel was designed to be a From 2009 onward, the number of collaborations and very general, portable parallel programming language; so the user interactions undertaken around Chapel increased signif- fact that it did not need to change as the Cascade architecture icantly, resulting in the first signs of a broader open-source evolved can be considered an indicator of success in that Chapel community outside of Cray [2], [3], [4], [5], [6]. regard. Chapel also came of age this year in that it began to be considered an expected participant within the HPC space III. CHAPEL OVERVIEW rather than yet another contender doomed to failure. At For readers who are unfamiliar with Chapel, this section SC10, the Chapel community met for the first in a series provides a brief summary of the language features. Those of annual CHUG (Chapel Users Group) happy hours. In who are familiar with Chapel can safely skip to the following August 2011, the Chapel logo was unveiled, based on the section. This overview is necessarily high-level and not in- winning entry in a contest held amongst Cray employees and tended to be a replacement for a thorough introduction to the language.
Recommended publications
  • Introduction to Openacc 2018 HPC Workshop: Parallel Programming

    Introduction to Openacc 2018 HPC Workshop: Parallel Programming

    Introduction to OpenACC 2018 HPC Workshop: Parallel Programming Alexander B. Pacheco Research Computing July 17 - 18, 2018 CPU vs GPU CPU : consists of a few cores optimized for sequential serial processing GPU : has a massively parallel architecture consisting of thousands of smaller, more efficient cores designed for handling multiple tasks simultaneously GPU enabled applications 2 / 45 CPU vs GPU CPU : consists of a few cores optimized for sequential serial processing GPU : has a massively parallel architecture consisting of thousands of smaller, more efficient cores designed for handling multiple tasks simultaneously GPU enabled applications 2 / 45 CPU vs GPU CPU : consists of a few cores optimized for sequential serial processing GPU : has a massively parallel architecture consisting of thousands of smaller, more efficient cores designed for handling multiple tasks simultaneously GPU enabled applications 2 / 45 CPU vs GPU CPU : consists of a few cores optimized for sequential serial processing GPU : has a massively parallel architecture consisting of thousands of smaller, more efficient cores designed for handling multiple tasks simultaneously GPU enabled applications 2 / 45 3 / 45 Accelerate Application for GPU 4 / 45 GPU Accelerated Libraries 5 / 45 GPU Programming Languages 6 / 45 What is OpenACC? I OpenACC Application Program Interface describes a collection of compiler directive to specify loops and regions of code in standard C, C++ and Fortran to be offloaded from a host CPU to an attached accelerator. I provides portability across operating systems, host CPUs and accelerators History I OpenACC was developed by The Portland Group (PGI), Cray, CAPS and NVIDIA. I PGI, Cray, and CAPs have spent over 2 years developing and shipping commercial compilers that use directives to enable GPU acceleration as core technology.
  • Threads Chapter 4

    Threads Chapter 4

    Threads Chapter 4 Reading: 4.1,4.4, 4.5 1 Process Characteristics ● Unit of resource ownership - process is allocated: ■ a virtual address space to hold the process image ■ control of some resources (files, I/O devices...) ● Unit of dispatching - process is an execution path through one or more programs ■ execution may be interleaved with other process ■ the process has an execution state and a dispatching priority 2 Process Characteristics ● These two characteristics are treated independently by some recent OS ● The unit of dispatching is usually referred to a thread or a lightweight process ● The unit of resource ownership is usually referred to as a process or task 3 Multithreading vs. Single threading ● Multithreading: when the OS supports multiple threads of execution within a single process ● Single threading: when the OS does not recognize the concept of thread ● MS-DOS support a single user process and a single thread ● UNIX supports multiple user processes but only supports one thread per process ● Solaris /NT supports multiple threads 4 Threads and Processes 5 Processes Vs Threads ● Have a virtual address space which holds the process image ■ Process: an address space, an execution context ■ Protected access to processors, other processes, files, and I/O Class threadex{ resources Public static void main(String arg[]){ ■ Context switch between Int x=0; processes expensive My_thread t1= new my_thread(x); t1.start(); ● Threads of a process execute in Thr_wait(); a single address space System.out.println(x) ■ Global variables are
  • Lecture 10: Introduction to Openmp (Part 2)

    Lecture 10: Introduction to Openmp (Part 2)

    Lecture 10: Introduction to OpenMP (Part 2) 1 Performance Issues I • C/C++ stores matrices in row-major fashion. • Loop interchanges may increase cache locality { … #pragma omp parallel for for(i=0;i< N; i++) { for(j=0;j< M; j++) { A[i][j] =B[i][j] + C[i][j]; } } } • Parallelize outer-most loop 2 Performance Issues II • Move synchronization points outwards. The inner loop is parallelized. • In each iteration step of the outer loop, a parallel region is created. This causes parallelization overhead. { … for(i=0;i< N; i++) { #pragma omp parallel for for(j=0;j< M; j++) { A[i][j] =B[i][j] + C[i][j]; } } } 3 Performance Issues III • Avoid parallel overhead at low iteration counts { … #pragma omp parallel for if(M > 800) for(j=0;j< M; j++) { aa[j] =alpha*bb[j] + cc[j]; } } 4 C++: Random Access Iterators Loops • Parallelization of random access iterator loops is supported void iterator_example(){ std::vector vec(23); std::vector::iterator it; #pragma omp parallel for default(none) shared(vec) for(it=vec.begin(); it< vec.end(); it++) { // do work with it // } } 5 Conditional Compilation • Keep sequential and parallel programs as a single source code #if def _OPENMP #include “omp.h” #endif Main() { #ifdef _OPENMP omp_set_num_threads(3); #endif for(i=0;i< N; i++) { #pragma omp parallel for for(j=0;j< M; j++) { A[i][j] =B[i][j] + C[i][j]; } } } 6 Be Careful with Data Dependences • Whenever a statement in a program reads or writes a memory location and another statement reads or writes the same memory location, and at least one of the two statements writes the location, then there is a data dependence on that memory location between the two statements.
  • The Problem with Threads

    The Problem with Threads

    The Problem with Threads Edward A. Lee Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.html January 10, 2006 Copyright © 2006, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement This work was supported in part by the Center for Hybrid and Embedded Software Systems (CHESS) at UC Berkeley, which receives support from the National Science Foundation (NSF award No. CCR-0225610), the State of California Micro Program, and the following companies: Agilent, DGIST, General Motors, Hewlett Packard, Infineon, Microsoft, and Toyota. The Problem with Threads Edward A. Lee Professor, Chair of EE, Associate Chair of EECS EECS Department University of California at Berkeley Berkeley, CA 94720, U.S.A. [email protected] January 10, 2006 Abstract Threads are a seemingly straightforward adaptation of the dominant sequential model of computation to concurrent systems. Languages require little or no syntactic changes to sup- port threads, and operating systems and architectures have evolved to efficiently support them. Many technologists are pushing for increased use of multithreading in software in order to take advantage of the predicted increases in parallelism in computer architectures.
  • GPU Computing with Openacc Directives

    GPU Computing with Openacc Directives

    Introduction to OpenACC Directives Duncan Poole, NVIDIA Thomas Bradley, NVIDIA GPUs Reaching Broader Set of Developers 1,000,000’s CAE CFD Finance Rendering Universities Data Analytics Supercomputing Centers Life Sciences 100,000’s Oil & Gas Defense Weather Research Climate Early Adopters Plasma Physics 2004 Present Time 3 Ways to Accelerate Applications Applications OpenACC Programming Libraries Directives Languages “Drop-in” Easily Accelerate Maximum Acceleration Applications Flexibility 3 Ways to Accelerate Applications Applications OpenACC Programming Libraries Directives Languages CUDA Libraries are interoperable with OpenACC “Drop-in” Easily Accelerate Maximum Acceleration Applications Flexibility 3 Ways to Accelerate Applications Applications OpenACC Programming Libraries Directives Languages CUDA Languages are interoperable with OpenACC, “Drop-in” Easily Accelerate too! Maximum Acceleration Applications Flexibility NVIDIA cuBLAS NVIDIA cuRAND NVIDIA cuSPARSE NVIDIA NPP Vector Signal GPU Accelerated Matrix Algebra on Image Processing Linear Algebra GPU and Multicore NVIDIA cuFFT Building-block Sparse Linear C++ STL Features IMSL Library Algorithms for CUDA Algebra for CUDA GPU Accelerated Libraries “Drop-in” Acceleration for Your Applications OpenACC Directives CPU GPU Simple Compiler hints Program myscience Compiler Parallelizes code ... serial code ... !$acc kernels do k = 1,n1 do i = 1,n2 OpenACC ... parallel code ... Compiler Works on many-core GPUs & enddo enddo Hint !$acc end kernels multicore CPUs ... End Program myscience
  • Openacc Course October 2017. Lecture 1 Q&As

    Openacc Course October 2017. Lecture 1 Q&As

    OpenACC Course October 2017. Lecture 1 Q&As. Question Response I am currently working on accelerating The GCC compilers are lagging behind the PGI compilers in terms of code compiled in gcc, in your OpenACC feature implementations so I'd recommend that you use the PGI experience should I grab the gcc-7 or compilers. PGI compilers provide community version which is free and you try to compile the code with the pgi-c ? can use it to compile OpenACC codes. New to OpenACC. Other than the PGI You can find all the supported compilers here, compiler, what other compilers support https://www.openacc.org/tools OpenACC? Is it supporting Nvidia GPU on TK1? I Currently there isn't an OpenACC implementation that supports ARM think, it must be processors including TK1. PGI is considering adding this support sometime in the future, but for now, you'll need to use CUDA. OpenACC directives work with intel Xeon Phi is treated as a MultiCore x86 CPU. With PGI you can use the "- xeon phi platform? ta=multicore" flag to target multicore CPUs when using OpenACC. Does it have any application in field of In my opinion OpenACC enables good software engineering practices by Software Engineering? enabling you to write a single source code, which is more maintainable than having to maintain different code bases for CPUs, GPUs, whatever. Does the CPU comparisons include I think that the CPU comparisons include standard vectorisation that the simd vectorizations? PGI compiler applies, but no specific hand-coded vectorisation optimisations or intrinsic work. Does OpenMP also enable OpenMP does have support for GPUs, but the compilers are just now parallelization on GPU? becoming available.
  • Modifiable Array Data Structures for Mesh Topology

    Modifiable Array Data Structures for Mesh Topology

    Modifiable Array Data Structures for Mesh Topology Dan Ibanez Mark S Shephard February 27, 2016 Abstract Topological data structures are useful in many areas, including the various mesh data structures used in finite element applications. Based on the graph-theoretic foundation for these data structures, we begin with a generic modifiable graph data structure and apply successive optimiza- tions leading to a family of mesh data structures. The results are compact array-based mesh structures that can be modified in constant time. Spe- cific implementations for finite elements and graphics are studied in detail and compared to the current state of the art. 1 Introduction An unstructured mesh simulation code relies heavily on multiple core capabili- ties to deal with the mesh itself, and the range of features available at this level constrain the capabilities of the simulation as a whole. As such, the long-term goal towards which this paper contributes is the development of a mesh data structure with the following capabilities: 1. The flexibility to deal with evolving meshes 2. A highly scalable implementation for distributed memory computers 3. The ability to represent any of the conforming meshes typically used by Finite Element (FE) and Finite Volume (FV) methods 4. Minimize memory use 5. Maximize locality of storage 6. The ability to parallelize work inside supercomputer nodes with hybrid architecture such as accelerators This paper focuses on the first five goals; the sixth will be the subject of a future publication. In particular, we present a derivation for a family of structures with these properties: 1 1.
  • CUDA Binary Utilities

    CUDA Binary Utilities

    CUDA Binary Utilities Application Note DA-06762-001_v11.4 | September 2021 Table of Contents Chapter 1. Overview..............................................................................................................1 1.1. What is a CUDA Binary?...........................................................................................................1 1.2. Differences between cuobjdump and nvdisasm......................................................................1 Chapter 2. cuobjdump.......................................................................................................... 3 2.1. Usage......................................................................................................................................... 3 2.2. Command-line Options.............................................................................................................5 Chapter 3. nvdisasm.............................................................................................................8 3.1. Usage......................................................................................................................................... 8 3.2. Command-line Options...........................................................................................................14 Chapter 4. Instruction Set Reference................................................................................ 17 4.1. Kepler Instruction Set.............................................................................................................17
  • Lithe: Enabling Efficient Composition of Parallel Libraries

    Lithe: Enabling Efficient Composition of Parallel Libraries

    BERKELEY PAR LAB Lithe: Enabling Efficient Composition of Parallel Libraries Heidi Pan, Benjamin Hindman, Krste Asanović [email protected] {benh, krste}@eecs.berkeley.edu Massachusetts Institute of Technology UC Berkeley HotPar Berkeley, CA March 31, 2009 1 How to Build Parallel Apps? BERKELEY PAR LAB Functionality: or or or App Resource Management: OS Hardware Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7 Need both programmer productivity and performance! 2 Composability is Key to Productivity BERKELEY PAR LAB App 1 App 2 App sort sort bubble quick sort sort code reuse modularity same library implementation, different apps same app, different library implementations Functional Composability 3 Composability is Key to Productivity BERKELEY PAR LAB fast + fast fast fast + faster fast(er) Performance Composability 4 Talk Roadmap BERKELEY PAR LAB Problem: Efficient parallel composability is hard! Solution: . Harts . Lithe Evaluation 5 Motivational Example BERKELEY PAR LAB Sparse QR Factorization (Tim Davis, Univ of Florida) Column Elimination SPQR Tree Frontal Matrix Factorization MKL TBB OpenMP OS Hardware System Stack Software Architecture 6 Out-of-the-Box Performance BERKELEY PAR LAB Performance of SPQR on 16-core Machine Out-of-the-Box sequential Time (sec) Time Input Matrix 7 Out-of-the-Box Libraries Oversubscribe the Resources BERKELEY PAR LAB TX TYTX TYTX TYTX A[0] TYTX A[0] TYTX A[0] TYTX A[0] TYTX TYA[0] A[0] A[0]A[0] +Z +Z +Z +Z +Z +Z +Z +ZA[1] A[1] A[1] A[1] A[1] A[1] A[1]A[1] A[2] A[2] A[2] A[2] A[2] A[2] A[2]A[2]
  • Thread Scheduling in Multi-Core Operating Systems Redha Gouicem

    Thread Scheduling in Multi-Core Operating Systems Redha Gouicem

    Thread Scheduling in Multi-core Operating Systems Redha Gouicem To cite this version: Redha Gouicem. Thread Scheduling in Multi-core Operating Systems. Computer Science [cs]. Sor- bonne Université, 2020. English. tel-02977242 HAL Id: tel-02977242 https://hal.archives-ouvertes.fr/tel-02977242 Submitted on 24 Oct 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Ph.D thesis in Computer Science Thread Scheduling in Multi-core Operating Systems How to Understand, Improve and Fix your Scheduler Redha GOUICEM Sorbonne Université Laboratoire d’Informatique de Paris 6 Inria Whisper Team PH.D.DEFENSE: 23 October 2020, Paris, France JURYMEMBERS: Mr. Pascal Felber, Full Professor, Université de Neuchâtel Reviewer Mr. Vivien Quéma, Full Professor, Grenoble INP (ENSIMAG) Reviewer Mr. Rachid Guerraoui, Full Professor, École Polytechnique Fédérale de Lausanne Examiner Ms. Karine Heydemann, Associate Professor, Sorbonne Université Examiner Mr. Etienne Rivière, Full Professor, University of Louvain Examiner Mr. Gilles Muller, Senior Research Scientist, Inria Advisor Mr. Julien Sopena, Associate Professor, Sorbonne Université Advisor ABSTRACT In this thesis, we address the problem of schedulers for multi-core architectures from several perspectives: design (simplicity and correct- ness), performance improvement and the development of application- specific schedulers.
  • Multi-Threaded GPU Accelerration of ORBIT with Minimal Code

    Multi-Threaded GPU Accelerration of ORBIT with Minimal Code

    Princeton Plasma Physics Laboratory PPPL- 4996 4996 Multi-threaded GPU Acceleration of ORBIT with Minimal Code Modifications Ante Qu, Stephane Ethier, Eliot Feibush and Roscoe White FEBRUARY, 2014 Prepared for the U.S. Department of Energy under Contract DE-AC02-09CH11466. Princeton Plasma Physics Laboratory Report Disclaimers Full Legal Disclaimer This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, nor any of their contractors, subcontractors or their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or any third party’s use or the results of such use of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof or its contractors or subcontractors. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. Trademark Disclaimer Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof or its contractors or subcontractors. PPPL Report Availability Princeton Plasma Physics Laboratory: http://www.pppl.gov/techreports.cfm Office of Scientific and Technical Information (OSTI): http://www.osti.gov/bridge Related Links: U.S.
  • HPVM: Heterogeneous Parallel Virtual Machine

    HPVM: Heterogeneous Parallel Virtual Machine

    HPVM: Heterogeneous Parallel Virtual Machine Maria Kotsifakou∗ Prakalp Srivastava∗ Matthew D. Sinclair Department of Computer Science Department of Computer Science Department of Computer Science University of Illinois at University of Illinois at University of Illinois at Urbana-Champaign Urbana-Champaign Urbana-Champaign [email protected] [email protected] [email protected] Rakesh Komuravelli Vikram Adve Sarita Adve Qualcomm Technologies Inc. Department of Computer Science Department of Computer Science [email protected]. University of Illinois at University of Illinois at com Urbana-Champaign Urbana-Champaign [email protected] [email protected] Abstract hardware, and that runtime scheduling policies can make We propose a parallel program representation for heteroge- use of both program and runtime information to exploit the neous systems, designed to enable performance portability flexible compilation capabilities. Overall, we conclude that across a wide range of popular parallel hardware, including the HPVM representation is a promising basis for achieving GPUs, vector instruction sets, multicore CPUs and poten- performance portability and for implementing parallelizing tially FPGAs. Our representation, which we call HPVM, is a compilers for heterogeneous parallel systems. hierarchical dataflow graph with shared memory and vector CCS Concepts • Computer systems organization → instructions. HPVM supports three important capabilities for Heterogeneous (hybrid) systems; programming heterogeneous systems: a compiler interme- diate representation (IR), a virtual instruction set (ISA), and Keywords Virtual ISA, Compiler, Parallel IR, Heterogeneous a basis for runtime scheduling; previous systems focus on Systems, GPU, Vector SIMD only one of these capabilities. As a compiler IR, HPVM aims to enable effective code generation and optimization for het- 1 Introduction erogeneous systems.