Ethernet: CSMA/CD
Total Page：16
File Type：pdf, Size：1020Kb
Course Introduction Purpose • The intent of this course is to provide an overview of the MC9S12NE64 16-bit MCU. Objectives • Describe the main features of the NE64. • Identify derivative availability. • Describe the Ethernet Media Access Controller (EMAC). • Describe the Ethernet Physical Transceiver (EPHY). • Relate their functions and capabilities to the IEEE 802.3 standard. • Describe the development tools environment. Content • 32 pages • 6 questions Learning Time • 50 minutes Welcome to the MC9S12NE64 Certification Training Course. The intent of this course is to provide an overview of the MC9S12NE64 (NE64) 16-bit MCU. The 128K and 256K versions will be offered with 32 bit solution and will not be part of the NE family. You will learn about the key features of this device, its available derivatives, the ever essential development tools environment available to support this device, and future derivatives of this device. You will also learn about the Ethernet Physical Interface (EPHY) and the Ethernet Medium Access Controller (EMAC) and how they work to implement the IEEE 802.3 standard. Finally, you will gain an understanding of the targeted applications for this technology. 1 MC9S12NE64 HCS12 CPU SPI 8-ch 10-Bit 25 MHz ADC 2 SCI 64K 4-ch 16-Bit IIC FLASH TIMER 10/100 TEST CONT 8K RAM BaseT TEST CONT EMAC V REG CRG 10/100 BaseT KBI EPHY KBI EXP BUS I/F 70 GPIO BDM PART NUMBER PACKAGE TEMP Orderable QTY’s MC9S12NE64VTU 80 TQFP-EP -40 TO 105 C 90 MC9S12NE64CPV 112 LQFP -40 TO 85 C 60 Let’s begin with an overview of the NE64 MCU, one of many derivatives available in the HCS12 portfolio of 16-bit MCUs. This device has full 16-bit data paths throughout and contains a wide variety of highly configurable memory and peripheral options. It is intended to provide a single- chip solution with a minimum number of external components in a wide variety of low cost, end node connectivity applications. The 10/100 BaseT EMAC and the 10/100 BaseT EPHY are two differentiated features in this device. We will discuss these features in greater detail later in this course. The NE64 device is offered in two package options. Option one is the 80-pin Thermally Enhanced Quad Flat Pack (TQFP). Samples can be ordered with two devices per kit or in production quantities of 90 devices per tray. This option has a total of 38 general purpose input/output (GPIO) pins, as well as 10 dedicated Input-only pins available to the user. Port pins that are not bonded out in this package should be initialized as inputs with enabled pull-up resistance to minimize excess current consumption. Option one has an exposed flag for additional heat dissipation. This should be accommodated during PCB layout by either a hatched pattern in the solder mask or by providing small copper areas under the flag. At least 50 percent of the total area of the flag should be soldered to the PCB to ensure adequate heat dissipation for this extended temperature (-40°C to 105°C) package. Option two is the 112-pin Low Profile Quad Flat Pack (LQFP). Samples can be ordered with two devices per kit or in production quantities of 60 devices per tray. This package has more pins available, which can support an expanded bus interface. This option has up to 70 GPIO pins, as well as 10 dedicated Input-only pins available to the user. We will describe the other blocks in greater detail later. 2 NE64 Features 1 Synchronous Serial Peripheral Interface (SPI) Mouse over each peripheral to learn more. • Master mode and slave mode • Serial clock with programmable polarity and phase 2 Asynchronous Serial Communications Interfaces ( 2 SCI) HCS12 CPU SPI 8-ch 10-Bit • 13-bit baud rate selection • Programmable 8- or 9-bit data format 25 MHz ADC 2 SCI • Selectable IrDA1.4 return-to-zero-inverted (RZI) format with programmable pulse widths Inter-IC Bus (IIC) 64K 4-ch 16-Bit • Two-wire bi-directional serial bus providing a simple effective method of data exchange IIC FLASH TIMER • Minimizes the need for large number of connections • Eliminates the need for an address decoder 10/100 10/100 Mbps Ethernet Media Access Controller (EMAC) TEST CONT 8K RAM BaseT • Media Independent Interface (MII) with data management EMAC • Full-duplex flow control V REG • Two receive buffers and One transmit buffer CRG 10/100 BaseT • Packet filtering to lower burden on MCU BaseT KBI – Address recognition filtering EXP BUS EPHY – EtherType filtering I/F • Auto speed selection (auto negotiation) 70 GPIO BDM • Full-/half- duplex modes (auto negotiation) 16-bit HCS12 CPU (25MHz) • Direct connection to socket/transformer •Upward compatible with M68HC11 instruction set • For 10BaseT operation, the internal bus clock must be >2.5 MHz •Interrupt stacking and programmer’s model identical to HC11/HC12 • For 100BaseT operation, the internal bus clock must be 25 MHz •20-bit ALU 10/100 Mbps Ethernet Physical Transceiver (EPHY) 64KB Flash Memory • Requires a minimum number of external components •Organized as 1024 rows of 64 bytes • For basic operation, the Reference Clock to the EPHY must be 25MHz (spec’d at 25ppm) •Erase sector size is 8 rows (512 bytes) Shared RAM Up to 70 I/O and 10 Inputs •Zero wait state accesses; (supports single-cycle misaligned word accesses • Each I/O pin can be configured by by several registers: Input/Output selection, drive strength reduction without wait states) select of pull up/pull down resistors, interrupt enable and status flags. •When the EMAC module is enabled, functions as the FIFO buffer (S/W • Some pins have optional features such as Open drain for wired-or connections and interrupt inputs with selectable from: .375K to 4.5K) •Allows same cycle read/write access from the CPU and the EMAC •ENET FIFO is configured as 1 Transmit and 2 Receive Buffers (A&B) Analog-to-Digital Converter (ADC) Clocks and Reset Generator Module (CRG) • Flexible 8-channel module with 10-bit resolution •PLL frequency multiplier • Supports external conversion trigger capability •Self clock in absence of reference clock Timer Module (TIMER) Multiplexed Expanded Bus Interface (MEBI) • PLL frequency multiplier •Available only in the 112-pin package at a specified maximum bus speed of 16 MHz • Self clock in absence of reference clock •For external bus speeds of 2.5 MHz to 16 MHz; only 10BaseT Port Integration Module (PIM) communication is supported • Establishes the interface between the peripheral modules and the input/output (I/O) pins for all ports •Multiplexed address and data (16-bit wide and 8-bit narrow bus modes) •Ability to enable/disable pull-up resistors and enable/disable reduced output • Input/Output selection, Pull up/Pull down selection, drive strength selection, etc. drive on Ports A,B,E, and K Voltage Regulator (V REG) •Supports a number of modes of operation including various emulation, • Provides 5 independent 2.5V output voltages from a 3.3V +/- 5 % input voltage special test and peripheral modes • Three modes of operation: full power, reduced power, shutdown • Includes the Low Voltage Reset (LVR) and Power On Reset (POR) functions Let’s take a look at the main features of the NE64. Roll your mouse pointer over each peripheral for more information. 3 Question Question Which of the following communications interfaces are available on board the NE64? Select all that apply and then click Done. SPI CAN IIC SCI 10/100 EMAC 10/100 EPHY Consider this question regarding the NE64’s basic feature set. Correct. The NE64 includes a number of integrated peripheral interfaces to simplify system design and components count for users. SPI, IIC, SCI, 10/100 EMAC, and 10/100 EPHY are all available as integrated peripheral interfaces on the NE64. The Controller Area Network (CAN) is not one of the communications interfaces available on the NE64. 4 NE64 Flash Memory Now, let’s examine the NE64’s Flash memory in more detail. The NE64 utilizes a 64-KB, .25µm Flash array, which offers automated program and erase algorithms. It is not possible to read from the Flash block while it is being programmed or erased. Cumulative programming of bits within a word are not allowed in the FTS64K Flash block, that is, a word must be erased before being programmed. The Flash array can be globally secured (protected). Additionally, two smaller sectors at the low and high end of Flash memory can be secured for critical data, like boot loader code. The Flash array uses the oscillator clock to perform Flash program or erase operations. The internal Flash clock frequency must be configured to run between 150 KHz and 200 KHz. The Clock Divider allows the user to divide down the oscillator clock to the desired range. 5 NE64 CRG Module Click the “Registers” block to learn about the flags in the CRGFLG register. Let’s take a few minutes to examine the NE64’s CRG module. In order for the NE64 to operate properly as an Ethernet device, the Phase-Locked Loop (PLL) should be selected, that is, the PLLSEL bit must be set. The SYSCLK must be configured to 25 MHz. As you can see from the block diagram, programming the CRG module can be challenging and time consuming. Processor Expert™ can be used within (or independent of) the CodeWarrior Integrated Development Environment (IDE) to simplify programming the CRG module and any other resource/module that must be software configured before it can be used on the NE64. A number of useful timing- and voltage-derived interrupts and resets are generated from this module. In addition to the physical signals, a number of flags are indicated in the CRG Flags Register (CRGFLG) within the registers block.