DOCSLIB.ORG

Java™ SE Performance Tuning Revision A

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Java™ SE Performance Tuning Revision A Java™ SE Performance Tuning Revision A SEM-DTJ-380-LA Copyright 2008 Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, California 95054, U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Sun, Sun Microsystems, the Sun logo, the Duke logo, Java, JavaServer Pages, JSP, Java HotSpot, Java VisualVM, Sun Fire T1000, Sun Fire T2000, UltraSparc, NetBeans, NetBeans Profiler, Sun Studio, and JavaScript are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The OPEN LOOK and Sun Graphical User Interface was developed by Sun Microsystems, Inc. for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface, which license also covers Sun's licensees who implement OPEN LOOK GUIs and otherwise comply with Sun's written license agreements. Federal Acquisitions: Commercial Software Government Users Subject to Standard License Terms and Conditions Export Laws. Products, Services, and technical data delivered by Sun may be subject to U.S. export controls or the trade laws of other countries. You will comply with all such laws and obtain all licenses to export, re-export, or import as may be required after delivery to You. You will not export or re-export to entities on the most current U.S. export exclusions lists or to any country subject to U.S. embargo or terrorist controls as specified in the U.S. export laws. You will not use or provide Products, Services, or technical data for nuclear, missile, or chemical biological weaponry end uses. DOCUMENTATION IS PROVIDED "AS IS" AND ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS, AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. Export Control Classification Number (ECCN) assigned:EAR99 Copyright 2008 Sun Microsystems Inc., 4150 Network Circle, Santa Clara, California 95054, Etats-Unis. Tous droits ré servé s. Ce produit ou document est proté gé par un copyright et distribué avec des licences qui en restreignent l'utilisation, la copie, la distribution, et la dé compilation. Aucune partie de ce produit ou document ne peut ê tre reproduite sous aucune forme, par quelque moyen que ce soit, sans l'autorisation pré alable et é crite de Sun et de ses bailleurs de licence, s'il y en a. Le logiciel dé tenu par des tiers, et qui comprend la technologie relative aux polices de caractè res, est proté gé par un copyright et licencié par des fournisseurs de Sun. Sun, Sun Microsystems, the Sun logo, the Duke logo, Java, JavaServer Pages, JSP, Java HotSpot, Java VisualVM, Sun Fire T1000, Sun Fire T2000, UltraSparc, NetBeans, NetBeans Profiler, Sun Studio et JavaScript sont des marques de fabrique ou des marques dé posé es de Sun Microsystems, Inc. aux Etats-Unis et dans d'autres pays. L'interfaces d'utilisation graphique OPEN LOOK et Sun a é té dé veloppé e par Sun Microsystems, Inc. pour ses utilisateurs et licencié s. Sun reconnaît les efforts de pionniers de Xerox pour larecherche et le dé veloppement du concept des interfaces d'utilisation visuelle ou graphique pour l'industrie de l'informatique. Sun dé tient une licence non exclusive de Xerox sur l'interface d'utilisation graphique Xerox, cette licence couvrant é galement les licencié s de Sun qui mettent en place l'interface d'utilisation graphique OPEN LOOK et qui en outre se conforment aux licences é crites de Sun. Lé gislation en matiè re dexportations. Les Produits, Services et donné es techniques livré s par Sun peuvent ê tre soumis aux contrô les amé ricains sur les exportations, ou à la lé gislation commerciale dautres pays. Nous nous conformerons à lensemble de ces textes et nous obtiendrons toutes licences dexportation, de ré -exportation ou dimportation susceptibles dê tre requises aprè s livraison à Vous. Vous nexporterez, ni ne ré -exporterez en aucun cas à des entité s figurant sur les listes amé ricaines dinterdiction dexportation les plus courantes, ni vers un quelconque pays soumis à embargo par les Etats-Unis, ou à des contrô les anti-terroristes, comme pré vu par la lé gislation amé ricaine en matiè re dexportations. Vous nutiliserez, ni ne fournirez les Produits, Services ou donné es techniques pour aucune utilisation finale lié e aux armes nuclé aires, chimiques ou biologiques ou aux missiles. LA DOCUMENTATION EST FOURNIE "EN L'ETAT" ET TOUTES AUTRES CONDITIONS, DECLARATIONS ET GARANTIES EXPRESSES OU TACITES SONT FORMELLEMENT EXCLUES, DANS LA MESURE AUTORISEE PAR LA LOI APPLICABLE, Y COMPRIS NOTAMMENT TOUTE GARANTIE IMPLICITE RELATIVE A LA QUALITE MARCHANDE, A L'APTITUDE A UNE UTILISATION PARTICULIERE OU A L'ABSENCE DE CONTREFAÇ ON. Course Objectives • Incorporate monitoring, profiling and tuning into the application development life cycle • Monitor the Operating System (OS) layer: Central Processing Unit (CPU), network, disk I/O, virtual memory, processes and locks • Monitor the Java Virtual Machine (JVM) and application layers • Profile the OS, JVM and application layers • Tune garbage collection (GC) The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 4 Course Objectives • Examine and manage the Just in Time (JIT) compiler • Examine JVM ergonomics • Examine 64 bit JVMs • Tune the JVM for multi-core platforms The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 5 Course Overview: What to Expect • Master Java™ SE performance monitoring by learning: > What and where to performance monitor > What to profile and what tools work the best for different use cases > Commonly observed patterns indicating performance issues > How Java™ HotSpot garbage collectors work and how to tune them > What you need to know about the JIT compiler > What is JVM ergonomics and how it works > What you need to know about 64-bit JVMs > How to tune the JVM for specific hardware platforms The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 6 Course Overview: What to Expect • In short, learn the basics of the JVM internals and learn enough about Java™ SE performance to know where to start and what to look for, to enable you to identify and resolve most of the JVM and Java™ performance issues you observe. The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 7 Course Overview: The Nature of Performance Tuning • Performance tuning is largely an art. • There is no one approach that is always necessarily the right approach. • There are performance issues which will require very specialized expertise to identify the root cause, and / or be able to recommend a solution. The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 8 Course Module Outlines ● Module 1: Examining Performance Tuning > Distinguishing between monitoring, profiling and tuning > Incorporating monitoring, profiling and tuning into the application development life cycle ● Module 2: Monitoring the OS Layer > Monitoring CPU utilization > Monitoring network performance > Monitoring disk input output (I/O) > Monitoring memory utilization > Monitoring process behavior The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 9 Course Module Outlines • Module 3: Monitoring the JVM and Application Layers > Examining generational collector architectures > Monitoring GC > Monitoring the JVM > Monitoring the application • Module 4: Profiling the OS, JVM and Application Layers > Examining profiling tools > Profiling CPU usage > Profiling the heap and memory usage > Detecting lock contention The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 10 Course Module Outlines • Module 5: Tuning GC > Tuning collector generation sizes > Selecting the collector that best fits application characteristics and requirements > Examining practices that negatively impact GC performance • Module 6: Examining and Managing the JIT compiler > Examining choices of JIT compilers > Tuning the JIT compiler > Creating micro benchmarks The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 11 Course Module Outlines • Module 7: Examining Ergonomics > Examining JVM ergonomics behavior • Module 8: Using 64 bit JVMs > Examine the issues associated with using 64 bit JVMs > Identify application characteristics that suit 64 bit JVMs > Tuning 64 bit JVM for different application requirements • Module 9: Optimize the JVM for Multi-core platforms > Examining JVM features that can leverage multi-core architectures > Optimize the JVM for various multi-core architectures > Tuning the JVM for the Sun Fire™ T1000/T2000 platform The Java™ SE Performance Tuning Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. Revision A 12 Module 1: Examining Performance Tuning SEM-DTJ-380-LA Objectives
Load more

Recommended publications
  • Oracle® Developer Studio 12.6
    ® Oracle Developer Studio 12.6: C++ User's Guide Part No: E77789 July 2017 Oracle Developer Studio 12.6: C++ User's Guide Part No: E77789 Copyright © 2017, Oracle and/or its affiliates. All rights reserved. This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws. Except as expressly permitted in your license agreement or allowed by law, you may not use, copy, reproduce, translate, broadcast, modify, license, transmit, distribute, exhibit, perform, publish, or display any part, in any form, or by any means. Reverse engineering, disassembly, or decompilation of this software, unless required by law for interoperability, is prohibited. The information contained herein is subject to change without notice and is not warranted to be error-free. If you find any errors, please report them to us in writing. If this is software or related documentation that is delivered to the U.S. Government or anyone licensing it on behalf of the U.S. Government, then the following notice is applicable: U.S. GOVERNMENT END USERS: Oracle programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, delivered to U.S. Government end users are "commercial computer software" pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations. As such, use, duplication, disclosure, modification, and adaptation of the programs, including any operating system, integrated software, any programs installed on the hardware, and/or documentation, shall be subject to license terms and license restrictions applicable to the programs.
    [Show full text]
  • Debugging Multicore & Shared- Memory Embedded Systems
    Debugging Multicore & Shared- Memory Embedded Systems Classes 249 & 269 2007 edition Jakob Engblom, PhD Virtutech [email protected] 1 Scope & Context of This Talk z Multiprocessor revolution z Programming multicore z (In)determinism z Error sources z Debugging techniques 2 Scope and Context of This Talk z Some material specific to shared-memory symmetric multiprocessors and multicore designs – There are lots of problems particular to this z But most concepts are general to almost any parallel application – The problem is really with parallelism and concurrency rather than a particular design choice 3 Introduction & Background Multiprocessing: what, why, and when? 4 The Multicore Revolution is Here! z The imminent event of parallel computers with many processors taking over from single processors has been declared before... z This time it is for real. Why? z More instruction-level parallelism hard to find – Very complex designs needed for small gain – Thread-level parallelism appears live and well z Clock frequency scaling is slowing drastically – Too much power and heat when pushing envelope z Cannot communicate across chip fast enough – Better to design small local units with short paths z Effective use of billions of transistors – Easier to reuse a basic unit many times z Potential for very easy scaling – Just keep adding processors/cores for higher (peak) performance 5 Parallel Processing z John Hennessy, interviewed in the ACM Queue sees the following eras of computer architecture evolution: 1. Initial efforts and early designs. 1940. ENIAC, Zuse, Manchester, etc. 2. Instruction-Set Architecture. Mid-1960s. Starting with the IBM System/360 with multiple machines with the same compatible instruction set 3.
    [Show full text]
  • Day 2, 1640: Leveraging Opensparc
    Leveraging OpenSPARC ESA Round Table 2006 on Next Generation Microprocessors for Space Applications G.Furano, L.Messina – TEC-EDD OpenSPARC T1 • The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC architecture 2005 specification and executes the full SPARC V9 instruction set. Sun has produced two previous multicore processors: UltraSPARC IV and UltraSPARC IV+, but UltraSPARC T1 is its first microprocessor that is both multicore and multithreaded. • The processor is available with 4, 6 or 8 CPU cores, each core able to handle four threads. Thus the processor is capable of processing up to 32 threads concurrently. • Designed to lower the energy consumption of server computers, the 8-cores CPU uses typically 72 W of power at 1.2 GHz. G.Furano, L.Messina – TEC-EDD 72W … 1.2 GHz … 90nm … • Is a cutting edge design, targeted for high-end servers. • NOT FOR SPACE USE • But, let’s see which are the potential spin-in … G.Furano, L.Messina – TEC-EDD Why OPEN ? On March 21, 2006, Sun made the UltraSPARC T1 processor design available under the GNU General Public License. The published information includes: • Verilog source code of the UltraSPARC T1 design, including verification suite and simulation models • ISA specification (UltraSPARC Architecture 2005) • The Solaris 10 OS simulation images • Diagnostics tests for OpenSPARC T1 • Scripts, open source and Sun internal tools needed to simulate the design and to do synthesis of the design • Scripts and documentation to help with FPGA implementation
    [Show full text]
  • Sun Ultratm 25 Workstation & Sun Ultra 45 Workstation Just the Facts
    Sun UltraTM 25 Workstation & Sun Ultra 45 Workstation Just the Facts SunWIN Token# 473547 SunWIN Token# 460409 Copyrights © 2006 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Ultra, Sun Blade, Java, Solaris, Java, NetBeans, Sun Fire, Sun StorEdge, SunLink, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunSolve, SunPCi, and SunVTS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. Ultra 25/45 JTF - 12/10/07 Sun Confidential – Internal Use Only 2 Table of Contents Positioning.....................................................................................................................................................................4 Introduction...............................................................................................................................................................4 Product Family Placement .......................................................................................................................................5 Sun Ultra 45 vs Sun Ultra 25 Workstation...............................................................................................................5
    [Show full text]
  • Performance Analysis of Multiple Threads/Cores Using the Ultrasparc T1
    Performance Analysis of Multiple Threads/Cores Using the UltraSPARC T1 Dimitris Kaseridis and Lizy K. John Department of Electrical and Computer Engineering The University of Texas at Austin {kaseridi, ljohn}@ece.utexas.edu Abstract- By including multiple cores on a single chip, Chip to the Server-on-Chip execution model. Under such an envi- Multiprocessors (CMP) are emerging as promising ways of utiliz- ronment, the diverged execution threads will place dissimilar ing the additional die area that is available due to process scaling demands on the shared resources of the system and therefore, at smaller semiconductor feature-size technologies. However, due to resource contention, compete against each other. Con- such an execution environment with multiple hardware context sequently, such competition could result in severe destructive threads on each individual core, that is able to execute multiple threads of the same or different workloads, significantly diverges interference between the concurrently executing threads. Such from the typical, well studied, uniprocessor model and introduces behavior is non-deterministic since the execution of each a high level of non-determinism. There are not enough studies to thread significantly depends on the behavior of the rest of the analyze the performance impact of the contention of shared re- simultaneously executing applications, especially for the case sources of a processor due to multiple executing threads. We of CMP where multiple processes run on each individual core. demonstrate the existence destructive interference on Chip Mul- So far, many researchers have recognized the need of tiprocessing (CMP) architectures using both a multiprogrammed Quality of Service (QoS) that both the software [6] and hard- and a multithreaded workload, on a real, Chip Multi-Threaded ware stack [7-10] has to provide to each individual thread in (CMT) system, the UltraSPARC T1 (Niagara).
    [Show full text]
  • Sparc Enterprise T5440 Server Architecture
    SPARC ENTERPRISE T5440 SERVER ARCHITECTURE Unleashing UltraSPARC T2 Plus Processors with Innovative Multi-core Multi-thread Technology White Paper July 2009 TABLE OF CONTENTS THE ULTRASPARC T2 PLUS PROCESSOR 0 THE WORLD'S FIRST MASSIVELY THREADED SYSTEM ON A CHIP (SOC) 0 TAKING CHIP MULTITHREADED DESIGN TO THE NEXT LEVEL 1 ULTRASPARC T2 PLUS PROCESSOR ARCHITECTURE 3 SERVER ARCHITECTURE 8 SYSTEM-LEVEL ARCHITECTURE 8 CHASSIS DESIGN INNOVATIONS 13 ENTERPRISE-CLASS MANAGEMENT AND SOFTWARE 19 SYSTEM MANAGEMENT TECHNOLOGY 19 SCALABILITY AND SUPPORT FOR INNOVATIVE MULTITHREADING TECHNOLOGY21 CONCLUSION 28 0 The UltraSPARC T2 Plus Processors Chapter 1 The UltraSPARC T2 Plus Processors The UltraSPARC T2 and UltraSPARC T2 Plus processors are the industry’s first system on a chip (SoC), supplying the most cores and threads of any general-purpose processor available, and integrating all key system functions. The World's First Massively Threaded System on a Chip (SoC) The UltraSPARC T2 Plus processor eliminates the need for expensive custom hardware and software development by integrating computing, security, and I/O on to a single chip. Binary compatible with earlier UltraSPARC processors, no other processor delivers so much performance in so little space and with such small power requirements letting organizations rapidly scale the delivery of new network services with maximum efficiency and predictability. The UltraSPARC T2 Plus processor is shown in Figure 1. Figure 1. The UltraSPARC T2 Plus processor with CoolThreads technology 1 The UltraSPARC
    [Show full text]
  • Opensparc – an Open Platform for Hardware Reliability Experimentation
    OpenSPARC – An Open Platform for Hardware Reliability Experimentation Ishwar Parulkar and Alan Wood Sun Microsystems, Inc. James C. Hoe and Babak Falsafi Carnegie Mellon University Sarita V. Adve and Josep Torrellas University of Illinois at Urbana- Champaign Subhasish Mitra Stanford University IEEE SELSE 4 - March 26, 2008 www.OpenSPARC.net Outline 1.Chip Multi-threading (CMT) 2.OpenSPARC T2 and T1 processors 3.Reliability in OpenSPARC processors 4.What is available in OpenSPARC 5.Current university research using OpenSPARC 6.Future research directions IEEE SELSE 4 – March 26, 2008 2 www.OpenSPARC.net World's First 64-bit Open Source Microprocessor OpenSPARC.net Governed by GPLv2 Complete processor architecture & implementation Register Transfer Level (RTL) Hypervisor API Verification suite and architectural models Simulation model for operating system bringup on s/w IEEE SELSE 4 – March 26, 2008 3 www.OpenSPARC.net Chip Multithreading (CMT) Instruction- Low Low Low Medium Low High level Parallelism Thread-level Parallelism High High High High High Instruction/Data Large Large Medium Large Large Working Set Data Sharing Low Medium High Medium High Medium IEEE SELSE 4 – March 26, 2008 4 www.OpenSPARC.net Memory Bottleneck Relative Performance 10000 CPU Frequency DRAM Speeds 1000 2 Years 100 Every Gap 2x -- CPU 6 10 -- 2x Every DRAM Years 1 1980 1985 1990 1995 2000 2005 Source: Sun World Wide Analyst Conference Feb. 25, 2003 IEEE SELSE 4 – March 26, 2008 5 www.OpenSPARC.net Single Threading HURRY Up to 85% Cycles Waiting for Memory
    [Show full text]
  • Sun Fire X4170, X4270, and X4275 Server Architectures
    SUN FIRE™ X4170, X4270, AND X4275 SERVER ARCHITECTURE Optimizing Performance, Density, and Expandability to Maximize Datacenter Value White Paper April 2009 Abstract In compact 1U and 2U form factors, the Sun Fire X4170, X4270, and X4275 servers combine the power of a new generation of Intel Xeon processors with Sun’s system engineering expertise. Based on Sun’s Open Network System design approach, these servers offer the needed performance, density, and expandability to satisfy demanding datacenter applications, especially for virtualization and consolidation initiatives. This white paper describes the architecture of the Sun Fire X4170, X4270, and X4275 servers, including the processor technology, I/O subsystem, built-in system management features, and range of supported operating systems. Sun Microsystems, Inc. This Page Intentionally Left Blank Sun Microsystems, Inc. Table of Contents Executive Summary . 1 Managing Capacity and Complexity . 2 Introducing the Sun Fire™ X4170, X4270, and X4275 servers . 2 Comparing the Sun Fire X4170, X4270, and X4275 servers . 4 A choice of operating systems . 6 The Intel Advantage . 7 New Intel Core Microarchitecture. 7 Modular architecture . 10 Power management technologies . 10 Intel Xeon Processor 5500 platform . 11 Sun Fire X4170, X4270, and X4275 Server Architectures . 12 Sun Fire X4170 system-level architecture . 12 Sun Fire X4170 server overview. 13 Sun Fire X4170 server enclosure . 14 Sun Fire X4170 server front and rear perspectives . 14 Sun Fire X4270 system-level architecture . 16 Sun Fire X4270 server overview. 17 Sun Fire X4270 server enclosure . 17 Sun Fire X4270 server front and rear perspectives . 18 Sun Fire X4275 system-level architecture . 19 Sun Fire X4275 server overview.
    [Show full text]
  • Sun Fire X2100 M2 and X2200 M2 Server Architecture
    SUN FIRE™ X2100 M2 AND X2200 M2 SERVER ARCHITECTURE Scalable, Compact, and Efficient Systems Based on Powerful Dual-Core and Quad-Core AMD Opteron™ Processors White Paper April 2008 Sun Microsystems, Inc. Table of Contents Executive Summary . 1 Scalable Computing without Complexity . 2 Meeting Modern Enterprise Needs . 4 Raising Expectations for Entry-Level Servers . 4 Maximizing Solution Longevity. 5 AMD Opteron™ Processor Technology . 6 Second-Generation Dual-Core AMD Opteron Processors . 6 Third-Generation Quad-Core AMD Opteron Processors . 8 High-Bandwidth I/O for High Performance Computing . 11 AMD Virtualization Technology. 12 Processor Design for Energy Efficiency . 13 Sun Fire X2100 M2 and X2200 M2 Server Architecture . 16 Motherboard. 16 Memory Architecture . 18 PCI Express Expansion. 19 Disk Drive and Hardware RAID . 19 Networking and I/O . 19 Enclosure and Rackmount. 21 Power and Cooling . 21 Specifications and Compliance . 22 System Management . 23 Embedded Service Processor — Out of Band System Management . 23 In-Band System Management. 25 Sun xVM Ops Manager Software . 25 A Universal Computing Platform. 26 A Choice of Operating Systems . 27 The Solaris™ Operating System . 27 Linux Environments . 29 Microsoft Windows Environments . 29 VMware. 29 Conclusion . 31 For More Information . 32 1 Executive Summary Sun Microsystems, Inc. Executive Summary IT organizations are under constant pressure to improve operations and lower costs. Many IT managers strive to gain efficiencies by standardizing platforms and procedures. Unfortunately, these efforts can stall as datacenters are often stocked with a mix of new 64-bit applications and a large inventory of legacy 32-bit code — requiring a variety of different chip architectures and operating environments for execution.
    [Show full text]
  • Ultrasparc T1 Sparc History Sun + Sparc = Ultrasparc
    ULTRASPARC T1 SUN + SPARC = ULTRASPARC THE PROCESSOR FORMERLY KNOWN AS “NIAGARA” Processor Cores Threads/Core Clock L1D L1I L2 Cache UltraSPARC IIi 1 1 550Mhz, 650Mhz 16KiB 16KiB 512KiB UltraSPARC IIIi 1 1 1.593Ghz I D 1MBa UltraSPARC III 1 1 1.05-1.2GHz 64KiB 32KiB 8MiBb UltraSPARC IV 2c 1 1.05-1.35Ghz 64KiB 32KiB 16MiBd UltraSPARC IV+ 1 2 1.5Ghz I D 2MiBe UltraSPARC T1 8 4 1.2Ghz 32KiB 16KiBf 3MiBg UltraSPARC T2h 16 (?) 8 2Ghz+ (?) ? ? ? Slide 1 Slide 3 aOn-chip bExternal, on chip tags cUltraSPARC III cores d8MiB per core e32MiB off chip L3 fI/D Cache per core g4 way banked hSecond-half 2007 This work supported by UNSW and HP through the Gelato Federation SPARC HISTORY INSTRUCTION SET ➜ Scalable Processor ARCHitecture ➜ RISC! ➜ 1985 – Sun Microsystems ➜ Berkeley RISC – 1980-1984 ➜ Load–store only through registers ➜ MIPS – 1981-1984 ➜ Fixed size instructions (32 bits) ➜ register + register Slide 2 Architecture v Implementation: Slide 4 ➜ register + 13 bit immediate ➜ SPARC Architecture ➜ Branch delay slot ➜ SPARC V7 – 1986 X Condition Codes ➜ SPARC Interntaional, Ltd – 1989 V (V9) CC and non-CC instructions ➜ SPARC V8 – 1990 V (V9) Compare on integer registers ➜ SPARC V9 – 1994 ➜ Synthesised instructions ➜ Privileged v Non-Privileged SUN + SPARC = ULTRASPARC 1 CODE EXAMPLE 2 CODE EXAMPLE V9 REGISTER WINDOWS void addr(void) { int i = 0xdeadbeef; } 00000054 <addr>: Slide 5 54: 9d e3 bf 90 save %sp, -112, %sp Slide 7 58: 03 37 ab 6f sethi %hi(0xdeadbc00), %g1 5c: 82 10 62 ef or %g1, 0x2ef, %g1 60: c2 27 bf f4 st %g1, [ %fp + -12 ] 64:
    [Show full text]
  • Table of Contents
    1 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Safe Harbor Statement The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle. 2 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Eine phatastische Reise ins Innere der Hardware Franz Haberhauer Stefan Hinker Oracle Hardware in 3D 5 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5 and M5 PCIe Carrier Card . Supports standard low-profile PCIe cards Air Flow PCIe Retimer x16 Connector (x8 electrical) 6 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. PCIe Data Paths: Full System . Two root complexes per T5 processor . Each PCIe port on a T5 processor controls a single PCIe slot 7 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5-2 Block Diagram DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB T5-0 T5-1 CPU CPU TPM Host & CPU PCIe Debug CPU PCIe Debug Data Flash DC/DCs 0 1 Port DC/DCs 0 1 Port x8 x8 FPGA x8 x4 x8 x1 HDD0 DBG SAS/SATA x1 HDD0 IO Controller x4 x4 PCIe PCIe SP Module HDD0 get rid of all inside x8 x8 SAS/SATA smallSwitch boxes 0 Switch 1 FRUID HDD0 IO Controller Sideband Mgmt DRAM HDD0 USB 1.1 Keyboard Mouse Service SPI x8 USB 3.0 x8 USB 2.0 Storage Flash HDD0 Host Processor SATA DVD NAND USB 2.0 Hub USB USB 3.0 USB Internal USB Hub VGA VGA REAR IO Board USB2 USB3 VGA USB0 USB1 VGA Serial Enet Quad 10Gig Enet DB15 Mgmt Mgmt Slot 2 (8) 2 Slot (8) 3 Slot (8) 4 Slot (8) 5 Slot (8) 6 Slot (8) 7 Slot (8) 8 Slot Slot 1 (8) 1 Slot 10/100 FAN BOARD REAR IO 8 Copyright © 2013, Oracle and/or its affiliates.
    [Show full text]
  • Sun Fire™ V60x Server and Sun Fire™ V65x Server Just the Facts
    Sun Fire™ V60x Server and Sun Fire™ V65x Server Just the Facts v4.0 — December 2003 (SunWIN token# 375850) Copyright 2003 Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, California 95054, U.S.A. All rights reserved. Sun Microsystems, Inc. has intellectual property rights relating to technology that is described in this document. In particular, and without limitation, these intellectual property rights may include one or more of the U.S. patents listed at http://www.sun.com/patents and one or more additional patents or pending patent applications in the U.S. and in other countries. This document and the product to which it pertains are distributed under licenses restricting their use, copying, distribution and decompilation. No part of the product or of this document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Third-party software, including font technology, is copyrighted and licensed from Sun suppliers. Parts of the product may be derived from Berkeley BSD systems, licensed from the University of California. UNIX is a registered trademark in the United States and in other countries, exclusively licensed through X/Open Company, Ltd. Sun, Sun Microsystems, the Sun logo, Forte, IPX, Java, ONC, Solaris, StarOffice, Sun Fire, Sun StorEdge, SunLink, SunReady, SunSpectrum, SunSpectrum Bronze, SunSpectrum Gold, SunSpectrum Platinum and SunSpectrum Silver are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and in other countries.
    [Show full text]