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Exploration and Analysis of Processor and Memory Architectures For Exploring Processor and Memory Architectures for Multimedia Iranpour, Ali 2012 Link to publication Citation for published version (APA): Iranpour, A. (2012). Exploring Processor and Memory Architectures for Multimedia. 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LUND UNIVERSITY PO Box 117 221 00 Lund +46 46-222 00 00 Exploring Processor and Memory Architectures for Multimedia Ali R. Iranpour Lund 2012 This thesis is submitted to the Board of Research: FIME --- Physics, Informatics, Mathematics and Electrical Engineering --- at Faculty of Engineering, Lund University, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Engineering. ISBN 978-91-976939-6-7 ISSN 1404-1219 Dissertation 38 ,2012 LU-CS-DISS:2012-1 Department of Computer Science Lund University P.O. Box 118 SE-221 00 Lund Sweden Abstract Multimedia has become one of the cornerstones of our 21st century society and, when combined with mobility, has enabled a tremendous evolution of our society. However, joining these two concepts introduces many technical challenges. These range from having sufficient performance for handling multimedia content to having the battery stamina for acceptable mobile usage. When taking a projection of where we are heading, we see these issues becoming ever more challenging by increased mobility as well as advancements in multimedia content, such as introduction of stereoscopic 3D and augmented reality. The increased performance needs for handling multimedia come not only from an ongoing step-up in resolution going from QVGA (320x240) to Full HD (1920x1080) a 27x increase in less than half a decade. On top of this, there is also codec evolution (MPEG-2 to H.264 AVC) that adds to the computational load increase. To meet these performance challenges there has been processing and memory architecture advances (SIMD, out-of-order superscalarity, multicore processing and heterogeneous multilevel memories) in the mobile domain, in conjunction with ever increasing operating frequencies (200MHz to 2GHz) and on-chip memory sizes (128KB to 2-3MB). At the same time there is an increase in requirements for mobility, placing higher demands on battery-powered systems despite the steady increase in battery capacity (500 to 2000mAh). This leaves negative net result in- terms of battery capacity versus performance advances. In order to make optimal use of these architectural advances and to meet the power limitations in mobile systems, there is a need for taking an overall approach on how to best utilize these systems. The right trade-off between performance and power is crucial. On top of these constraints, the flexibility aspects of the system need to be addressed. All this makes it very important to reach the right architectural balance in the system. The first goal for this thesis is to examine multimedia applications and propose a flexible solution that can meet the architectural requirements in a mobile system. Secondly, propose an automated methodology of optimally mapping multimedia data and instructions to a heterogeneous multilevel memory subsystem. The proposed methodology uses constraint programming for solving a multidimensional optimization problem. Results from this work indicate that using today’s most advanced mobile processor technology together with a multi-level heterogeneous on-chip memory subsystem can meet the performance requirements for handling multimedia. By utilizing the automated optimal memory mapping method presented in this thesis lower total power consumption can be achieved, whilst performance for multimedia applications is improved, by employing enhanced memory management. This is achieved through reduced external accesses and better reuse of memory objects. This automatic method shows high accuracy, up to 90%, for predicting multimedia memory accesses for a given architecture. iii iv Contents v Contents Abstract ........................................................................................................................ iii Contents ......................................................................................................................... v Preface .......................................................................................................................... ix Acknowledgements ...................................................................................................... xi 1 Introduction ............................................................................................................. 15 1.1 Background .................................................................................................... 15 1.2 Motivation ...................................................................................................... 18 1.3 Structure of the thesis ..................................................................................... 20 2 Challenges with Multimedia Applications in Embedded Systems ....................... 21 2.1 Embedded Architectures for Video and Audio .............................................. 21 2.2 Multimedia Processing ................................................................................... 22 2.3 Multimedia Memory ....................................................................................... 34 3 Related work ............................................................................................................ 39 3.1 Processing ....................................................................................................... 39 3.2 Memory .......................................................................................................... 43 4 Papers Survey .......................................................................................................... 47 5 Contributions ........................................................................................................... 51 6 Conclusions and Future Trends ............................................................................. 53 7 Bibliography ............................................................................................................. 57 8 Included Papers ....................................................................................................... 67 1 Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4 ...................................................................................................................... 69 1.1 Introduction .................................................................................................... 70 1.2 Media applications impact on embedded architectures .................................. 71 1.3 Baseline architecture ...................................................................................... 72 vi Contents 1.4 Methodology .................................................................................................. 75 1.5 Experiments and Discussion ........................................................................... 77 1.6 Related work .................................................................................................. 83 1.7 Conclusions and future work .......................................................................... 84 References ................................................................................................................ 84 2 Analysis of Embedded Processors for Streaming Media Applications ............... 87 2.1 Introduction .................................................................................................... 88 2.2 ARM Architecture .......................................................................................... 90 2.3 MPEG-4 Application ...................................................................................... 92 2.4 Methodology .................................................................................................. 92 2.5 Experimental Results ...................................................................................... 94 2.6 Discussion of the Results................................................................................ 99 2.7 Conclusion .................................................................................................... 100 References .............................................................................................................. 100 3 Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors .................................................................................................................
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