Emmanuel S. Yakubu, M.S. December, 2020 PHYSICS

MODELING AND FABRICATION OF AN DISPLAY (0 pp.)

Director of Dissertation:

In this thesis, the use of a specific type of Thin-Film (TFT), namely

Organic Field Effect Transistor (OFET), in a single-pixel circuit to produce a flexible display is studied. The goal is to characterize and optimize organic thin-film tran- sistors in an Active-Matrix Organic -Emitting (AM-OLED) single-pixel circuit in order to get an optimized setup of a Flat-Panel Display (FPD). We use LT

Simulation Program with Emphasis (LT-Spice) to simulate the driving circuit of an individual pixel to find target values of mobility and resistance.

Finally, a small 2x2 pixel array based on the data produced from the simulation is produced as first step toward a full-size flat panel operation. MODELING AND FABRICATION OF AN ACTIVE MATRIX DISPLAY

A dissertation submitted to

Kent State University in partial

fulfillment of the requirements for the

degree of Doctor of Philosophy

by

Emmanuel S. Yakubu

December, 2020

c Copyright

All rights reserved

Except for previously published materials Dissertation written by

Emmanuel S. Yakubu

Approved by

Dr. Bj¨orn L¨ussem , Advisor

Dr. James T. Gleeson , Chair, Department of Physics

Dr. Mandy Munro-Stasiuk , Interim Dean, College of Arts and Sciences TABLE OF CONTENTS

TABLE OF CONTENTS ...... iv

LIST OF FIGURES ...... vi

LIST OF TABLES ...... viii

1 Introduction ...... 1

2 Background ...... 4

2.1 Organic Field Effect Transistor (OFET) ...... 4

2.2 Organic Light Emitting Diode (OLED) ...... 8

2.3 Influence of Mobility µ ...... 9

2.4 Acknowledging Contact Resistance Rc ...... 13

2.5 Flat-Panel Display ...... 15

2.5.1 Passive Matrix ...... 15

2.5.2 Active Matrix ...... 18

3 SPICE Simulations ...... 22

3.1 Description of Simulation Model ...... 22

3.2 Influence of the Mobility, Resistance, and Capacitance ...... 23

iv 4 Standard OFET ...... 30

4.1 Structure of Device ...... 30

4.2 Results ...... 31

5 OFET in a Backplane ...... 36

5.1 Modelling ...... 36

5.2 Results ...... 36

6 Conclusion ...... 42

6.1 Outline ...... 42

v LIST OF FIGURES

2.1 Illustration of an electrolyte gated organic field-effect transistor with

pdEthAA deposited on P3HT layer [3]...... 5

2.2 Standard Structure of OFET [17]...... 5

2.3 Output Characteristic denoting the Linear and Saturation regions of

a Transistor ...... 7

2.4 Structure of a typical OLED ...... 9

2.5 Operation framework of OLED ...... 10

2.6 Active Matrix (left) and Passive Matrix (right) Addressing [18]. . . . 16

2.7 Example of an AM-OLED Single-Pixel Circuit [9] ...... 21

3.1 AM-OLED Single-pixel Simulation Schematic ...... 24

3.2 LT-Spice syntax for AM-OLED FPD simulation ...... 24

3.3 Voltage Pulse at Gate of Switching Transistor (Top, V(vg1)), Current

driven into OLED (mid, I(D1)), and Voltage Pulse at Gate of Driving

Transistor (bottom, V(vg2)) ...... 25

3.4 Voltage Pulse at Gate of Driving Transistor with varying Resistance . 27

3.5 Voltage Pulse at Gate of Driving Transistor with varying Mobility . . 28

3.6 Voltage Pulse at Gate of Driving Transistor with varying Capacitance 29

4.1 Lateral view of OFET ...... 30

4.2 Fabricated OFET with the highlighted Drain-Source-Gate electrodes 32

vi 4.3 Voltage Transfer Characteristic of OFET ...... 33

4.4 Error Plots for Mobility between Au and doped P5 ...... 34

4.5 Error Plots for Threshold Voltage between Au and doped C60 . . . . 35

4.6 Error Plots for Hysteresis between Au and Al ...... 35

5.1 Shadow Masks ...... 37

5.2 Resulting Substrate ...... 38

5.3 Voltage Characteristic of Backplane OTFT ...... 39

5.4 Linear fit of The Square Root of the Drain Current ...... 40

5.5 Fabricated transistor vs. Mask plan ...... 41

vii LIST OF TABLES

3.1 Varied Resistance and KP and Their Respective Time Constants . . . 26

viii CHAPTER 1

Introduction

Semiconductors and their devices have served as integral components of circuitry found in almost all electrical devices today. Ever since 1874, when Ferdinand Braun

firstly discovered the rectification properties of a point contact on the lead sulfide, our reliance on and its devices has grown exponentially.

Semiconductors originally existed as solely inorganic. The semiconductor layer is typically (crystalline silicon being the most prominent form of silicon in tran- sistors) with transparent oxides due to their bandgaps being greater than 3eV [25].

Mobility, being the most important factor to focus on, can be improved by control- ling the morphology of the semiconductor from either amorphous, nanocrystalline, microcrystalline, polycrystalline, to single crystalline Silicon [25].

Inorganic semiconductors show a very high performance caused by their high charge carrier mobility. Organic semiconductors, however, outperform inorganic de- vices when criteria such as low-cost production and mechanical flexibility are re- quired. Organic semiconductors are currently used in solar cells that pave a way towards renewable energy, Organic Light-Emitting () illuminating the screens of our mobile phones, sets and so on. The focus of this thesis shall be the Organic Field-Effect Transistor (OFET) which has a strong footing in imaging sensor and display electronics [16].

1 The OFET provides benefits such as low-cost manufacturing, flexibility, and tun- ability. Research in this field is very widespread and more advantages of this type of device are being studied.

The application of an OFET for this paper is the operating of flexible displays in backplane electronics. Flexible displays have come a long way too. There are two main types of backplane architecture, namely; direct addressing, which is usually applied in traffic , and matrix addressing which is also divided into two sub- sets named passive matrix and active matrix addressing [9]. Passive matrix (PM) examples include pagers, classic printers, calculators, et cetera. This type of matrix involves the pixels in all rows and columns turning on at once while aligned in an orthogonal orientation (cf. Figure 2.6). PM displays are currently being replaced by active matrix addressing with examples such as: smart watches, television sets, or even the media interface in modern vehicles [9].

The pixels for AM addressing are in a standard row and column arrangement.

In contrast to PM addressing, every pixel is addressed by one or more Thin-film

Transistors (TFT). Unlike the PM, where all pixels are switched on, AM activates the pixels one row at a time in a cyclic sequence (see figure 2.6)[4, 12, 5, 9].

Thin-film have been quintessential to the operation and improvement of flexible displays. Traditionally, the dielectric and semiconductor layers are de- posited on glass substrates, but to achieve flexibility, substrates are usually the way to go [7]. Metal-foil substrates are also recommended for high temperature

2 fabrication processes, which are typically needed to fabricate high performing tran- sistors. Nowadays, flexible displays have more than proven themselves in aspects of low cost manufacturing, mechanical flexibility, and high performance [7, 12].

Contact Resistance, a plague that hinders the performance of semiconductors can arise from numerous instances. Examples of causes may be mishandling of device during fabrication, exposure of sensitive layers to air, misalignment of the metal and the transport layer of the semiconductor, or even just incompatibility between the material layers of the device [20].

The aim of this thesis is to evaluate the use of organic field-effect transistors for active matrix displays. Target performance parameters for OFETs will be derived by a circuit-level SPICE simulations. High-performance OFETs will be processed and the influence of contact resistance will be evaluated to arrive at device properties that will enable an OLED/liquid crystal to produce a lucid display.

3 CHAPTER 2

Background

The OFETs in this thesis are fabricated and characterized to -on (or off) and drive the OLEDs in the active matrix configuration to produce a low cost,

flexible, display.

2.1 Organic Field Effect Transistor (OFET)

OFETs are a fascinating candidate of the organic device family. The intramolec- ular bonds of organic semiconductors are van der Waals weak forces, which allow for low energy and low temperature processing [8].

A metal-oxide-semiconductor consisting of polyacetylene, polysiloxane, aluminum, and gold as the semiconductor, gate dielectric, gate, and source/drain electrodes respectively, as shown in figure 2.1, was first assembled by Ebisawa et al. in 1982[8]. The corresponding transistor operated in depletion mode with a low modulation and transconductance. Regardless, Ebisawa and Nara, working at NTT in 1982 at the time, deemed this new transistor ”promising” [8]. This first report on OFETs was followed up in 1986 by Ando, Tsumura, and Koezuka at Mitsubishi

Chemical [8], which achieved a substantial current boost by an in-situ poylmerized polythiophene transistor.

The source and drain contacts are integral layers of an OFET. The junction

4 Figure 2.1: Illustration of an electrolyte gated organic field-effect transistor with pdEthAA deposited on P3HT layer [3].

Figure 2.2: Standard Structure of OFET [17].

5 between them and the channel can cause a parasitic impedance due to the formation of an energy barrier [8]. This barrier, however, can be minimized when proper materials are chosen that balance the energy levels of the semiconductor with the work function of the metal of the source/drain electrodes [8].

The operational basis of FETs illustrated in 2.2 involve channelling a current from source to drain. The charge transport mechanism dictate if the OFET is a n-type ( charge transport) or p-type (holes) device. Given that it is p-type, a negative voltage bias will be applied to the gate, hence creating a depletion region across the channel enabling charge transport from source to drain via the organic layer [8].

When the gate-source voltage is greater than the threshold voltage (VGS > VT ), there is charge accumulation at interface between the insulator and semiconductor.

This accumulation forms a conductive channel, and if a potential is applied between drain and source (the drain-source potential VDS), a current ID starts to flow from drain to source. [1, 5, 7, 23].

Figure 2.3 shows a sample output characteristic of an OFET. It is illustrated that the OFET can be operated in two regimes, namely; the linear regime, in which the drain current ID is directly proportional to the drain source potential VDS, and the saturation regime, where the drain current saturates in the interface of the contacts and channel layer.

6 Figure 2.3: Output Characteristic denoting the Linear and Saturation regions of a Transistor

• At VDS < VGS − VT , the OFET is operating in the linear region with ID:

W  1  W I = C µ (V − V )V − V 2 ≈ C µ (V − V )V (2.1) D i FE L GS T DS 2 DS i FE L GS T DS

Where Ci: gate capacitance; µFE: field-effect mobility; W/L: channel width/length.

• At VDS > VGS − VT , the device is said to be operating in the saturation region

with ID independent of VDS. ID is given by:

1 W I = C µ (V − V )2 (2.2) D 2 i sat L GS T

where µsat is the saturation mobility.

7 2.2 Organic Light Emitting Diode (OLED)

OLEDs are technological marvels that operate on the basis of .

Electroluminescence occurs when recombine with holes inside the emissive layer of the diode [11]. The structure involves a series of thin films made up of organic semiconductors. In the off state, these curious devices can be transparent, diffusing, or mirrored [11].

OLEDs are currently the best contenders when it comes to large-area lighting and flat-panel display applications due to their potentiality for high-contrast, fast response, wide-view-angle, and low-power operation [11]. The first double-layer diode consisting of separate hole and electron transport layers was made in 1987 and investigated by Steven Van Syke and Ching W. Tang. The structure enabled recombination and light emission in the middle of the organic layer which allowed for low operation voltages [11].

Referencing figure 2.4 and 2.5, we can see the working mechanism of a typical

OLED. The presence of the enables electron transport through the ETL to the emissive layer. The same happens with holes which move from the , across the HIL, HTL and finally, to the emissive layer where electron-hole recombination and hence electroluminescence occurs. The thickness of each organic layer ranges from 100nm to 200nm. When an electric field is applied, electron injection occurs at the lowest unoccupied molecular orbit (LUMO) and holes at the highest occupied molecular orbit (HOMO) forming triplet or singlet when the charge carriers recombine on the emitter molecule in the emissive layer [11].

8 Figure 2.4: Structure of a typical OLED

A multi-layer OLED comes with unique device operation function per layer. In

figure 2.4 the initial layer is the glass substrate (can be substituted with plastic foil), next is the transparent anode (ITO), hole transport layer (HTL), electron blocking layer (EBL), emissive layer, hole-blocking layer (HBL), ETL and cathode with the charge transport and luminescence mechanism illustrated in figure 2.5 [11].

2.3 Influence of Mobility µ

Mobility is a property that is quintessential to the operation of semiconductor devices. It is the ratio of the charge carrier velocity and the applied electric field.

The force of the applied field cause the carriers to speed up until the momentum is dissipated in scattering events [8]. The relationship between the velocity on the applied field is assumed to be linear. The mobility with units cm2V −1s−1, can hence be defined by [8]:

9 Figure 2.5: Operation framework of OLED

v µ = (2.3) E

where v: velocity; E: applied electric field.

The current flow in the semiconductor layer of the device is defined as the charge per volume at unit speed of the charge transport. A layer with density per area

(Q(Ccm−2)) and width W , will yield a current [8]:

Charge I = (2.4) t = QW µE (2.5)

This model works for low fields because of the linear dependency between velocity and electric field. The relationship becomes non-linear at high fields. In OFETs

10 specifically, the mobility is not necessarily constant when the device is operating in the linear regime. The activity in that regime occurs when IDS is not constant.

Significant difference in layer thickness, alignment, and even deposition can affect the magnitude of mobility and hence techniques have been developed in order to characterize the value and any other factor that will influence it. Alternating single and multiple bonds resulting in π-orbitals compose the molecular structure of any . The delocalized π-electrons contribute to charge transport

[1]. The conductivity of this transport mechanism is:

σc = neµ (2.6)

Where σc: conductivity; n: no. of charge carriers; e: charge of electron; µ: charge carrier mobility.

The methods used to measure the charge mobility include :

1. The method of Space-Charge-Limited-Currents or SCLC can be used to mea-

sure the mobility in thin films with thicknesses of roughly 200nm to 2µm. The

two types of this technique are the Dark Injection and Trap Free SCLC [1].

2. Impedance Spectroscopy has the same requirements as the SCLC but instead

of a constant voltage, a DC and minor AC signal are applied to the device.

This technique is often employed to observe charge transport and relaxation

mechanism associated with solid state devices.

3. Time of Flight (TOF) works best at thickness of > 1µm. Transparent and

11 semi-transparent electrodes are needed as well, whilst the data extracted from

the transient is supposed to be plotted on a double logarithmic scale.

4. Double Injection (DoI) works best when driven by a forward bias pulse on a

device with two charge injection contacts. DoI does a good job in highlighting

the influence of electric field as well as temperature. The positive pulse on the

device activates both p and n type charge transport mechanisms while all the

readings are collected via oscilloscope [1].

5. Carrier Extraction by Linearly Increasing Voltage or CELIV supports both p

and n-type carrier mechanisms but it depends on the Photogenerated-CELIV

(or Photo-CELIV) to identify holes from electrons in the osc layer.

6. This final method of characterization is the primary method used for this pa-

per. Field-Effect Transistors (FETs) (technique is named after device) drive

with ohmic contacts composed of the source (grounded) and drain electrodes.

The current injected at the source is guided by the gate via capacitive cou-

pling of the dielectric before collected at the drain. This method highlights

two operation regions of the device which are namely; ohmic (or linear) and

saturation regimes. Both regimes themselves can be used to characterize ei-

ther the Output Characteristics (IDS vs. VDS at constant VGS) or the Voltage

Transfer (IDS vs. VGS at constant VDS). [Formulae shown for linear, 2.1 and

saturation, 2.2 respectively]. The slope of the voltage transfer characteristics

12 can be used to find charge carrier mobility [1]:

δIDS W = µCsVDS (2.7) δVGS L

These techniques are applied to a variety of semiconductor devices in order to accommodate the reading of influential parameters. For more insight on these tech- niques, Ref [1] discusses them in greater detail.

2.4 Acknowledging Contact Resistance Rc

Through the years, the phenomenon known as contact resistance has been studied and techniques to reduce its influence on device performance have been developed.

The late 90s saw an average with magnitudes of 104 Ωcm. Today we see average values of contact resistances from 10 to 102 Ωcm [20].

Contact resistances Rc stem from potential barriers that hinder injection of charge carriers at the source or drain electrodes which leads to inaccurate measurement of device parameters. OFETs operate in two regimes; linear and saturated which can be disrupted during measurement due to contact resistance [20].

For our device to operate at peak performance, both the metal work function and electron affinity both need to be at the same level. The Schottky barrier φB is the energy difference between the work function φM of the electrode material and electron affinity of the organic semiconductor in a transistor. If the magnitude of the barrier is low, charge transport would be relatively high and vice versa [20].

13 Depending on the desired charge carrier, the barrier may exist between the work function of the metal and either the Highest Order Molecular Orbit (HOMO) or the

Lowest Unoccupied Molecular Orbit (LUMO) of the semiconductor. The respective energy bands dictate the dominant charge carrier of the layer. The injection mech- anism of the HOMO are holes and for the LUMO are electrons. Their respective devices are the p-type and n-type [20][2].

The considerations to look at when modifying the Schottky barrier according to Ref [20] are the geometry of the device, interface and bulk contributions, and

finally influence of the gate dielectric layer. If the gate dielectric is too thin, the device will short circuit, too thick and we risk adding to the contact resistance. The material taken into consideration is also very important. Ref [20] provides extensive knowledge on the matter as well as more sources for experimentally proven research pertaining to the characterization and control of contact resistance.

Measures taken in the fabrication to alleviate the weight of contact resistance include the thickness of the organic semiconductor (osc) layer. Too thin and there will be little to no charge conduction, too thick and we risk losing the contribution of vertical conduction and trapstate density in the layer. Depending on the level of the conduction band, one would assume it plays a factor in deciding the specific thickness of semiconductor used. Using dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT) for the osc with thickness of 20nm ∼ 50nm. Gold, Fulleren: : 2-(2-Methoxyphenyl)-

1,3-dimethyl-1Hbenzoimidazol-3-ium iodide (C60: o-MeO-DMBI), and

(P5) played the role of the contacts. Gold itself has a metal work function close

14 to the HOMO of DNTT, which are respectively 5.3eV and 5.0eV.

2.5 Flat-Panel Display

Flat-panel displays enable high quality digital images with full colors, maximiza- tion of display size for a given space, and aim to consume as little power as possible.

There are a myriad of different kinds of flat-panel displays, ranging from electronic billboards with 400x1400 pixels to smart watches with an average of 200x180 pixels.

A display consists of independently addressable, uniformly aligned pixels. The most simple type of display uses direct addressing. A calculator is a typical example for direct addressing, where only alphanumeric with limited special characters are displayed. The scheme involves all pixels to be connected to a specific driver. The matrix addressing aligns the pixels in rows and columns with each pixel having leads for both row and column, each in a cell [9][24].

For a more complex display, matrix addressing has to be used. Two types of schemes are possible, which will be further discussed in forthcoming subsections.

2.5.1 Passive Matrix

A passive matrix as shown in Figure 2.6 consists of rows and columns organized orthogonally. A pixel is formed at every crossing of the top and bottom electrode with an electronic switch or electric driver to address each row [4].

For an OLED based display, the pixel brightness is directly proportional to the drive current, which is driven between the top and bottom electrodes. In a passive matrix, only one row can be addressed at a time. Considering that the of

15 Figure 2.6: Active Matrix (left) and Passive Matrix (right) Addressing [18]. the display is kept constant, the display time for each row decreases with increasing number of rows.

In a passive matrix, the pixels only light up when they are addressed. Therefore, the instantaneous luminance needed to reach an average luminance of the display,

Ld, becomes

ML L(0) = d (2.8) rad with d: operation cycle; M: number of rows [4].

The quantity ra is the aperture ratio, i.e. the effective area of the display that emits light which is represented as [4]:

WrWc ra = (2.9) (Wr + Dr)(Wc + Dc)

16 Where Wr: wide row length; Wc: wide column length; Dr: distance between rows;

Dc: distance between columns.

Overall, Equation 2.8 sets the first size limit for passive matrix displays. If the number of rows in the display M becomes too large, the instantaneous luminance of the individual pixel increases to reach an acceptable average display brightness in the

−2 range of Ld = 100 − 200cdm . However, the lifetime of OLEDs drops exponentially with its brightness, severely dropping beyond an instantaneous brightness of L(0) =

1000cdm−2 [15]. Overall, the maximum number of rows that can be installed on a

PM addressing is ∼1000 due to low pixel duty factor.

Additionally, passive Matrix displays are severely limited by cross-talk between pixels. If a pixel at row i and column j is addressed, other pixels in different rows will be reversed-biased. This coupling will drive a leakage current Ileakage through the display. To keep this reverse current small, the display size has to be limited

[4], to lower the power consumption caused by Ileakage and retain a proper brightness control. A detailed analysis by Gu et al[4] shows that the product MNNg is less

7 than ∼ 10 as a result of the limits arising from the leakage current Ileakage (N: no. of columns; Ng: no. of gray levels).

Finally, not only is the number of pixels in a passive matrix display limited, but its physical size has to be kept small to avoid excessive voltage drop along the row and column electrodes. Overall, the display dimensions are below ∼ 1600cm2[4].

The response time τ in a pm display is mainly limited by capacitive charging,

17 and is given by:

A C = (2.10) Z τ = rC, (2.11) where : permitivity of organic layer; Z the thickness of the pixels, and r: output resistance.

In summary, these factors play a role as to why the PM technology is gradu- ally becoming obsolete, making way for active matrix addressing, which can handle displays of very large sizes and brightness.

2.5.2 Active Matrix

Active matrix addressing gives higher resolution and/or larger display size than the PM addressing.

Figure 2.7 illustrates an example of an AM-OLED single-pixel circuit. The format used is referred to as the 2T1C (2-Transistors, 1-Capacitor) pixel architecture [16].

The sequence of addressing the light-emitting diode is as follows:

1. A voltage is supplied through the power line.

2. A row is selected via the . Applying a voltage to the scan line turns

on the switching transistor TFTswitching

3. If the OLED is supposed to be turned on, a high voltage is applied to the data

line. As the switching transistor is on, the voltage on the data line charges up

18 the capacitor [4].

4. The voltage is removed from the scan line, turning the switching transistor

off. However, the charges stored by the capacitor retains the potential at the

gate of the driving transistor Tdriving. Hence, the driving transistor remains on,

driving a current through the OLED, i.e. the OLED turns and remains on.

5. The capacitor will slowly discharge due to leakage currents. Before the dis-

charge causes the voltage at the gate of the driving transistor to drop below

the threshold voltage, which would turn the OLED off, the pixel has to be

refreshed, i.e. the whole addressing cycle has to be restarted.

Several transistor parameters are essential for a correct functioning of this switch- ing mechanism. The On/Off ratio of the switching transistor has to be large in order to avoid a discharge of the pixel capacitor by residual off currents.

W Furthermore, a high mobility, or more precise a large factor µ L is essential for a fast charging of the pixel capacitor. The following relationship has to be satisfied

[16]:

2BApLf µ > 2 (2.12) CipηW (Vg − Vth) where Ci: gate dielectric capacitance; Vg: applied gate voltage; Vth: threshold - age; Ap: pixel area; f: fraction of light (specific color e.g. blue, red) needed to make white light; p: transmission of ; η: OLED efficiency; B: OLED brightness

[16].

19 The active matrix may be the leading display format on the market, but it is not short of pitfalls. The most important challenge for active matrix displays is an instability of the threshold voltage of OFETs under constant gate bias stress or due to varying temperatures.

These downsides can be compensated with more complex circuitry that has more than just two TFTs. The current programming schemes self stabilize the gate-source voltage of the driving transistor by using a current mirroring architecture, and the voltage compensation scheme generates the threshold of the driving device across its source-gate junction before adding to the pixel voltage [16].

Compensation circuits have a dependency on gate-source voltage. The circuit can fail if the drive TFT has a VGS that is so high, it prevents the transistor from working in the saturation region for a specific applied voltage and there will also be a voltage drop across the OLED [16][13].

20 Figure 2.7: Example of an AM-OLED Single-Pixel Circuit [9]

21 CHAPTER 3

SPICE Simulations

The driving sequence of an active matrix display was modelled for the purpose of determining the requirements this circuit puts on the organic transistor and the storage capacitor.

Simulation Program with Integrated Circuit Emphasis (SPICE) was employed because it was constructed to read circuit design integrity and predict circuit per- formance of both integrated and board-level circuitry. Figure 3.1 illustrates the simulated circuit for a single pixel in a flat-panel display replicated on LT-Spice which is an open-source analogue electronic circuit simulation program.

3.1 Description of Simulation Model

The addressing sequence starts with a voltage pulse travelling through the scan line, which in the Spice code shown in Figure 3.2 is represented by the source Vselect.

The scanned pulse is received by the gate of the switching transistor, which turns it on. The in parallel to the capacitor describes leakage currents through the capacitor; an infinitely large resistor would ensure that there are no leakage currents.

The storage capacitor CS is charged through the selection transistor. Further- more, the gate source voltage of the driving transistor is increased, turning the transistor on. Finally, the driving transistor forces a current through the OLED and

22 the display pixel turns on. [10].

When the pulse applied to the scan line drops, the switching transistor turns off.

At that point, the storage capacitor keeps the potential of the gate of the driving transistor high enough to ensure that the OLED remains on until the pulse comes back in the next cycle.

Figure 3.3 illustrates the pulse of the signal on the scan line V(vg1) and the transient current charging the storage capacitor I(C1). The bias at the drain of switching device is connected to the gate of the driving device as show in the figure denoted as V(vg2). From the figure, we see that even when the switching transistor is off, i.e. if there is no voltage on the signal line, the storage capacitor keeps the voltage on the gate of the driving transistor high, ensuring that the OLED remains on as exhibited in figure 3.3.

3.2 Influence of the Mobility, Resistance, and Capacitance

To study the influence of the performance of the transistor on the switching speed of the backlplane, parameters such as the parallel resistance, capacitor and the charge mobility of the semiconductor were varied. The parallel resistor models the leakage current of the storage capacitor.

The resistor was varied from 900Ω to 530MΩ keeping the capacitance at a con-

−5 2 −1 stant value of 150nF and KP = µCox = 2.42 · 10 F cm (V s) .

Figure 3.4 plots the voltage at the gate of the driving transistor Vg2 vs. time for all . It can be seen that the capacitor charges at the same charge rate,

23 Figure 3.1: AM-OLED Single-pixel Simulation Schematic

Figure 3.2: LT-Spice syntax for AM-OLED FPD simulation

24 Figure 3.3: Voltage Pulse at Gate of Switching Transistor (Top, V(vg1)), Current driven into OLED (mid, I(D1)), and Voltage Pulse at Gate of Driving Transistor (bottom, V(vg2)) independently of the resistance. However, we see a dramatic decrease in leakage as the magnitude of the resistance is increased. Whereas a value below R = 40kΩ is too small, i.e. the voltage at the gate of the driving transistor drops rapidly, the gate capacitor keeps the necessary voltage for larger leakage resistances. It can be seen that the leakage current Ileakage still degrades the performance of the driving device

3 6 at 3x10 Ω. 7.29x10 Ω does not totally eliminate Ileakage at the gate which causes a voltage drop across the OLED. 5.1 · 108Ω maintains a steady on state of the device while keeping the OLED steady, and with a decrease in time delay as shown in table

3.1 and illustrated in 3.4.

There is a significant decrease in the discharge time delay of the capacitor as the mobility (Kp) increases as show in table 3.1 and figure 3.5 (with time in the

25 2 Resistance(Ω) τ R(ms) KP (F cm /Vs) τ µ(ms) Capcitance (nF) τC (ms) 9x102 100 8.08x10−8 22.25 150 1.33 3x103 1.40 5.27x10−6 1.65 200 1.40 4x105 1.33 2.42x10−5 1.33 300 1.40 7.29x106 1.33 4x10−4 1.12 500 1.53 5.1x108 1.33 6.35x10−2 1.08 700 1.65

Table 3.1: Varied Resistance and KP and Their Respective Time Constants logarithmic scale). This is due to the corresponding increase in charge transport mechanisms with magnitude of mobility. During the discharge of charges into the gate of the driving transistor, since time delay and capacitance are directly propor- tional to each other, we saw longer discharge times for higher values of capacitance

(Figure 3.6). This is expected due to the high charge density from the discharging capacitor.

26 Figure 3.4: Voltage Pulse at Gate of Driving Transistor with varying Resistance

27 Figure 3.5: Voltage Pulse at Gate of Driving Transistor with varying Mobility

28 Figure 3.6: Voltage Pulse at Gate of Driving Transistor with varying Capacitance

29 CHAPTER 4

Standard OFET

4.1 Structure of Device

The OFET that is used here is sketched in Figure 4.1. The transistor is of

Bottom-Gate-Top-Contact (BGTC) type [1] with a glass substrate, Aluminum gate and Al2O3 as the gate dielectric. DNTT is used as the semiconductor layer, with

Aluminum source/drain electrodes. Each column of the 4x4 substrate holder were each deposited with specific contacts. The first column was a direct deposition of aluminum on the DNTT layer, the second was gold, third was Pentacene doped with

F6TCNNQ, and the final column was with doped C60:o- MeO-DMBI [21][22].

The structure of the fabricated device is illustrated in figure 4.1. The materials were all deposited via thermal evaporation process. Following the order of the dia- gram from bottom to top, 150nm of aluminum (the gate electrode) is first deposited

Figure 4.1: Lateral view of OFET

30 on a glass substrate.

Secondly, anodization follows up in order to develop the Aluminum oxide layer.

Anodization is the process of covering a metal with an insulating oxide through an electrolytic process [21]. Tetratetracontane (TTC) is the next material which is a [22] deposited at a thickness of 40nm at 150◦C and pressure of 8.40 ×

10−8 Torr, followed by the featured organic semiconductor, dinaphtho[2,3-b:2’,3’- f]thieno[3,2-b]thiophene (DNTT) at 204◦C and 8.01 × 10−8 Torr to form thickness of 50nm, with channel length/width of 150µm/1.5mm. The contact of the result presented below in figure 4.3 and the finished device shown in figure 4.2 is Gold with 20nm in depth. The top and final layer to be deposited was the source/drain electrodes with material of aluminum and a thickness of 50nm.

4.2 Results

After the trasistors were fabricated, they were placed in an automated measure- ment system in order to measure the voltage transfer characteristics, as shown in

figure 4.3. The drain current is in logarithmic scale and plotted on the left (indi- cated by the blue line). The square-root of the magnitudes of the drain current

(green) which is directly proportional to the transconductance of the device is on the right [14].

The transistor of graph 4.3 gave us a mobility of 0.1cm2V −1s−1, threshold voltage at -1.5V, and with On/Off ratio of 105. These values were extracted from the devices fabricated with gold contacts which yielded the best results compared to devices with

31 Figure 4.2: Fabricated OFET with the highlighted Drain-Source-Gate electrodes

32 Figure 4.3: Voltage Transfer Characteristic of OFET with doped P5, C60:o- MeO-DMBI, and a direct deposition of the aluminum layer on DNTT.

Four substrates with 12 transistors each were processed for all injection contacts.

The mobility, threshold voltage and hysteresis is collected and averaged per for all devices.

In terms of mobility of the device shown in figure 4.2 and the results in 4.4, the deviation with the gold contacts seem to be more than that of doped pentacene.

However, pentancene delivered lower magnitudes of mobility than gold. The second cycle of doped pentacene gave an average mobility of 0.04cm2V −1s−1. This is a low magnitude and considering the size of the deviation, most transistors from this contact operated at low currents which is shown in figure 4.4.

33 Figure 4.4: Error Plots for Mobility between Au and doped P5

The threshold voltages were compared between samples with gold and doped

C60 contacts. Both Gold and C60 gave average threshold voltages from the second substrate at -1.5V and 1.7V respectively. From the graph illustrated in figure 4.5, charge injection will occur later in c60 than in gold.

In figure 4.6, we see the Hysteresis (the difference in drain current behavior between the on and off state) between gold and the direct deposition of aluminum on the organic layer. The contacts were varied due to the different electron affinity of the organic contacts but gold triumphed being that it is a metal with good compatibility with DNTT in terms of charge transport.

34 Figure 4.5: Error Plots for Threshold Voltage between Au and doped C60

Figure 4.6: Error Plots for Hysteresis between Au and Al

35 CHAPTER 5

OFET in a Backplane

5.1 Modelling

The structure of the OFET discussed in the previous section is then redeposited using backplane shadow masks and minor changes to the lateral structure. According to the illustration provided in 5.1, using a gate mask (A), aluminum is deposited at thickness of 150nm which was then anodized at 40V to form the oxide layer at a thickness of 50nm. The organic mask (B) is then used to deposit TTC and DNTT at thicknesses of 40nm and 30nm respectively. TTC was deposited at a temperature and pressure of 177.8◦C and 3.58E−7T orr. DNTT was at 222◦C and 3.17E−7T orr.

After the organic layer was deposited, the source/drain (C) was utilized to deposit gold at a thickness of 40nm. The final mask is the liquid crystal crystal mask which would be used in depositing the liquid crystal. As shown in figure 5.5, the final substrate alongside the shadow mask plan are shown. The source (marked

S) serves as the power line, the gate (G) is the scan line and the drain (D) will accommodate the OLED [19][23][6].

5.2 Results

As shown in the graph 5.3, we see operating conditions unsuitable to switch on and drive the OLED/liquid crystal as desired.The results collected can not advocate

36 Figure 5.1: Shadow Masks

37 Figure 5.2: Resulting Substrate for a well-functioning transistor. The device shorts because of the etiolated deposition of the source/drain contacts directly on the TFT. Given that the device did work,

The mobility would be derived from the slope, m illustrated in figure 5.4 using the relationship:

q q ID = W µC/2L(VG − Vth) (5.1) q m = W µC/2L (5.2)

In figure 5.5, we see a side-by-side of how the source/drain contacts are supposed to be look based on the mask plan and a sample. Ways in tackling this error and improvements to the device are discussed in the outline.

38 Figure 5.3: Voltage Characteristic of Backplane OTFT

39 Figure 5.4: Linear fit of The Square Root of the Drain Current

40 Figure 5.5: Fabricated transistor vs. Mask plan

41 CHAPTER 6

Conclusion

In summary, the characterization of the OFET as an independent device and as a driving/switching device in backplane circuitry is studied. A simulation was undertaken to study the real time implications of running a single-pixel circuit in order to optimize the performance of the circuit components specifically; the tran- sistors, capacitor, and parallel resistor. OFETs were fabricated in accordance to the specifications required of the device to thrive in the backplane. The standard OFET operated as expected but the backplane device did not perform properly so the re- sults extracted will not be relaible in calculating the mobility and On/Off ratio. In the backplane, the shadow masks were employed to accommodate the deposition of an OLED on the drain of the device in order to switch/drive it. The capacitance and resistance of the model circuit will be derived from the material make up of the

OLED itself.

6.1 Outline

Due to time limitations, changes were not made to maximize the results obtained.

In terms of architecture, the source-drain shadow masks can be slightly altered to cater to the short caused by the faded deposition. Application of another dielectric layer other than the oxide can be deposited in the region where the gate and source

42 layers intersect. In the fabrication of the standard OFET in chapter 4, Al was used as the electrode on top of Au contacts as opposed to the backplane OFET where Al was neglected with an increase in the thickness of Au. The former orientation will be re-employed in future runs.

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