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Intel Stratix 10 Configuration User Guide

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Intel Stratix 10 Configuration User Guide Intel Stratix 10 Configuration User Guide Updated for Intel® Quartus® Prime Design Suite: 19.4 Subscribe UG-S10CONFIG | 2020.03.06 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Intel® Stratix® 10 Configuration User Guide.......................................................................................................................... 6 1.1. Intel® Stratix® 10 Configuration Overview....................................................................................................................... 6 1.1.1. Configuration and Related Signals..................................................................................................................... 10 1.1.2. Intel Download Cables Supporting Configuration in Intel Stratix 10 Devices............................................................ 11 1.2. Intel Stratix 10 Configuration Architecture......................................................................................................................12 1.2.1. Secure Device Manager................................................................................................................................... 13 2. Intel Stratix 10 Configuration Details...................................................................................................................................18 2.1. Intel Stratix 10 Configuration Timing Diagram................................................................................................................ 18 2.2. Configuration Flow Diagram......................................................................................................................................... 22 2.3. Additional Clock Requirements for HPS, PCIe, eSRAM, and HBM2 ..................................................................................... 25 2.4. Intel Stratix 10 Configuration Pins.................................................................................................................................25 2.4.1. SDM Pin Mapping............................................................................................................................................ 26 2.4.2. MSEL Settings................................................................................................................................................ 27 2.4.3. Device Configuration Pins for Optional Configuration Signals................................................................................. 28 2.5. Configuration Clocks....................................................................................................................................................37 2.5.1. Setting Configuration Clock Source....................................................................................................................37 2.5.2. OSC_CLK_1 Clock Input...................................................................................................................................38 3. Intel Stratix 10 Configuration Schemes................................................................................................................................40 3.1. Avalon-ST Configuration.............................................................................................................................................. 40 3.1.1. Avalon-ST Configuration Scheme Hardware Components and File Types ................................................................ 42 3.1.2. Enabling Avalon-ST Device Configuration............................................................................................................43 3.1.3. The AVST_READY Signal ................................................................................................................................. 44 3.1.4. RBF Configuration File Format...........................................................................................................................46 3.1.5. Avalon-ST Single-Device Configuration...............................................................................................................46 3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme............................................................................. 50 3.1.7. QSF Assignments for Avalon-ST x8....................................................................................................................51 3.1.8. QSF Assignments for Avalon-ST x16.................................................................................................................. 53 3.1.9. QSF Assignments for Avalon-ST x32.................................................................................................................. 55 3.1.10. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core............................. 57 3.2. AS Configuration.........................................................................................................................................................84 Intel Stratix 10 Configuration User Guide Send Feedback 2 Contents 3.2.1. AS Configuration Scheme Hardware Components and File Types ...........................................................................86 3.2.2. AS Single-Device Configuration.........................................................................................................................88 3.2.3. AS Using Multiple Serial Flash Devices............................................................................................................... 90 3.2.4. AS Configuration Timing Parameters..................................................................................................................92 3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines......................................................................... 93 3.2.6. Programming Serial Flash Devices.....................................................................................................................94 3.2.7. Serial Flash Memory Layout..............................................................................................................................98 3.2.8. AS_CLK......................................................................................................................................................... 99 3.2.9. Active Serial Configuration Software Settings ................................................................................................... 100 3.2.10. Intel Quartus Prime Programming Steps......................................................................................................... 101 3.2.11. Debugging Guidelines for the AS Configuration Scheme.................................................................................... 106 3.2.12. QSF Assignments for AS...............................................................................................................................107 3.3. SD/MMC Configuration..............................................................................................................................................110 3.3.1. SD/MMC Single-Device Configuration............................................................................................................... 111 3.4. JTAG Configuration....................................................................................................................................................112 3.4.1. JTAG Configuration Scheme Hardware Components and File Types.......................................................................114 3.4.2. JTAG Device Configuration..............................................................................................................................115 3.4.3. JTAG Multi-Device Configuration......................................................................................................................118 3.4.4. Debugging Guidelines for the JTAG Configuration Scheme...................................................................................119 4. Including the Reset Release Intel FPGA IP in Your Design................................................................................................. 122 4.1. Understanding the Reset Release IP Requirement.......................................................................................................... 123 4.2. Assigning INIT_DONE To an SDM_IO Pin...................................................................................................................... 124 4.3. Instantiating the Reset Release IP In Your Design..........................................................................................................126 4.4. Gating the PLL Reset Signal........................................................................................................................................126 4.5. Guidance When Using Partial Reconfiguration (PR).........................................................................................................127 4.6. Detailed Description of Device Configuration................................................................................................................. 127 4.6.1. Device Initialization....................................................................................................................................... 129 4.6.2. Preventing Register Initialization During Power-On ............................................................................................129 4.6.3.
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