Atomic Layer Deposition of Lanthanum Oxide Gate Dielectrics for Ingaas Channel

Master thesis

Atomic layer deposition of lanthanum oxide gate dielectrics for InGaAs channel

Tokyo institute of technology Department of electrical and electronic Engineering Dissertation for degree of Master of Engineering

Hiroshi Oomine

Supervisor Prof. Hiroshi Iwai Associate prof. Kuniyuki Kakushima

Tokyo institute of technology Department of electrical and electronic Engineering Dissertation for degree of Master of Engineering

Atomic layer deposition of lanthanum oxide gate dielectrics for InGaAs channel

Candidate: Hiroshi Oomine Student Code: 12M36078

Supervisor: Prof. Hiroshi Iwai Associate prof. Kuniyuki Kakushima

ABSTRACT

Atomic layer deposition of lanthanum oxide gate dielectrics for InGaAs channel

Supervisor: Prof. Hiroshi Iwai Associate prof. Kuniyuki Kakushima Tokyo Institute of Technology Department of Electrical and Electronic Engineering Hiroshi Oomine

InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) have been expected for future scaled devices owing to high mobility and injection velocity of electrons which result in high drive current at low supplied voltage. One of the issues of InGaAs MOSFETs is to achieve thermally stable high quality interface with strong thermal endurance. Although low interface state density (Dit) has been reported with atomic-layer-deposited (ALD) Al2O3 using self-cleaning effect, low dielectric constant of 9 for Al2O3 and poor thermal stability up to 400 oC may pose difficulty in thickness scaling and implementation into device fabrication process. Recently, E-beam deposited

La2O3 films have shown excellent electrical properties as gate dielectrics for InGaAs MOS devices by forming thermally stable LaInGaO interfacial layer. Although nice interface properties are reported, research on deposition method has not been intensively done. Based on the requirements for gate dielectrics such as precise thickness control over large area and conformal deposition to three dimensional channels, ALD process with wide process window is indispensable.

In this thesis, we investigate the interface properties of ALD La2O3 gate i dielectrics using La( PrCp)3 gas with H2O oxidant, which is known to achieve ALD conditions on Si substrates. InGaAs MOS capacitors have been fabricated by chemical cleaning with surface passivation process. La2O3 films have been grown in a hot-wall type thermal ALD reactor and gate metals have been formed by sputtering method. MOSFETs have been fabricated with Si ion implantation to source and drain regions.

From substrate temperature dependent film growth rate measurement from 140 to 230 oC together with Ar purging time optimization, a growth rate of 0.14 nm/cycle has been found to be stable between 140 to 160 oC, which suggests that ALD mode can be achieved within this temperature range. It is found that at this temperature range, La2O3/InGaAs MOS 11 -2 capacitors have shown Dit of the order of 10 cm /eV, which are comparable to e-beam deposited samples. One prominent feature is that sulfur treatment to terminate the surface atoms by S atoms, which is known to prevent formation of trivalent oxides, has little effect on Dit, which is advantageous for industrial purpose. MOSFETs with ALD La2O3 has shown high effect mobility of 345cm2/Vs at capacitance equivalent thickness of 1.1 nm.

In conclusion, La2O3 deposited by low growth temperature at ALD mode can be realized low Dit < 1012eV-1cm-2 as a consequence of interface of ALD deposited La2O3 films on InGaAs substrate obtained stable interface state in annealed temperature at 420oC. On the other hands, low growth temperature deposited La2O3 film has large amount of impurity and defect is related to high gate leakage current and substhreshould slope value. Besides, interface roughness of ALD-La2O3/InGaAs has approximately 0.5 nm, it is rough compare with ALD-Al2O3/InGaAs interface. As a results, rough interface 2 reduced effect mobility less 1000 cm /Vs. In the future, ALD-La2O3 process is necessary to improve of oxidation methods in ALD sequence. Reduction interface roughness is considered to be effective changing pre-treatment method.

INDEX Chapter 1 Introduction

1.1 Advance of LSI technology and evolution of CMOS transistors 6

1.2 Advantages and challenges of III-V compound semiconductors in CMOS 8 technology

1.3 Challenges of high-k/InGaAs gate stack technology 14

1.4 Merit of La2O3 gate stacks for InGaAs MOS structures 18

1.5 Technology for 3D structure InGaAs MOSFETs 19

1.6 Purpose and organization of this thesis 21

1.7 References 22

Chapter 2 Fabrication and characterization

2.1 Advance of LSI technology and evolution of CMOS transistors 26

2.1.1 ALD mechanism 26 2.1.2 Selection of ALD precursor and oxidation source 30

2.2 Fabrication process 33 2.2.1 InGaAs cleaning and Sulfur passivation 34 2.2.2 RF magnetron sputtering 34 2.2.3 Reactive ion etching 34 2.2.4 Post metallization annealing (PMA) in FG ambient 34 2.2.5 Vacuum evaporation for Al back side electrode 35

2.3 Characterization of MOS devices 35

2.3.1 Ideal CV characterization of MOS capcitors 35

2.3.2 Admittance characterization of MOS capacitors 37

2.4 References 40

Chapter 3 Growth characteristics of ALD-La2O3 on InGaAs substrate

3.1 Growth condition of ALD-La2O3/InGaAs stacks 42

3.1.1 ALD condition 42 3.1.2 Growth condition 42

3.2 Effect of growth temperature and post metallization annealing (PMA) 46 3.2.1 MOS capacitor fabrication process 46

3.2.2 CV and interface state density (Dit) chracteristics 47 3.2.3 Gate leakage current of MOS capacitors 56

3.3 Effect of Sulfur passivation for ALD-La2O3/InGaAs MOS capacitors 59 3.3.1 Physical properties 59 3.3.2 Electrical properties 62

3.4 Challenging for scaling and conclusions 65

3.5 References 68

Chapter 4 Electrical properties of InGaAs nMOSFETs with ALD-La2O3

4.1 Growth condition of ALD-La2O3/InGaAs stacks 71

4.2 Electrical characteristics 73 4.3 Conclusions 77

4.4 References 78

Chapter 5 Conclusions

5.1 Conclusions of this study 81

5.2 Prospects for future study 81

Acknowledgments 83

Chapter 1 Introduction

1.1 Advance of LSI technology and evolution of CMOS transistors 1.2 Advantages and challenges of III-V compound semiconductors in CMOS technology 1.3 Challenges of high-k/InGaAs gate stack technology

1.4 Merit of La2O3 gate stacks for InGaAs MOS structures 1.5 Technologies for 3D structure InGaAs MOSFETs 1.6 Purpose and organization of this study 1.7 References

1.1 Advance of LSI technology and evolution of CMOS transistors

It is not an exaggeration to say that the life of our daily is made up of electronics. There is smart phone as typical examples. In recent years, people are enamored by convenience of smart phone, while walking on the street or during the movement of the train. There is little tool, such as to attract many people in history of mankind. In the background, scaling of semiconductor devices greatly involved performance improvement of electronics. Point contact transistors that it may be said that is a model were discovered by William B. Shockley Jr., John Bardeen and Walter H. Brattain in Bell laboratories at 1947. In 10 years later, First Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) on a silicon substrate using SiO2 as the gate insulator was fabricated in 1960 by Dawon Kahng, Martin M. Atralla (figure 1.1).

(a) The point-contact transistor (b) The first MOSFET

Figure 1.1 (a) the point-contact transistor, (b) the first fabricated MOSFET

using Ge [1.2] and SiO2/Si gate stack [1.3].

10 years after, The integrated circuits (IC) was released in 1971 by Intel Corp. Gordon E. Moore, one of the co-founder of Intel Corp. predicted and observed for the semiconductor industry from him excellent knowledge, who announced for the complexity of (number of transistor on) IC doubles approximately every two years in 1965. This is Moore’s law in a later. This law was established by the word-wide exertion technology development. There is technology node to index of transistor scaling. It is called “device pitch” and “gate pitch”, and is defined as the ground rules of a process governed by the smallest feature printed in a repetitive array. Example of technology node of MOSFETs on IC by Intel Corp. showed in figure 1.2.

First LSI Intel 4004 Modern LSI

Figure 1.2 The moore’s law and modern LSI by Intel [1.4].

It is found that MOSFET was scale-down about 0.7 times two years from figure 1.2. The scaling rule which was first published by R. Dennard [1.5] is very simple, it states that if the device dimensions and supply voltage of MOSFETs are reduced by a factor α, then the circuit operation speed is increase by the same factor (figure 1.3).

Original Device Scaled Device “Scaling” Supply Voltage, V ( α times smaller) Supply Voltage, V/α X j Gate X /α j Gate tox tox/α source drain source drain

Wd Lg/α

Lg substrate doping αNA substrate doping N A Figure 1.3 Principles governing scaling rule

Every two years, the number of transistors packed to unit chip area is doubles accompanied by almost 50% reduction in the cost of each transistor. Simply put, it is only miniaturize a MOSFETs. But, recent year, scaling rule was limit. IBM said “Classical CMOS scaling died” in 130 nm generation [1.6]. For this reason, many semiconductor companies try to prolong the life of Moore’s law by introducing new technology, such as new materials.

Product year: 2005 2007 2009 2011 Process node: 65nm 45nm 32nm 22nm

TEM cross section:

SiGe New technology: Fin-FET Strained Silicon High-k/Metal gate Device stracture: Bulk Planar 3D

Figure 1.4 Current MOSFETs released by Intel [1.4].

Figure 1.4 shows MOSFETs released by Intel Corp. To improve mobility stressed Si substrate introduce of SiGe for S/D in 2005,to reduction of gate leakage current introduced high-k/metal gate technology, realizing 3- dimensional structure devices, Intel called Fin-FET, in 2011. Development of semiconductor device technologies will continue, and will enter the electronics, such as fascinating a lot of people.

1.2 Advantages and challenges of III-V compound semiconductors in CMOS technology

The basic structure of a MOSFET is shown figure 1.3. It is three-terminal device with the terminals designated as gate, source and drain. The MOSFET is usually referred to as a unipolar or majority-carrier devices. The relationship between drain current and gate voltage (Ids-Vg) of MOSFETs is shown figure 1.5.

OFF state ON state OFF state ON state linear log

ION A)

I (

A) ON

) )

(

DS (I

I S.S. ln

IOFF 0 V V 0

T DD VT VDD Drain current current Drain

Gate Voltage Vg (V) current Drain Gate Voltage Vg (V)

Figure 1.5 (a) linear, and (b) logarithmic Ids-Vg characteristics of an n- MOSFET.

The total power consumption in a CMOS circuit can be separated two components, dynamic power (when the transistor is ON state) and static power (when the device is OFF state). Power consumption and drive current

(ION) of a MOSFET can be related to device parameters approximately by the following equations [1.7].

푉 2 푡ℎ 푃푐표푛푠푢푚푝푡𝑖표푛 ≈ 푎푓퐶푙표푎푑푉푑푑 + 퐼0. 10 푆 . 푉푑푑 + 퐼푙푒푎푘. 푉푑푑 (1.1)

퐼푂푁 ≈ 퐶𝑔(푉푑푑 − 푉푡ℎ). 휐(푉푑푑) (1.2)

Here α is a constant value, f is the operating frequency, Cload is the load capacitance, I0 is the drain current at Vg of Vth, S is the subthreshold swing factor, Ileak is the total leakage current, Cg is the gate capacitance and υ is the electron velocity near the source region. The static power consumption component is represented by the third section of equation (1.1) and is dominated by leakage current. The second part of equation (1.1) is due to the momentary pass of current that is created as a result of necessary time for one transistor to switch off in an inverter circuit. The first part of equation (1.1) is the activate power which is drawn from the power supply when the transistor is operating at a clock frequency of f. From equation (1.1) can be derived than in order to realize low-power MOSFETs, lower Vdd higher Vth, smaller S (higher immunity to short-channel effect), and lower Ileak are necessary. However, according to equation (1.2) lowering Vdd and increasing

Vth leads to drastic reduction in ION. Furthermore, the thickness of the gate

9 oxide (Tox), should be large enough to reduce the gate leakage current which conflicts with the need for increasing ION. As a consequence, satisfying a high performance and low power consumption device with good device with good device characteristics based on only traditional scaling methods becomes increasingly difficult. In order to make both requirements of low power consumption and high performance compatible, high-mobility channel material are actively investigated for 10 nm and smaller MOSFET gate lengths. Superior carrier properties of non-Si channel material, if utilized fully, would directly result in achieving higher carrier mobility on drain current and gate voltage characteristics of a MOSFET is shown in Figure 1.6.

High mobility materials Increase in drive current log due to high velocity

A) Si

( ION channels

) ) SD

(I S.S. ln Reduction in supply voltage IOFF 0 VT V’DD VDD Drain current current Drain Gate Voltage Vg (V)

Figure 1.6 Effect of carrier mobility on MOSFET transfer characteristics.

Table 1.1 summarizes the bulk electron and hole mobility, the electron and hole effective mass, the band gap and the permittivity of Si, Ge, and main III–

V semiconductors. In this study, In0.53Ga0.47As was selected. Because,

In0.53Ga0.47As has (1) lower band-to-band tunneling (BTBT) leakage current than other III-V semiconductors and (2) obtain high quality epitaxial growth substrate [1.8].

Table 1.1. Summary of Si, Ge and compound semiconductors physical properties.

Si Ge InP GaAs In0.53Ga0.47As InAs electron mob. (cm2/Vs) 1600 3900 5400 9200 10000 40000 electron effective mt:0.19 mt:0.082 0.08 0.067 0.041 0.026 mass (/m0) ml:0.916 mt:1.467 hole mob. (cm2/Vs) 430 1900 200 400 250 500

hole effective mHH:0.49 mHH:0.082 mHH:0.45 mHH:0.45 mHH:0.45 mHH:0.57 mass (/m0) mLH:0.16 mLH:0.044 mLH:0.12 mLH:0.082 mLH:0.052 mLH:0.35 band gap (eV) 1.12 0.66 1.34 1.42 0.74 0.36

The electron mobility of the III–V materials is quite high, and the enhancement factor of the electron mobility against Si can be higher than 3– 50 times than in the bulk. This high mobility is basically attributed to the light effective mass. However, most high mobility materials also have a significantly smaller band gap compared to Si, leading to a very high band- to-band tunneling (BTBT) leakage currents, which could limit their scalability. BTBT leakage current in the darin, which is caused by coupling of valence band and conduction band due to thermal lattice vibration of the semiconductor, can become the dominant off-state leakage current in small band gap semiconductors, thus negating the efforts to reduce the static power dissipation of the device. Therefore the trade off relationship between these material properties should be taken into consideration for device application purposes. InGaAs allows for a very good tradeoff between the excellent transport properties of narrow band gap InAs and the low leakage of wider band gap GaAs. The In mole fracture in InGaAs can be adjusted to increase mobility or increase band gap. In0.53Ga0.47As with In mole concentration at 53%, has matching lattice constant with InP and InAlAs (Figure 1.7).

In0.53Ga0.47As

Figure 1.7 Lattice constant vs band alignment properties of various III-V materials.

This fact can be utilized for high quality epitaxial growth of In0.53Ga0.47As for both MOSFET and HEMT structures. Highest performance HEMT devices have been reported on In0.53Ga0.47As HEMTs on InP substrate [1.9]. However, there is a problem in that lower ON current than Si MOSFETs in InGaAs MOSFETs. The reason for needing a dielectric constant with higher dielectric constant, arises from the nature of InGaAs electrical structural. ON current of a MOSFET, is directly related to the amount of charges that gate can modulate in the channel region. This relation can be shown by

Q = C (푉𝑔 − 푉푡ℎ) (1.7)

Where Q is the channel charge, C is the gate capacitance and Vg-Vth is the gate overdrive voltage. The gate capacitance should be increased to enable accumulation of more charges in the channel region and gain more ON current. The gate capacitance in turn, mainly consists of two components, the oxide capacitance (Cox) and the semiconductor capacitance (CDOS) and their relation can be shown using the following equation. 1 1 1 = + (1.8) 퐶 퐶표푥 퐶퐷푂푆

The light electron effective mass in In0.53Ga0.47As, results In0.53Ga0.47As having a smaller density of states in the conduction band (2.17×1017 cm-3 in

In0.53Ga0.47As compared to 3.2×1019 cm-3 in Si). This means less gate capacitance and according to equation (1.7) less charge in the channel region. Therefore, it is more important to use thin oxides, which can provide higher

Cox, for high mobility channel materials such as In0.53Ga0.47As. Figure 1.8 shows band disorder’s and dielectric constant each high-k on InGaAs.

4 Al O La O 3 2 3 2 3 HfO 2 2 1 Conduction Band

0 In0.53Ga0.47As -1 Valence Band

-2 Gd2O3

-3 ZrO2

Band discontinuity (eV) discontinuity Band LaAlO -4 Ga O (Gd O ) -5 2 3 2 3 0 10 20 30 40 Dielectric constant Figure 1.8 band disorders and dielectrics constant each high-k on

In0.53Ga0.47As.

Using high-k dielectrics is the solution for fabricating thin oxides while maintaining low gate leakage current in MOSFETs. Numerous high-k dielectrics have been investigated on InGaAs substrate with various In

(Indium) contents. Dielectrics such as HfO2, ZrO2, TaSiOx, SrTa2O6, etc. have been tried and electrically characterized. All of these dielectrics have higher dielectric constant than Al2O3 and are preferred over Al2O3 for scaling purposes; however generally these dielectrics exhibit high Dit values at their interface with InGaAs which make their application in device structures unpractical. High level of Dit, degrade the sub-threshold slope (SS) of the transistor which can be shown using the following relation [1.1],

푘푇 푞2퐷 +퐶 SS = 2.3 (1 + 𝑖푡 푑푒푝) (1.9) 푞 퐶표푥

Where Cdep is the depletion capacitance and Cox is the oxide capacitance. Sub-threshold slope (SS) describes the ability of MOSFET to switch on and off. Smaller SS means that small OFF current (Figure 1.9) when the device is switched off which translates to smaller stand-by power.

)

2 140 log D =1013 eV-1cm-2 130 it

120

(A/cm )

) ) S.S. 110 SD

dec 100 (I Reduction in S=60(1+ ln I’OFF supply voltage 90 80 12

S S (mV/ 10 70 IOFF 1011 60 0 V 50 T 0 1 2 3 4 5 Drain current current Drain Gate Voltage Vg (V) EOT (nm)

Figure 1.9 Effect of Dit for Sub-threshold slop (SS) degrade

1.3 Challenges of high-k/InGaAs gate stack technology

Origin of interface states are widespread, models have been proposed. In this section, as applicable to the MOS interface, two models, Unified Defect Model (UDM) of Spicer [1.11] and Disorder-Induced Gap State (DIGS) model of Hasegawa [1.12], are introduce. UDM have to be in the local structure of the specific of the interface state, such as the dangling bonds present at the interface, vacancy of missing III (In, Ga elements) and V (As element) groups, anti-site present in a different position, dimer V groups together bound. DIGS model is that disorder of bound state were induced bonding of the substrate and dielectric cause band gap exudation of electronic state of conduction band and valence band. Figure 1.10 shows models of UDM and DIGS [1.11-1.12].

(a) Unified defect model [1.11] (b) Unified disorder induced gap state model [1.12]

Dit origin Dit origin Native oxides (Adsorption Interface roughness, oxygen), Dimer, Anti-site… Crystal disorder (quality)…

Figure 1.10 interface state densities model (a) UDM [1.11] and (b) DIGS [1.12].

From figure 1.10, two models indicated that the origin of Dit are native oxides and defects of substrate surface, interface roughness and stress of dielectrics and substrates. Recently, there have been reports on experimental demonstration of non- planar InGaAs MOSFETs, which show much enhanced electron injection velocities and high drive current at smaller supply voltage [1.13]. However, various challenges remain to enable commercialization of high mobility channel MOSFETs. One of the key challenges is demonstration of a high quality high-k/InGaAs (III-V in general) interface. The high-k/InGaAs gate stack also needs to be scalable since for sub-16 nm nodes, highly scaled gate length devices would require very low EOT to maintain electrostatic control of the channel. This requires elimination of low-k layer (native oxides) at the interface of III-V and gate dielectric. It is reported that an all in-situ process with InGaAs growth followed by high-k deposition can suppress the formation

15 of native oxides [1.14], however from the manufacturing point of view, an ex- situ process flow is more desirable. The ability of MOSFET to switch on and off is described by sub-threshold slope (SS). The value of SS is dependent not only on the accumulation capacitance, but also on the capacitance due to interface state density (Dit). In order to improve the switching capability (reduce passive power dissipation), it is imperative to reduce the effect of parasitic capacitance by reducing Dit at high-k/InGaAs interface. Numerous high-k dielectrics have been investigated on InGaAs substrate with various In (Indium) contents. Dielectrics such as HfO2, ZrO2, TaSiOx,

SrTa2O6 and Al2O3 have been tried and electrically characterized. Dielectrics such as HfO2 have higher dielectric constant than Al2O3 and are preferable for gate stack for scaling purposes; however generally these dielectrics have high Dit values at their interface with InGaAs which make their application in device structures very difficult. A typical Capacitance-Voltage (CV) characteristic of HfO2/In0.53Ga0.47As interface is shown in Figure 1.11. Significant frequency dispersion is observed in all ranges of the gate voltage bias. The mechanism of dispersion in each region is different. The effect of high levels of mid-gap Dit ( ~1013 eV-1 cm-2) can be seen as the capacitance response in lower measurement frequencies in the inversion condition

(negative gate bias in this case). Also, the thermal stability of HfO2 gate stack is usually lower than 500oC. Formation of an interfacial layer

HfO2/In0.53Ga0.47As interface is commonly reported even at low annealing temperatures, which degrades the CV characteristics of the capacitor (Figure 1.11 [1.15] and 1.12 [1.16]).

Figure 1.11 CV characteristics and TEM image of ALD HfO2/InGaAs MOS devices with 1.9 nm IL [1.15].

PMA 420 oC, FG 5min 2 n-InGaAs 1 kHz o 1.5 (a) HfO2 depo at 100 C W

HfO2 In Ga As 1 1 MHz Defects 0.53 0.47 o (b) Interface HfO2 depo at 300 C W 0.5 HfO2 Defects In0.53Ga0.47As 25 µm×25 µm 50 nm 0 -1.5 -1 -0.5 0 0.5 1 1.5 Gate Voltage (V)

Figure 1.12CV characteristics and TEM image of W/HfO2/InGaAs MOS capacitor at a gate first process [1.16].

High quality and atomically flat dielectric/InGaAs interfaces have been reported by using Al2O3. By using Atomic Layer Deposition (ALD) method for synthesizing Al2O3 films on InGaAs, mid-gap Dit ( ~1012 eV-1 cm-2) has been demonstrated. The improvement in interface is attributed to so called “self- cleaning effect” of trimethylaluminum (TMA) gas which is used as the precursor gas for ALD-Al2O3 deposition. This effect refers to removal of As- oxide species by exposing the InGaAs substrate to TMA gas during the first cycle of ALD deposition [1.8].

Although in the recent publications, Al2O3 commonly is used as the gate dielectric for InGaAs-based device performance demonstrations, the relatively low dielectric constant of Al2O3 (k≈9) and the low thermal budget of

Al2O3/InGaAs interface ( ~400 oC) will make it inevitable to replace Al2O3 with a high-k dielectric with better or at least equal level of interface quality. Table

1.2 summarizes the scalability, Dit and annealing temperature tolerance of main high-k candidates on InGaAs from the recently reported results.

Table 1.2 Summary of present interface properties for common high- k/InGaAs interface.

k-value D High temperature High-k it scalability (cm-2/eV) endurance × Al O * ~9 (△) ~9x1011 2 3 (~400oC) ** 12 △ HfO2 ~16 (○) >10 HfO / 2 ~16/9 (○) >1012 △ Al O stack*** 2 3

1.4 Merit of La2O3 gate stacks for InGaAs MOS structures

Here, I would like to introduce lanthanum oxide (La2O3) for InGaAs MOS capacitors. Because, La2O3 has a high dielectric constant (k~24) and promising results with high quality interface and small EOT have been reported on Si using La2O3 as the gate dielectric [1.17]. Lanthanum can form a complex network of amorphous structure with Si and Ge [1.18], leading to the formation of an interfacial layer (IL) at the oxide/sub interface. On the other hand, La2O3 can react at InGaAs surface through the formation the formation of Ga-O-La and In-O-La bonds. A cross-sectional TEM image of EB- deposited La2O3 on InGaAs is shown figure 1.13.

TiN TiN (45 nm) W W (5 nm) La2O3 La2O3 LaInGaO 50 nm n-InGaAs (10 nm) x n-InGaAs

TiN (45 nm) 50 50 As 40 W (5 nm) 40 In 1 30 La 30 Ga La O O2 2 2 3 20 20 (10nm) 10

Atomic Ratio (%) Ratio Atomic 10

3 (%) Ratio Atomic n-InGaAs 0 0 4 0 1 2 3 4 0 1 2 3 4 Measurement point Measurement point Figure 1.13 Cross-section TEM image and schematic image of

La2O3/InGaAs interface, EDX analysis of dielectric layer show the

LaInGaOx layer at the interface [1.19].

EDX analysis indicated the formation of an amorphous interfacial layer in the form of LaInGaOx. The composition and thickness of this layer can be manipulated through gate metal selection and PDA process. The k-value of gate stacks estimated to ~19 from the thickness dependence which is much larger than Al2O3 gate stacks. Well-behaved CV characteristics and Dit value below 1012 (eV-1cm-2) are achieved in a wide annealing temperature window (Figure 1.14).

3 ) 1 2 13 10100 ZrO2 2.5 HfO2/

/cm 0.5 )

2 Al O

μF 2 3

( 2 keff ~19

CET (nm)CET 0 Nitrogen-passivated

/cm 1 1.5 0 2 4 6 - 12 HfO2 ZrO2/ Thickness EB-La2O3 1010 4.0 nm (eV 8.2x Al2O3

1 it [1]

D 11 100 kHz 4.5 nm 10 EB-La2O3

Capacitance Capacitance 0.5 5.0 nm

5.5 nm density state Interface 11 0 101 -1.5 -1 -0.5 0 0.5 1 1.5 0.5 0.73 1 1.5 2 Gate voltage (V) Capacitance equivalent oxide thickness (CET) (nm)

Figure 1.14 CV characteristics and Dit value of EB-La2O3/InGaAs MOS capacitors [1.19].

The frequency dispersion in the accumulation region for capacitor with 5.0 nm La2O3 was 11%, which is quite small considering the sub-nm CET value. This work presented in IEDM 2013 [1.19].

1.5 Technologies for 3D structure InGaAs MOSFETs

In 2011, the FinFET design was implemented for the first time on Intel’s 22 nm technology [1.4]. The basic idea of 3D-Transistor was published from Hitachi corp. in IEDM 1989 [1.20]. The structural benefits of FinFETs, such as improved gate electrostatic and higher mobility and on-current due to low channel dopant density was combined with several other complex fabrication

19 procedures (Figure 1.15).

[1.21] Intel [1.22] Intel

log Planer

(

) ) SD

(I S.S. Fin FET ln [1.23] AIST [1.24] imec Reduction in IOFF S-factor I’’OFF 0

VT Drain current current Drain Gate Voltage Vg (V)

Figure 1.15 The structural benefits of FinFETs, such as improved gate electrostatic and higher mobility and on-current [1.21-1.24].

For this reason, the application of 3D structure MOSFET can be expected in the III-V MOSFETs. Figure 1.15 shows III-V FinFETs. However, it is diffeicult for PVD process (such as EB deposition etc.) to control thickness precisely over large wafer. In addition, PVD is not suited for conformal deposition on 3D-channels such as fins and nanowires. From the view point of CMOS manufacturing, atomic layer deposition (ALD) is preferred techniques. ALD is able to control the film thickness with atomic precision as well as with excellent conformity and uniformity. Therefore, development a suitable ALD process is deemed necessary for high quality dielectric film synthesis. Furthermore the chemical nature of ALD process could enable improvement and accurate control of interface conditions. In this study, we have introduced La(iC3H7-C5H4)3 (La(iPrCp)3) and H2O as precursors to produce high quality atomic layer deposited La2O3 thin films at low growth temperature. The new methods and guidelines for improving ALD-

La2O3/In0.53Ga0.47As interface properties are also discussed.

1.6 Purpose and organization of this thesis

La2O3 (k~24), on the other hand, is considered as a next-generation high-k material and recent studies have shown excellent electrical properties for

La2O3-based InGaAs MOS devices. Besides development a suitable ALD process is deemed necessary for high quality dielectric film synthesis. Furthermore the chemical nature of ALD process could enable improvement and accurate control of interface conditions. In this study, we have introduced

La(iC3H7-C5H4)3 (La(iPrCp)3) and H2O as precursors to produce high quality atomic layer deposited La2O3 thin films at low growth temperature The new methods and guidelines for improving ALD-La2O3/In0.53Ga0.47As interface properties are also discussed. This thesis consists of 6 chapters. Chapter 1 describes the background of MOSFET scaling history and the evolution of CMOS technology. The necessity of new channel material with higher carrier transport properties, such as III-V compound semiconductors, to keep with the low power demands of the circuits are discussed. The common experimental scheme used throughout this study, is described in Chapter 2. In

Chapter 3, properties of ALD-La2O3/InGaAs stacks investigated. The effect of ALD growth temperature and Sulfur passivation are introduced using various characterization methods. In chapter 4, InGaAs MOSFET operation with La2O3 as high-k gate dielectric and Ni/InGaAs as metal source and drain, is demonstrated. Finally, in chapter 5, conclusions and prospects for future work are described. Chapter structure in this thesis is summarized in the following chart.

Chapter 1. Introduction

Chapter 2. Fabrication and characterization

Chapter 3. Growth condition of ALD-La2O3 on InGaAs substrate 3.1 Growth condition of ALD-La2O3/InGaAs stacks

3.2 Effect of growth temperature and 3.3 Effect of Sulfur passivation for

post metallization annealing (PMA) ALD-La2O3/InGaAs MOS capacitors

3.4 Conclusion

Chapter 4. Electrical properties of n-InGaAs MOSFETs with ALD-La2O3 Chapter 5. Conclusions

1.7 References

[1.1] Y. Taur, T. H. Ning “Fundamentals of modern VLSI devices second edition” Cambridge, 1998.

[1.2] “The birth of modern electronics the point-contact transistor” http://smithsonianchips.si.edu/augarten/p2.html.

[1.3] H. Iwai “Future of Nano CMOS Technology” IEEE EDS Distingushed Lecture, at IIT-Bombay, Mumbai, India, January 20, 2014

[1.4] Intel HP: http://www.intel.co.jp/content/www/jp/ja/homepage.html.

[1.5] R. H. Dennard, F. H. Gaensslen, H-N, Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion-implanted MOSFET’s with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, 1974.

[1.6] B. Meyerson “Collaborative Innovation; A New Lever in Information Technology Development” Hot Chips: A Symposium on High Performance Chips 18 (2006),

[1.7] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000

[1.8] S. Oktyabrasky, P. D. Ye “Fundamentals of III-V Semiconductor MOSFETs” Springer, 2010.

[1.9] M. W. Pospieszalski, pp. 25, IEEE MTTT-S Digest 2000

[1.11] W. E. Spicer, L. Lindau, P. Skeath, and C. Y. Su “Unified defect model and beyond” J. Vac. Sci. Technol., 17(5) 1980.

[1.12] H. Hasegawa, H. Ohno “Unified disorder induced gap state model for insulator-semiconductor and metal-semiconductor interfaces” J. Vac. Sci. Technol. B. 4(4) 1986.

[1.13] M. V. Fischetti, L. Wang, B. Yu, C. Sachs, P. M. Asbeck, Y. Taur, and M. Rodwell, “Simulation of electron transport in high-mobility MOSFETs: Density of states

22 bottleneck and source starvation” IEDM. 109, 2007.

[1.14] F. Ren et al., “Ga2O3(Gd2O3)/InGaAs enhancement-mode n-channel MOSFETs” IEEE Electron Device Lett. 19, 309, 1998.

[1.15] Y. HR. D. Long, É. O’Connor, S. B. Newcomb, S. Monaghan, K. Cherkaoui, P. Casey, G. Hughes, K. K. Thomas, F. Chalvet, I. M. Povey, M. E. Pemble, and P. K. Hurle “Structural analysis, elemental profiling, and electrical characterization of HfO2 thin films deposited on In0.53Ga0.47As surfaces by atomic layer deposition” J. Appl. Phys. 106, 084508, 2009.

[1.16] D. Zade, K. Kakushima, T. Kanda, Y.C. Lin, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, E. Y. Chang, K. Natori, T. Hattori and H. Iwai, “Improving electrical characteristics of

W/HfO2/In0.53Ga0.47As gate stacks by altering deposition techniques” Microelec. Eng., 7(88) (2011) 1109.

[1.17] T. Kawanago, K. Kakushima, P. Anmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, “Covalent Nature in La-silicate Gate Dielectrics for Oxygen Vacancy Removal” IEEE Electron Device Lett. pp 423-425, 33(2012).

[1.18] J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori and H. Iwai, “ Improvement of interfacial properties with interfacial layer in La2O3/Ge structure” Microelec. Eng. 84(2007) 2336.

[1.19] D. Hassan Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.

Wakabayashi, K. Tsutsui, K. Natori and H. Iwai, “Low Dit high-k/In0.53Ga0.47As Gate Stack, with CET Down to 0.73 nm and Thermally Stable Silicate Contact by Suppresion of Interfacial Reaction” IEDM 36, 2013.

[1.20] Digh Hisamoto, T. Kaga, Y. Kawamoto and E. Takeda, “A Fully Depleted Lean- channel Transistor (DELTA) –A novel vertical ultra thin SOI MOSFET—“ IEDM 833, 1989.

[1.21] M. Radosavljevic, G. Dewey, D. Basu, J. Boardman, B. Chu-Kung, J. M. Fastenau, S. Kabehie, J. Kavalieros, V. Le, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, H. W. Then and Robert Chau, “Electrostatics Improvement in 3-D Tri-gate Over Ultra-Thin Body Planar InGaAs Quantum Well Field Effect

Transistors with High-K Gate Dielectric and Scaled Gate-to-Drain/Gate-to-Source Separation” IEDM Tech. Dig. pp. 765, 2011.

[1.22] M. Radosavljevic, G. Dewey, J. M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, and Robert Chau, “Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications,” IEDM Tech. Dig., pp. 126-130, 2010.

[1.23] T. Irisawa, M. Oda, K. Ikeda, Y. Moriyama, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Ishihara, M. Hata and T. Tezuka, “High Mobility p-n Junction-less InGaAs-OI Tri-gate nMOSFETs with Metal Source/Drain for Ultra-low-power CMOS Applications” SOI Conference , 2012

[1.24] imec “Imec demonstrates World’s First III-V FinFET Devices Monolithically Integrated on 300mm Silicon Wafers” Leuven November 5, 2013: http://www2.imec.be/be_en/press/imec-news/imeciiivfinfet.html.

Chapter 2 Fabrication and characterization

2.1 Atomic layer deposition (ALD) technique 2.1.1 ALD mechanism 2.1.2 Selection of ALD precursor and oxidation source 2.2 Fabrication process 2.2.1 InGaAs cleaning and Sulfur passivation 2.2.2 RF magnetron sputtering 2.2.3 Reactive ion etching 2.2.4 Post metallization annealing (PMA) in FG ambient 2.2.5 Vacuum evaporation for Al back side electrode 2.3 Characterization of MOS devices 2.3.1 Ideal CV characteristics of oxide/In0.53Ga0.47As capacitors 2.3.2 Admittance characterization of MOS capacitors 2.4 References

2.1 Atomic layer deposition (ALD) technique 2.1.1 ALD mechanism

Atomic Layer Deposition (ALD) method is a surface reaction technique in which ultra-thin films can be deposited sub-monolayer by sub-monolayer supply and purge cycles [2.1]. Figure 2.1 shows outline of ALD method.

Figure 2.1 Schematic illustration of one ALD cycle [2.1].

In dielectric films, active-surface by OH termination exchange react ligands of precursor with H elements, metal precursor absorbed surface. At this moment, metal strongly bond with substrate surface. This bonding state are called chemical bonding. Then, a pump and/or purge step is executed with an inert gas (typically Ar) during which the volatile reaction by-products are removed from the reactor along with the excess of precursor. In the second half of the cycle, the surface is exposed to a co-reactant (typically a gas, such as O2 or NH3, or a vapor such as H2O) which reacts with the surface which is now covered with the elements from the precursor, again in a self-limiting manner. After a pump and/or purge step to remove the reaction by-products

26 and the excess of co-reactant from the reactor, one ALD cycle is completed and the surface groups are equal to those with which the cycle started. Therefore, by controlling the number of reaction cycle, materials of an accurate film thickness are able to be deposited. In addition, the self-terminating mechanism gives ALD number of advantages, such as (1) Precise control of film thickness over larger wafers and (2) conformal deposition on 3D structure. Here, I would like to introduce ALD mechanism. ALD method is part of Chemical Vapor Deposition (CVD) method, is deposition technique using the surface reaction in the many of reaction. Figure 2.2 shows ALD reaction flow.

Main flow of reactant gases Gaseous by-products

① Boundary ⑤ layer

② Interface ③ ④ (negligible thickness)

Substrate

① diffusion in of reactants through boundary layer ② Adsorption of reactants on substrate ③ Chemical reaction take place ④ Desorption of adsorbed species ⑤ Diffusion out of by-products

Figure 2.2 Surface reaction mechanism of ALD technique.

The gas sources in the ALD chamber are absorb with surface by the surface diffusion (Figure 2.2 ① ~ ② ), absorption in surface by ligand exchange reaction ( ③ ). The by-products through ligand exchange reaction are desorption and out diffuse from surface (④~⑤). Adsorption can be divided into two general classes on the basic of the interaction between the adsorbing molecule (adsorptive) and the solid surface (adsorbent) physisorption and

27 chemisorption (Figure 2.3).

Adsorption

Physisorption Chemisorption (weak interaction) (strong interaction)

Figure 2.3 Adsorption classes.

There is a difference in adsorption power chemisorption and physisorption. The extra sources, piled up on the surface (image of physisorted precursors) eliminate using difference of adsorption power. Growth rate is not a size of one atomic layer or more. Because, two factors have been identified to cause the saturation of the surface with adsorbed species in a self-terminating gas- solid reaction (Figure 2.4): (a) steric hindrance of the ligands and (b) the number of reactive sites.

(a) Steric hindrance of the ligands

(b) Number of reactive surface sites

Figure 2.4 Factors identified to cause saturation of irreversible chemisorption: (a) steric hindrance of the ligands and (b) number of reactive surface sites [2.1].

Steric hindrance of the ligands can cause the ligands of the chemisorbed species to shield part of the surface from being accessible to the precursor reactant. The surface site can be considered “full”. The number of bonding sites on the surface may also be less than that required for achieving the maximum ligand coverage. In that case, although space remains available on

28 the surface, no bonding sites are accessible. In any case, the growth rate is constant value which is independent of reactants purge time (Figure 2.5(a)).

(a) Growth rate dependence on (b) Growth rate dependence on purge time growth temperature Precursor decomposition Precursor decomposition (CVD-like mode) Self-limiting growth Self-limiting growth (ALD mode) Etching reactions, desorption

ALD window

Growth rate / cycle / rate Growth Growth rate / cycle / rate Growth Low reactivity of the precursor

Purge time Growth temperature

Figure 2.5 ALD growth per cycle rate dependence on purge time of ALD reactants and schematic of possible behavior for growth rate dependence on growth temperature showing “ALD window” [2.2].

It is called self-limiting mode (or ALD mode) that the constant growth rate can be obtained without depending reactants supply time. On the other hands, the growth rate is increase in proportion to reactants supply time, this growth mode conceivable reaction in the gas phase (CVD mechanism) deposition. If growth rate is reduction in proportion to supply time, this is conceivable that desorption or loss of surface species reaction caused. As a result of the aforementioned reasons, low impurity in the deposited films are realizing by self-limiting reaction. The processing temperature range for ALD or the so- called “ALD window (or ALD mode)” is the region of nearly ideal ALD behavior between the nonideal regions as shown in figure 2.5(b). At lower temperatures, the reactants could condense on the surface or the surface reactions may not have enough thermal energy to reach completion. At higher temperatures, the surface species could decompose and allow additional reactant adsorption. This behavior is similar to CVD by unimolecular decomposition. The surface species needed for ALD could also desorb from the

29 surface at higher temperatures and be unavailable for additional surface reactions [2.2-2.3].

2.1.2 Selection of ALD precursor and oxidation source

The precursor was bonding with metal, because metal were reactive. For this reason, the difference ligands structure and type significantly change properties, such as ALD growth temperature condition etc. It is considered to be affect properties of high-k/InGaAs and gate leakage current by the changes such as growth temperature conditions. In this section, we introduce type and properties of the ALD precursors, and oxidants too. In the end, we introduce selected ALD precursor and oxidants. Figure 2.6 shows list of metal precursors for ALD reactants [2.1].

M M M M O O O X R n R n R n R n Halides Alkoxides β-diketonates Alkyls (X=F, Cl, Br, I) M M M M=Metal N R N N R=Alkyl groups n R n R R R n Cyclopentadienyls Alkylamides Amidinates

Figure 2.6 List of precursors for ALD/CVD technique [2.1].

M shows metal, R shows ligand, X shows other single atom, such as F. Cl, Br and I. Halides are the oldest class of ALD source. A benefit of halide reactants is the availability of volatile halides for many metals. Halides are also benefit generally regarded highly reactive and thermally stable. The high reactivity of halides is reflected in the variety of materials grown from them: oxides, nitrides, sulphides, etc. Alkoxides and β-diketonates has M-

O bonding. This bonding state is strong bonding. Similarly, alkylamides (alkys) and amidinates has M-N bonding. M-N bonding is strong too. Alkoxide were introduced as ALD reactants in the early 1990s. Decomposition at low temperatures is a typical drawback of alkoxide reactants. β-diketonates are in use as ALD reactants in the late 1980s. There are β -diketonates reactants available for groups 2-14 elements (except group 12 has not been demonstrated), which make them the most broadly used class of ALD reactants.β-diketonates cannot been made for nitride films. Similarly as for alkoxides, nitrides are missing from the type of materials made, which may be related to the difficulty of replacing the metal-oxygen bond in the β-diketonates with metal-nitrogen bond. Alkyls were introduced in the mid-1980s. Nowadays, alkyls are often used as reactants especially for aluminum and zinc. Alkyls are true organometallic compounds, which make them very reactive. Consequently, a variety of materials have been grown from alkyls (oxides, nitrides, sulphides, etc.). The alkyls ligands are also rather small, minimizing the steric hindrance effects, and the growth rate in alkyl-reactant-based process is often rather high. Cyclopentadienyls were introduced as ALD reactants in the early 1990s and have gained popularity in the 2000s. An advantage of the cyclopentadienyls is the fact that they can be synthesized also for alkaline-earth metals (such as lanthanum, etc.), for which other compounds have been scarce. Similarly as alkyls, cyclopetadienyls are organometallic containing a direct metal- carbon bond. This makes them reactive, and, for example, oxide can be grown through reaction with H2O. The gashouse by-products from reactions with the typical nonmetal reactants H2O, NH3 and H2S are presumably hydrocarbons, which do not readsorb on the surface, although studies of the gaseous reaction products have been rare. One study indicated the gaseous reaction product to be the hydrogenated ligands [2.1]. Figure 2.7 shows relationship between type of precursor and M-ligands bonding power.in general, the strong bonding power tends to be high growth temperature of ALD, because, needs high energy for break the M-ligand bond.

β-diketonates Amidinates

Alkoxides Alkylamides

Cyclopentadienyls

Alkyls Halides

precursor binding binding energy precursor -

M Figure 2.7 M-ligand bonding power with ALD reactants types.

Figure 2.8 show list of La-precursors with the growth temperature and the concentrate of impurities in the La2O3 films (on Si substrate).

Reactant type β -diketonate Silyamide Cyclopentadienyl Amidinate

Structural formula In the La La[N(SiMe3)2]4 o Growth 200 C ~ Around 175oC ~ 350oC ~ temperature 450oC o o o (bulky ligand) 250 C 300 C 500 C C: 3 at.% Impurities C: 11.5 at.% H: 20 at.% C: 0.44 at.% C, H, N in film H, O Si: 6 at.% (Pr[N(SiMe3)2]3/H2O) Ref. R. L. Puurunen., J. Appl. Phy. 97(2005)121301, T. Suzuki et al., J.Vac.Sci.Technol. A 30(2012)051507

Figure 2.8 list of La-precursors for ALD reactant [2.1, 2.4].

From above list, in this thesis, the triscyclopentadienyl-lanthanum

(La(iPrCp)3) is used as the metal source, because La(iPrCp)3 has excellent properties such as (1) the low impurity in the La2O3 films (carbon concentration = 0.44 at.%) and (2) the low growth temperature (175 to 300oC) [2.4]. In the second half of the cycle, the surface is exposed to an oxidants,

32 typically, such as H2O, O2, O3, N2O and H2O2. Given an example in Figure 2.9 [2.5].

H2O O2 plasma O3 plasma

Figure 2.9 The Al2O3 films deposited on Si substrate using H2O vapor, O2

plasma and O3 for oxidant source [2.5].

Al2O3 thin films were deposited on hydrogen-terminated (HF cleaned) Si substrate using trimethylaluminum (TMA) and an oxidant source H2O vapor,

O2 plasma, or O3. In the TEM analysis, interface layers with the thickness of about 1.7 and 1.3 nm were obtained in as-deposited Al2O3 using O2 plasma and O3. However, when using H2O vapor, the interfacial layer cannot be obtained. Reactive oxidants such as O2 plasma and O3 attacked Si substrate until its whole surface was fully covered with Al2O3 layer and thick enough to suppress the diffusion of oxidant source to Si surface. However, H2O vapor was not reactive enough to break H-Si bond and oxidize H-terminated Si surface, and consequently, apparent interfacial layer was not formed during the growth of Al2O3 films. In the InGaAs substrate, interface oxidizing were origin high Dit value. H2O vapor is suitable oxidant source for InGaAs substrate.

2.2 Fabrication process 2.2.1 InGaAs cleaning and Sulfur passivation

In this study, the InGaAs substrates were cleaned by using acetone, ethanol and DI (de-ionized) water. DI water is highly purified and filtered to remove all traces of ionic, particulate and bacterial contamination. The substrates were first degreased by acetone and ethanol in ultrasonic environment. Subsequently, the substrates were dipped in concentrated hydrofluoric acid (HF, 20%) for 2min. to remove native oxides. Then samples were rinsed in DI

33 water. Next, all substrates were immediately dipped in a (NH4)2S solution (concentration 6%) at room temperature for 20 min. to acquire a sulfur passivated surface. Finally, the cleaned substrates were transferred to the deposition chamber to avoid any extra re-oxidation of the substrate surface due to prolonged air exposure.

2.2.2 RF magnetron sputtering

Tungsten (W) and titanium nitride (TiN) which are used as gate metal in this study is deposited by radio frequency (RF) magnetron sputtering with As gas. An RF with 13.56 MHz at a power of 150W is applied between substrate side and separated. A magnet is set underneath the target, so that the plasma damage is minimized. Electrons run through the circuit from substrate side to target side is subjected to be conductive and target side is subject to be insulated. Then, target side is negative biased and Ar ions hit target.

2.2.3 Reactive ion etching

Reactive ion etching (RIE) is one of the patterning methods. Etching gas becomes the plasma in a similar way in the case of RF sputtering. However, RIE is not only physical but also chemical reaction. For etching of tungsten, HCl chemistry is used as etching gas in this study. The tungsten which is uncovered with resist reacts with Cl- and becomes WCl which is gas at room temperature. When the resist react is eliminated, O2 is used as etching gas and this process is called ashing.

2.2.4 Post metallization annealing (PMA) in FG ambient

Post metallization annealing (PMA) is effective to recover the defects in the dielectric film, which is made during fabrication process such as sputtering.

In addition, PMA is done in forming gas (FG) (N2:H2=97%:3%), so that the effect of recovering the dangling bonds of high-k/InGaAs substrate is a very important factor to achieve high quality MOS devices. In this study, different annealing condition such as annealing temperature are examined.

2.2.5 Vacuum evaporation for Al back side electrode

Al for wiring and backside contact is deposited by vacuum evaporation. Al source is set on W boat and heated up to boiling point of Al by joule heating. However, melting point of W is higher than boiling point of Al, W boat doesn’t melt. The base pressure in the chamber is maintained to be 10-3 Pa.

2.3 Characterization of MOS devices

2.3.1 Ideal CV characteristics of oxide/In0.53Ga0.47As capacitors

Figure 2.11 shows the schematic band structure of In0.53Ga0.47As at room temperature (T=300k) using the parameters from Ref. 2.6.

mГ = 0.043 mx = 0.74 mL = 0.42

E = 0.32 Г Ei

Ehh = -0.42

Figure. 2.11 Band structure of In0.53Ga0.47As at room temperature

The small electron effective mass of In0.53Ga0.47As results in small conduction band density of states (DOS) which causes the Fermi level move into conduction band at large electric fields. This means that for calculating electron density, the related equation for degenerate semiconductors must be used. Also the nonparabolicity of the lowest conduction band valley (Г) should be taken into account to allow for an accurate evaluation of band bending within the semiconductor. The ideal CV calculation is driven by solving the Poisson equation: 2 푑 푉(푥) 푑퐸(푥) 푒[푁푑 − 푁푎 + 푝(푥) − 푛(푥)] 2 = 퐸(푥) = − (2.1) 푑푥 푑푉(푥) 휀푠 Where Nd and Na are the donor and acceptor concentrations in the semiconductor, n(x) and p(x) are the electron and hole densities and εs is the

35 dielectric constant. The electric field E(x) inside the semiconductor can be calculated by integrating Equation (2.1) from the bulk of semiconductor to depletion region. The electron density equation assuming only Г valley occupations is given by: 2√휋 ∞ (퐸 − 퐸 )1/2 푛[푉(푥)] = 푁 ∫ 퐶 푑퐸 (2.2) 푘푇3/2 퐶 [퐸−푉(푥)]/푘푇 퐸퐶 1 + 푒 Where Ec is the conduction band edge energy, Nc is the effective density of states in the semiconductor conduction band and T is the temperature. If the higher lying conduction band valleys (X and L) are also taken into account for ideal CV calculations, a small upturn of capacitance in accumulation region at higher gate voltages is observed. This can be attributed to occupation of these valleys with electrons at high electric fields, however an upturn of capacitance in accumulation condition, in experimental data has never been observed. Therefore, only the occupation of Г valley is assumed for calculation of the ideal CV curve in this thesis. Total charge Qs per unit area inside the semiconductor can be obtained by Applying Gauss’s law and integrating Equation (2.2),

Φ푠 푄푠(Φ푠) = −2Sign(Φ푠) × √∫ −푒휀푠{푁푑 − 푁푎 + 푝[푉(푥)] − 푛[푉(푥)]}푑푉(푥) (2.3) 휓퐵 The ideal capacitance therefore can be expressed by:

푑푄푠(Φ푠) 퐶푠(Φ푠) = − (2.4) 푑Φ푠 The gate voltage causing the band bending ψs, is calculated from

푄푠(Φ푠) 푉𝑔 = Φ푠 + Δ휙푚푠 − (2.5) C표푥

An example of the calculated ideal CV for oxide/n-In0.53Ga0.47As interface with a doping concentration of 1×1016 cm-3 and considering the InGaAs band structure, is shown in Figure 2.7. The capacitance equivalent thickness (CET) is taken to be 2 nm, where accumulation capacitance is lower than the oxide capacitance (Cox) for the assumed CET value. Although this method for calculating CET is logical is used by many InGaAs research groups [2.7], evaluating CET on InGaAs capacitors is not always unified in the literature, since not all groups incorporate accurate band model as is described above. Therefore some reported CET values which have taken only the accumulation capacitance and not Cox for CET calculations, could be actually smaller if

36 adopted by this method. Also it should be noted that in Si-CMOS field, CET can be directly calculated from accumulation capacitance of the capacitor because unlike InGaAs, the density of states in conduction band of Si is large enough to enable accumulation capacitance reach Cox. Furthermore, it is universal amongst Si-CMOS to report Equivalent Oxide Thickness (EOT) of the capacitor which includes the quantum effect of carriers being limited to the surface of the channel regions [2.8]. Considering the quantum effect, EOT values are typically 0.3~ 0.4 nm smaller than CET value. The discrepancy of CET and EOT evaluation amongst Si and InGaAs devices which arises from different respective band structures needs a resolution as reports on InGaAs devices increase and a unified method is required to enable a fare comparison between different device structures.

6.00E-066.0 16 -3 n-In0.53Ga0.47As (Nd:1x10 cm ) 5.00E-06

) 5.0 2

4.00E-06/cm 4.0 CET= 0.5 nm μF

3.00E-063.0

2.00E-062.0

Capacitance ( Capacitance = 1.99 nm 1.00E-061.0

0.00E+000 -1.5 -1 -0.5 0 0.5 1 1.5 2 Gate voltage (V)

Figure. 2.12 Simulation of ideal CV characteristics for InGaAs MOS at room temperature.

2.3.2 Admittance characterization of MOS capacitors

Interface state density (Dit) of the high-k/InGaAs interface in this study is extracted by measuring the impedance of MOSCAPs as a function of voltage,

37 frequency, and temperature of high-k/semiconductor interfaces. Figure 2.13 shows a schematic energy band diagram of an n-type MOSCAP in depletion condition.

Depletion

e- Ec Ef ψB Ei Eg

Figure. 2.13 Band diagram of the semiconductor in depletion condition with majority carriers trapping and de-trapping at interface state sites.

A dc gate bias, Vg, with an AC signal (amplitude:25 mV and frequency f: 1 kHz~ 1 MHz) superimposed to it, is applied to the metal gate. The dc voltage modulates the position of the Fermi level at the interface while the superimposed ac signal causes the Fermi level to oscillate around that energy level. As a result, the traps within the Fermi level proximity are charged and discharged, creating a parasitic capacitance which is related to the interface trap density by Cit = qDit, where q is the elemental charge. The equivalent circuit model used for extracting the admittance of dielectric/semiconductor interface is shown in Figure 2.14, assuming that the minority carrier contribution in depletion condition is negligible.

Cox Cox

Cit Cs Cm Gm Cm Gm Git

Figure. 2.14 Equivalent circuit diagram of the MOS capacitance used in conductance measurements.

The conductance method is based on analyzing the loss that is caused by the change in the trap level charge state (2.6). The equivalent parallel conductance Gp is related to the measured impedance Gm by:

2 2 휔 퐶표푥퐺푚 퐺푝 = 2 2 2 (2.6) 퐺푚+휔 (퐶표푥−퐶푚) Interface traps in the proximity of Fermi level can change their occupancy. Maximum loss occurs when interface traps are in resonance with the applied ac signal frequency. Assuming that surface potential fluctuations can be neglected, the Dit is estimated from the normalized parallel conductance peak, (Gp/ω)max:

2.5 퐺푝 퐷𝑖푡 ≈ ( ) (2.7) 퐴푞 휔 푚푎푥 where A is the device area. Typically the portion of the band gap that can be probed by conductance measurement is from flatband to weak inversion. An accurate measurement of Cox is needed in order to use the conductance method for interface trap evaluation. However, in contrast to Si, using the accumulation capacitance to estimate Cox is not possible for n-type channels, because of the low conduction band DOS of III-V semiconductors. In this thesis, Cox is estimated by fitting the experimental results to theoretical ideal CV curve.

2.4 References

[2.1] R. L. Puurunen, “Sulface chemistry of atomic layer deposition: A case study for the trimehylaluminum/water process” J. App. Phy. 97(2005)121301.

[2.2] S. M. George, “Atomic Layer Deposition: An Overview” Chem. Rev. 110(2010) 111.

[2.3] O. Sneh, R. B. Clark-Phelps, A. R. Londergan, J. Winkler and T. E. Seidel, “Thin film stomic layer deposition equipment for semiconductor processing” Thin Solid Films, 402(2002) 248.

[2.4] T. Suzuki, M. Kouda, P. Ahmet, H. Iwai, K. Kakushima and T. Yasuda, “La2O3 gate insulators prepared by atomic layer deposition: Optimal growth conditions and MgO/La2O3 stacks for improved metal-oxide-semiconductor characteristics” J. Vac. Sci. Technol. A 30(2012) 051507.

[2.5] S. C. Ha, E. Choi, S. H. Kim and J. S. Roh, “Influence of oxidant source on the property of atomic layer deposited Al2O3 on hydrogen-terminated Si substrate” Thin Solid Films 476(2005) 252.

[2.6] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge, 1998.

[2.7] R. Engel-Herbert, Y. Hwang, and S. Stemmer, “Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces” J. App. Phys. vol 108, 124101, 2010.

[2.8] Y. Taur and T. H. Ning, “Fundamentals of modern VLSI devices” Cambridge press, 2009.

Chapter 3

Growth characteristics of ALD-La2O3 on InGaAs substrate

3.1 Growth condition of ALD-La2O3/InGaAs stacks 3.1.1 ALD condition 3.1.2 Growth condition 3.2 Effect of growth temperature and post metallization annealing (PMA) 3.2.1 MOS capacitor fabrication process 3.2.2 CV and interface state density (Dit) characteristics 3.2.3 Gate leakage current of MOS capacitors 3.3 Effect of Sulfur passivation for ALD-La2O3/InGaAs MOS capacitors 3.3.1 Physical properties 3.3.2 Electrical properties 3.4 Challenging for scaling and Conclusions 3.5 References

3.1 Growth condition of ALD-La2O3/InGaAs stacks 3.1.1 ALD condition

Figure 3.1 shows ALD reaction cycle for synthesizing La2O3 film, and table 3.1 shows ALD sequence conditions in this study.

1 Cycle Supply Gas: Supply Gas: Ar Purge i Ar Purge H2O La( PrCp)3

La2O3

n-InGaAs S: 1×1016 n-InGaAs n-InGaAs n-InGaAs n-InP n-InP n-InP n-InP

Figure 3.1 ALD reaction cycle for synthesizing La2O3 film.

Table 3.1 ALD sequence condition.

i Purge gaseous Ar La( PrCp)3 Ar Ar H2O Ar Supply time (sec.) 10 5 10 10 5 10

exhaust time 30 20 30 30 50 30 (sec.)

From table 3.1, Ar purge were needs twice, because by-products of La(iPrCp)3 is difficult reabsorb on surface. The gas feed times and exhaust times were investigated for optimal electrical performance of the capacitors. The surface reaction typically occur by elevating the substrate temperatures to 150 ~ 230oC.

3.1.2 Growth condition

In this section, growth condition of ALD using La(iPrCp)3 and H2O is considered. The effect of growth temperature during ALD cycles, on growth rate is shown in Figure 3.2.

0.24 0.22 0.2 0.18 ALD mode 0.16 0.14

Growth rate(nm/cycle) Growth 0.12 0.1 100 120 140 160 180 200 220 240 Growth temp. (oC)

Figure 3.2 Growth rate dependence on growth temperature.

The growth rate does not depending on growth temperature from 140 to 160oC. This result indicated that synthesized temperature needs to be below 160oC the self-limiting growth and that above 180oC give rise to the CVD-like mechanism. Figure 3.3(a) shows that growth rate dependence on La gas feed time for 140 and 150oC, (b) past work [3.1].

Growth temp. o 0.4 0.4 = 250 C CVD-like 0.3 0.3 mode [1] = 225oC Growth temp. = 140oC 0.2 0.2 = 200oC = 175oC o 0.1 = 150 C 0.1 = 150oC Growth rate(nm/cycle) Growth ALD mode [1] 0 0 0 2 4 6 8 10 12 0 2 4 6 8 10 12 i i La( PrCp)3 feed time(sec.) La( PrCp)3 feed time(sec.)

Figure 3.3 (a) the growth rate dependence on H2O purge time and (b) with reference date [3.1].

From figure 3.3(a), the growth rate does not depend on H2O purge time for growth temperature 140 and 150oC conditions. This results indicated that ALD mode are realized by growth temperature 140 to 160oC. Figure 3.4 shows

La2O3 thickness dependence on ALD cycles. La2O3 thickness were calculated from the XPS spectrum obtained by varying measurement angle [3.2] in 10,

20 cycles, and measurement from TEM cross-section, the La2O3 thickness has liner relation to ALD cycles. In this study, self-limiting growth (ALD mode) condition is clearly identified at growth temperature 140 to 160oC.

12 Extracted from TEM 10 In0.47Ga0.53As sub. 8 y = 0.1446x

6 Extracted

thickness (nm) thickness from XPS

3 4 O 2 Si sub. La 2 Extracted from ellipsometry 0 0 20 40 60 80 ALD cycle (cycle)

Figure 3.4 ALD-La2O3 thickness dependence on ALD cycle number.

3.2 Effect of growth temperature and post metallization annealing (PMA) 3.2.1 MOS capacitor fabrication process

In this section, ALD-La2O3 films on InGaAs substrate are revealed its characterization, such as crystalline and interface physical properties. After initial surface treatment, the substrate were loaded to ALD chamber for La2O3 films synthesis, followed by in-situ metal deposition by RF magnetron sputtering. A TiN (45 nm)/W (5 nm) metal gate was used as the gate electrode. The samples were post-metallization annealed in FG ambient for 5 min. Finally, Al was deposited on the back side of the InGaAs/InP substrate to form the back contact. (Figure 3.5)

16 -3 n-In0.53Ga0.47As (Nd=2×10 cm ) Acetone Ethanol cleaning + Oxide removal by HF (20%)

(NH4)2S treatment ALD-La O deposition 140oC < Growth temp. < 230oC In-situ 2 3 Gate electrode (TiN/W) deposition by RF sputtering

Reactive ion etching (RIE) (Cl2:Ar) of gate electrode

Post metallization annealing (PMA) in FG(N2:H2=97%:3%) for 5min. Backside Al contact TiN (45nm) W (5nm) Measurement ALD-La2O3 (75 cycles)

n-In0.53Ga0.47As Si: 2 x 1016 (cm-3) n-InP Al

Figure 3.5 Schematic illustration of MOS capacitor process.

3.2.2 CV and interface state density (Dit) characteristics

HR-XPS spectra of TiN(10nm)/W(5nm)/InGaAs MOS capacitor Figure 3.6 shows the XPS spectra for (a) As 2p3/2, (b) Ga 2p3/2, and (c)In 3d5/2 for a TiN (8 nm)/W (3 nm)/La2O3 (75 cycles, 150oC)/InGaAs MOS capacitors at as deposited and also after PMA 320, 420oC. Formation of all species of As and Ga oxides is effectively suppressed from as-deposited condition to annealing temperature up to 420oC. Small amounts of In-O bonds on the other hand, are detected for PMA at 420oC. Although InOx species are reported to be stable and do not degrade interface quality, they might contribute to increase in gate leakage current at scaled gate stacks.

hν= 7486.6eV, TOA= 90o

(a) As 2p3/2 (b) Ga 2p3/2 (c) In 3d5/2 Substrate

Substrate Substrate .)

In-S a.u TiNTiN(13nm)(8nm) In-OH no PMA W (3nm) In-O-La ALD-La2O3 o 75 Cycles

Intensity ( Intensity 320 C n-In Ga As 420oC 0.47 0.53

447 445 443 1327 1324 1321 1121 1119 1117 1115 446 445 444 443 1326 1323 1320Binding energy (eV)

Figure 3.6 XPS spectra of (a) As 2 p3/2, (b) Ga2 p3/2, and (c)In 3d5/2 of TiN/W/

ALD-La2O3(75 cycles)/InGaAs MOS capacitors

Cross-sectional TEM image of TiN(45nm)/W(5nm)/ALD-

La2O3(75cycles)/InGaAs MOS capacitor is shown in figure 3.7.

Figure 3.7 Cross-sectional TEM of TiN(45nm)/W(5nm)/ALD-

La2O3(75cycles)/InGaAs MOS capacitors (a) as-deposited sample and (b) forming gas annealed at 320oC for 5min. sample.

The crystalline of ALD-La2O3 has mixture of poly-crystalline and amorphous part, and a sharp ALD-La2O3/InGaAs interface can be observed with no void-like defects as was seen for HfO2/InGaAs interface [3.3]. When forming gas annealed at 320oC for 5min, thickness of La2O3 films on InGaAs has increased by 0.5nm, which predicts the intermixing of La2O3 and InGaAs and forming LaInGaOx interfacial layer. TEM image measure of

La2O3/InGaAs interface shows a smooth interface roughness of < 0.5 nm at annealing temperature 320oC. The use of fast fourier transforms for the estimation of ALD-La2O3 crystal structure in shown figure 3.8.

JCPDS 05-0602(La2O3 Hexagonal) [011] incidence d1=0.32nm d100=0.341 nm 1 Φ12=34.8o 2 d2=0.20nm d2-11=0.187 nm 3 Φ23=36.1o d1-11=0.298 nm d3=0.32nm Φ12=34.5o Φ23=29.6o

Figure 3.8 FFT image of ALD-La2O3 crystalline structure.

Obtained miller index from FFT image agree with joint committee for

48 powder diffraction standards (JCPDS) card number 05-0602 of hexagonal

La2O3. Analysis of crystal structure were indicated that the crystal structure of ALD deposited films have hexagonal La2O3. All above discussion, the detail of metal/ALD-La2O3/InGaAs structure is considered shown in figure 3.9. The crystal structure ALD-La2O3 has mixture hexagonal poly crystalline with amorphous, forming LaInGaOx interfacial layer (< 0.5 nm).

Poly crystalline TiN (hexagonal) W

Amorphous La2O3 ALD-La2O3 75 Cycles La-In-O, La-Ga-O or Sub-Oxides

In-S, Ga-S n-In0.47Ga0.53As

Figure 3.9 Schematic of TiN/W/ALD-La2O3/InGaAs MOS structure.

Figure 3.10 shows CV characteristics at 100 kHz of as-deposited and PMA of ALD-La2O3/InGaAs capacitors.

1.2 Growth temp. 160oC

ALD-La2O3 (11nm)

) 1 2 100kHz

/cm 0.8

μF no 0.6 PMA

0.4 w/ S PMA o Capacitance( 0.2 320 C

0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 Gate voltage (V)

Figure 3.10 CV characteristics at 100 kHz of ALD-La2O3/InGaAs capacitors.

The clear stretch-out observed in as-deposited CV response is mostly eliminated by performing annealing, this result indicated that impurities in

La2O3 films reduced by annealing in FG. Impurities in the synthesized film were reduced by PMA in FG.

The CV characteristics of TiN (45 nm)/W (5 nm)/La2O3/InGaAs capacitors with ALD synthesized La2O3 film after PMA 320oC is shown in Figure 3.11. ALD is performed for 75 cycles and the substrate temperature is set to (a) 150 and (b) 180oC during the deposition.

PMA 320oC PMA 320oC 1.2E-061.2 1.2 1.1E-06 (a) Growth temp. = 150oC 1.1 (b) Growth temp. = 180oC

1.0E-06) 1.0 1 ) 2 Hysterisys = 3.0mV 1.0 Hysterisys = 140mV

9.0E-07 2 0.9 /cm

8.0E-070.8 CET = 2.3nm /cm 0.8 CET = 2.6nm μF 7.0E-07 μF 0.7 5 kHz 6.0E-070.6 5 kHz 0.6 10 kHz 5.0E-07 10 kHz 0.5 100 kHz 4.0E-070.4 100 kHz 0.4 3.0E-07 0.3 1 MHz

Capacitance ( 1 MHz 2.0E-070.2 Capacitance ( 0.2 1.0E-07 Ideal C-V 0.1 0.0E+000 00 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 Gate voltage (V) Gate voltage (V)

Figure 3.11 CV characteristics of metal/ALD-La2O3(75cycles)/InGaAs MOS capacitor deposited at (a) 150 and (b) 180oC after PMA in FG at 320oC for 5min.

Samples fabricated at a growth temperature of 150oC exhibit superior capacitance-voltage (CV) response with reduced frequency dispersion in all bias conditions. The capacitance value is normalized to Cmax. Figure 3.11(a) compares the CV characteristics of ALD-La2O3 capacitors. Identical CV characteristics for both ALD deposited capacitors indicate the formation of high quality of interface. At 180 oC growth temperature, samples show large hysteresis. The hysteresis has been attributed to formation of elementary arsenic (As) at the interface of La2O3/InGaAs. Oxide species of As (AsOx) are easiest to form, but are also very unstable and disintegrate to more stable

GaOx and elemental As, when annealing capacitors [3.4-3.5]. Hysteresis for the CV characteristics of the capacitors, are compared as a function of ALD growth temperatures for various PMA temperatures, in Figure 3.12 and 3.13.

Vfb-1.5V → Vfb+1.5V 100 PMA temp. 470oC

mV) o ( 0 420 C 370oC 320oC

flatband -100 at at

-200 Hysterisys -300 120 140 160 180 200 220 240 Growth temperature (oC)

Figure 3.12 Hysteresis dependence of metal/ La2O3 (75cycles)/InGaAs capacitors at 100 kHz, on growth temperature of PMA temperature.

Vfb-1.5V → Vfb+1.5V 100 Growth temp. 180oC 160oC

(mV) 0 150oC 140oC

-100

flatband at

-200 Hysterisys -300 300 350 400 450 500 PMA temperature (oC)

Figure 3.13 Hysteresis dependence of metal/La2O3 (75cycles)/InGaAs capacitors at 100 kHz, on PMA temperature of growth temperature.

It is found that lowest hysteresis values can be achieved for growth temperature of 140 to 150oC (ALD-mode deposition). A minimum hysteresis value of 5mV is obtained for the capacitor with La2O3 growth temperature of 150oC and PMA at 320oC in FG. A higher growth temperature however, cause a sharp increase in the hysteresis. These fact mean that the ALD-mode deposition can effectively modify the quality of InGaAs native oxide and reduce the density of slow traps causing hysteresis.

Figure 3.14(a) shows CV characteristics InGaAs capacitor with La2O3 (75cycles) films deposited at 150, 160, 180 and 230oC.

(a) (b) ALD CVD like PMA 320oC mode mode 1.2E-061.2 4 1.1E-06 100 kHz CET = 2.3nm

) 75 cycles 1.0E-062 1.0 Growth temp.

9.0E-07 150oC 3.5 /cm

8.0E-070.8 160oC μF 7.0E-07 o 6.0E-070.6 180 C 3 o PMA temp. 5.0E-07 230 C CET = 3.2nm (nm) CET 470oC 4.0E-070.4 o 3.0E-07 2.5 420 C o 2.0E-070.2 370 C 1.0E-07( Capacitance 320oC 0.0E+000 2 -1.5 -1 -0.5 0 0.5 1 1.5 120 140 160 180 200 220 240 Gate voltage (V) Growth temp. (oC)

Figure 3.14 (a)CV characteristics InGaAs capacitor with La2O3 (75cycles) films deposited at 150 to 230oC, (b) CET values of La2O3/InGaAs capacitors dependence on the growth temperature.

It is found that CV characteristics depend on growth temperature. CET values of InGaAs capacitor increased and the upturn of capacitance in negative bias is suppressed by lowering growth temperature at 150 and 160oC.

Figure 3.14(b) shows capacitance equivalent SiO2 thickness (CET) value of

La2O3/InGaAs capacitors have lowest at grown 140 and 150oC by PMA at 320oC. The smaller CET values for lower annealing temperatures could be due to the presence of low impunity and low defect in synthesized films. Conductance method was used to quantitatively evaluate the interface

53 state density (Dit) of samples at various growth temperatures and the results are shown in Figure 3.15 and 3.16. The increase in Dit value for higher annealing temperatures is the similar to EB deposited samples. However a sharper increase for ALD case is observed. The smaller Dit values for lower annealing temperatures could be due to the presence of residual carbon (C) atoms within the synthesized dielectric film which diffuses towards the interface as the annealing temperature increases. Further physical analysis of the film is necessary to accurately characterize the quality of film and its impurity level. Adjusting the purge and exhaust time during deposition cycles, has been reported to be effective in reducing the impurity levels within the dielectric layer [3.6-3.8], therefore further optimization of experimental procedure is required.

E-Ei = 0.1 eV 101.E+1313

75 cycles

)

cm 1 - 12 101.E+12 Growth temp. (eV 230oC it CVD-like mode o D 180 C 160oC ALD mode 150oC 140oC 101.E+1111 300 350 400 450 500 PMA temperature (oC)

Figure 3.15 Growth temperature effect on Dit of TiN/W/ALD-

La2O3(75cycles)/InGaAs MOS capacitors as a function of PMA temperature.

E-Ei = 0.1 eV

1.E+131013

)

1 -

1.E+12(eV 1012

it PMA temp. D 470oC 420oC 370oC 320oC

1.E+111011 120 140 160 180 200 220 240 Growth temperature (oC)

Figure 3.16 Dit of TiN/W/ALD-La2O3(75cycles)/InGaAs MOS capacitors as a function of growth temperature at various PMA temperature.

Figure 3.17 shows Dit of TiN/W/La2O3(75cycles)/InGaAs MOS capacitors as a function of CET value at various growth temperature. In summaries, these above results indicated that the high quality interface properties can be obtain from low deposition temperature.

E-Ei = 0.1 eV 1.00E+131013 75 cycles

PMA 320oC

)

cm 1

- o 1.00E+121012 230 C

(eV 180oC it

D 160oC Growth temp. = 150oC 1.00E+111011 2 2.5 3 3.5 CET (nm)

Figure 3.17 Dit of TiN/W/La2O3(75cycles)/InGaAs MOS capacitors as a function of CET value at various growth temperature.

3.2.3 Gate leakage current of MOS capacitors

Figure 3.18 and 3.19 summarized the gate leakage current behavior of the two samples at various deposition temperatures. The sample with ALD mode has five orders of magnitude smaller leakage current density at 320oC PMA. The growth rate at 180oC was as high as 0.17nm/cycle (see Figure 3.2), indicating that a significant portion if the growth took place via the CVD like mechanism. Therefore, it is speculated that the La2O3 films grown in the CVD mode included more carbon impurities due to the CVD mechanism, which should degrade the film quality.

PMA 320oC, FG 1.0E+0110 Growth temp. at 230oC 1.0E+001 (CVD-like mode)

1.0E-0110-1 ) 2 1.0E-0210-2

1.0E-0310-3 (A/cm

1.0E-04g -4 J 10 1.0E-0510-5 Growth temp. at 150oC -6 1.0E-0610 (ALD mode) 1.0E-0710-7 1.0E-0810-8 0 0.25 0.5 0.75 1 Gate Voltage (V)

Figure 3.18 JV characteristics of TiN/W/La2O3(75cycles)/InGaAs MOS capacitors deposited at 150 and 180oC.

1.E+0110 1.E+001

) -1

2 1.E-01

) 10 2 1.E-0210-2 1.E-0310-3

1.E-0410-4 PMA temp. at 1V (A/cm 1V at

at 1V(A/cmat o 1.E-05-5 470 C g 10

Jg o J 420 C -6 1.E-0610 370oC 1.E-0710-7 320oC 1.E-0810-8 120 140 160 180 200 220 240 Growth temperature (oC)

Figure 3.19 Gate leakage current of various deposition temperature from

150 to 230oC at Vg=1V as a function of PMA temperature.

Figure 3.19 shows gate leakage current of TiN/W/La2O3(75cycles)/InGaAs

MOS capacitors as a function of CET value at various growth temperature. In summaries, these above results indicated that the high quality films can be obtain from low deposition temperature.

CVD-like La2O3 Gate Metal

o High PMA 320 C La2O3 1.00E+01101 impurities 75 cycles 1.00E+001 Surface

) o In0.53Ga0.47As oxidation 1.00E-012 10-1 230 C

1.00E-02-2 10 Growth temp. o (A/cm 180 C = 150oC 1.00E-0310-3 ALD-La O 1V 1V 2 3

1.00E-04at 10-4

g Gate J 1.00E-0510-5 Metal

-6 1.00E-0610 160oC La2O3 1.00E-0710-7 2 2.5 3 3.5 In0.53Ga0.47As CET (nm)

Figure 3.20 Gate leakage current (Jg) of TiN/W/La2O3(75cycles)/InGaAs MOS capacitors as a function of CET value at various growth temperature.

3.3 Effect of Sulfur passivation for ALD-La2O3/InGaAs MOS capacitors 3.3.1 Physical properties

Figure 3.21 shows the Ga 3s and S 2p XPS spectra for ALD-La2O3 (10 cycles)/InGaAs structure.

Figure 3.21 XPS spectra of S 2p and Ga 3s peaks for ALD-La2O3/InGaAs with and without S-passivation.

The S-passivated sample, shown in row TOA=20o, reveals clear S 2p peaks (162~163eV) suggesting passivation of sulfur atoms. Analysis of

La2O3/InGaAs chemical state 10 cycles of oxide deposition shows clear presence of S close to the interface for sulfur passivated devices, indicated that sulfur atoms are not evaporated from the surface during the ALD process.

Figure 3.22 shows the As 2p3/2, Ga 2p3/2 and In 3d5/2 XPS spectra for (a) HF (20%) treated sample and (b) HF(20%) with S treatment after cleaning samples. The S-passivated sample, shown in (b), reveals clear As+3 (~3.6 eV chemically shifted from the substrate peak), Ga+3 (~1.0eV chemically shifted from the substrate peak) and In+3 (~1.0eV chemically shifted from the substrate peak) suggesting oxidation formed during the growth of La2O3 films. The ratio of In, Ga and As trivalent-oxide (M+3 peak) or sub-oxide (M+1 peak) state peak intensity to un-oxidized substrate peaks are shown in figure 3.23. By S-passivation, As+3 and Ga+3 peak intensities has reduced by 20%, whereas Ga+1 and In+1 peak intensities are increased by 101 and 120%. In+1 or Ga+1 have considered to form compounds of M-S, M-O-La and sub-oxide species. Using S-passivation, it is known that the sulfur was bonded with In, Ga or As atoms [3.9-3.10]. This bonding state known to obtained chemical stable high- k/InGaAs interface. By S-passivation, the oxidation of interface could be converted to more stable Ga and In state in the system.

hν= 1486.6eV, TOA= 90o As 3d Ga 2p 1+ In 3d Ga 5/2 Sub Sub Sub Sub Ga-S In1+ HF(20%) As3+ Only Ga3+ In3+

Intensity (a. u.) (a. Intensity HF(20%) +

(NH4)2S

47 45 43 41 39 112237 1120 1118 1116 1114447447 446 445 444 443 442 Binding Energy (eV)

Figure 3.22 XPS spectra of ALD-La2O3/InGaAs (a) without and (b) with S- passivation.

M3+ (M2O3) M1+ (M-O-La, M-S, Sub Ox.) 0.4 0.14 HF(20%) Only HF(20%) Only 0.35 0.12 HF(20%) + 0.3 0.1 (NH4)2S 0.25 HF(20%) + 0.08 0.2 (NH4)2S 0.06 peakintensity ratio 0.15 0.1 0.04 sub. No 0.02 0.05 detect 0 0 As3+ In3+ Ga3+ As1+ In1+ Ga1+

Oxide to /Sub /Sub /Sub /Sub /Sub /Sub

Figure 3.23 Measured intensity ratio of oxides of with and without S- passivation samples.

The La2O3 deposition thickness at growth temperature of 150 oC, is calculated from La 3d5/2 peak intensity for 10 and 20 cycles of deposition

(Figure 3.24).

3.0 ALD growth

2.5 temp:150oC (nm) 2.0

1.5

hickness

t 3

O 1.0 2

La HF only 0.5 HF+(NH4)2S 0.0 0 10 20 30 ALD cycles

Figure 3.24 La2O3 deposition rate for growth temperature of 150oC with and without Sulfur treatment.

Same deposition rate of ~0.85 nm/cycle is obtained regardless of the surface treatment method. It is not observed effect of the ALD-La2O3 film thickness by Sulfur treatment.

Figure 3.25 shows schematics of interface chemical state in the ALD-La2O3 (10cycles)/InGaAs structure.

w/o S-passivation w/ S-passivation No-PMA M O ALD-La2O3 2 3 ALD-La2O3 10 Cycles (Trivalent oxides) 10 Cycles La-In-O, La-Ga-O or Sub-Oxides n-In Ga As n-In Ga As 0.47 0.53 In-S, Ga-S 0.47 0.53

Figure 3.25 Schematic of effect on S-passivation for ALD-La2O3/InGaAs interface chemical state.

S-passivation can prevent the interfacial oxidized layer form forming.

3.3.2 Electrical properties

Figure 3.26 shows the effect on S-passivation for capacitance-voltage (CV) characteristics of metal/La2O3/InGaAs MOS capacitors annealed in FG (a)

EB-deposited La2O3 and (b) ALD deposited La2O3. In this case, the annealing temperature is elevated 370oC for EB-deposited La2O3 and 320oC for ALD-

La2O3.

(a) EB deposited La2O3 (b) ALD deposited La2O3 1.4 1.2 Growth temp. 160oC

La2O3 = 10.5nm ) 1.2 2 1 75 cycles (10.5nm)

) 100kHz 2 100kHz

w/o S /cm

1 0.8 /cm PMA μF w/ S o μF 0.8 o 370 C 0.6 PMA 320 C w/o S 0.6 CET PMA 0.4 =2.4 nm 320oC 0.4 w/ S CET PMA 0.2 ( Capacitance 0.2 o =2.6 nm Capacitance ( Capacitance 370 C 0 0 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 Gate voltage (V) Gate voltage (V)

Figure 3.26 the effect on S-passivation for CV characteristics of

metal/La2O3/InGaAs capacitors using (a) EB and (b) ALD deposition technique.

A very different capacitance response is obtained between the two MOS capacitors. The without S-passivation samples in ALD-La2O3 shows superior CV response with significant reduction in stretch-out in enter voltage sweep range. Moreover, the capacitance bumps, in inversion region are resolved compared with EB-deposited samples for without S-passivation using EB methods is indicative of high midgap interface state density [3.11]. This is because the surface potential (Ψs) is not able to effectively sweep the InGaAs

62 bandgap due to the presence of interface states, therefore the inversion layer cannot be formed and the depletion capacitance is affected by the gate voltage.

Interface state density (Dit) dependence on PMA temperature shown in figure 3.27.

13 5x10 EB deposition w/o S La2O3 = 10.5nm 13

1.00E+1310

) 2

- w/ S

cm 1 - ALD

w/o S (eV

it 1.00E+1212 D 10 w/ S Growth temp. = 160oC 75 cycles (11nm) 1.00E+111011 270 320 370 420 470 PMA temperature (oC)

Figure 3.27 The Dit dependence on PMA temperature.

EB deposited samples has large difference with and without S-passivation, but ALD deposited samples shows almost same Dit values in annealing temperature 320 to 370oC. In high temperature > 420oC, without S- passivation samples has slightly increasing Dit value, because the S- passivation sample can be maintain chemically and electrically stable interface property at high temperature annealing. However, the gate leakage current of S-passivated samples shows increasing by high temperature annealing (Figure 3.28).

1.00E-0310-3

1.00E-0410-4 ) 2 ALD (11nm) w/ S EB deposition 10.5nm

1.00E-0510-5 (A/cm Out diffused sulfur was 1.00E-06 1V 10-6

at caused leakage current. g J w/o S 1.00E-0710-7 Gate Metal La O 1.00E-0810-8 2 3 S SS 270 320 370 420 470 S S S S S S PMA temperature (oC) In0.53Ga0.47As

Figure 3.28 The gate leakage current dependence on PMA temperature.

This result is indicated that out diffused sulfur atoms by high temperature annealing was caused leakage current. In this study, S-passivation is not affected the Dit value in ALD technique, because the amount of In+1, Ga+1 oxide peak ratio are almost unchanged (see Figure 3.25). Hence, sub-oxide state (M+1) forming ALD deposition are estimated In-O-La and Ga-O-La bonds. Electrical interface property (such as Dit) is decided by interface oxide state, ALD-La2O3 technique was formed LaInGaOx during deposited films. Moreover, at high temperature, sulfur atoms out-diffuse and caused increasing leakage current. However, S-passivation samples can slightly reduce the CET values 2.6 to 2.4 nm, this result is considered that with S- passivation samples can be prevent forming InGaAs substrate oxidized interfacial layer.

3.4 Challenging for scaling and Conclusions

Main obstacle of ALD-La2O3 is high leakage current. It is considered that

ALD deposited La2O3 films has low films density. Oxidation process in the ALD sequence is important for deposited films qualities, such as film density or amount of impunity in the film. I challenged more high scalability film deposition by H2O vapor time optimize. Figure 3.29 and 3.30 shows CV characteristics and benchmark of (a) interface state density (Dit) and (b) gate leakage current (Jg) as a function of CET between capacitors fabricated in this thesis with other recently reported results [3.12-3.16].

Growth temp. = 150oC 75 cycles CET= 1.6E-061.6 100kHz 1.6nm

1.4E-061.4 )

2 t = 15 sec. 1.9nm 1.2E-061.2 H2O

/cm 2.3nm 1.0E-06

μF 1.0 tH2O = 8.0E-070.8 10 sec. t = 6.0E-070.6 H2O 5 sec.

4.0E-070.4

Capacitance ( Capacitance Capacitance (mF/cm2) Capacitance 2.0E-070.2 0.0E+000 -1.5 -1 -0.5 0 0.5 1 1.5 Gate Voltage (V) Figure 3.29 CV characteristics of ALD-La2O3/InGaAs MOS capacitors grown

by various tH2O from 5 to 15 sec.

(a) E-E = 0.1 eV (b) i 1.E+0110 La2O3/Si/InGaAs EB-La O [3.12] 1E+1313 2 3 10 [3.13] 1.E+001 tH2O =

tH2O = ) 2 5 sec. ) 1.E-01-1 2 10 - 15 sec. 2) HfO2 - [3.14] -2 cm 1.E-0210 t = 1 ZrO H2O

- 2 HfO2/Al2O3 1cm [3.15]

- 15 sec. 1E+121012 [3.16] 1.E-0310-3

(eV ZrO2 /Al2O3 tH2O = it

[3.15] (A/cm 1V at -4 D 5 sec. 1.E-04 g 10

EB-La2O3 [3.12] J La2O3/Si/InGaAs Dit (eV Dit

1.E-0510-5 [3.13] Jg at Vg=1V (A/cm2) Vg=1V at Jg 1E+111011 1.E-0610-6 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 CET (nm) CET (nm)

Figure 3.30 (a)Dit and (b) Jg vs CET benchmark of capacitors in this work with recent published results [3.12-3.16].

Increase of oxidation time can obtained high CET value with low leakage current. These result indicated needs the high power oxidation process, such as plasma or H2O2 etc., for synthesizing high quality film.

High quality interface properties ALD deposited La2O3 on InGaAs were fabricated by self-limiting growth mode (ALD mode) deposition technique.

Self-limiting surface reaction using La(iPrCp)3 and H2O vapor is indicated formed LaInGaOx interfacial layer (<0.5nm) during synthesized La2O3. ALD

La2O3 deposited technique can be eliminated the sulfur passivation process in pre-treatment. Elimination of S-passivation process is an advantage to prevent sulfur damage for process chamber. However, S-passivation can be prevent the forming interfacial oxidation layer (composed of trivalent oxide spaces), interfacial oxidation layer cause increase the CET value. However,

ALD-La2O3 using La(iPrCp)3 and H2O vapor has high leakage current, due to poly crystalline and high contained impurities. Figure 3.29 shows schematic of TiN/W/ALD-La2O3/InGaAs with or without S-passivation at pre-treatment.

66 w/o S-passivation w/ S-passivation

TiN Poly crystalline TiN (hexagonal) W W

ALD-La2O3 Amorphous La2O3 ALD-La2O3 75 Cycles 75 Cycles La-In-O, La-Ga-O IL < 0.5nm n-In0.47Ga0.53As In-S, Ga-S n-In0.47Ga0.53As

M2O3 (Trivalent oxides)

Figure 3.29 Schematic illustrating the effect of S-passivation of the

interfacial layer at ALD-La2O3/InGaAs interface.

3.5 References

[3.1] T. Suzuki, M. Kouda, P. Ahmet, H. Iwai, K. Kakushima and T. Yasuda, “La2O3 gate insulators prepared by atomic layer deposition: Optimal growth conditions and

MgO/La2O3 stacks for improved metal-oxide-semiconductor characteristics” J. Vac. Sci. Technol. A 30(2012) 051507.

[3.2] 奥田和明, 伊藤秋男, “X 線光電子分光法による薄い金属表面酸化膜の膜厚測定” Jap. Sci. Anal. Chem. 40(1991) 691.

[3.3] D. Zade, K. Kakushima, T. Kanda, Y.C. Lin, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, E. Y. Chang, K. Natori, T. Hattori and H. Iwai, “Improving electrical characteristics of

W/HfO2/In0.53Ga0.47As gate stacks by altering deposition techniques” Microelec. Eng., 7(88) (2011) 1109.

[3.4] R. P. H. Chang, T. T. Sheng, C. C. Chang, J. J. Coleman, “The effect of interface arsenic domains on the electrical properties of GaAs MOS structures” Appl. Phys. Lett. 33(1978) 341

[3.5] C. D. Thurmond, G. P. Schwartz, G. W. Kammlott, B. Schwartz, “GaAs Oxidation and the Ga-As-O Equilibrium Phase Diagram” J. ElectroChem. Soc. 127(6) (1980) 1366.

[3.6] S. D. Elliot, “Improving ALD growth rate via ligand basicity: Quantum chemical calculations on lanthanum precursors” Surf. & Coating Technol. 201(2007) 9076.

[3.7] D. Eom, S. Y. No, C. D. hwang and H. J. Kim, “Deposition Characteristics and

Annealing Effect of La2O3 Films Prepared Using La(iPrCp)3 Precursor” J. ElectroChem. Soc. 154(3) (2007) G49.

[3.8] S. Y. No, D. Eom, C. S. Hwang and H. J. Kim, “Properties of lanthanum oxide thin films deposited by cyclic chemical vapor deposition using tris(isopropyl- cyclopentadienyl)lanthanum precursor” J. Appl. Phy. 100(2006) 024111.

[3.9] B. Brennan, D. M. Zhernokletov, H. Dong, C. L. Hinkle, J. Kim and R. M.

Wallace, “In situ pre-treatment study of GaAs and In0.53Ga0.47As” Appl. Phy. Lett. 100(2012) 151603.

[3.10] H. D. Trinh, E. Y. Chang. P. W. Wu, Y. Y. Wong, C. T. Chang, Y. F. Hsieh, C. C. Yu, H. Q. Nguyen, Y. C. Lin, K. L. Lin and M. K. Hudait, “ The influences of surface treatment and gas annealing conditions on the inversion behaviors of the atomic- layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitor” Appl. Phy. Lett. 97(2010) 042903.

[3.11] Y. Hwang, R. Engel-Herbert, N. G. Rudawski, and S. Stemmer. “Analysis of trap state densities at HfO2/In0.53Ga0.47As interfaces” Appl. Phys. Lett. 96(2010) 102910.

[3.12] D. Hassan Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.

[3.13] D. H. Zadhe, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori and H. Iwai, “Scalable La-silicate Gate Dielectric on InGaAs Substrate with High Thermal Stability and Low Interface State Density” SSDM p. 714, 2013.

[3.14] V. Chobpattana, J. Son, J. J. M. Law, R. Engel-Herbert, C.-Y. Huang, and S. Stemmer, “Nitrogen-passivated dielectric/InGaAs interfaces with sub-nm equivalent oxide thickness and low interface trap densities”, Appl. Phys. Lett., 102(2013) pp.022907.

[3.15] J. Huang, N. Goel, H. Zhao, C. Y. Kang, K.S. Min, G. Bersuker, S. Oktyabrsky, C.K. Gaspe, M.B. Santos, P. Majhi, P. D. Kirsch, H.-H. Tsengd, J.C. Lee, and R. Jammy., “InGaAs MOSFET Performance and Reliability Improvement by Simultaneous Reduction of Oxide and Interface

Charge in ALD (La)AlOx/ZrO2 Gate Stack”, IEDM, p. 335, 2009.

[3.16] S. Takagi, R. Zhang, S.-H Kim, N. Taoka, M. Yokoyama, J.-K. Suh, R. Suzuki and M. Takenaka, “MOS interface and channel engineering for high-mobility Ge/III-V CMOS”, IEDM, p. 505, 2012.

Chapter 4 Electrical properties of InGaAs nMOSFETs with ALD-La2O3

4.1 Transistor fabrication process 4.2 Electrical characteristics 4.3 Conclusions 4.4 References

4.1 Transistor fabrication process

The fabrication process for InGaAs-based transistors is summarized in

Figure 4.1. p- type In0.53Ga0.47As (100) substrates epitaxially grown on InP substrate with doping concentration of 2×1017 cm-3, were cleaned by acetone/ethanol followed by surface oxide removal by concentrated HF (20%).

A 400 nm protective SiO2 layer was deposited by chemical vapor deposition

(CVD) using Tetraethyl orthosilicate (TEOS) gas. The SiO2 layer was patterned and etched away by BHF to create diode contact areas. Substrates were then transferred to an RF sputtering chamber for Ni deposition. After the 10 nm of Ni deposition samples were annealed in N2 at 250oC to form Ni- InGaAs alloy at the contact areas. The samples were then subjected to BHF and HF 10% to remove metal and SiO2 simultaneously from non-contact regions in a lift-off process and thus form the Source/Drain contact regions. A second SiO2 layer with TEOS was subsequently deposited and patterned to create field isolation. Channel area was cleaned and passivated by (NH4)2S as described in previous sections. The substrates were the loaded to ALD chamber for La2O3 films synthesis at 150oC for 75 cycles, followed by in-situ metal deposition by RF sputtering. A TiN(45 nm)/W(5 nm) metal gate was used as the gate electrode. The samples were post-metallization annealed in forming gas ambient (N2:H2 = 97%:3%) for 5 min. After Source/Drain contact formation, Al was deposited on the back side of the InGaAs/InP substrate to form the back contact.

17 -3 p-In0.53Ga0.47As (Nd=1×10 cm ) Acetone Ethanol cleaning + Ni-alloy Ni-alloy Oxide removal by HF (20%) p-InGaAs (Zn: 1×1017) SiO2 deposition (100 nm by TEOS) for channel region protection Ni deposition (10 nm by sputtering ) Low temperature anneal (250oC, N , 1min.) 2 ALD-La2O3 SiO2 removal by BHF (S/D formation)

S/D field SiO2 deposition SiO2 SiO2 (400 nm by TEOS)

Channel cleaning (HCl 10%, (NH4)2S) Ni-alloy Ni-alloy 17 -3 ALD-La2O3 deposition p-InGaAs (Zn: 1×10 cm ) (150oC, 75 cycles) In-situ Gate electrode deposition TiN/W Ni-alloy by sputtering TiN/W Gate patterning, S/D contact, Al pad deposition Al Al FG anneal for 5 min.

Backside Al contact

Measurement Ni-alloy Ni-alloy p-InGaAs (Zn: 1×1017cm-3) Al

Figure 4.1 Fabrication process flow of InGaAs MOSFET fabrication

The outline of the mask used for MOSFET fabrication in this thesis is shown in Figure 4.2. The spacing off-set for channel and gate metal edges is designed at 2μm tolerance.

Al pad Channel Al pad

SD contact Field Isolation CVD-SiO Metal Gate 2

Figure 4.2 Mask outline used to fabricate InGaAs MOSFETs.

4.2 Electrical characteristics

Figure 4.3 shows drain current- drain voltage (ID-VD) characteristics of

TiN(45 nm)/W(5 nm)/ALD-La2O3(75 cycles at 150oC)/p-InGaAs after PMA 320oC. Well-behaved MOSFET operation is confirmed albeit the apparent high contact resistance at source/drain.

X 10-4 6.E-046.0 L/W = 20/50 mm

4.E-044.0

VGS= 0～1.6V

(A)

D I

2.E-042.0

0.E+000 0 0.2 0.4 0.6 0.8 1

VD (V)

Figure 4.3 ID-VD characteristics of TiN(45 nm)/W (5 nm)/ALD-La2O3 (75 cycles at 150oC)/p-InGaAs after PMA 320oC.

ID-Vg chracteristics of the same MOSFET at a linear and saturation drain voltage (VD) of 50 mV and 1 V are shown in Figure. 4.4 A substhreshold slope (SS) of ~ 139 mV/dec is exctracted which is roughly similar to the reported values for Al2O3 gate stacks on planar InGaAs MOSFETs [4.3], indicating a high quality of high-k/InGaAs interface.

1.E-0310-3 L/W = VD= 1 V 20/50 mm 1.E-0410-4

1.E-05(A) -5 VD= 50 mV

D 10 I

1.E-0610-6 SS= 139 mV/dec 1.E-0710-7 -0.5 0 0.5 1 Vg (V)

Figure 6.4 ID-Vg characteristics of TiN(45 nm)/W (5 nm)/ALD-La2O3 (75 cycles at 150oC)/p-InGaAs after PMA 320oC.

The gate to channel CV characteristics of MOSFET in 100 kHz ( Figure

4.5) was used to calculate the ffective mobility (µeff). The CET= 1.1 nm is extracted by fitting the curve to the ideal CV as described in chapter 2. The effective mobility characteristics as a function of surface carrier concentration is shown in Figure 4.6.

2 CET = 1.1 nm

)

F/cm m

( 1

gc C

100 kHz 0

-1 -0.5 0 0.5 1 1.5 Vg (V)

Figure 4.5 100 kHz split C-V characteristics of Ni-SD InGaAs MOSFET with ALD-

La2O3.

1000

)

Vs / 2 CET = 1.1 nm

100 Mobility (cm Mobility

10 1.E+12 1.E+13 -2 Ns (cm )

Figure 4.6 Mobility characteristic of InGaAs MOSFET with ALD-La2O3.

Figure 4.7 shows the high field mobility mobility vs. CET plot for various reported high-k/InGaAs planar n-MOSFETs in the literature.

high-k/p-InGaAs (planar) 600

) HfO2/Al2O3 [4.3] Al2O3 Vs

/ 500 [4.4] 2

400 Flourine-treated HfO2 [4.5] 300 HfO2 [4.3] La2O3 200 [this work]

100 12 -2 Effective Mobility (cm Mobility Effective Ns= 9×10 (cm ) 0 0 2 4 6 8 10 CET (nm)

Figure 4.7 High field mobility vs. CET plot for various planar n-MOSFETs high- k/InGaAs.

Although a higher effective mobility can be obtained for Al2O3/InGaAs, there is a severe CET penalty. At smaller CET where the effective thickness reaches ~1.0 nm region,

La2O3 layer with no complicated passivation technique, achieves high electron mobility 12 -2 comparable to HfO2/InGaAs at Ns= 9×10 (cm ). In table 4.1, list of recent results on various gate stack and junction technologies used on InGaAs platform, as well as the results from this thesis is summarized. The scalability, low Dit, and thermal stability of La2O3/InGaAs interface a great potential for their application in future device technology nodes.

Table 4.1 Comparison of gate stack properties in this thesis with recent reported results. Gate -1 -2 References dielectric Dit (eV cm ) CET (nm) S. Takagi et al., Al O & 2x1012 2 3 1.08 12 2012 IEDM [4.6] HfO2/Al2O3 2x10 X. Gong et al., HfO /SiO 2 2 1.9x1012 1.26 2012 VLSI [4.7] and Si cap N. Goel et al., 12 2008 IEDM [4.8] ZrO2 2x10 0.73 ALD- This thesis 8x1011 1.6 La2O3

4.3 Conclusions

InGaAs MOSFET operation with ALD-La2O3 as high-k gate dielectric with CET= 1.1 nm and Ni as metal source/drain has been demonstrated. Well behaved MOSFET transfercharacteristics were achieved although the high contact resistance at source/drain regions contribute to smaller Ion/Ioff ratio of drain current. The effective mobility at high surface carrier concentration was found to be equal or surpassing the best reported results with HfO2 as gate dielectric. However, further research on process conditioning to improve the low field mobility with ALD dielectric by optimizing deposition conditions is required.

4.4 References

[4.1] J. J. Gu, X. W. Wang, J. Shao, A. T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye “III-V Gate-all-around Nanowire MOSFET Process Technology: From 3D to 4D” IEDM, 529 , 2012.

[4.2] M. Fischetti, T. P. O’Regan, S. Narayanan, C. Sachs, S. Jin, J. Kim, and Y. Zhang “Theoretical Study of Some Physical Aspects of Electronic Transport in nMOSFETs at the 10- nm Gate-Length” Trans. Electcon. Devices, 54, 2116, 2007.

[4.3] M. Oda, T. Irisawa, Y. Kamimura, O. Ichikawa, and T. Tezuka “Effects of interfacial layer between high-k gate dielectric and InGaAs surface on its invesion layer electron mobility” Ext. Abs. of Solid State Dev.and Materials, pp. 797, 2012.

[4.4] M. El Kazzi, L. Czornomaz, C. Rossel, C. Gerl, D. Caimi, H. Siegwart, J. Fompeyrine, and C. Marchiori “Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate- first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors” Appl. Phys. Lett, 100, 063505, 2012.

[4.5] Y.-T. Chen, Y. Wang, F. Xue, F. Zhou, and J. C. Lee “Physical and Electrical Analysis of

Post-HfO2 Fluorine Plasma Treatment for the Improvement of In0.53Ga0.47As MOSFETs’ Performance” Trans. Electcon. Devices, 59,139, 2012.

[4.6] S. Takagi, R. Zhang, S.-H Kim, N. Taoka, M. Yokoyama, J.-K. Suh, R. Suzuki and M. Takenaka, “MOS interface and channel engineering for high-mobility Ge/III-V CMOS”, IEDM, p. 505, 2012.

[4.7] X. Gong, S. Su, B. Liu, L. Wang, W. Wang, Y. Yang, E. Kong, B. Cheng, G. Han, and Y.-C.

Yeo, “Towards High Performance Ge1-xSnx and In0.7Ga0.3As CMOS: A Novel Common Gate Stack featuring Sub-400 ºC Si2H6 Passivation, Single TaN Metal Gate, and Sub-1.3 nm EOT”,VLSI symp., 99, 2012.

[4.8] N. Goel, D. Heh, S. Koveshnikov, I. Ok, S. Oktyabrsky, V. Tokranov, R. Kambhampati, M.

Yakimov, Y. Sun, P. Pianetta, C.K. Gaspe, M.B. Santos, J. Lee, S. Datta, P. Majhi,, and W. Tsai,

“Addressing The Gate Stack Challenge For High Mobility InxGa1-xAs Channels For NFETs” IEDM Tech. Dig. 363, 2008.

Chapter 5 Conclusions

5.1 Conclusions of this study 5.2 Prospects for future study

5.1 Conclusions of this study

In this thesis, interface problem of high-k/InGaAs described in chapter 1, are experimentally investigated and effective solutions to those problems are proposed. In chapter 3, the result and summary of the studies in this thesis is and their importance on improving high-k/InGaAs interface is described.

In chapter 3, atomic layer deposition (ALD) method with (La(iPrCp)3 and

H2O) for La2O3 film synthesis. (1) ALD growth condition were confirmed ALD growth mode at growth temperature 140 to 160oC. (2) It was shown that near ideal CV characteristics with low density of interface state (~8×1011 eV-1cm-2) can be obtained for TiN/W/ALD-

La2O3/InGaAs MOS capacitors. It was found that controlling the

substrate temperature (~150oC) during La2O3 synthesis was essential for prevention of substrate oxidization during deposition.

(3) In-O-La and Ga-O-La bonding state were formed during La2O3 films deposited, Sulfur passivation does not affect the interface state density

(Dit). (4) Sulfur treatment for InGaAs MOS capacitors prevent forming interfacial oxidation layer.

In chapter 4, InGaAs MOSFET operation with Ni as metal SD and ALD-

La2O3 as gate dielectric was demonstrated. Effective electron mobility at high surface carrier concentration region (Ns: 9×1012 cm-2) was comparable to reported HfO2-based InGaAs MOSFETs at CET ~ 1.1 nm.

5.2 Prospects for future study

Given the superior interface quality of La2O3/InGaAs interface, it is possible to achieve MOSFET operation with better results than those of reported for Al2O3-based InGaAs MOSFETs. Low subthreshold value (~60mV) is necessary to utilize low power/high performance benefits of

InGaAs-based devices. ALD technique using (La(iPrCp)3 and H2O has high leakage current due to high impurities and high defect in the deposited films.

Further process optimization of ALD-deposited La2O3 is necessary to improve subthreshold value and achieve high mobility in gate stack with smaller equivalent oxide thickness. The dielectrics used in this thesis and references are summarized in the following table.

Table 5.1 Comparison of MOS capacitor and nMOSFET in this thesis with recent reports.

Device MOS capacitor nMOSFET Interface State Capacitance Thermal Mobility 2 Density (Dit) Equivalent Stability (cm /Vs) cm-2eV-1 Thickness (oC) /CET(nm) Dielectric (E-Ei=0.1eV) (nm)

[1] 12 ALD-Al2O3 2x10 1.08 - 550/10

[2] 12 HfO2 6x10 - - 350/2.3

[3] 11 EB-La2O3 7x10 0.78 620 -

11 ALD-La2O3 9x10 1.6 470 345/1.1 (This study) [1] M. El Kazzi et al., Appl. Phys. Lett 100(2012) 063505 [2] M. Oda et al., SSDM 2012 [3] D. H. Zadeh et al., Solid-State Elec. 82(2013) 29

Acknowledgments

First of all, I would like to express my deep gratitude first and foremost to Prof. Hiroshi Iwai of Tokyo Institute of Technology for his consistent, always kind and to the point guidance as my adviser on this thesis. I am also grateful to Prof. Kuniyuki Kakushima, Prof. Kazuo Tsutsui, Prof. Akira Nishiyama, Prof. Hitoshi Wakabayashi, Prof. Yoshinori Kataoka, Prof. Nobuyuki Sugii, Prof. Takeo Hattori, and Prof. Kenji Natori, for their invaluable guidance and help throughout my research also Dr. A. Parhat for his assistance with experiments. I truly appreciate all the help students in Prof. Iwai’s Laboratory provided me with, in particular master student Yuya Suzuki and Dr. Dariush Hassan Zadhe for valuable advice and support in my study. I would also like to thank Prof. Iwai’s secretaries Ms. Akiko Matsumoto and Masako Nishizawa for their kind support and help with filling and handing in numerous and various documents throughout my student years. Finally, I would like to express my deepest gratitude to my dear parents and brothers for their continuous and unconditional support, love and help, as I am indebted all my accomplishments to them.

I would like to thank JSPS through FIRST program for a grant that made it possible to complete my study.

Hiroshi Oomine February 2014