D5.3A Cover Sheet
Total Page：16
File Type：pdf, Size：1020Kb
VISIT Deliverable Report Cover Sheet Workpackage: WP5: Packaging, System-level Evaluation, Standardization, and Exploitation Deliverable number D5.3a Deliverable name Final assessment of VISIT Project-related Standards Lead beneficiary: INT Workpackage leader (name): VIS Description writer (name): Prof. Dr. Nikolay N. Ledentsov Date planned: 31.10.2011 Date finished: 14.02.2012 Deliverable reached not reached Deliverable description and summary of achieved results (max. 2400 char.): This Deliverable D5.3a is a supplement to the original Deliverable D5.3 report (dated 30 May 2010). Therefore the purpose of this Deliverable report is to provide a final update, assessment, and commentary on the current, on-going, and future planned Standards activities that are relevant to the component and systems technology that was (and continues to be through post-project exploitation) devleoped within the EC-funded FP7 VISIT project. As before in this report we briefly discuss progress on IEEE-directed Standards for optical data transfer such as the IEEE 802.3ba 40G and 100G Ethernet Standard. We also comment on the evolving Standards for the Common Electrical Interface, Infiniband, Fibre Channel, and consimer markets that include Light Peak (and Thunderbolt) optical (and electrical) interconnects. Contributors: VIS Public 14.02.2012 VISIT Deliverable Report Technical Annex Deliverable number: D5.3a Deliverable name: Final assessment of VISIT Project-related Standards An update on Standards for next-generation systems that include high-speed VCSEL-based optical interconnects and an assessment of Standards that may be impacted by the technology developed in the VISIT Project Introduction As silicon scaling continues, the density of transistors on a chip doubles each two years. The computational power of the processor doubles allowing a dramatic increase in the computational power. Within 2008-2010 the peak computational power of petascale1 supercomputers increased 10- fold form 1 petaflops (IBM Roadrunner 2008) up to peak power of 8-10 petaflops (K-computer2, Fujistu, 2011). Furthermore, construction of 50 petaflops (PF) supercomputers is already announced3. At the same time reaching this performance is a challenging task, particularly for interconnects, which may contribute for exascle supercomputers to above 80% of the total power consumption and up to 90% of the performance4. According to IBM, 5 million optical links may be needed already for 10PF supercomputers5. With silicon scaling and the related increase in the computational power of processors, it is important to keep the same physical space for interfaces or in other words scale the bandwidth density with each generation by a factor of two. As the number of channels may hardly be increased, the speed per channel must double. This “scaling” is already an extremely challenging task. 1 petascale refers to the speed of the computer and means it could perform a thousand trillion mathematical operations a second 2 http://www.nsc.riken.jp/K/diary_eng.html 3 http://www.zdnet.co.uk/news/emerging-tech/2011/05/25/cray-taps-gpus-for-50-petaflop-supercomputer-40092887/ 4 Alan Benner, IBM, "Optical Interconnects for HPC" Short-Distance High-Density Optical Interconnects. An OIDA Roadmapping Workshop, Stanford Photonics Research Center, Stanford University, CA, April 12-13, 2011 5 Bert Jan Offrein, IBM Silicon Photonics Workshop, Munich, 23 May 2011 http://www.siliconphotonics.eu/munich_slides/2_IBM.pdf Public Deliverable number: D5.1 Deliverable name: Assessment 1 of IEEE standard definition Common Electrical Interface Common electrical interfaces (CEI) are being developed by the Optical Internetworking Forum (OIF), which promotes the development and deployment of interoperable networking solutions and services through the creation of Implementation Agreements (IAs) for optical networking products, network processing elements, and component technologies. The Common Electrical Interface Standard supports the chip-to-chip and chip-to-module links allowing connections between different elements on a printed circuit board (PCB) that services optical networking components. This has sparked great interest in the development of suitable optical circuit boards and optical backplanes for high-speed optical interconnects. Presently ten OIF members are uniting to showcase multi-vendor participation in OIF Interoperability 2012 – Enabling High-Speed Dynamic Services. The OIF’s Physical and Link Layer (PLL) demonstration will showcase interoperability of the Forum’s Common Electrical Interface (CEI) 28G (28 Gbit per second or 28 Gbps) Very Short Reach (VSR) draft implementation agreement that defines chip-to-module electrical interfaces. Demonstrations of the CEI-25G-LR signal for backplane interfaces will also be tested. These demonstrations will be on display at the Optical Fiber Conference (OFC/NFOEC) during 06-08 March 2012 at the OIF booth #713. The associated marketing literature notes that, “This demonstration of CEI-28G-VSR shows the ability to reach 100G for next-generation 4 x 25Gb/s based optical transceivers,” said Ed Frlan of Gennum and the OIF PLL Interoperability Working Group Chair. “The CEI-25G-LR and CEI-28G-VSR electrical interface and signaling schemes being tested for interoperability support multiple 100G applications.” The following companies are participating in the OIF Interoperability 2012 during OFC 2012: Altera, Amphenol, Fujitsu Optical Components, Gennum, IBM, Inphi, Luxtera, Molex, Tyco Electronics (TE) Connectivity, and Xilinx. The equipment that will be used for a systems demonstration includes host integrated circuits (ICs) with VSR SERDES ICs, host PCB traces, optical module connectors, module re-timers, and optical transceivers. The test equipment used in the demonstration is supplied by Tektronix, Inc. “This interoperability test and demonstration shows a critical mass, with multiple vendors supporting the CEI-28G-VSR,” said Rod Smith of TE Connectivity and the OIF Marketing Awareness & Education Committee co-chair. “There is momentum in the marketplace to incorporate higher speed signals.” The summary of the time frames for the related CEI-28G-VSR Standards acceptance is given next in Figure 1. 14 February 2012 3/14 – Public – Deliverable number: D5.3a (a supplement to D5.3) Deliverable name: Final assessment of VISIT Project-related Standards Figure 1. A Roadmap that illustrates timeframes for different Standard interfaces. Within 2012 four single channel electrical interfaces at 25 Gb/s – 28 Gb/s are to be standardized. In 2012 four types of copper interfaces at 25 to 28 Gbps are to be standardized: CEI-25G-LR, CEI- 28G-SR, CEI-28G-VSR, and FC32G6. The roadmap for 50 Gbps is already set (CEI-50G-SR, due for certification in 2015). One should mention that the introduction of 28G interfaces will enable the planned Fibre Channel 32GFC Standard in 2012 (which already includes optical interfaces) and 25Gx4 links for 100G IEEE next generation interfaces over copper (IEEE 802.3bj) and over optical fiber (IEEE NextGenOPIX). The latter two Standards are expected to be ratified in 2014. 6 http://www.lsi.com/AIS2011/Documents/LSI_Deploying100GtoPreparing400G.pdf 14 February 2012 4/14 – Public – Deliverable number: D5.1 Deliverable name: Assessment 1 of IEEE standard definition Infiniband Infiniband represents the most important interface in high-performance (“super”) computing. As Gordon Moore’s Law continues to be valid the computational power of computers continues to rapidly increase (by about three orders of magnitude per decade reaching presently 10-20 petaflops7). To match the demand the bandwidth density of interconnects must scale up with the serial data bit rate per channel increasing 4-fold each 5 years. Copper now gives us data rates at about and above 10 Gigabits per second (Gbps). Already in the 10PF-scale IBM machine the number of optical links at 10 Gbps has increased to 5 million8. In 2012 the first two supercomputer systems at 20PF (IBM9 and Cray) are due. In Figure 2 an evolution of the data bit rate per single channel and per electrical link for the most relevant high-performance computing Infiniband standard is shown. The roadmaps provided by the Infiniband Industry Association in June 2010 and June 2011 are given. As one can see from the comparison the 26 Gb/s data bit rate (eight data rate or EDR or 8X) expected for 2011 has been shifted towards 2013. Instead an intermediate speed of 14 Gb/s will be applied. Even the reduced speed is partially compensated by the improved efficiency of coding (97% for 64/66 versus 80% for 8/10), still there is no doubling of the affective data bit rate. To compensate the delay 26 Gb/s (equivalent to 32 Gb/s for the old coding scheme) is planned for 2013. It is also important to note that the HDR (hexadecimal data rate or 16X) Standard expected at ~50 Gb/s is still planned for use starting in 2014. The delay with the EDR Standard clearly indicates that no adequate solution for such an interconnection has been found. However, EDR was announced to be used in a 20PF supercomputer this year (Sequoia by IBM in 2012). Thus either the solution will be outside of the Standard, or the Sequoia Project will fail, similar to the failed 10PF Blue Waters project of IBM10 which was still based on 10 Gb/s links. 7 http://www.top500.org/static/lists/2011/11/TOP500_201111_Poster.pdf 8 Bert Jan Offrein, IBM Silicon Photonics Workshop, Munich, 23 May 2011. 9 http://www.hpcwire.com/hpcwire/2012-01-12/first_racks_of_20-petaflop_sequoia_supercomputer_arrive_at_llnl.html 10 http://insidehpc.com/2011/08/08/ibm-cancels-blue-waters “Rumors at ISC’11 centered on problems with the Blue Waters proprietary interconnect.” 14 February 2012 5/14 – Public – Deliverable number: D5.3a (a supplement to D5.3) Deliverable name: Final assessment of VISIT Project-related Standards Figure 2. Roadmap illustrating the increase in the serial transmission data bit rate for the most important Standard (Infiniband) for high-performance computing. The serial data bit rate doubles each 2-2.5 years. Note the delay in the introduction of the EDR standard in the roadmap of 2011.