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United States Patent [19] [11] E Patent Number: Re United States Patent [19] [11] E Patent Number: Re. 33,629 Palmer et a1. [45] Reissued Date of Patent: Jul. 2, 1991 [54] NUMERIC DATA PROCESSOR 1973, IEEE Transactions on Computers vol. C-22, pp. [75] Inventors: John F. Palmer, Cambridge, Mass; 577-586. Bruce W. Ravenel, Nederland, Co1o.; Bulman, D. M. "Stack Computers: An Introduction," Ra? Nave, Haifa, Israel May 1977, Computer pp. 18-28. Siewiorek, Daniel H; Bell, C. Gordon; Newell, Allen, [73] Assignee: Intel Corporation, Santa Clara, Calif. “Computer Structures: Principles and Examples," 1977, [21] Appl. No.: 461,538 Chapter 29, pp. 470-485 McGraw-Hill Book Co. Palmer, John F., “The Intel Standard for Floatin [22] Filed: Jun. 1, 1990 g-Point Arithmetic,“ Nov. 8-11, 1977, IEEE COMP SAC 77 Proceedings, 107-112. Related US. Patent Documents Coonen, J. T., "Speci?cations for a Proposed Standard Reissue of: t for Floating-Point Arithmetic," Oct. 13, 1978, Mem. [64] Patent No.: 4,338,675 #USB/ERL M78172, pp. 1-32. Issued: Jul. 6, 1982 Pittman, T. and Stewart, R. G., “Microprocessor Stan Appl. No: 120.995 dards,” 1978, AFIPS Conference Proceedings, vol. 47, Filed: Feb. 13, 1980 pp. 935-938. “7094-11 System Support For Numerical Analysis,“ by [51] Int. Cl.-‘ ........................ .. G06F 7/48; G06F 9/00; William Kahan, Dept. of Computer Science, Univ. of G06F 11/00 Toronto, Aug. 1966, pp. 1-51. [52] US. Cl. .................................. .. 364/748; 364/737; “A Uni?ed Decimal Floating-Point Architecture For 364/745; 364/258 The Support of High-Level Languages,‘ by Frederic [58] Field of Search ............. .. 364/748, 745, 737, 736, N. Ris, Yorktown Heights, NY. (Oct. 1978), Signum 364/200 newsletter 11 #3, pp. 18-23. [56] References Cited Goldberg, “27 Bits are not Enough for 8-Digit Accu racy" Communications oftheACM. vol. 10, No. 2. Feb. US. PATENT DOCUMENTS 1967, pp. 105-106. 3.434.114 3/1969 Arulpragasam et al. 364/745 Haley. A. C. D., "The KDFB Computer System", 3.594.565 7/1971 Ragen .................... .. 364/745 English Electric Co., Ltd., Kidsgrove, Stoke-on-Trent, 3,603,934 9/1971 Heath, Jr. et al. ..... .. 364/737 England, Proceedings-Fall Joint Computer Confer 3,871,578 3/1975 Van De G001’ ct a1. 364/748 ence (1962), pp. 108-120. 3.905.025 9/1975 Davis et a1. ............ .. 364/200 Am95l1A, MOS/LS1 Data Book (1980), pp. 7-66 to 4.021.655 5/1977 Healey et al. ..................... .. 364/200 7-73. OTHER PUBLlCATlONS Am9512, MOS/LSI Data Book (1980), pp. 7-91 to 7-99. Moore, R. E., Interval Analysis, 1966, Prentice-Hall, Haddon, B. K. and Waite, W. M., “Experience with the Inc. Universal Intermediate Language Janus", Software- Kahan, W., “A More Complete Interval Arithmetic," Practice and Experience, vol. 8, pp. 601-616, (1978). Jun. 17-21, 1968, Lecture Notes. Gentleman, W. M. and Marovich, S. B., “More on Dekker, T. J ., “A Floating Point Technique for Extend Algorithms that Reveal Properties of Floating Point ing the Available Precision,” 1971, Numerishe Math Arithmetic Units", Communications of the ACM, vol. ematik vol. 18, pp. 224-242. 17, No. 5, May 1974, pp. 276-277. Brent, R., “On the Precision Attainable with Various August, et a1., System Architecture Reference Guide, Floating Point Systems,” IEEE Transactions on Cam Prime Computer, Inc., Framingham, Massachusetts, puters, vol. C-22, 1973, pp. 601-607. Jul. 1983 (First Edition, Apr. 1979), pp. iii, 6-23, 6-25. Yohe, J. “Roundings in Floating-Point Arithmetic,” Cates, Julia, “F-Series Extends Computing Power of Re. 33,629 Page 2 HP 1000 Computer Family", H-P Journal, Oct. 1978, Attorney, Agent. or Firm—Arnold, White & Durkee pp. 1, 15, 16. Hull, T. E. and Swenson, J. R., “Tests of Probabilistic [57] ABSTRACT Models for Propagation of Roundoff Errors", Commu A floating point, integrated, arithmetic circuit is orga nications of the ACM, vol. 9, No. 2, Feb. 1966, pp. nized around a file format having a ?oating point nu 108-413. meric domain exceeding that of any single or double Kahan, William, “A Survey of Error Analysis”, Com precision floating point numbers, long or short integer puter Science Dept. University of California, Berkeley, words or BCD data upon which it must operate. As a California, Information Processing 71, North~Holland result the circuit has a greater reliability, range and Publishing Co., (1972), pp. 12144239. precision than ever previously achieved without entail The 8086 Family User’s Manual, Numerics Supplement, ing additional circuit complexity. Reliability is further Jul. 1980, pp. 5-1 and 5-2, Intel Corporation._ enhanced by a systematic three bit rounding ?eld, and 8080/8085 Floating-Point Arithmetic Library User’s by including means for detecting every error or excep Manual, Intel Corp. 1979. tion condition with an optional expected response pro SEC 310 High-Speed Mathematics Unit Hardware vided thereto by hardware. As a result of such organiza Reference Manual, Intel Corp., 1977. tion, an unexpected increase of capacity is achieved 8232 Floating Point Processor, Intel Corp., Sep. 1979. wherein transcendental functions can be computed to PDP-ll Processor Handbook, 1978-79 Revision, DEC, tally in hardware, and whereby mixed mode arithmetic pp. 246-301. can be implemented without difficulty. The numeric System/370 Principles of Operation, IBM, pp. 157-170. processor also includes a programmable shifter capable Palmer, J. and Baron, J., “A Partial 8087 Emulator”, External Reference Speci?cation, Intel Corp, Rev. 0, of arbitrary numbers of bit and byte shifts in a single 12/30/77. clock cycle, as well as an arithmetic unit capable of Baron, J., Optimized Partial 8087 Emulator, Product implementing multiplication, division, modulo reduc Requirement Document, Intel Corp., 10/2/78. tion and square roots directly in hardware. Primary Examiner—David I-I. Malzahn 5 Claims, 7 Drawing Sheets US. Patent July 2, 1991 Sheet 1 of 7 Re. 33,629 ME9 kw US. Patent July 2, 1991 Sheet 3 of 7 ‘ Re. 33,629 1""1a. 5'. be LEI-'7’ 1.090 9ND ~94 new Reno wrsprace x‘l lMs: 5w: m 2% 5H,”. 2% D5000“ : aw: aH/Fr ~90 COUNT av. ‘I8 MATRIX L 51,} _ _ _ - - - - -' - — — - - "Iva 7 an 9 ~ , 81f ' SHIFT a!’ 060005? i ‘8/7 ‘gH/Fr I02 cw”, a’. a MA‘TR/X 7 5,02 5/04 z.’l ,Zca map/1' 1.000 mm [96 (EFT REQD INTEA’FQCE '3 t US. Patent July 2, 1991 Sheet 5 of 7 Re. 33,629 aha-n 1' 0 (av- supra") 1 /__/33 TI Z1,‘ (Or-21¢ ? I36 '/ ?ag' Z a . 64 (M1) 1 / 72 r 70 ‘ @q/Ff / B - PEG .szau Mux ,. con'rm I ‘5’ ’” 2 Mu! < M” TIMING 1'54 I W r r r'67 74 ,I Q ‘7 "68 RDDE'R IE] [5E NRC/{INF EZI CON TROL E] 62-5 478 494 88 52) L Quonsrvr SHIFT R56, US. Patent July 2, 1991 Sheet 6 0f 7 Re. 33,629 06%.“‘Hum US. Patent July 2, 1991 Sheet 7 of 7 Re. 33,629 Re. 33,629 1 2 tions or special cases such as zero and in?nity arithme NUMERIC DATA PROCESSOR tic. Matter enclosed in heavy brackets [ ] appears in the BRIEF SUMMARY OF THE INVENTION original patent but forms no part of this reissue speci?ca The present invention includes an improvement in a tion; matter printed in italics indicates the additions made numeric data processor for performing calculations on a by reissue. plurality of data formats representable by a fraction and exponent representation comprising a ?rst means or TABLE OF CONTENTS circuit for converting the plurality of the formats to a BACKGROUND OF THE INVENTION tile format wherein the tile format has a numeric frac 1. Field of the Invention tion and exponent domain greater than any one of the 2. Description of Prior Art - plurality of data formats. A fraction and exponent bus is BRIEF SUMMARY OF THE INVENTIO coupled to this ?rst means or circuit for converting the BRIEF DESCRIPTION OF THE DRAWINGS plurality of data formats. A stack of registers, which are DETAILED DESCRIPTION OF THE PRE con?gured to store numeric information in the file for FERRED EMBODIMENT . mat, are coupled to the exponent and fraction bus. An I. General Discussion of Data and Numeric Repre arithmetic unit which is used to perform arithmetical sentations operations in ?le format on the numeric information is II. General Introduction to the System Context of the also coupled to the fraction bus. By reason of this com Numeric Processor of the Present Invention bination of elements, the reliability of computation is III. Arithmetic Operations of the Numeric Processor substantially increased since all data formats are con A. Multiplication verted to a ?le format which has a greater range of bits B. Division in the signi?cand and a greater exponent range than any C. Modulus Arithmetic of the numerical quantities which the numeric proces D. Square Root 25 sor may be called upon to manipulate. Generally, then, E. Rounding Apparatus and Methodology_ the only errors which are likely to occur are errors in F. Programmable Shifter conversion and transfer rather than in computation. IV. Architecture and Organization of the Floating This combination allows mixed mode arithmetic since Point Execution Unit the ?le format is able to include all data formats after A. General Discussion their conversion. B. Handling of Denormalized and Unnormalized The present invention also includes a circuit or means Numbers C. Signed Zero and In?nity Generation and Han for detecting and indicating numeric exceptions or er dling rors during any computational operation and for han V. Summary And Advantages of the Invention 35 dling of such exceptions or errors.
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