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Energy Consumption Evaluation of Flip-Flops for Dynamic Voltage Scaling Systems and Circulating-Temperature Applications

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Energy Consumption Evaluation of Flip-Flops for Dynamic Voltage Scaling Systems and Circulating-Temperature Applications Title Page Energy Consumption Evaluation of Flip-Flops for Dynamic Voltage Scaling Systems and Circulating-Temperature Applications by Minghe Shao Submitted to the Graduate Faculty of the Swanson School of Engineering in partial fulfillment of the requirements for the degree of Master of Science University of Pittsburgh 2021 Committee Membership Page UNIVERSITY OF PITTSBURGH SWANSON SCHOOL OF ENGINEERING This thesis was presented by Minghe Shao It was defended on March 5, 2021 and approved by In Hee Lee, PhD, Assistant Professor, Department of Electrical and Computer Engineering Samuel Dickerson, PhD, Assistant Professor, Department of Electrical and Computer Engineering Rajkumar Kubendran, PhD, Assistant Professor, Department of Electrical and Computer Engineering Thesis Advisor: In Hee Lee, PhD, Assistant Professor, Department of Electrical and Computer Engineering ii Copyright © by Minghe Shao 2021 iii Abstract Energy Consumption Evaluation of Flip-Flops for Dynamic Voltage Scaling Systems and Circulating-Temperature Applications Minghe Shao, M.S. University of Pittsburgh, 2021 CMOS circuit technology has developed with a help of transistor scaling. In past decades, previous studies found that operating environment of digital system affects circuit performance significantly. For example, extensive research has been performed to learn temperature dependency of CMOS circuits and optimize their performance at given temperature. Adaptive voltage scaling (AVS) is one of the important techniques, responses to operating temperature and dynamically change supply voltage of digital circuits to optimize circuit performance. AVS can enable energy optimization for a system experiencing significant temperature variation, including a space satellite. However, inappropriate AVS results in functional failure in an extreme condition, which can cause substantial problem for a critical mission. This work proposes technique to evaluate recently published flip-flops considering their power-delay product (PDP) and reliability for an AVS system operating under circulating temperature. The 8 flip-flops are evaluated under different temperature and supply voltage. Their PDPs are compared assuming that temperature changes linearly. Functional reliability is quantitatively evaluated using corner and Monte-Carlo simulations, and failure mechanisms of flip-flops are discussed as well. iv Table of Contents Acknowledgement ......................................................................................................................... x 1.0 Introduction ............................................................................................................................. 1 1.1 Background & Motivation ............................................................................................. 1 1.2 Related Work .................................................................................................................. 2 1.2.1 CMOS Circuits under Voltage and Temperature Variations .........................2 1.2.2 Temperature Dependence in Subthreshold Region ..........................................3 1.2.3 Adaptive Voltage Scaling Based on Temperature Variation ...........................4 1.2.4 Power-Delay Product ...........................................................................................5 1.3 Contribution of This Work ............................................................................................ 5 1.4 Organization ................................................................................................................... 6 2.0 Proposed Evaluation Process ................................................................................................. 7 2.1 Introduction .................................................................................................................... 7 2.2 Evaluated Flip-Flops ...................................................................................................... 7 2.2.1 Conventional Transmission-Gate Flip-Flop ......................................................7 2.2.2 Write-Port Master-Slave-Latch Flip-Flop .........................................................8 2.2.3 18-Transistor Single-Phase-Clocked ................................................................10 2.2.4 Static Single-Phase Contention-Free Flip-Flop ...............................................11 2.2.5 Adaptive-Coupling Flip-Flop ............................................................................12 2.2.6 Change-Sensing Flip-Flop .................................................................................14 2.2.7 Topologically Compressed Flip-Flop ...............................................................15 2.2.8 Static Contention-Free Differential Flip-Flop .................................................16 v 2.3 Transistor Sizing for Flip-Flops .................................................................................. 19 2.4 Testbench for Evaluation ............................................................................................. 21 2.5 Evaluation Process ........................................................................................................ 23 2.6 Conclusion ..................................................................................................................... 26 3.0 Evaluation Result and Analysis ........................................................................................... 27 3.1 Introduction .................................................................................................................. 27 3.2 Evaluation Results of the First Step Using Corner Simulation ................................ 27 3.3 Evaluation Results of the Second Step Using Monte-Carlo Simulations. ............... 31 3.4 Analysis of Device Failures and Energy Efficiency ................................................... 35 3.4.1 WPMS Retention Failure from Pass Transistor .............................................35 3.4.2 TCFF Failure from Contention ........................................................................36 3.4.3 Potential Contention in TSPC ...........................................................................39 3.4.4 Unstable Phase in CSFF from Floating Nodes ................................................40 3.4.5 Write-Failure in ACFF from Weak NMOS Pull-Up ......................................42 3.4.6 Energy Efficiency Analysis ................................................................................43 3.5 Conclusion ..................................................................................................................... 45 4.0 Conclusion and Future Work .............................................................................................. 46 Appendix A Program Codes for Transistor Sizing in Voltage-Temperature Variation .................................................................................................................................................. 47 Appendix B Program Codes for Flip-flop Functionality Test with PVT Variation ............. 48 Appendix C Energy Performance Gained from AVS ............................................................. 51 Bibliography ................................................................................................................................ 52 vi List of Tables Table 1. Extreme cases simulation result. ................................................................................. 28 Table 2. Minimal supply voltage found from functionality tests for 100 kHz [V]. ............... 29 Table 3. Minimal supply voltage found from functionality tests for 2 MHz [V]. ................. 30 Table 4. 1000-Sample Monte-Carlo simulation result at -100 ℃ and 100 kHz frequency. 32 vii List of Figures Figure 2.2-1. Schematic of TGFF (Clock inputs of NMOS of the transmission gates are not shown). ............................................................................................................................... 8 Figure 2.2-2. Schematic of WPMS. .............................................................................................. 9 Figure 2.2-3. Schematic of 18TSPC. .......................................................................................... 10 2 Figure 2.2-4. Schematic of S CFF. ............................................................................................. 12 Figure 2.2-5. Schematic of ACFF. ............................................................................................. 13 Figure 2.2-6. Schematic of CSFF. .............................................................................................. 15 Figure 2.2-7. Schematic of TCFF. .............................................................................................. 16 Figure 2.2-8. Schematic of SCDFF. ........................................................................................... 18 Figure 2.3-1. Result of DC simulation of single inverter. ........................................................ 19 Figure 2.3-2. Simulation result with different NMOS width and PMOS width. .................. 20 Figure 2.3-3. Simulation result with Wp-temperature-VDD combinations. ............................ 21 Figure 2.4-1. Test circuit for flip-flops. ..................................................................................... 22 Figure 2.4-2. Simulation waveforms.......................................................................................... 23 Figure
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