Donald Cullen, Witold Paw, John Swanson, Lenora Toscano Macdermid, Inc

ELIMINATING MICROVOID RISK VIA AN OPTIMIZED SURFACE FINISH PROCESS Donald Cullen, Witold Paw, John Swanson, Lenora Toscano MacDermid, Inc. Waterbury, CT USA Abstract The Pb-free transition in the electronics industry has seen immersion silver emerge as a leading circuit board finish for ROHS compliant assemblies and finished goods. The immersion silver finish has now been in high volume production for ten years and is utilized in a wide cross-section of end-use applications, both simple and technically sophisticated. The strengths of immersion silver are numerous: process simplicity, contact functionality, durability to multiple reflows, high frequency performance, and others. Recently, a phenomena arising after the soldering assembly operation, commonly referred to as microvoiding, has been linked to immersion silver processing. Studies of microvoiding have shown it to occur infrequently and somewhat unpredictably, so identification of root causes has been difficult. Reliability testing of "worst-case" microvoiding indicates it to be a problem deserving industry investigation. As an update to an earlier publication on this topic, this paper describes an investigation which identified key enablers for microvoid formation, a mechanism for their formation, and the successful implementation of an optimized silver process which minimizes microvoid formation and risk. ` Figures 1 a,b,c: Solderjoint Microvoiding by Optical Cross-Section and X-Ray Inspection Introduction Voids exist in solderjoints in many forms. The microvoids discussed in this work are characterized by three factors. First, the voids are very small, generally on the order of less than 10 microns. Next, the microvoids of concern exist at the interface of the copper substrate and the bulk solder, or more specifically, where the copper-tin intermetallic meets the bulk solder. Last, the problematic microvoids exist in large numbers, all on the same plane. These characteristics differ from other types of solderjoint voids such as bulk process voids, Kirkendall voids, and shrinkage voids. The impact of solderjoint microvoids on functional reliability is a topic of much debate. This paper will not address that topic. Intuitively, engineers believe that voiding in solderjoints reduces performance. While some work has shown that solderjoint voids may interrupt crack propagation, most engineers believe that planar microvoids, also known as champagne voids, can pose a real reliability risk when present in large proportions. In earlier investigations, a link was found between the formation of solderjoint microvoids with various PCB fabrication and assembly steps1. A combination of extremely high silver thickness and inadequate reflow temperature was found to lead to microvoiding. Other links to microvoiding were observed empirically. The earlier work provided observations of microvoids in solderjoints and ways to reduce the voiding. The mechanism of void formation at the solder/copper interface was not fully discovered in time for the earlier publication, however. At that time, a proposed mechanism involved the interaction between flux chemistry and silver metal. Later work found this theory difficult to reproduce with some of the fluxes use in production. The industry continued to seek a more thorough mechanistic explanation of microvoid formation. As with many difficult failure modes in PCB manufacturing, the defect occurred with such infrequency that many experiments were required to collect enough data to evolve the theories of microvoid formation. The issue of contamination remains as a leading contributor to microvoid vulnerability. Early samples demonstrating microvoids were traced to fabrication process areas with process control issues. Contamination on boards included oils, developer foam, tin resist and films of sublimated soldermask volatiles. Cross-contamination from shared rinses, organic coated conveyors, and immersion tin provided additional residue. The silver process was improved to provide adequate pre-cleaning, silver bath analysis, use of a cleaner and microetch, dedicated rinsing, and improved rework procedures. After these steps were implemented, the X-ray occurrence of microvoiding was nearly eliminated. Laboratory Methods Several methods are used in the industry for studying solderjoint microvoids. The most direct method involves physical destruction of a BGA solderjoint with techniques such as “dye and pry.” In the physical destructive methods, a component is assembled to the test specimen, and then physically removed, often by simple torque such as from the use of a screwdriver. The component removal can be conducted following thermal cycling tests, or other stressful environments. Alternatively, X-Ray equipment has been applied as a tool to detect and study microvoids. X-Ray equipment has reached a level of power and resolution to allow detection of microvoids. X-Ray inspection is non-destructive, but is slow and expensive and not readily used as an assembly quality control. In addition, there is not industry consensus that voids found by X-Ray can be attributed to the location within the solderjoint at the copper interface. Voids not located at the interface are not always considered to be of high importance. The most expedient method for detecting microvoids is through careful cross-sectioning. A surface under investigation is soldered, often to a BGA component or more simply, to a solder sphere. An assembled solderjoint can be optically inspected after cross-sectioning to reveal microvoids at the copper/solder interface. The cross- sectioned solderjoint is more precisely studied with the use of focused ion beam. The FIB technique removes very small layers of material on the surface of the section, revealing fine detail such as voids, caves, and chimneys, as discussed later. 0 1 2 3 4 5 6 7 8 9 Figure 2: Scale Used to Rank Microvoid Severity None of the techniques listed here allows bare PCB’s to be screened before assembly. Some work at various industry R&D labs has attempted to connect microvoid propensity with solderability results, thickness distribution, and even tarnish observation. Without a reliable method for predicting microvoids at the bare PCB stage, extra emphasis is placed on prevention techniques such as chemical process control. Results With cross section evaluation, it was possible to conduct the large number of experiments needed to collect sufficient data to form conclusions on microvoid formation. The scale used in Figure 2 allowed quantification of microvoids and statistical treatment. One particular experiment produced a clear result simply by sorting the data according to the type of microetch used to prepare the copper for silver plating. Figure 3 shows the sorted data from an experiment conducted using variables including microetch type, flux type, and silver thickness. When arranged according to microvoid rating, all samples created with peroxide type microetch resulted in the highest microvoiding. This empirical result prompted further investigation into the nature of copper microetches. 10 9 8 Peroxide Microetch Modified Persulfate Microetch 7 6 5 4 3 2 1 0 FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF ME FF M E FF ME FF ME Su rf Surf Su rf Surf Su rf Surf Su rf Surf Surf Surf Surf Surf Surf Surf Surf Surf 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Prep Prep Prep Pr ep Prep Pr ep Prep Pr ep Prep Pr ep Prep Pr ep Prep Prep Prep Prep Figure 3: Sorted Data Demonstrating the Effect of Microetch on Microvoids Several hypotheses were proposed relating to the effects of copper surface structure on the production of solderjoint microvoids. The copper may be altered in several different processing areas. The deposition of copper itself may produce rough deposits due to current density variations. Tin stripping and soldermask preparation processing may significantly affect the copper structure prior to surface finish. The final finish process employs a cleaner and microetch, but these relatively mild solutions are not adequate to overcome extremely rough or dirty copper. Another process capable of producing a poor copper structure is silver rework. For various reasons, operators may attempt silver rework by processing the PCB repeatedly through the plating bath. This method, along with other silver stripping methods, may easily compromise the integrity of the copper and silver deposits. Once altered by any of the above processes, copper deposits affect the quality of solderjoints. Microetching of copper is a complicated system of itself. Using the methods resulting in the above experiment, the etched copper surface was studied in more detail. Figures 4 and 5 show the copper surfaces formed with peroxide sulfuric microetching system and a modified persulfate sulfuric (mixed peroxydisulfate salts) system. The type of peroxide system used in these experiments produced a structure which, when viewed under SEM and AFM, demonstrated a sharp rugged texture. The modified persulfate microetch, on the other hand, yielded a copper structure of less jagged copper interface. It has been discussed in other work that the silver coating formed with thin immersion coatings does not significantly change the surface texture of the underlying copper. So, the silver interacts with the microetched copper surface during the initial plating, and the solder interacts with a silver surface which mimics the underlying copper. At this point in the investigations, it was not known if the silver interaction with rough copper, or the

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