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EEC 216 Lecture #1: CMOS Power Dissipation and Trends

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EEC 216 Lecture #1: CMOS Power Dissipation and Trends EEC 216 Lecture #1: CMOS Power Dissipation and Trends Rajeevan Amirtharajah University of California, Davis Outline • Administrative Details • Why Care About Power? • Trends in CMOS Power Dissipation • Dynamic Power Dissipation • Short Circuit (Overlap) Current • Power-Delay Metric • Energy-Delay Metric • Logic Level Power Estimation • Next Topic: High Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 2 Outline • Administrative Details • Why Care About Power? • Trends in CMOS Power Dissipation • Dynamic Power Dissipation • Short Circuit (Overlap) Current • Power-Delay Metric • Energy-Delay Metric • Logic Level Power Estimation • Next Topic: High Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 3 Permissions to Use Conditions & Acknowledgment • Permission is granted to copy and distribute this slide set for educational purposes only, provided that the complete bibliographic citation and following credit line is included: "Copyright 2002 J. Rabaey et al." Permission is granted to alter and distribute this material provided that the following credit line is included: "Adapted from (complete bibliographic citation). Copyright 2002 J. Rabaey et al." This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. • Slides 5-10 Adapted from CSE477 VLSI Digital Circuits Lecture Slides by Vijay Narayanan and Mary Jane Irwin, Penn State University R. Amirtharajah, EEC216 Winter 2008 4 Why Power Matters • Packaging costs • Power supply rail design • Chip and system cooling costs • Noise immunity and system reliability • Battery life (in portable systems) • Environmental concerns – Office equipment accounted for 5% of total US commercial energy usage in 1993 – Energy Star compliant systems for appliances – Green data center initiatives by Google, HP, and others R. Amirtharajah, EEC216 Winter 2008 5 Why worry about power? Power Dissipation LeadLead microprocessorsmicroprocessors powerpower continuescontinues toto increaseincrease 100 P6 Pentium ® 10 486 8086 286 386 8085 1 8080 Power (Watts) 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year PowerPower deliverydelivery andand dissipationdissipation willwill bebe prohibitiveprohibitive Source: Borkar, De Intel® R. Amirtharajah, EEC216 Winter 2008 6 Why worry about power? Chip Power Density Sun’s 10000 Surface Rocket 1000 Nozzle Nuclear …chips might become hot… 100 Reactor 8086 Hot Plate 10 4004 P6 8008 Pentium® Power Density (W/cm2) 8085 386 286 8080 486 1 1970 1980 1990 2000 2010 Year Source: Borkar, De Intel® R. Amirtharajah, EEC216 Winter 2008 7 Chip Power Density Distribution Power Map On-Die Temperature 250 110 100 200 90 150 80 70 100 Temperature (C) Heat Flux (W/cm2) Heat 60 50 50 0 40 • Power density is not uniformly distributed across the chip • Silicon not the best thermal conductor (isotopically pure diamond is) • Max junction temperature is determined by hot-spots – Impact on packaging, w.r.t. cooling R. Amirtharajah, EEC216 Winter 2008 8 Why worry about power ? Battery Size/Weight 50 Rechargable Lithium 40 Ni-Metal Hydride 30 20 Nickel-Cadmium Battery (40+ lbs) 10 Nominal Capacity (W-hr/lb) 0 65 70 75 80 85 90 95 Year Expected battery lifetime increase over the next 5 years: 30 to 40% From Rabaey, 1995 R. Amirtharajah, EEC216 Winter 2008 9 Recent Battery Scaling and Future Trends • Battery energy density increasing 8% per year, demand increasing 24% per year (the Economist, January 6, 2005) R. Amirtharajah, EEC216 Winter 2008 10 Why worry about power? Standby Power Year 2002 2005 2008 2011 2014 Power supply Vdd 1.5 1.2 0.9 0.7 0.6 (V) Threshold VT (V) 0.4 0.4 0.35 0.3 0.25 Drain leakage will increase if VT decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 8KW 50% …and phones leaky! 40% 1.7KW 30% 400W 20% 88W 12W 10% Standby Power 0% Source: Borkar, De Intel® R. Amirtharajah, EEC2162000 Winter 2002 2008 2004 2006 2008 11 Fundamental Shift: Near Constant VDD Year 2002 2005 2008 2011 2014 Power supply Vdd 1.5 1.2 1.0 1.0 1.0 (V) Threshold VT (V) 0.4 0.4 0.35 0.3 0.3 Leakage problem has caused voltage scaling with technology to slow down and potentially stop! New devices might restart trend (e.g., FinFET)… More emphasis on operating devices below threshold for low power applications R. Amirtharajah, EEC216 Winter 2008 12 Emerging Microsensor Applications Industrial Plants and Power Line Monitoring Operating Room of the Future (courtesy ABB) (courtesy John Guttag) Target Tracking & Detection NASA/JPL sensorwebs Location Awareness (Courtesy of ARL) (Courtesy of Mark Smith, HP) Websign R. Amirtharajah, EEC216 Winter 2008 13 Power as a System Design Consideration • Battery operated devices – Reasonable lifetime with limited weight for portability – Low to medium performance – Examples: PDAs, cell phones, multimedia terminals, laptops, wireless sensors • High performance applications – Power delivery and heat removal an issue for system and package cost, reliability – On chip hot spots degrade performance – Examples: desktops, servers, networking equipment R. Amirtharajah, EEC216 Winter 2008 14 Outline • Administrative Details • Why Care About Power? • Trends in CMOS Power Dissipation • Dynamic Power Dissipation • Short Circuit (Overlap) Current • Power-Delay Metric • Energy-Delay Metric • Logic Level Power Estimation • Next Topic: High Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 15 CMOS Inverter Example Idyn I sc Itun CL I subth R. Amirtharajah, EEC216 Winter 2008 16 Components of CMOS Power Dissipation • Dynamic Power – Charging and discharging load capacitances • Short Circuit (Overlap) Current – Occurs when PMOS and NMOS devices on simultaneously • Static Current – Bias circuitry in analog circuits • Leakage Current – Reverse-biased diode leakage – Subthreshold leakage – Tunneling through gate oxide R. Amirtharajah, EEC216 Winter 2008 17 Aside: NMOS Inverter Example Idyn constant I sc Itun CL I subth • Depletion NMOS always on, sourcing static current R. Amirtharajah, EEC216 Winter 2008 18 Power Dissipation as Technology Scales • From 2001 ITRS R. Amirtharajah, EEC216 Winter 2008 19 Outline • Administrative Details • Why Care About Power? • Trends in CMOS Power Dissipation • Dynamic Power Dissipation • Short Circuit (Overlap) Current • Power-Delay Metric • Energy-Delay Metric • Logic Level Power Estimation • Next Topic: High Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 20 Extremely Brief MOSFET Review μC W 2 Saturation: I = ox ()()V −V 1+ λV D 2 L GS T DS W ⎛ V 2 ⎞ ⎜ DS ⎟ Triode: I D = μCox ⎜()VGS −VT VDS − ⎟ L ⎝ 2 ⎠ V V GS ⎛ − DS ⎞ nkT kT Subthreshold: I = I e q ⎜1− e q ⎟ D S ⎜ ⎟ ⎝ ⎠ “Classical” MOSFET model, will discuss deep submicron modifications as necessary R. Amirtharajah, EEC216 Winter 2008 21 CMOS Delay and Power Dissipation CΔV C V Delay: Δt = = L dd I I D Total Power: PTOT = Pdyn + Psc + Pstat + Pleak ⎛ t + t ⎞ 2 ⎜ r f ⎟ = αCLVdd f +Vdd I peak ⎜ ⎟ f ⎝ 2 ⎠ +Vdd I static +Vdd Ileak To reduce power, minimize each term – starting with the biggest! Historically, biggest has been dynamic power… R. Amirtharajah, EEC216 Winter 2008 22 Low-to-High Transition Equivalent Circuit VDD iVDD vout CL R. Amirtharajah, EEC216 Winter 2008 23 Energy Drawn From Power Supply vout (t) iVDD (t) ∞ ∞ E = P (t)dt = i (t)V dt VDD ∫ VDD ∫ VDD DD 0 0 ∞ dv VDD = V C out dt = C V dv DD ∫ L L DD ∫ out 0 dt 0 2 = CLVDD R. Amirtharajah, EEC216 Winter 2008 24 Energy Stored on Load Capacitor ∞ E = i (t)v dt C ∫ VDD out 0 ∞ dv VDD = C out v dt = C v dv ∫ L out L ∫ out out 0 dt 0 1 2 = CLVDD 2 2 CLVDD • Compared to E , we see that dissipated VDD 2 • Same amount dissipated when capacitor discharged • Independent of MOSFET resistance R. Amirtharajah, EEC216 Winter 2008 25 Aside: Can We Do Better on Energy? 2 • Seems that C L V DD is pretty fundamental – Independent of resistance, circuit delay • Static CMOS logic basically configures FETs as switches connected to voltage sources – Transient determined by capacitor dynamics, RCL • But, suppose we use a current source to charge the capacitor instead… R. Amirtharajah, EEC216 Winter 2008 26 Preview: Adiabatic Charging R C iDD (t) L ∞ E = i (t)v (t)dt IDD ∫ DD IDD 0 • By controlling the current, we can control the voltage developed across the resistor, and reduce power consumption by charging slowly R. Amirtharajah, EEC216 Winter 2008 27 Deriving Dynamic Power • Each charge/discharge cycle dissipates total energy EVDD • To compute power, account for switching the circuit at frequency f • Typically, output does not switch every cycle, so we scale the power by the probability of a transition α • Putting it all together, we derive the dynamic power component of CMOS power dissipation: 2 Pdyn = αCLVDD f R. Amirtharajah, EEC216 Winter 2008 28 Why Is Power Getting Worse? • Same reason performance is getting better: scaling! – Finer lithography and thinner gate oxides imply faster devices… – …but we have to scale the supply voltage to maintain reliability… – …so in turn we have to decrease the threshold voltages to maintain performance… – …while we pack more devices onto bigger die • In the bad old days, supply voltage was fixed while devices got smaller (fixed voltage scaling) – Did not reap the full benefits of scaling MOS technology R. Amirtharajah, EEC216 Winter 2008 29 Competing Factors in Power Trend • Recently, we scaled supply voltages more closely with lithography generations • Suppose full scaling (constant electric field) with factor 1/S – Intrinsic gate delay
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