CS401 - Computer Architecture and Programming New Lecture Wise Questions& Answers for final terms Prepared BY “Virtualians.pk”

Lecture no 23:

Q)what are the basic purposes/operations of the "BIOS vs DOS"?

The BIOS software is built into the PC, and is the first code run by a PC when powered on ('boot firmware'). When the PC starts up, the first job for the BIOS is the power-on self-test, which initializes and identifies system devices such as the CPU, RAM, video display card, keyboard and mouse, hard disk drive, optical disc drive and other hardware. The BIOS then locates boot loader software held on a peripheral device (designated as a 'boot device'), such as a hard disk or a CD/DVD, and loads and executes that software, giving it control of the PC. This process is known as , or booting up, which is short for bootstrapping.

DOS is an for -based personal computers. It was the most commonly used member of the DOS family of operating systems

Q)what is firmware?

In electronic systems and computing, firmware is the combination of persistent memory and program code and data stored in it. Typical examples of devices containing firmware are embedded systems (such as traffic lights, consumer appliances, and digital watches), computers, computer peripherals, mobile phones, and digital cameras. The firmware contained in these devices provides the control program for the device. Firmware is held in non-volatile memory devices such as ROM, EPROM, or flash memory.

Q)What is effect of SP when we push something in stack? Please explain in detail with example.

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For understanding, consider the stack in lower part of memory in green color as below. Stack pointer is always pointing to the top of the stack. Now anything you place (push) onto the stack it will grow upward which will result in the decrement of stack pointer by 2 as read and write (push and pop) can be done only in word form i.e. 2 bytes. So Push AX will decrement SP by two.

1. 2.

3. 4. 5.

6. 7. 8.

9. 10. ↑ 11. ←SP

12. 13. Growing 14. Upward

15. 16.

Lecture no 24:

Q)what is a buffer memory? Buffer is a region of a physical memory storage used to temporarily prevent data from continuing while it is being moved from one place to another. Typically, the data is stored in a buffer as it is retrieved from an input device (such as a mouse) or just before it is sent to an output device (such as speakers).

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Q)Regarding execute any programme in debugger, What is difference in F1 and F2?

For executing assembly commands both F1 and F2 keys can be used. There is one difference between them. F2 is used when we are executing simple assembly instructions and F1 is helpful when we want to execute a subroutine line by line otherwise if we execute a subroutine with F2 key, it will execute that subroutine as a whole in one step.

Q)Difference between CS and DS? Can we use CS at the right or bottom in the debugger?

CS means Code segment while DS stands for Data segment. These are two of the four segments that we have for every assembly program. Each segment is of size 64K.

AFD debugger is used to see the step by step working of our program and it also provides us two memory windows M1 and M2 where we can load any segment whose content we want to see. There is no such hard association between these windows and segments.

Lecture no 25:

Q)What does segment over write mean?

Segment override prefix makes us able to use and access memory location other than current segment. In instruction

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Mov AX, [123]

We are moving the content at an offset address 123 in current segment pointed by CS register and through following instruction we can access any part in the main memory.

Mov AX, [4455:123]

In above, we are moving the content at an offset address 123 in a segment having base address 4455.

Thus segment override makes us able to avoid default association of registers with segments.

Q)Main difference between CS and DS?

CS means Code segment while DS stands for Data segment. These are two of the four segments that we have for every assembly program. Each segment is of size 64K.

What are function of I/O ports I/O ports are used to communicate with external world, the data is stored in mostly accumulator register and size depends upon the architecture to architecture.

The term real world means the world out side the system/processor/computer.

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Lecture no 26: Q) What is PIC Ports

All input and output on the PIC is performed via the I/O ports. I/O ports are like RAM locations with wires leading from the bits to the pins of the microchip.

I/O ports on a PIC are memory mapped. This means that to read from or write to a port on a PIC the program must read from or write to a special RAM location. To access PORTA on the 16F84, 16F628, 16F88, 16F876 or 16F877 the program must access the RAM at address location 5.

The I/O ports on the PIC can be used as either inputs or outputs. In order to use a port as an input it must be configured as an input. To use it as an output it must be configured as an output. Configuring a port for input or output is done by setting or clearing the data direction register for the port. On the PIC each bit of each port has a data direction bit. Therefore it is possible to set some bits within a port as inputs and others within the same port as outputs. The data direction bits can be thought of as flags that mark the direction in which the data moves between the outside world and the PIC (into the PIC or out of the PIC). A data direction register on the PIC is called a TRIS register

Q)What is difference between I/O devices and Prepheral devices?

There are many peripheral devices in computer and for communicating with these peripheral devices the processor uses I/O ports. Remember, port is the gateway used to read or write data for peripheral devices. For this purpose we write assembly programs in which we access I/O port of the device and then read / write data in to it. There are many assembly programs we have made to access keyboard, VGA, PIC etc.

Lecture no 27:

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Q)When we press a key then it run IRQ 1 and cause of this INT 9 invoke. Then when INT 16 invoke internally when we press a key?(as it's also inturrept of keyboard so when i invoke internally)

Through INT 16 various BIOS keyboard services are accessed. Let say, you want to get an input a character from the user in your program then how you will read a character in your assembly program? This can be done using INT 16 with get a key service by setting AH to 0. So

MOV AH, 0

INT 0x16

The above two lines we are accessing BIOS get a key service using INT 16 and this will halt the program until a key is pressed by the user and that will be returned in AL register.

But whenever a key is pressed on keyboard then IRQ 1 is generated which invokes service routine INT 9 to handle this key press event. We can use this INT 9 to read the scan code of the pressed key from port 60 by hooking it with our own interrupt service routine.

Lecture no 28:

Q)Regarding INT 0x16, it's BIOS keyboard service, it's clear but INT 9 is not BIOS service? BIOS is not offereing INT 9? If yes then why we explicitly say with INT 0x16 but not with INT 9.??

INT 9 is also a BIOS interrupt call and its implementation is provided mainly by Manufacturer in the BIOS which is stored on ROM. We do not call it is a service because it does not offer various service like INT 16 or INT 10 does. INT 9

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performs its designated functions when invoked by IRQ 1 and we can hook our routine to do some desired operations.

WHAT IS TSR? TSR programs are pop-ups or special device drivers. The TSR mechanism provides a convenient way for you to load your own routines to replace or augment BIOS routines. Your program loads into memory, patches the appropriate interrupt vector so that it points at an interrupt handler internal to your code and then terminates and stays resident,when the appropriate interrupt instruction is executed, your code will be called rather than BIOS.

Lecture no 29:

If we want a keystrok then we use the following instructions as you mentioned

mov ah, 0 0x16 but the same work do with the following instruciton in al, 0x60 ; this instruction also for keystroke then what is difference between these two methods?

Using mov ah, 0 int 0x16

We will get ASCII code in AL.

But with in al, 0x60

We will get scan code in AL.

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That’s the difference. ASCII and Scan codes are different.

Q)What is main difference between and DMA?

In systems programming, an interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention.

Direct memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit (CPU).

Lecture no 30:

The Memory Address Register (MAR) is a CPU register that either stores the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored.

Segment registers used to point towards a specific segment.

The 6 Segment Registers are: • Stack Segment (SS). Pointer to the stack. • Code Segment (CS). Pointer to the code. • Data Segment (DS). Pointer to the data. • Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra').

The control transfer instructions used to direct the flow of execution. Conditional control transfers depend on the results of operations that affect the flag register. Unconditional control transfers are always executed. Fetch means to read/take an instruction.

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Q)DEBUGGER USING SINGLE STEP INTERRUPT Explain ? The use of the trap flag has been deferred till now. The three flags not used

for mathematical operations are the direction flag, the interrupt flag and the

trap flag. The direction and interrupt flags have been previously discussed.

If the interrupt flag is set, the after every instruction a type 1 interrupt will

be automatically generated. When the IVT and reserved interrupts were

discussed this was named as the single step interrupt. This is like the divide

by zero interrupt which was never explicitly invoked but it came itself. The

single step interrupt behaves in the same manner.

The debugger is made using this interrupt. It allows one instruction to be

executed and then return control to us. It has its display code and its code to

wait for the key in the INT 1 handler. Therefore after every instruction the

values of all registers are shown and the debugger waits for a key. Another

interrupt used by the debugger is the break point interrupt INT 3. Apart from

single stepping debugger has the breakpoint feature. INT 3 is used for this

feature. INT 3 has a single byte opcode so it can replace any instruction. To

put a breakpoint the instruction is replaced with INT 3 opcode and restored

in the INT 3 handler. The INT 3 opcode is placed again by a single step

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interrupt that is set up for this purpose after the replaced instruction has

been executed.

Lecture no 31 Pins correspondence

mov dx, 0x37A mov al,0x01 which pin will be set.

mov dx, 0x378 mov al, 0x9D out dx, al which pins will be at what position.

answer

In the instruction mov dx, 0x37A , 0x37A is the port number for accessing control port within parallel port. In the next instruction mov al, 0x01, first bit (pin) of control port is set to 1.

Similarly, in the instruction, mov dx, 0x378 , 0x378 is the port number for accessing data port within parallel port. When the instruction, mov al, 0x9D is executed, bits 1, 3, 4, 5 and 8 of the data port are set to 1.

To see how it works, let us convert the value 0x9D in its binary representation. The binary representation of 0x9D is 10011101. From this binary representation, it can be clearly seen those bits which are set.

Q)Interrupts are basically categorized into two broad classes. These classes are hardware interrupts and software interrupts.

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A hardware interrupt occurs as result of some signal sent to the processor from an external device, either a part of the computer itself such as a disk controller or an external peripheral. There are many external devices that need the processor’s attention like the keyboard, hard disk, floppy disk, sound card. All of them need real time interrupts at some point in their operation. One example can be taken is of Printer, when the printer is busy printing we cannot send it more data. As soon as it gets free from the previous job it interrupts the processor to inform that it is free now. When a hardware interrupt occurs, all interrupts are disabled and registers are pushed onto the stack.

On the other hand, a software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed. Software interrupts are also called Traps or Exceptions. Exceptions or traps are used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself.

What is multitasking? The ability to execute more than one task at the same time, a task being a program. The terms multitasking and multiprocessing are often used interchangeably, although multiprocessing implies that more than one CPU is involved. In multitasking, only one CPU is involved, but it switches from one program to another so quickly that it gives the appearance of executing all of the programs at the same time. There are two basic types of multitasking: preemptive and cooperative. In preemptive multitasking, the operating system parcels out CPU time slices to each program. In cooperative multitasking, each program can control the CPU for as long as it needs it.

Lecture no 32:

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Q)Concept of MultitaskingExplain? In essence multitasking is simple, even though we have to be extremely careful when implementing it.

The environment of a program in the very simple case is all its registers and stack.

We will deal with stack later. Now to get control from the program without the program knowing about it,

we can use the IRQ 0 highest priority interrupt that is periodically coming to the processor.

Q)Which registers are uses as scratch when we call a function?

It seems that you want to ask about the calling a function written into high level language, from an assembly language program. In this case, registers EAX, ECX and EDX are used as scratch registers.

Lecture no33:

Q)When IRQ is automatically generated, it is our responsiblty to give the EOI instruction, or it will automatically ends, and other IRQ will enable automatically? Interrupt request from a device enters the PIC as an IRQ, from there it reaches the INT pin of the processor, the processor receives the interrupt number from the PIC, generates the designated interrupt, and finally the interrupt handler gain control and can do whatever is desired. At the end of servicing the interrupt the handler should inform the PIC that it is completed so that lower priority interrupts can be sent from the PIC.

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This signal is called an End Of Interrupt (EOI) signal and is sent through the I/O ports of the interrupt controller.

Lecture no 34: Q)Do we assume that "kernal type" program means multi-tasking ? There are, IIRC, some (a few?) pre-emptive multi-tasking kernels available that load a TSR in advance of your program and one that will incorporate the multi tasking in the program via a unit. IIARC, this requires a number of changes to your code.

The pre-emptive multi taasking means you don't have to worry about making explicit calls to task switchers.

Q)How can we clear the trap flag if there is mechanism or any way to set or clear the trap flag.?

There is no instruction to set or clear the trap flag like there are instructions for the interrupt and direction flags. We use two special instructions PUSHF and POPF to push and pop the flag from the stack. We use PUSHF to place flags on the stack, change TF in this image on the stack and then reload into the flags register with POPF. The single step interrupt will come after the first instruction after POPF. The interrupt mechanism automatically clears IF and TF otherwise there would an infinite recursion of the single step interrupt. The TF is set in the flags on the stack so another interrupt will comes after one more instruction is executed after the return of the interrupt.

Lecture no 35:

Q)what is the benefit of this termination than full free termination.?

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In DOS, there is a pointer freemem which points at the beginning of the free memory. When DOS loads a non-TSR program, the freemem pointer is moved to the end of memory, all the available space is allocated to it, and when it exits the freemem pointer comes back to its original place thereby reclaiming all space. But in case of a TSR, the memory remains allocated to the program.

If it is a non-TSR program, then our program will be crashed because the interrupt routine will be overwritten after memory being de-allocated. But If we can tell DOS not to reclaim the memory of the interrupt routine, then it will not crash that is the reason for writing TSR programs.

Q) What is IVT and STR?

An interrupt vector table, a concept common across various processor architectures, is a table of interrupt vectors that associates an interrupt handler with an interrupt request in a machine specific way while In systems programming an interrupt handler, also known as an Interrupt Service Routine (ISR), is a callback subroutine in microcontroller firmware, operating system or whose execution is triggered by the reception of an interrupt. Interrupt handlers have a multitude of functions, which vary based on the reason the interrupt was generated and the speed at which the interrupt handler completes its task.

Lecture no 36:

Q)Can we use PUSHF and POPF for trap flag directly?

There is no instruction to set or clear the trap flag like there are instructions for the interrupt and direction flags. We use two special instructions PUSHF and POPF to push and pop the flag from the stack. We use PUSHF to place flags on the stack, change TF in this image on the stack and then reload into the flags register with POPF. The single step interrupt will come after the first instruction after POPF. The interrupt mechanism automatically clears IF and TF otherwise there would an infinite recursion of the single

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step interrupt. The TF is set in the flags on the stack so another interrupt will comes after one more instruction is executed after the return of the interrupt

Lecture no 37:

Q)What is the main difference b/w int1 and int 3 instruction? INT 1, is a Trap, Single step Interrupt. Which is used in debugging with the trap flag. If the trap flag is set the Single Step Interrupt is generated after every instruction. By hooking this interrupt a debugger can get control after every instruction and display the registers etc. 8088 was the first processor that has this ability to support debugging.

INT 3 is a Debug Interrupt. The only special thing about this interrupt is that it has a single byte opcode and not a two byte combination where the second byte tells the interrupt number. This allows it to replace any instruction whatsoever. It is also used by the debugger and will be discussed in detail with the debugger working.

Q)What is meant by IVT and STR?

An interrupt vector table, a concept common across various processor architectures, is a table of interrupt vectors that associates an interrupt handler with an interrupt request in a machine specific way while In systems programming an interrupt handler, also known as an Interrupt Service Routine (ISR), is a callback subroutine in microcontroller firmware, operating system or device driver whose execution is triggered by the reception of an interrupt. Interrupt handlers have a multitude of functions, which vary based on the reason the interrupt was generated and the speed at which the interrupt handler completes its task.

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Lecture no 38:

Q) what is meant by no re entry?? No re-entry means once executed cant be used or executed again. Are INT1 and INT3 both single step intrupt means after every statement execution are they generated?

INT 1 is a single step Interrupt, which is used in debugging with the trap flag. If the trap flag is set the Single Step Interrupt is generated after every instruction. By hooking this interrupt a debugger can get control after every instruction and display the registers etc. 8088 was the first processor that has this ability to support debugging.

. INT 3 is a debug Interrupt. The only special thing about this interrupt is that it has a single byte opcode and not a two byte combination where the second byte tells the interrupt number. This allows it to replace any instruction whatsoever. It is also used by the debugger and will be discussed in detail with the debugger working

Q) Difference b/w the INT 1 AND INT 3. ?

NT 1 is a single step Interrupt, which is used in debugging with the trap flag. If the trap flag is set the Single Step Interrupt is generated after every instruction. By hooking this interrupt a debugger can get control after every instruction and display the registers etc. 8088 was the first processor that has this ability to support debugging.

INT 3 is a debug Interrupt. The only special thing about this interrupt is that it has a single byte opcode and not a two byte combination where the second byte tells the interrupt number. This allows it to replace any instruction whatsoever. It is also used by the debugger and will be discussed in detail with the debugger working.

Lecture no 39:

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Q)What is LBA and waht is the purpose of LBA in partion?

Logical block addressing (LBA) is a common scheme used for specifying the location of blocks of data stored on computer storage devices, generally secondary storage systems such as hard disks.

Q)what is MBR and what is the purpose of MBR?

A (MBR) is a special type of boot sector at the very beginning of partitioned computer mass storage devices like fixed disks or removable drives intended for use with IBM PC-compatible systems and beyond. The MBR holds the information on how the logical partitions, containing file systems, are organized on that medium. Besides that, the MBR contains executable code to function as an operating system- independent chain boot loader in conjunction with each partition's (VBR).

MBRs are not present on non-partitioned media like floppies, superfloppies or other storage devices configured to behave as such.

Lecture no 40: Q)Why are device drivers necessary, given that the BIOS already has code that communicates with the computer's hardware?

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BIOS only defines the lowest level of control over the hardware. It defines the interaction between the motherboard and hardware in order to hardware to work. For example, controlling the clock speed of CPU and RAM, how the ports control the hard drives and optical drives, defining the boot priorities of different devices etc. All of these are applied before the OS loads and when the OS is fully loaded, this control given to the OS.

As far as working of a device drivers are concerned, their role comes into play when OS is fully loaded. The device drivers then define how to operate or control a particular type of device that is attached to a computer. If there is a setting in the BIOS the hardware knows how to interact, but once the OS boots and it doesn't have the driver to use this particular setting the hardware won't be usable due to not understanding it.

Lecture no 41:

Q)DEBUGGER USING BREAKPOINT INTERRUPT Explain?

We now write a debugger using INT 3. This debugger stops at the same point every time where the breakpoint has been set up unlike the previous one which stopped at every instruction. The single step interrupt in this example is used only to restore the breakpoint interrupt which was removed by the breakpoint interrupt handler temporarily so that the original instruction can be executed

Lecture no 42

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.Q) What is SUN SPARC PROCESSOR?

The Sun SPARC is a very popular processing belonging to the RISC

(reduced instruction set computer) family of processors. RISC processors originally named because of the very few rudimentary instructions they provided, are now providing almost as many instruction as CISC (complex instruction set computer). However some properties like a fixed instruction size and single clock execution for most instructions are there.

SPARC stands for Scalable Processor ARChitecture. SPARC is a 64bit processor. It byte order is user settable and even on a per program basis. So one program may be using little endian byte order and another may be using big endian at the same time. Data types include byte, Halfword, Word (32bit), and Double Word (64bits) and Quadword. It has a fixed 32bit instruction size. It has a concept of ASI (Address Space Identifier); an 8bit number that works similar to a segment.

There are 8 global registers and 8 alternate global registers. One of them is active at a time and accessible as g0-g7. Apart from that it has 8 in registers

(i0-i7), 8 local registers (l0-l7), and 8 out registers (o0-o7). All registers are

64bit in size. The global registers can also be called r0-r7, in registers as r8- r15, local registers as r16-r23, and out registers as r24-r31.

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SPARC introduces a concept of register window. One window is 24 registers and the active window is pointed to by a special register called

Current Window Pointer (CWP). The actual number of registers in the processor is in hundreds not restricted by the architecture definition. Two instruction SAVE and RESTORE move this register window forward and backward by 16 registers. Therefore one SAVE instruction makes the out register the in registers and brings in new local and out registers. A

RESTORE instruction makes the in registers out registers and restores the old local and in registers. This way parameters passing and returning can be totally done in registers and there is no need to save and restore registers inside subroutines.

Lecture no 43

Q) What is MOTOROLLA 68K PROCESSORS ?

Motorolla 68K processors are very similar to Intel x86 series in their architecture and instruction set. The both are of the same era and added various features at the same time. The instructions are very similar however the difference in architecture evident from a programmer’s point of view must be understood.

68K processors have 16 23bit general purpose registers named from A0-A7

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and D0-D7. A0-A7 can hold addresses in indirect memory accesses. These can also be used as software stack pointers. Stack in 68K is not as rigit a structure as it is in x86. There is a 32bit program counter (PC) that holds the address of currently executing instruction. The 8bit condition code register

(CCR) holds the X (Extend) N (Negative) Z (Zero) V (Overflow) C (Carry) flags.

X is set to C for extended operations (addition, subtraction, or shifting).

Motrolla processors allow bit addressing, that is a specific bit in a byte or a bit field, i.e. a number of bits can be directly accessed. This is a very useful feature especially in control applications. Other data types include byte, word, long word, and quad word. A special MOVE16 instruction also accepts a 16byte block.

68K allows indirect memory access using any A register. A special memory access allows post increment or predecrement as part of memory access.

These forms are written as (An), (An)+, and –(An).

Lecture no 44:

Q)What is the function of this code bp+4?

By default, address reference made through BP register is associated with Stack segment. Now let say BP=20 then [BP] will access memory location in Stack segment at offset 20

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and [BP+4] will access memory location in Stack segment at offset 24. This is generally used to access parameter passed to routine through stack.

Lecture no 45:

Q)What is the difference between software intruppet and hardware intruppe Are these confiluct ech other ?

some times when we are using any computer key board it feels that key board is not responding and few seconds it will works Is it due to intruppets. Hardware interrupts are the real interrupts generated by the external world. Software interrupts on the contrary are not generated from outside the processor. They just provide an extended far call mechanism. Far call allows us to jump anywhere in the whole megabyte of memory. To return from the target we place both the segment and offset on the stack. Software interrupts show a similar behavior. It however pushes one more thing before both the segment and offset and that is the FLAGS register.

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