Technical Reference Manual

PIP3x

High-Tech • Made in Switzerland Technical Reference Manual

PACKED INDUSTRIAL PC WITH INTEL CORE i PROCESSOR

The PIP is a low power, highly integrated rugged industrial PC with a specially designed aluminum housing. This allows to operate the PIP in a moderate or also in a harsh environment without fan or ventilation holes. The design integrates standard connectors for easy connection. Therefore the PIP can be used for any PC application where a complete solution is needed. The PIP housing, available in different sizes, offers space for miscellaneous add-ons. With the integrated SATA ports, the PCI/104-Express interface and the two PCI-Express Full-Mini Card sockets there are flexible expansion interfaces available. Fully bootable flash disks are supported for shock and vibration critical projects. Particular precautions have been taken that the entire system EMC is within the CE and FCC limits. All these features make the PIP the ideal solution for the industry wherever a flexible, rugged, durable and complete Industrial PC is needed.

Features: ● PIP31: Celeron 927UE 1.5 GHz single core with ● Two SATA 2.0 ports (3 Gb/s) 1.0 MiB Cache ● One eSATAp port (with USB 2.0 and SATA 2.0) ● PIP32: Celeron 1047UE 1.4 GHz dual core with ● One ePCIe x1 External Cabling port (500 MB/s) 2 MiB Cache ● Two serial ports with RS232 interface ● PIP37: 3rd Gen Core i7-3517UE 1.7 GHz dual ● Two serial ports with RS232 or RS485 interface core with 4 MiB Cache (optional) ● PIP38: 3rd Gen Core i7-3555LE 2.5 GHz dual ● One PCI/104-Express Type 1 connector core with 4 MiB Cache ● One mPCIe / mSATA Full-Mini Card combo socket ● Up to 12 GiB dual channel DDR3-1600 memory ● One mPCIe Full-Mini Card socket (including 4 GiB soldered down memory) ● Super-IO watchdog timer with hardware reset ● ECC support in soldered down memory capability ● Intel HD Graphis 2000 or 4000 with DP++, DVI-I ● Power input with load dump and reverse polarity and 24 Bit LVDS interface protection ● Four Intel Gb Ethernet ports ● Power input with galvanic isolation (optional) ● Four USB 3.0 ports (4800 Mb/s) ● DIN rail or flange installation ● Up to five USB 2.0 ports (480 Mb/s) ● RoHS compliant ● Two SATA 3.0 ports (6 Gb/s)

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TABLE OF CONTENTS

1 INTRODUCTION...... 7 1.1 ABOUT THIS MANUAL...... 7 1.2 SAFETY PRECAUTIONS AND HANDLING...... 7 1.3 ELECTROSTATIC DISCHARGE (ESD) PROTECTION...... 7 1.4 EQUIPMENT SAFETY...... 7 1.5 MANUAL REVISIONS...... 8 1.5.1 RELATED PRODUCTS...... 8 1.5.2 REVISION HISTORY...... 8 1.6 RELATED DOCUMENTATION...... 9 1.7 STANDARDS COMPLIANCE...... 10 1.7.1 EMC...... 10 1.7.2 ENVIRONMENTAL...... 10 1.7.3 SAFETY...... 10 1.7.4 TYPE APPROVAL...... 10 1.8 ORDERING INFORMATION...... 11

2 SPECIFICATIONS...... 12 2.1 FEATURES SUMMARY...... 12 2.2 ELECTRICAL RATINGS...... 14 2.2.1 POWER INPUT...... 14 2.2.2 POWER DISSIPATION...... 14 2.3 MECHANICAL SPECIFICATIONS...... 14 2.4 ENVIRONMENTAL CONDITIONS...... 15

3 HARDWARE REFERENCE...... 16 3.1 HOUSING DIMENSIONS...... 16 3.1.1 TOP VIEW...... 16 3.1.2 BOTTOM VIEW...... 17 3.1.3 SIDE VIEW 1...... 18 3.1.4 SIDE VIEW 2...... 19 3.1.5 SIDE VIEW 3...... 20 3.1.6 SIDE VIEW 4...... 20 3.2 OPENING THE CASE...... 21 3.3 DIMENSIONS AND PLACEMENT...... 22 3.3.1 PCB DIMENSIONS...... 22 3.3.2 PARTS LOCATION...... 23 3.4 SWITCH SETTINGS...... 24 3.4.1 DIP SWITCH 1 (S1) – IGNITION INPUT POLARITY SELECTION...... 24 3.4.2 DIP SWITCH 2 (S2) – PERIPHERAL SETTINGS...... 24 3.4.3 DIP SWITCH 3 (S3) – PCI/104-EXPRESS IO-VOLTAGE SELECTION...... 24 3.4.4 DIP SWITCH 4 (S4) – ON BOARD LVDS PORT (LCD PANEL) SETTINGS...... 25 3.4.5 DIP SWITCH 5 (S5) – PCIe EXT. CABLING REDRIVER SETTING...... 25 3.4.6 DIP SWITCH 7 (S7) – RESERVED...... 26 3.4.7 DIP SWITCH 8 (S8) – eSATAp SATA REDRIVER SETTING...... 26 3.4.8 DIP SWITCH 9 (S9) – ETHERNET WAKE ON LAN (WOL) SETTINGS...... 26 3.4.9 DIP SWITCH 2000 (S2000) – BACKLIGHT ENABLE LOGIC LEVEL...... 26 3.5 CONNECTORS...... 27 3.5.1 EXTERNAL CONNECTORS...... 27 3.5.1.1 Serial-1 (J65) and Serial-2 (J67) Connectors...... 27 3.5.1.2 Optional Serial-3 and Serial-4 Connectors...... 27 3.5.1.3 External Power Connector (J21)...... 28

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3.5.1.3.1 Pin Assignment...... 28 3.5.1.3.2 Power Input Protection Circuits...... 28 3.5.1.3.3 Power Up Behavior...... 28 3.5.1.3.4 Power Input Circuit...... 28 3.5.1.4 Ignition Input, Reset- and Power Button Connector (J53)...... 29 3.5.1.4.1 Pin Assignment...... 29 3.5.1.4.2 IGN, PWR- and RST-Button Circuit...... 29 3.5.1.5 PS/2 Keyboard and Mouse Connector (J49)...... 30 3.5.1.6 Dual USB 3.0 Connectors (J8, J4)...... 30 3.5.1.7 Dual USB 2.0 Connector (J9)...... 30 3.5.1.8 DVI-I Connector (J16)...... 31 3.5.1.9 Gb Ethernet Connectors (J22, J34, J26, J28)...... 31 3.5.1.10 eSATAp Connector (J40)...... 32 3.5.1.11 PCIe External Cabling Connector (J51)...... 32 3.5.1.12 Dual Mode Display Port (DP++) Connector (J18)...... 33 3.5.2 INTERNAL CONNECTORS...... 34 3.5.2.1 SATA 3.0 Signal Connectors (J12, J13)...... 34 3.5.2.2 SATA 2.0 Signal Connectors (J73, J74)...... 34 3.5.2.3 SATA Power Connectors (J75, J76)...... 34 3.5.2.4 SATA SGPIO Connector (J2002)...... 34 3.5.2.5 LED Indicator Panel Connector (J42)...... 35 3.5.2.6 LVDS Connector (J14)...... 35 3.5.2.7 Backlight Inverter Connector (J15)...... 36 3.5.2.8 Panel Dimming Connector (J24)...... 36 3.5.2.9 Internal Power Connector 1 (J36)...... 36 3.5.2.10 Internal Power Connector 2 (J37)...... 37 3.5.2.11 Power Input Extension Connector (J35)...... 37 3.5.2.12 High Definition Audio Connector (J43)...... 37 3.5.2.13 USB2.0 Header Connector (J58, J59, J60)...... 37 3.5.2.14 Reset & Power Button Connector (J7)...... 38 3.5.2.15 PCI/104-Express Interface Type 1 Connector (J2, PCIe Part)...... 39 3.5.2.16 PCI/104-Express Interface Connector (J3, PCI Part)...... 40 3.5.2.17 PCI/104-Express Power Connector (J52)...... 40 3.5.2.18 Internal TTL Level Serial Port 3 (J68) and 4 (J69) Connectors...... 41 3.5.2.19 mPCIe Full-Mini Card Socket 1...... 41 3.5.2.20 mPCIe Full-Mini Card Socket 1 WLAN Disable Connector (J38)...... 41 3.5.2.21 mPCIe / mSATA Full-Mini Card Combo Socket 2...... 42 3.5.2.22 mPCIe / mSATA Full-Mini Card Combo Socket 2 WLAN Disable Connector (J70)...... 42 3.5.2.23 Fan 1 and Fan 2 Connectors (J2000, J2001)...... 42 3.5.2.24 IPT700 Connector (J19)...... 42 3.5.2.25 LPC Bus Expansion Connector (J7)...... 42 3.5.2.26 JTAG Port Connector (J78)...... 43 3.5.2.27 SPI Port Connector (J6)...... 43 3.6 MODULE SOCKETS...... 44 3.6.1 MEMORY MODULE...... 44 3.6.1.1 Electrical and Mechanical Requirements...... 44 3.6.1.2 Mounting the Memory Module...... 44 3.6.2 RS232 AND RS422 / RS485 INTERFACE MODULES...... 44 3.6.3 PCI/104-EXPRESS MODULES...... 44 3.6.4 mPCIe AND mSATA MODULES...... 44 3.7 SYSTEM-VOLTAGES SUPPLIED BY THE PIP...... 45 3.7.1 -12 V AND +12 V...... 45 3.7.2 +3.3 V STANDBY, +3.3 V, +5 V STANDBY AND +5 V...... 45

4 THEORY OF OPERATION...... 46 4.1 BLOCK DIAGRAM...... 46 4.2 STATUS INDICATORS...... 47 4.3 BATTERY CIRCUIT...... 47 4.4 RS485 / RS422 INTERFACES...... 48 4.5 WATCHDOG TIMER...... 48 4.6 TEMPERATURE SENSORS...... 48

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4.7 EARTHING AND GALVANIC ISOLATION...... 48 4.7.1 DESKTOP PC EARTHING SCHEME (PIP DEFAULT)...... 49 4.7.2 GALVANICALLY ISOLATED HOUSING (OPTIONAL)...... 49 4.7.3 GALVANICALLY ISOLATED HOUSING AND POWER INPUT (OPTIONAL)...... 49 4.7.4 CONCLUSION...... 49

5 SOFTWARE...... 50 5.1 PIP EXTENSION REGISTER SET...... 50 5.1.1 OVERVIEW...... 50 5.1.2 SERIAL PORTS STATUS REGISTER...... 51 5.1.3 BOOT LED REGISTER...... 51 5.1.4 SATA POWER REGISTER...... 52 5.1.5 ACPI BIOS SCRATCH REGISTER...... 52 5.1.6 USER LED REGISTER...... 52 5.1.7 PIP STATUS REGISTER 1...... 53 5.1.8 PIP STATUS REGISTER 2...... 53 5.1.9 PIP PCB REVISION REGISTER...... 54 5.1.10 PLD CODE ID REGISTER...... 54 5.1.11 PLD CODE REVISION REGISTER...... 54 5.2 BIOS...... 55 5.3 DEVICE DRIVERS...... 55 5.4 TOOLS...... 55

6 COPYRIGHT...... 56

7 DISCLAIMER...... 56

8 TRADEMARKS...... 56

9 SUPPORT...... 56 9.1 FAQs...... 56 9.2 SERIAL NUMBER AND REVISION...... 56 9.3 CONTACTING MPL AG...... 56

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TABLE OF FIGURES Figure 1: PIP Housing Top View (with Cover Foil)...... 16 Figure 2: PIP Housing Bottom View...... 17 Figure 3: PIP Housing Side View 1...... 18 Figure 4: PIP Housing Side View 2...... 19 Figure 5: PIP Housing Side View 3...... 20 Figure 6: PIP Housing Side View 4...... 20 Figure 7: Removing The 6 Screws...... 21 Figure 8: Lift Up The Top Cover...... 21 Figure 9: Locations Of The Standoff And Mounting Holes...... 22 Figure 10: Parts Location...... 23 Figure 11: DIP Switch 1...... 24 Figure 12: DIP Switch 2...... 24 Figure 13: DIP Switch 3...... 24 Figure 14: DIP Switch 4...... 25 Figure 15: DIP Switch 5...... 25 Figure 16: DIP Switch 7...... 26 Figure 17: DIP Switch 8...... 26 Figure 18: DIP Switch 9...... 26 Figure 19: DIP Switch 2000...... 26 Figure 20: Serial Port Connector (DSUB 9 Male) (Compona, 363 011-0)...... 27 Figure 21: Serial Port Connector (DSUB 9 Male) (Compona, 329 351-5)...... 27 Figure 22: Power Connector (Phoenix Contact AG, PSC 1,5/3-M-PE)...... 28 Figure 23: Connections Between all the PIP Power Connectors...... 28 Figure 24: Mini DIN Connector (Compona, 129164-3)...... 29 Figure 25: External Ignition Switch and External Power- and Reset-Button Circuits...... 29 Figure 26: PS/2 Keyboard & Mouse Connector (Compona, 129108-7)...... 30 Figure 27: Dual USB 3.0 (Type A) Connector (TE, 1932355-1)...... 30 Figure 28: Dual USB 2.0 (Type A) Connector (FCI, 72309-0010B)...... 30 Figure 29: DVI-I Connector (Molex , 074320-1003)...... 31 Figure 30: RJ45 Connector (HanRan HR921148C)...... 31 Figure 31: eSATAp Connector (FCI, 10074703-001RLF)...... 32 Figure 32: ePCIe Connector (Molex, 74960-3018)...... 32 Figure 33: DP++ Connector (TE, 2040204-1)...... 33 Figure 34: SATA Connector (Molex, 67800-8125)...... 34 Figure 35: SATA Connector (Molex, 67800-8125)...... 34 Figure 36: Power Connector for SATA Devices (Samtec, IPL1-105-02-S-D)...... 34 Figure 37: SGPIO Connector for SATA RAID LED Indicators (Molex, 501331-0507)...... 34 Figure 38: LED Indicator Panel Connector (Molex, 501331-0707)...... 35 Figure 39: LVDS Panel Connector (Molex, 501190-3017)...... 35 Figure 40: Backlight Inverter Connector (Hirose, DF11CZ-16DP-2V)...... 36 Figure 41: Panel Dimming Connector (Molex, 501331-0407)...... 36 Figure 42: Internal Power Connector (Samtec, IPL1-104-02-S-D)...... 36 Figure 43: Internal Power Connector 2 (Samtec, IPL1-105-02-S-D)...... 37 Figure 44: Power Input Extension Connector (Molex, 39-28-1043)...... 37 Figure 45: HD Audio Connector (Molex, 501331-1207)...... 37 Figure 46: USB2.0 Header Connector (Molex 501331-0407)...... 37 Figure 47: Reset & Power Button Connector (Samtec, IPL1-102-02-S-D)...... 38 Figure 48: PCI/104-Express Connector (Samtec, ASP-129637-03)...... 39 Figure 49: PC/104+ Connector (Samtec, ESQT-130-03-MQ-368)...... 40 Figure 50: PCI/104-Express Power Connector (Samtec, IPL1-105-02-L-S-K)...... 40 Figure 51: TTL Level Serial Port Connector (Fischer, SLY-2-085-12G)...... 41 Figure 52: mPCIe Full-Mini Card Socket Connector (JAE, MM60-52B1-E1-R650)...... 41 Figure 53: WLAN Disable Solder Pads...... 41 Figure 54: mPCIe / mSATA Full-Mini Card Combo Socket Connector (JAE, MM60-52B1-E1-R650)...... 42 Figure 55: WLAN Disable Solder Pads...... 42 Figure 56: Fan 1 and Fan 2 Connectors (Molex, 501331-0607)...... 42 Figure 57: Mounting The Memory Module...... 44 Figure 58: Complete PIP Block Diagram...... 46

High-Tech • Made in Switzerland Technical Reference Manual

Figure 59: Removing the 6 screws...... 47 Figure 60: PIP Label...... 56

High-Tech • Made in Switzerland Technical Reference Manual

1 INTRODUCTION

1.1 ABOUT THIS MANUAL This manual and the appropriate PIP System BIOS User Manual provide information for handling and configuring the PIP industrial PC. Be sure to read this manual before attempting to use the PIP, and keep the manual close at hand for reference during operation. This manual is written for advanced technical personnel responsible for integrating the PIP into their systems.

1.2 SAFETY PRECAUTIONS AND HANDLING For personal safety and safe operation of the PIP, follow all safety procedures described here and in other sections of the manual.

● Remove power from the system before installing (or removing) the PIP, to prevent the possibility of personal injury (electrical shock) and / or damage to the product. ● Handle the product carefully; i.e. dropping or mishandling the PIP can cause damage to assemblies and components. ● Do not expose the equipment to moisture.

1.3 ELECTROSTATIC DISCHARGE (ESD) PROTECTION Various electrical components within the product are sensitive to static and electrostatic discharge. Even a small static discharge can be sufficient to destroy or degrade a component's operation! Do not touch any electronic components at a PIP in an open standard housing or at an open frame cooling plate. Handle or touch only the unit chassis. Handle and mount SO-DIMM modules, PCI/104-Express cards, mSATA or other add-on modules and also cables to internal connectors only in an ESD protected environment.

1.4 EQUIPMENT SAFETY Great care is taken by MPL AG that all its products are thoroughly and rigorously tested before leaving the factory to ensure that they are fully operational and conform to specification. However, no matter how reliable a product, there is always the remote possibility that a defect may occur. The occurrence of a defect on this device may, under certain conditions, cause a defect to occur in adjoining and/or connected equipment. It is the customers responsibility to protect such equipment when installing this device. MPL AG accepts no responsibility whatsoever for such defects, however caused.

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1.5 MANUAL REVISIONS

1.5.1 RELATED PRODUCTS Manual Related To Revision A, B • PIP31-1 rev. B • PIP38-1 rev. B C • PIP31-1 rev. C and later • PIP31-2 rev. A and later • PIP32-1 rev. A and later • PIP37-1 rev. A and later • PIP38-1 rev. C and later

1.5.2 REVISION HISTORY Manual Revision Description Revision Date A 2013-02-21 - Initial release of this document. B 2013-04-05 - Some typos corrected. - Chap 2.1: PIP38 triple display capability changed to dual display capability. C 2013-08-15 - Specification added for PIP31-2, PIP32-1 and PIP37-1. - PIP31 CPU changed to 927UE. - Amount of on board memory changed to 4 GiB. - mPCIe / mSATA sockets specified as Full-Mini Card sockets. - Some typos corrected.

High-Tech • Made in Switzerland Technical Reference Manual

1.6 RELATED DOCUMENTATION The following documents are related to this manual. For detailed Information about a specific PIP setting or feature please see this additional manuals or data sheets. Reference Description Available from [1] PIP3x System BIOS User Manual MPL AG: www.mpl.ch/t2400.html [2] PIP3x App Note 1 (Lockable Headers) MPL AG: www.mpl.ch/t2400.html [3] PIP2x WinXP Watchdog Timer Driver App Note MPL AG: www.mpl.ch/t2400.html [4] SerifV User Manual MPL AG: www.mpl.ch/t2400.html [5] PCI Local Bus Specification Rev. 3.0 PCI-SIG: www.pcisig.com [6] PCI Express Base Specification 1.1 PCI-SIG: www.pcisig.com [7] PCI Express Base Specification 3.0 PCI-SIG: www.pcisig.com [8] PCI Express Mini Card Electromechanical PCI-SIG: www.pcisig.com Specification v1.2 [9] PCI Express External Cabling Specification 1.0 PCI-SIG: www.pcisig.com [10] PCI/104-Express Specification, Rev. 2.01 PC/104 Embedded Consortium: www.pc104.org [11] Serial ATA Specification Revision 3.1 SATA International Organisation: www.sata-io.org [12] SMSC SCH301x Super-IO data sheet SMSC: www.smsc.com [13] Intel 82574IT GbE Controller data sheet Intel: www.intel.com [14] Intel QM77 Plattform Controller Hub data sheet Intel: www.intel.com [15] Intel Celeron 927UE CPU data sheet Intel: www.intel.com [16] Intel Celeron 1047UE CPU data sheet Intel: www.intel.com [17] Intel Core i7-3517UE CPU data sheet Intel: www.intel.com [18] Intel Core i7-3555LE CPU data sheet Intel: www.intel.com

High-Tech • Made in Switzerland Technical Reference Manual

1.7 STANDARDS COMPLIANCE The PIP3x is designed to meet or exceed the most common industry and military standards. Particular references are:

1.7.1 EMC • EN 55022 Class B (Information technology equipment - Radio disturbance characteristics - Limits and methods of measurement) • EN 55024 (Information technology equipment - Immunity characteristics - Limits and methods of measurement) • EN 61000-4-1 (Electromagnetic compatibility (EMC) -- Part 4-1: Testing and measurement techniques - Overview of IEC 61000-4 series) • EN 61000-4-2 Level 3, Criterion B (Electromagnetic compatibility (EMC) -- Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test) • EN 61000-4-3 Level 3, Criterion A (Electromagnetic compatibility (EMC) -- Part 4-3: Testing and measurement techniques - Radiated, radio-frequency, electromagnetic field immunity test) • EN 61000-4-4 Class 3 (Electromagnetic compatibility (EMC) -- Part 4-4: Testing and measurement techniques - Electrical fast transient/burst immunity test) • EN 61000-4-5 Class 3 (Electromagnetic compatibility (EMC) -- Part 4-5: Testing and measurement techniques - Surge immunity test) • EN 61000-4-6 Class 3 (Electromagnetic compatibility (EMC) -- Part 4-6: Testing and measurement techniques - Immunity to conducted disturbances, induced by radio-frequency fields) • EN 61000-6-1 (Electromagnetic compatibility (EMC) -- Part 6-1: Generic standards - Immunity for residential, commercial and light-industrial environments) • EN 61000-6-2 (Electromagnetic compatibility (EMC) -- Part 6-2: Generic standards - Immunity for industrial environments) • EN 61000-6-3 (Electromagnetic compatibility (EMC) -- Part 6-3: Generic standards - Emission standard for residential, commercial and light-industrial environments) • EN 61000-6-4 (Electromagnetic compatibility (EMC) -- Part 6-4: Generic standards - Emission standard for industrial environments) • MIL-STD-461E (REQUIREMENTS FOR THE CONTROL OF ELECTROMAGNETIC INTERFERENCE CHARACTERISTICS OF SUBSYSTEMS AND EQUIPMENT)

1.7.2 ENVIRONMENTAL • EN 50155 (Railway applications - Electronic equipment used on rolling stock) • MIL-STD-810-F (ENVIRONMENTAL ENGINEERING CONSIDERATIONS AND LABORATORY TESTS)

1.7.3 SAFETY • EN 60601-1 (Medical electrical equipment -- Part 1: General requirements for safety) • EN 60950 Class III (Information technology equipment - Safety)

1.7.4 TYPE APPROVAL • EN 60945 Protected Equipment (Maritime navigation and radiocommunication equipment and systems - General requirements - Methods of testing and required test results) • E10 (Test Specification for Type Approval)

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1.8 ORDERING INFORMATION The table below gives you an overview of the different PIP variants and their features. All PIP3x are based on the same PIP_10p PCB design. Product Name Product Features PIP31-1 • PIP31: Intel Celeron 927UE PIP32-1 • PIP32: Intel Celeron 1047UE PIP37-1 • PIP37: Intel 3rd Gen Core i7-3517UE PIP38-1 • PIP38: Intel 3rd Gen Core i7-3555LE • 4 GiB DDR3 soldered down memory with ECC support • 204 pin DDR3 SO-DIMM socket • Intel HD Graphis with DP++, DVI-I and 24 Bit LVDS interfaces • Four Intel 82574IT Ethernet controllers • Four USB 3.0 ports • Two USB 2.0 ports, optionally additional three USB 2.0 ports • Two SATA 3.0 ports • Two SATA 2.0 ports • One eSATAp port • One ePCIe External Cabling port • One mPCIe / mSATA Full-Mini Card combo socket • One mPCIe Full-Mini Card socket • One PCI/104-Express Type 1 connector • Two serial ports with RS232 interface, optionally additional two RS232 or two galvanically isolated RS422/RS485 ports possible • Super-IO watchdog timer with hardware reset capability • Suspend to Disk (ACPI S4) support • RoHS compliant PIP31-1V1 • Same basic configuration than PIP3x-1, but instead of the Standard IO connectors lockable PIP32-1V1 headers are assembled PIP37-1V1 • Please see the PIP3x App Note 1 (Lockable Headers) for more information about the used PIP38-1V1 connectors • eSATA, ePCIe and USB3.0 feature is removed PIP31-2 • Depopulated PIP31-1 version • Two Intel 82574IT Ethernet controllers • One PCIe/104 Type 1 connector • Without soldered down memory • Without ePCIe External Cabling port • Without eSATA port • Custom assemblies are available for order quantities of 100 units and more. • Please contact MPL AG for further information. There are also many more options available for: • Housing size, displays, touch, IP65 • PCI/104-Express card –, PCI Express Mini Card –, PCI card – and PCIe card extensions • Lockable headers instead of standard interface connectors (please see PIP3x App Note 1 (Lockable Headers)) • RAID, Solid State Disks • Extended temperature Please have a look at the MPL AG homepage www.mpl.ch/t2400.html or contact MPL AG for further information.

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2 SPECIFICATIONS

2.1 FEATURES SUMMARY

Item Specifications Processor, PIP31: Graphics Controller • Intel Celeron 927UE 1.5 GHz single core processor, 1 MByte Cache (Ivy Bridge) • Intel HD Graphics 2000, 350 – 900 MHz graphics engine, dual independent display capable, Gen2 PCI Express Graphics port PIP32: • Intel Celeron 1047UE 1.4 GHz dual core processor, 2 MByte Cache (Ivy Bridge) • Intel HD Graphics 2000, 350 – 900 MHz graphics engine, dual independent display capable, Gen2 PCI Express Graphics port PIP37: • Intel 3rd Gen Core i7-3517UE 1.7 – 2.8 GHz dual core processor, 4 MByte Cache (Ivy Bridge) • Intel HD Graphics 4000, 350 – 1000 MHz graphics engine, dual independent display capable, Gen3 PCI Express Graphics port PIP38: • Intel 3rd Gen Core i7-3555LE 2.5 – 3.2 GHz dual core processor, 4 MByte Cache (Ivy Bridge) • Intel HD Graphics 4000, 550 – 1000 MHz graphics engine, dual independent display capable, Gen3 PCI Express Graphics port All: • DDR3-1600 memory interface • Intel 64 architecture • Enhanced Intel SpeedStep Technology • Catastrophic thermal protection Chipset • Intel QM77 (Panther Point) • Supports ACPI power states S1 (Stop Grant), S4 (Suspend to Disk), S5 (Soft Off) Memory • Dual channel architecture • 4 GiB DDR3 soldered down memory with ECC support • 204 pin DDR3 SO-DIMM socket supports up to 8 GiB memory modules (16x 4 Gib memory chips) Graphics Interfaces DVI-I: • VGA signals support resolutions up to 2048x1536 with 32 Bit color at 75 Hz • TMDS signals support resolutions up to 1920x1200 at 60 Hz • ESD protected connector DisplayPort: • Supports resolutions up to 2560x1600 at 60 Hz • Dual mode DisplayPort (DP++) supports external passive DP to DVI or DP to HDMI adapters • ESD protected connector LVDS: • Supports resolutions up to 1920x1200 with 18 or 24 Bit color at 60 Hz • Internal 1mm header connector PCI Express Graphics (PEG) port: • x16 lane on PCI/104-Express connector • Supports 3rd party PCI/104-Express graphics controller cards USB • 4 USB 3.0 ports with 1.5/12/480/4800 Mb/s (all on external connectors) • 5 USB 2.0 ports with 1.5/12/480 Mb/s (2 on external, 3 on internal connectors) • Supports USB keyboards and mice as legacy devices • ESD protected external connectors SATA • 2 SATA 3.0 ports with 6 Gb/s • 2 SATA 2.0 ports with 3 Gb/s • RAID 0/1/5/10 support eSATAp • eSATAp port with SATA 2.0 and USB 2.0 signals • ESD protected connector

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Item Specifications ePCIe • PCI Express Gen2 external cabling x1 lane port with 500 MB/s • Up to 4 m cable length • ESD protected connector LAN • 4 Intel 82574IT GbE LAN controller • Each controller resides on a dedicated PCI Express x1 port • 9 kB jumbo frame support • Magic Packet Wake on LAN (WOL) support on all interfaces • ESD protected connectors PS/2 • Keyboard and mouse on a combo 6 pin Mini-DIN connector • ESD protected connector Serial Ports • 2 full modem RS232 ports on DB9 connectors, 16C550 compatible (16 Byte Receive and 16 Byte Transmit FIFO) • 2 TTL level serial ports on internal headers (please see below, Optional Features) • Selectable transfer rates up to 115.2 kBaud (optional up to 1.5 MBaud) • ESD protected external connectors mPCIe / mSATA • One mPCIe / mSATA Full-Mini Card combo socket with SATA 2.0 or PCI Express Gen2 x1 lane and USB 2.0 • One mPCIe Full-Mini Card socket with PCI Express Gen2 x1 lane and USB 2.0 PCI/104-Express • 2 USB 2.0 (Type 1) • 4 PCI Express Gen2 x1 lane • One PCI Express Gen2 or Gen3 (depends on processor) Graphics x16 lane • 32 Bit, 33 or 66 MHz PCI bus supports up to 4 PCI/104 bus masters HDAudio • Intel HDAudio signals are available at a 1 mm internal header TPM • Trusted Plattform Module soldered down on board RTC • Backed with a field changeable on board battery Indicator LEDs • Power and reset state LEDs (at SerLED PCB) • HDD, LAN and mPCIe sockets status LEDs • 2 programmable user LEDs at case cover RST/PWR Button • Reset- and Power Button are available at case top Ignition Input • Reset-, Power Button and Ignition Input are also available at a 4 pin Mini-DIN connector • ESD protected connector Watchdog Timer • SCH3114 Super-IO watchdog timer is used • Configurable granularity from 1 to 255 seconds or from 1 to 255 minutes • Hardware reset capability Temperature Sensors • Monitors the CPU, the on board memory and the board temperature Power Input • With load dump and reverse polarity protection

Optional Features • 2 more full modem RS232 ports or two galvanically isolated RS422/RS485 ports with auto direction control on DB9 connectors (occupy the TTL level serial ports) • Galvanically isolated power input

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2.2 ELECTRICAL RATINGS

2.2.1 POWER INPUT

Item Specifications

Input Voltage • 8 VDC .. 36 VDC Inrush Current The inrush current depends on parameters that are not PIP specific, like: • Power supply internal resistance • Power supply voltage rise time and voltage value • Power cable impedance Typical PIP Power Up • 2.2 A @ 12 V Current (without add- • 1.1A @ 24 V on cards) • 0.8 A @ 36 V Protection Circuits • ESD and EMC protected power input

• -36 VDC reverse polarity protection • 150 V / 5 ms load dump protection Fuse • PIP31, PIP32: 3.15 A (Time Lag) • PIP37, PIP38: 6.3 A (Time Lag) • 5 x 20 mm snap in type

2.2.2 POWER DISSIPATION The power usage change in a wide range according to the selected PIP variant, the installation of a memory module or add-on cards and also according to the needed CPU, memory, graphics and interfaces usage. Please find some reference values in the table below: Power State PIP31-1 PIP32-1 PIP37-1 PIP38-1 ATX Soft Off w/o WOL *1 0.4 W TBD 0.4 W 0.4 W ATX Soft Off w/ 2 Ethernet ports with WOL *1 1.0 W 1.0 W 1.0 W ATX Soft Off w/ 4 Ethernet ports with WOL *1 1.5 W 1.5 W 1.5 W BIOS Setup Screen *2 17 W 15 – 18 W *3 18 W Win7 Desktop Screen w/o CPU Load *2 13 W 12 W 10 W Win7 w/ Prime95 *2 20 W 20 – 33 W *3 36 W Win7 w/ Prime95 and Intel Extreme Tuning 27 W 37 – 42 W *3 45 W Utility Graphics Stress Test *2 *1: PIPs are connected to 4 Ethernet lines. Input voltage is 12 V. *2: PIPs are equipped with 4 GiB on board SDRAM, SDRAM module, 2.5” SSD, one GbE Link, DVI or DP Monitor. Input voltage is 24 V. *3: The Core i7-3517UE CPU Thermal Design Power (TDP) Boot Mode can be configured with down, nominal / disabled or up. Dependent on this setting the power dissipation changes. For more information about how to change this configuration please read the PIP3x System BIOS User Manual.

2.3 MECHANICAL SPECIFICATIONS

Item Specifications Housing • Aluminum • Without ventilation holes • Easily mountable on 35 mm DIN rail or with flanges (optional) Form Factor • Length: 270 mm (10.63 inch) standard version 440 mm (17.32 inch) Wintergarden version with PCI slot extension • Width: 162 mm (6.38 inch) • Height: 62.0 mm (2.44 inch) standard version 82.5 mm (3.25 inch) 120 mm (4.72 inch) Weight • Typically 2.0 kg (62 mm housing, with 2.5” HDD)

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2.4 ENVIRONMENTAL CONDITIONS

Item Specifications Storage Temperature • -45 °C to +85 °C (-49 °F to +185 °F) Operating Temperature • -20 °C to +60 °C (-4 °F to +140 °F), with full CPU, 3D video and memory usage, mounted on a DIN rail with freely natural convection • Extended operating temperature range available (screening) Relative Humidity • 5% to 95%, non-condensing Shock and Vibration • TBD

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3 HARDWARE REFERENCE

3.1 HOUSING DIMENSIONS

3.1.1 TOP VIEW SIDE VIEW 3 y E l F 0 0 n . . 0 0 o T

0 0 . . A y

l C C 3 p 1 1 . . . p 6 2 2

u 1 1 / C C

. . S - e

0 0 1 C r p 6 6 0 C . . D e ° y 2 0 0 0

- V T 0 w 0

o 6 3 : : 6 e 2 r 3 P + C C 1

u - A A - 0

1 M M C P -

s C o l ° 3 4 s I D V

c N N a 0 E V l n

A A 2 P M 8 C - E L L C D 0 0 . . ] 0 0 0 0 . A . [ C C

1 1 . . 5 2 2 6 C C . . 0 0 3 6 6 : . . 1 t 0 0 n 2 0 0

: : m C C n A A : o g : M M :

r n i e S : 1 2 i t v p N N O N I a / n y A A T S B R E L L 2 1 ,

r e m W W h c m E E ö 5 I I , L

2 V V

t r z e E E n s s a D D t e I I s e m S S g h s c r u u a

D 2 , n e g i e z n A - D r E e t L

s m e n d m e n 5 F ,

e 2 e g

t r e i n l e r e s r e s t a e n p u s m r n h a a c d r r

t r

u 6 ü D f 1 0 2 . 9 . . 0 6 7 7 0 2 2 1

SIDE VIEW 4 41.6 48.3 162.1

Figure 1: PIP Housing Top View (with Cover Foil)

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3.1.2 BOTTOM VIEW SIDE VIEW 4 1

W E W I E V I

V E

D E I D S I S 0 0 0 0 . . . . 0 5 0 5 5 . 0 8 7 6 5 1 2 1 8 1

SIDE VIEW 3 59.5 81.1 109.5 162.1

Figure 2: PIP Housing Bottom View

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3.1.3 SIDE VIEW 1 SIDE VIEW 3

21.4

8.5

21.2

23.8 W E W I E V I

V M

P O T O T T O B

22.1 3 0 2 0 0 3 0 . . . . . 3 3 . . 8.5 21.6 . . 3 1 5 1 0 8 4 2 0 3 7 0 4 7 5 9 2 4 1 1 2 2 2

SIDE VIEW 4 62.0 (82.5), [120.0]

Figure 3: PIP Housing Side View 1

Note: Use the values in parentheses for the higher housing versions (82.5 mm) [120 mm].

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3.1.4 SIDE VIEW 2 SIDE VIEW 4

24.9

24.0

20.9 W E W I E V I

M P O O T T T

22.5 O B 0 . 0 9 1 8 4 . 2 6 . 2 4 . . 7 24.6 . . . . 0 5 3 6 2 2 0 3 1 4 0 4 8 2 4 6 8 2 1 1 2

SIDE VIEW 3 62.0 (82.5), [120.0]

Figure 4: PIP Housing Side View 2 Note: Use the values in parentheses for the higher housing versions (82.5 mm) [120 mm].

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3.1.5 SIDE VIEW 3

144,9 ] ] 0 4 . . 0 5

2 1 67,7 1 1 [ [

, , ) ) 5 9 . . TOP VIEW

2 7 17,2 8 7 ( ( 1

W W E I E I V

E E D I D I S 4 0 S , , 6 7 2 , 5 6 4 5 , 8 59.5 94,4 BOTTOM VIEW 109.5 162,1

Figure 5: PIP Housing Side View 3 Note: Use the values in parentheses for the higher housing versions (82.5 mm) [120 mm].

3.1.6 SIDE VIEW 4 ] ] 0 4 . . 0 5 1 2 144,9 1 1 [ [

, ,

) ) 94,4 5 9 . . TOP VIEW 17,2 7 2 7 8 ( ( 2

W W E I E I V

E E D I D I S 4 0 S , , 6 7 2 , 5 6 4 5 , 8 52.5 67,7 BOTTOM VIEW 102.5 162,1

Figure 6: PIP Housing Side View 4 Note: Use the values in parentheses for the higher housing versions (82.5 mm) [120 mm].

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3.2 OPENING THE CASE ● Remove the 6 screws from the case top.

Figure 7: Removing The 6 Screws ● Lift up the top cover gently. Please be careful with the cables.

Figure 8: Lift Up The Top Cover

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3.3 DIMENSIONS AND PLACEMENT

3.3.1 PCB DIMENSIONS

116.10mm. 112.30mm. 38.63mm. 36.09mm. 1 O N O N O N V V 0 3 . . 5 3 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 D C B A 0 1 3 1 4 / 3 / 2 2 / / 1 1 N N A A 1 L L

: : L L O O W W B d B 5 d . 9 2 / / : 7 0

: p : u O N A m q T E E A e p 1 2 r S n e P I 1 1 1 1 2 1 t c x . o . t e l t - - c 1 t t c a o o 1 a

5 5 o o h w b b g i o 1 1 l h

1 N 1 N O O

L L B B 1 1 1 1 1 1 1 1 1 1 2 1 h w g i o H L - - N N G G I I 1 5 3 0 2 4 1

1 2 1 3 4 ...... m m m m m m m m m m m . m m m m m m m m m m m m m m m m m m m m 0 0 1 4 7 2 0 0 1 6 0 0 0 9 0 m 0 5 0 5 6 7 9 6 7 4 0 8 2 1 . . 7 ...... 0 . . . . 9 9 4 1 1 1 2 3 3 7 0 0 7 7 0 7 . 5 7 6 1 4 6 0 1 5 5 7 9 4 5 7 5 2 1 1 1 1 1 1 2 2 2 2

. 6.20mm. 4.30mm.

m 65.41mm. m 0

0 67.32mm. . 3 71.12mm. 94.62mm. 147.30mm. 153.50mm. 162.10mm.

Figure 9: Locations Of The Standoff And Mounting Holes

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3.3.2 PARTS LOCATION ) ) ) ) ) ) r 8 0 s s 2 3 4 5 ) o ) 3 7 s s t e e l l 3 S S S S 6 J J e e c ( ( ( ( ( ( r J r b b

D e ( p p ( a a

4 2 3 5 1 2 y n

x x s s ) r i t i t n h h h o h D 2 e E E t d o d o o t c c c c - - l l 5 t E t t c t t i i i i 4 4 C J S S a L e N N

(

0 0 w w w w r t n B A A e e 1 1 e S I S S I S o n / / L L

I I o o w C C P P P P C C W W o I I I I B C P P P P P D D D D m m 1 O N O N O N V ) V 0 3 s . 8 . / 5 3 t 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 2 4 i J # B (

t r G e o ) 1 t n / l 1 r c D 0 a 5 e e 0 C n J h g n r ( t 1 B

/ n n e r i E t l 0 A o o x e 1 t C 0 1 E c b

3 ) e a e s I 6 n / C t 3 2 n i C J # o B

P (

C t r ) G e o 4 1 t ) ) / n 3 c r 1 9 8 0

J e e ( 7 0 S d

n h ( r J 1 r t

( / n 1 a

o 9 E t 0 t o

r C ) c 1

h C o s 4 e 4 c / / M t t P 2 2 n i I i 3

/ # J n ) 2 2 S B w ( / / G )

o 0 t 1 1 r S ) 2 G A 4

C 1 e N N o 1 3 1 T J t / A A t P n 1 p ( 4 J I J c r 2 L L

( 0 o

J l r

A : : e e D ( 0 r d L L o S T h n r t 1 r o

t O O / t n a ) A c o e E c 0 t o W W I 8 e S C c 1 e

n C C S e ) ) ) e n ( n

M s P 1 2 5 2 6 n n I /

o 8 t B 1 7 2 r 7 r n ) o

i m S d B C J J J # e e o 6 ) h 5 B C

( d ( ( . g J

c ) 2 9 w w C 2 t t ( r r r / t A / G n i

2 7 r o o i 7 : e 2 o 0 o o r

1 T

J t t t 3 : p o : w / n P t P ) ( o m u O N c c c J A r A t 0 P m o S ( q 2 r T l e e e

e c

A A S E 0 m I E 0 i r o A n n n e h e S P p t 1 2 1 T T r t P 0 S e o I m / O n n n D n 2 n c t ) e P I I ) A A s 2 o E S 0 , l o o o D n c e 1 N 9 J u b S S 1 e G e o ( e r n 0 C C C I 4 A o

n S n o n m r 1 0 C J

t C F a ( M n o o

o 2

c t A P r o P d J & C C 1 e c

T o n ,

m C n t e 1 1 A a 0 d c n n

r 0 2 S e ) o n 1 a 0 n 4 o 3 C o N ) 2 n 7 b C & 7 J 1 A J o ( y 2

S F

, e C ( t s

3 c x t K o h r 7 l e . . - t - c 1 t t J o t c t ( c o o i 1 a P a

5 5 o o

s w b b w h r 0 1 1 s o ) g . S l i o )

s t 6 2 h 1 2

N 1 e c P 2 6 I r J N O A e J t (

) p r ( O r D n L T

r 3 x 1 o e r L B n ) o A 1 d E B o t & P o 0 - t J

S a c l 0 )

0 c C 4

, e e r a 2 0 e r i s 0 2 n ) t o r 4 H 2 n e 1 t r 1 n t 5 J / e n 1 S I a J r ) ( o o 1 l (

( S o c e )

r P C i J e C

v ( 7 s h 4 o C d

n P r t 0 2 n J c 6 o r . n

i I t a ( c o I i t J

o t 3 1

d 1 1 t r ( t e r P )

c w u h o c n r D o 1 6 A e t S g e n o A P ) 1 i E

n c t T

l n o 1 l J 9 L n c e P k ( A D n 4 a I 6

C l i o e n c I r o S r t J - H D e n n a r ( I C o e

C t v n o o B r V S c e o o C P D e t L

l C

) ) c n a L 7 3 i e n ) ) ) r T J 1 n 6 n o 8 ( 6 7 s 0 e 8 9 T J t o n C i t t t r r ( r u 6 5 5 1 S r r r o s o J o e J J r B t o o o ( ( (

n C d o

P c t P r P r P r a a C l

e 1 c o o o p e r a 0 t 0 t 0 t P n e i x . . . o c c c r L H n n t 2 2 2 E e e e e

o n c n n n S B B B e o ) C n n n n 5 S S S 1 C ) o o o n 1 6 4 U U U

C C C o t J 1 r (

) J C o r

( 8 o t P S t 1

r l J c D o ( a ) i e

V P r r 1 8

n L e M ) o & 3 y 6 n l t

t n 7 t A t J S a o c e l r ( e J o e

R v e t ( p C o k r t s e n s r D c o i P u e M t L

n o n o l

S i t D B c R

o M

a L S c I P l r i e

C r T e a n e y ) 0 D 4 ) e r n - T & n n 7 6 w 0 r 3 r o n S t n o 3 1 O o 2 e 5 e o - e J o t m C S J t P ( 3 w s t ( C n e

I o e u R 2 r 2 1

M P o R r B D

5 t

) l ) , o r c D t 6 & a 9 h r n e e w c 3 4 g J n i e o

o ( r n i w e J t

H L t ( r e w i - n - o n

s t o r o n N o N n 1 P n

o I g G G o P P C r I t I I

l c o C 0 t 1 a . e 5 c n 2 n r e 3 n e n B 0 t o n 2 t S n r C I o 1 ) U o & C 8 ) P 0 J

( 5 t t 4 1 ) g r r 3 u s 1 u n J o e r ) p ( 2 b o o

9 P i w n 1 2 J t r e I ( 1 s o

c o 0

D J t n r . r e P (

1 c e 3 o l n e 0 t t e a n 0 x c w B

n 3 4 n o 7 e o E r 3 n S n P ) C e P o & t U n 4 T 2 C I x J o t ( E

r C r o o t P

c e 0 e s . n u 3

n F

B o t S u C p U n I

Figure 10: Parts Location

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3.4 SWITCH SETTINGS

3.4.1 DIP SWITCH 1 (S1) – IGNITION INPUT POLARITY SELECTION This switch selects the ignition signal logic level polarity on connector J2 and J53. Default switch settings are in parentheses. SW1 Ignition Input Polarity Selection (OFF) Ignition ON if IGN signal pulled to VIN_CON IGN-Low ON Ignition ON if IGN signal pulled to GND_CON IGN-High

Figure 11: DIP Switch 1

3.4.2 DIP SWITCH 2 (S2) – PERIPHERAL SETTINGS Default switch settings are in parentheses. SW2-1 Battery Backup OFF CMOS battery backup off (ON) CMOS battery backup on SW2-2 No Reboot Mode (OFF) Reboot after system failure (TCO Timer system reboot feature enabled) ON No Reboot after system failure (TCO Timer system reboot feature disabled) SW2-3 BIOS Setup Recovery 1 O (OFF) Please read the PIP3x System BIOS User Manual for further information 2 N ON 3 SW2-4 Reserved 4 (OFF) Not used 5 ON Not used 6 SW2-5 Ethernet Controller 4 Disable 7 8 (OFF) Ethernet Controller 4 enabled ON Ethernet Controller 4 disabled SW2-6 Ethernet Controller 3 Disable Figure 12: DIP Switch 2 (OFF) Ethernet Controller 3 enabled ON Ethernet Controller 3 disabled SW2-7 Ethernet Controller 2 Disable (OFF) Ethernet Controller 2 enabled ON Ethernet Controller 2 disabled SW2-8 Ethernet Controller 1 Disable (OFF) Ethernet Controller 1 enabled ON Ethernet Controller 1 disabled

3.4.3 DIP SWITCH 3 (S3) – PCI/104-EXPRESS IO-VOLTAGE SELECTION Default switch settings are in parentheses. SW3 PCI Bus IO Voltage Selection (OFF) PCI/104-Express socket PCI Bus IO-Voltage is 5.0 V 3.3 V ON PCI/104-Express socket PCI Bus IO-Voltage is 3.3 V

5.0 V

Figure 13: DIP Switch 3

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3.4.4 DIP SWITCH 4 (S4) – ON BOARD LVDS PORT (LCD PANEL) SETTINGS Default switch settings are in parentheses. SW4-1 GMCH Graphics Disable (OFF) Enable internal Graphics Controller ON Disable internal Graphics Controller SW4-2 SW4-3 SW4-4 Backlight Inverter Definition (OFF) (OFF) (OFF) Type 1 ON OFF OFF Type 2 OFF ON OFF Type 3 ON ON OFF Type 4 Please read the PIP3x System BIOS User OFF OFF ON Type 5 Manual for further information ON OFF ON Type 6 OFF ON ON Type 7 1 O ON ON ON Type 8 2 N SW4-5 SW4-6 SW4-7 SW4-8 Panel Type 3 ON ON ON ON Type 1 4 5 OFF ON ON ON Type 2 6 ON OFF ON ON Type 3 7 OFF OFF ON ON Type 4 8 ON ON OFF ON Type 5 OFF ON OFF ON Type 6 Figure 14: DIP Switch 4 ON OFF OFF ON Type 7 OFF OFF OFF ON Type 8 Please read the PIP3x System BIOS User ON ON ON OFF Type 9 Manual for further information OFF ON ON OFF Type 10 ON OFF ON OFF Type 11 OFF OFF ON OFF Type 12 ON ON OFF OFF Type 13 OFF ON OFF OFF Type 14 ON OFF OFF OFF Type 15 (OFF) (OFF) (OFF) (OFF) Type 16

3.4.5 DIP SWITCH 5 (S5) – PCIe EXT. CABLING REDRIVER SETTING Default switch settings are in parentheses. SW5-1 SW5-2 Output De-Emphases (Depends on Output Amplitude)

875 mVPP 1000 mVPP 1100 mVPP (OFF) X -2.5 dB -3.7 dB -4.6 dB O ON OFF -5.5 dB -6.4 dB -6.6 dB 1 2 N ON ON -9.5 dB -9.4 dB -8.7 dB 3 SW5-3 SW5-4 Input Equalization (Only at PCIe Gen II Speed) 4 (OFF) X 0 dB 5 ON OFF 7 dB 6 ON ON 15 dB SW5-5 SW5-6 Output Amplitude Figure 15: DIP Switch 5 (OFF) X 1000 mVPP

ON OFF 875 mVPP

ON ON 1100 mVPP

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3.4.6 DIP SWITCH 7 (S7) – RESERVED DIP switch 4 is reserved for MPL AG use only. SW7 Reserved (OFF) Default setting ON Do not use

Figure 16: DIP Switch 7

3.4.7 DIP SWITCH 8 (S8) – eSATAp SATA REDRIVER SETTING Default switch settings are in parentheses. SW8-1 Output Pre-Emphasis (OFF) 0 dB 1 O ON 2.5 dB 2 N SW8-2 Input Equalization (OFF) 7 dB Figure 17: DIP Switch 8 ON 9 dB

3.4.8 DIP SWITCH 9 (S9) – ETHERNET WAKE ON LAN (WOL) SETTINGS Default switch settings are in parentheses. SW7 WOL Capability Selection (OFF) WOL enabled for LAN1 and LAN2 port ON WOL enabled for LAN1, LAN2, LAN3 and LAN4 port WOL: LAN1/2/3/4 WOL: LAN1/2

Figure 18: DIP Switch 9

Note: General WOL enabling or disabling is made via the BIOS setup. For more information about this setting please read the PIP3x System BIOS User Manual.

3.4.9 DIP SWITCH 2000 (S2000) – BACKLIGHT ENABLE LOGIC LEVEL This switch selects the backlight enable signal logic level on connector J15 pin 15. Please refer to chapter 3.5.2.7 Backlight Inverter Connector (J15) for more information. Default switch settings are in parentheses. SW7 Backlight Enable Signal Logic Level (OFF) Backlight Enable with High Logic Level BL ON low act. ON Backlight Enable with Low Logic Level

BL ON high act.

Figure 19: DIP Switch 2000

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3.5 CONNECTORS

3.5.1 EXTERNAL CONNECTORS

3.5.1.1 Serial-1 (J65) and Serial-2 (J67) Connectors These connectors support standard RS232 interfaces. Pin Signal Description Pin Assignment 1 DCD Carrier detect 2 RXDn Receive data 1 5 3 TXDn Transmit data 4 DTR Data terminal ready 5 GND Ground 6 DSR Data set ready 6 9 7 RTS Request to send Figure 20: Serial Port Connector (DSUB 9 Male) 8 CTS Clear to send (Compona, 363 011-0) 9 RI Ring indicator 3.5.1.2 Optional Serial-3 and Serial-4 Connectors These connectors only are available if the Internal TTL Level Serial Port 3 (J68) and 4 (J69) Connectors are equipped with two SerifV-1 (RS232) or SerifV-2 (RS485) modules. With this ports the Ring Indicator (RI) wake up from ATX Soft Off Power State (S5) is not available. The SerifV connectors are lead through the PIP case right above the Serial-1 and Serial-2 connectors (J65, J67). With RS232 Module (SerifV-1) Pin Assignment Pin Signal Description 1 DCD Carrier detect 2 RXDn Receive data 3 TXDn Transmit data 4 DTR Data terminal ready 5 GND Ground 6 DSR Data set ready 1 5 7 RTS Request to send 8 CTS Clear to send 9 RI Ring indicator With RS485 Module (SerifV-2) 6 9 Pin Signal Description 1 NC Not connected Figure 21: Serial Port Connector (DSUB 9 Male) 2 Rx+ Receive data + (Compona, 329 351-5) 3 Tx+ Transmit data + 4 NC Not connected 5 GND_isolate Galvanically isolated Ground 6 NC Not connected 7 Rx- Receive data - 8 Tx- Transmit data - 9 NC Not connected

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3.5.1.3 External Power Connector (J21)

3.5.1.3.1 Pin Assignment The power input connector counterpart is: Phoenix Contact AG, PSC 1,5/3-F with a SCT-D-SUB 9-KG case. Pin Signal Description Pin Assignment 1 VIN_CON Input Voltage (8 to 36 V) 2 GND_CON Power Connector Ground, 1 3 connected to Case EARTH 3 IGN Ignition Input (same signal than J53 pin 1)

Figure 22: Power Connector (Phoenix Contact AG, PSC 1,5/3-M-PE)

3.5.1.3.2 Power Input Protection Circuits

Item Specifications Reverse polarity protection -36 V Load dump protection +150 V / 5 ms The PIP includes a reverse polarity protection up to the reverse nominal supply voltage. If this condition occurs, switch the power supply off, connect it the right way and turn it on again for powering up the PIP. The load dump protection circuit cuts the supply voltage to 36 V. To avoid an overheat condition in the load dump protection circuit, the PIP immediately shuts down, if the over voltage (> 36 V) is applied longer than ~7 ms. 3.5.1.3.3 Power Up Behavior A voltage greater than 8 V between VIN_CON and GND_CON, lets boot the PIP. If the PIP was shut down with the OS functionality you have to start the PIP again with a short activation of the Power Button, or you can cycle VIN_CON. After a Power Button Override (push the Power Button 4 seconds) the PIP will shut down immediately. After this kind of shutdown, you must push the Power Button to start the PIP. If you only cycle the VIN_CON voltage, the PIP will not start. For a proper power up, there is a 5 s timeout included between a power down and an immediately started power up cycle. 3.5.1.3.4 Power Input Circuit J35 1 2 Power Input 3 Extension 4 Connector External Power

Connector VINCON VINFLT J21 FUSE 6.3A T 1 Load Dump Input Filter and VIN 2 Protection and ESD Protection 3 Filter 0 Ohm 0 Ohm

GND GNDCON GND_IN J36 CASE_EARTH 1 VIN 2 VIN 3 VIN 4 Internal Power VCC_+12V +12V 5 IGN, RST-, GND Connector 1 6 GND PWR-BTN 7 GND 8 Connector GND J53 1 to Ignition Signal Logic GND 2 J52 1 3 to Power Button Logic VCC_-12V -12V 2 4 GND 3 PCI/104-Express to Reset Button Logic GND GND 4 GNDCON VCC_+12V +12V Power Connector 5 +12V

Figure 23: Connections Between all the PIP Power Connectors

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NOTE:

+12 V and -12 V must be supplied to the Internal Power Connector 1 (J36) or the PCI/104- Express Power Connector (J52) from a separate power supply. Else these voltages are NOT available from the PIP.

3.5.1.4 Ignition Input, Reset- and Power Button Connector (J53)

3.5.1.4.1 Pin Assignment The Mini-DIN connector counterpart with interlock is: Compona, 129 103-6. Pin Signal Description Pin Assignment 1 IGN Ignition Input (same signal than J21 pin 3) 2 PWRBTNn Power Button Input, connect to GND_CON 4 3 for activation 3 RSTBTNn Reset Button Input, connect to GND_CON 2 1 for activation 4 GND_CON Power Connector Ground Figure 24: Mini DIN Connector (Compona, 129164-3)

3.5.1.4.2 IGN, PWR- and RST-Button Circuit The PIP provides a separate connector for Ignition Signal Input, Reset- and Power Button. All this inputs withstand -36 V .. 60 V voltage levels. External Power Connector J21 1 8 - 36 V VIN_CON System 2 GND_CON Ground 3

Ignition IGN, RST-, Switch PWR-BTN Connector J53 1 to Ignition Signal Logic External 2 Power Button 3 to Power Button Logic System 4 Ground to Reset Button Logic External GND_CON Reset Button System Ground Figure 25: External Ignition Switch and External Power- and Reset-Button Circuits

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3.5.1.5 PS/2 Keyboard and Mouse Connector (J49) A keyboard can directly be connected to the PS/2 interface. With an Y-cable both, a mouse and a keyboard, can be used in common on this port.

NOTE:

The standard Y-cables assume a mouse is directly connected to the PS/2 port (laptop behavior). So for an accurate operation at PIP3x you have to connect the mouse to the Y-cable keyboard branch and the keyboard to the Y-cable mouse branch.

Pin Signal Description Pin Assignment 1 KB_DAT Keyboard Data 2 MS_DAT Mouse Data 6 5 3 GND Ground 4 VCC +5 V Keyboard, Mouse Power 4 3 5 KB_CLK Keyboard Clock 6 MS_CLK Mouse Clock 2 1

Figure 26: PS/2 Keyboard & Mouse Connector (Compona, 129108-7)

3.5.1.6 Dual USB 3.0 Connectors (J8, J4) Pin Signal Description Pin Assignment 1 VCC0/2 Port 0/2 Cable Power +5 V 2 P0/2- Port 0/2 Balanced Data Line - 3 P0/2+ Port 0/2 Balanced Data Line + 4 GND0/2 Port 0/2 Cable Ground 5 USB30_RX0/2- USB3.0 Port 0/2 Receive - 18 14 6 USB30_RX0/2+ USB3.0 Port 0/2 Receive + 10 13 7 GND0/2 Port 0/2 Cable Ground 8 USB30_TX0/2- USB3.0 Port 0/2 Transmit - 9 USB30_TX0/2+ USB3.0 Port 0/2 Transmit + 10 VCC1/3 Port 1/3 Cable Power +5 V 11 P1/3- Port 1/3 Balanced Data Line - 1 4 12 P1/3+ Port 1/3 Balanced Data Line + 9 5 13 GND1/3 Port 1/3 Cable Ground 14 USB30_RX1/3- USB3.0 Port 1/3 Receive - Figure 27: Dual USB 3.0 (Type A) Connector (TE, 15 USB30_RX1/3+ USB3.0 Port 1/3 Receive + 1932355-1) 16 GND1/3 Port 1/3 Cable Ground 17 USB30_TX1/3- USB3.0 Port 1/3 Transmit - 18 USB30_TX1/3+ USB3.0 Port 1/3 Transmit + 3.5.1.7 Dual USB 2.0 Connector (J9) Pin Signal Description Pin Assignment 1 VCC4 Port 4 Cable Power +5 V 2 P4- Port 4 Balanced Data Line - 5 6 7 8 3 P4+ Port 4 Balanced Data Line + 4 GND4 Port 4 Cable Ground 5 VCC5 Port 5 Cable Power +5 V 6 P5- Port 5 Balanced Data Line - 7 P5+ Port 5 Balanced Data Line + 8 GND5 Port 5 Cable Ground 1 2 3 4

Figure 28: Dual USB 2.0 (Type A) Connector (FCI, 72309-0010B)

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3.5.1.8 DVI-I Connector (J16) DVI-I Connector with single channel TMDS port and legacy analog port. Pin Signal Description Pin Assignment 1 TMDS Data2- 2 TMDS Data2+ 3 Shield Data2 4 NC 5 NC 6 DDC Clock 7 DDC Data 8 Analog Vertical Sync 9 TMDS Data1- 10 TMDS Data1+ 11 Shield Data1 12 NC C5 13 NC 1 8 C1 C2 14 +5 V DVI Power 15 Ground 16 Hot Plug Detect 17 TMDS Data0- 18 TMDS Data0+ 17 24 C3 C4 19 Shield Data0 20 NC Figure 29: DVI-I Connector (Molex , 074320-1003) 21 NC 22 Shield Clock 23 TMDS Clock+ 24 TMDS Clock- C1 Analog Red C2 Analog Green C3 Analog Blue C4 Analog Horizontal Sync C5 Analog Ground

NOTE:

It is not possible to use a CRT and a digital monitor at the same time on the DVI-I port. The DVI-I connector has only one DDC (Display Data Channel) Bus to recognize a monitor. But digital and analog monitors answers to the same DDC bus address on requests. So if both monitors simultaneously are connected to the DVI-I connector (with an Y-cable), there is a mismatch with the monitor information on the DDC bus.

3.5.1.9 Gb Ethernet Connectors (J22, J34, J26, J28) Standard RJ45 connector for a 100 ohm cable. Pin Signal Description Pin Assignment 1 TD0+ Data 0 + 2 TD0- Data 0 - 1 8 3 TD1+ Data 1 + 4 TD2+ Data 2 + 5 TD2- Data 2 - 6 TD1- Data 1 - 7 TD3+ Data 3 + Figure 30: RJ45 Connector (HanRan HR921148C) 8 TD3- Data 3 -

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3.5.1.10 eSATAp Connector (J40) External SATA connector with SATA 2.0 and USB 2.0 signals. Pin Signal Description Pin Assignment 1 VCC9 Port 9 Cable Power +5 V 2 P9- USB 2.0 Port 9 Balanced Data Line - 11 5 3 P9+ USB 2.0 Port 9 Balanced Data Line + 4 GND9 Port 9 Cable Ground 5 GND Ground 6 A+ SATA 2.0 Port 4 Differential Signal Pair A 7 A- 8 GND Ground 1 4 9 B- SATA 2.0 Port 4 Differential Signal Pair B 10 B+ Figure 31: eSATAp Connector (FCI, 10074703-001RLF) 11 GND Ground

3.5.1.11 PCIe External Cabling Connector (J51) PCIe External Cabling Connector with PCIe Gen 2 x1 lane. Pin Signal Description Pin Assignment A1 PERn0 Differential PCI Express Receiver Lane A2 PERp0 A3 RSVD Not Connected A4 SB_RTN Signal Return for Single Ended Sideband Signals A5 CREFCLKn Differential 100 MHz Cable Reference Clock A6 CREFCLKp B9 B1 A7 PWR_RTN Return for +3.3 V Power A8 CPERST# Cable Reset A9 GND Ground Reference for PCIe TX Lane B1 GND Ground Reference for PCIe RX Lane B2 RSVD Not Connected B3 CWAKE# Power Management Signal for Wakeup Events A9 A1 B4 CPRSNT# Cable and Downstream Subsystem Present B5 GND Ground Reference for Cable Reference Clock Figure 32: ePCIe Connector (Molex, 74960-3018) B6 PWR +3.3 V Power B7 CPWRON Upstream Subsystem’s Power Valid Notification B8 PETn0 Differential PCI Express Transmitter Lane B9 PETp0

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3.5.1.12 Dual Mode Display Port (DP++) Connector (J18) Display Port Connector according DP v1.1 with up to 2.7 Gb/s data rate per lane. Also Display Port to DVI-D or Display Port to HDMI passive adapters are supported. Pin Signal Description Pin Assignment 1 ML_Lane0p DP Lane 0 + 2 GND Ground 3 ML_Lane0n DP Lane 0 - 4 ML_Lane1p DP Lane 1 + 5 GND Ground 6 ML_Lane1n DP Lane 1 - 19 1 7 ML_Lane2p DP Lane 2 + 8 GND Ground 9 ML_Lane2n DP Lane 2 - 10 ML_Lane3p DP Lane 3 + 11 GND Ground 12 ML_Lane3n DP Lane 3 - 13 CONFIG1 DP DVI-D / HDMI Adapter Detection 20 2 14 CONFIG2 (GND) Ground 15 AUX_CHp Auxiliary Channel + Figure 33: DP++ Connector (TE, 2040204-1) 16 GND Ground 17 AUX_CHn Auxiliary Channel - 18 Hot Plug Hot Plug Detect 19 Return Return for Power 20 DP_PWR +3.3V Power

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3.5.2 INTERNAL CONNECTORS

3.5.2.1 SATA 3.0 Signal Connectors (J12, J13) Shrouded SATA connector with up to 600 MB/s data transfer rate. Pin Signal Description Pin Assignment 1 GND Ground 2 SATA0/1_A+ SATA 3.0 Port 0/1 Differential Signal Pair A 1 3 SATA0/1_A- 4 GND Ground 5 SATA0/1_B- SATA 3.0 Port 0/1 Differential Signal Pair B 6 SATA0/1_B+ 7 7 GND Ground Figure 34: SATA Connector (Molex, 67800-8125)

3.5.2.2 SATA 2.0 Signal Connectors (J73, J74) Shrouded SATA connector with up to 300 MB/s data transfer rate. Pin Signal Description Pin Assignment 1 GND Ground 2 SATA2/3_A+ SATA 3.0 Port 2/3 Differential Signal Pair A 1 3 SATA2/3_A- 4 GND Ground 5 SATA2/3_B- SATA 3.0 Port 2/3 Differential Signal Pair B 6 SATA2/3_B+ 7 7 GND Ground Figure 35: SATA Connector (Molex, 67800-8125)

3.5.2.3 SATA Power Connectors (J75, J76) Shrouded 2.54 mm header with latch. Pin Signal Description Pin Assignment 1 +5V_SATA0/2 Switched 5 V Power for SATA Port 0/2 2 +5V_SATA1/3 Switched 5 V Power for SATA Port 1/3 10 6 3 GPn0/2 SATA Device Detection at Port 0/2 4 GND Ground 5 GND Ground 6 GND Ground 7 GND Ground 5 1 8 GPn1/3 SATA Device Detection at Port 1/3 Figure 36: Power Connector for SATA Devices 9 +3.3V_SATA1/3 Switched 3.3 V Power for SATA Port 1/3 (Samtec, IPL1-105-02-S-D) 10 +3.3V_SATA0/2 Switched 3.3 V Power for SATA Port 0/2 3.5.2.4 SATA SGPIO Connector (J2002) Shrouded 1.00 mm header with friction lock used to control SATA RAID LED indicators. Pin Signal Description Pin Assignment 1 SCLOCK Serial GPIO Clock 2 SLOAD Serial GPIO Frame Load 3 SDATAOUT Serial GPIO Data Out 4 +3.3V +3.3 V System Voltage 5 GND Ground 5 1

Figure 37: SGPIO Connector for SATA RAID LED Indicators (Molex, 501331-0507)

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3.5.2.5 LED Indicator Panel Connector (J42) Shrouded 1.00 mm header with positive lock used to connect MPL AGs SerLED-x module. Pin Signal Description Pin Assignment 1 RSTBTNn Reset Button 2 PWRBTN Power Button 3 DATA Serial Data 7 4 GATE Gate 5 CLOCK Clock 6 +3.3V +3.3 V System Voltage 1 7 GND Ground Figure 38: LED Indicator Panel Connector (Molex, 501331-0707)

3.5.2.6 LVDS Connector (J14) Shrouded 1.00 mm header with positive lock used to connect flat panel displays with 18 or 24 Bit LVDS interface. Pin Signal Description Pin Assignment 1 LVDS1_TX0- Channel 1 Port 0 Data - 2 LVDS1_TX1- Channel 1 Port 1 Data - 3 LVDS1_TX0+ Channel 1 Port 0 Data + 4 LVDS1_TX1+ Channel 1 Port 1 Data + 5 LVDS1_TX2- Channel 1 Port 2 Data - 6 LVDS1_CLK- Channel 1 Clock - 7 LVDS1_TX2+ Channel 1 Port 2 Data + 8 LVDS1_CLK+ Channel 1 Clock + 9 LVDS1_TX3- Channel 1 Port 3 Data - 10 +3.3V +3.3 V System Voltage 11 LVDS1_TX3+ Channel1 Port 3 Data + 2 30 12 +3.3V +3.3 V System Voltage 13 VDDENA Flat Panel VDD enable 14 +5V +5 V System Voltage 15 DDCDAT DDC Bus Data 16 GND Ground 17 DDCCLK DDC Bus Clock 18 +5V +5 V System Voltage 1 29 19 GND Ground 20 LVDS2_TX0- Channel2 Port 0 Data - Figure 39: LVDS Panel Connector (Molex, 501190- 3017) 21 GND Ground 22 LVDS2_TX0+ Channel 2 Port 0 Data + 23 LVDS2_TX1- Channel 2 Port 1 Data - 24 LVDS2_TX2- Channel 2 Port 2 Data - 25 LVDS2_TX1+ Channel 2 Port 1 Data + 26 LVDS2_TX2+ Channel 2 Port 2 Data + 27 LVDS2_CLK- Channel 2 Clock - 28 LVDS2_TX3- Channel 2 Port 3 Data - 29 LVDS2_CLK+ Channel 2 Clock + 30 LVDS2_TX3+ Channel 2 Port 3 Data +

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3.5.2.7 Backlight Inverter Connector (J15) Shrouded 1.27 mm header with friction lock used to connect several flat panel display backlight inverters. Pin Signal Description Pin Assignment 1 VIN Connected to the Input Voltage on J36 Pin 1-3 *1 2 GND Ground 3 VIN Connected to the Input Voltage on J36 Pin 1-3 *1 4 GND Ground 5 VIN Connected to the Input Voltage on J36 Pin 1-3 *1 6 GND Ground 2 1 7 +5VSWITCHED +5 V Power, Switched with BLENA Signal 8 GND Ground 9 +5VSWITCHED +5 V Power, Switched with BLENA Signal 10 GND Ground 11 +5V +5 V System Voltage 12 GND Ground 16 15 13 +5V +5 V System Voltage Backlight Dimming (analog): Figure 40: Backlight Inverter Connector (Hirose, DF11CZ-16DP-2V) 14 DIMM_ANA Dependent on S4 Settings, Several Voltage Ranges are Possible (max. Range: 0 V .. 5 V). Backlight Enable: 15 BLENA Depends on S2000 Settings, Positive or Negative Logic is Possible (ON: 0 or 5 V, OFF: 5 or 0 V). Backlight Dimming (Puls With Modulation): 16 DIMM_PWM Depends on S4 Settings, Several PWM Duty Cycle an Frequencies are Possible. Note: *1: With a 14 V over voltage shut down to protect the backlight inverter from wrongly applied high PIP input voltages. So PIPs what supply LVDS panel backlight inverters need a 12 V input voltage. 3.5.2.8 Panel Dimming Connector (J24) Shrouded 1.00 mm header with friction lock used for flat panel display backlight dimming. Pin Signal Signal Description Pin Assignment 1 UP# Increase Brightness 2 DOWN# Decrease Brightness 3 GND Ground 4 GND Ground 4 1

Figure 41: Panel Dimming Connector (Molex, 501331-0407)

3.5.2.9 Internal Power Connector 1 (J36) Shrouded 2.54 mm header with latch. For a schematic diagram of all the PIP power connectors please see chapter 3.5.1.3.4. Pin Signal Description Pin Assignment 1 VIN Input Voltage (8 to 36 V) 2 VIN Input Voltage (8 to 36 V) 4 8 3 VIN Input Voltage (8 to 36 V) 4 +12 V Input for PCI/104-Express 12 V Power 5 GND Ground 6 GND Ground 1 5 7 GND Ground Figure 42: Internal Power Connector (Samtec, 8 GND Ground IPL1-104-02-S-D)

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3.5.2.10 Internal Power Connector 2 (J37) Shrouded 2.54 mm header with latch. Pin Signal Description Pin Assignment 1 +5 V +5 V System Voltage 2 +5 V +5 V System Voltage 5 10 3 NC Not Connected 4 GND Ground 5 GND Ground 6 GND Ground 1 6 7 GND Ground 8 NC Not Connected Figure 43: Internal Power Connector 2 (Samtec, 9 +3.3 V +3.3 V System Voltage IPL1-105-02-S-D) 10 +3.3 V +3.3 V System Voltage 3.5.2.11 Power Input Extension Connector (J35) Shrouded 4.2 mm header with latch. For a schematic diagram of all the PIP power connectors please see chapter 3.5.1.3.4. Pin Signal Signal Description Pin Assignment 1 VIN_CON Connected to Power Input behind the Load Dump Protection and the Filter Circuit 3 1 2 VIN Connected to Power Input behind the Fuse 3 GND_IN Connected to Power Input Ground 4 GND Connected to System Ground 4 2

Figure 44: Power Input Extension Connector (Molex, 39-28-1043)

3.5.2.12 High Definition Audio Connector (J43) Shrouded 1.00 mm header with positive lock used to connect MPL AGs HD Audio expansion module (optional). Pin Signal Signal Description Pin Assignment 1 RSTn HD Audio Codec Reset 2 SPKR Speaker Signal 3 +5.0V 5.0 V System Voltage 12 4 GND Ground 5 SDIN HD Audio Serial Data In 6 SDOUT HD Audio Serial Data Out 7 +3.3V 3.3 V System Voltage 8 GND Ground 1 9 BCLK 24 MHz Serial Data Bit Clock Figure 45: HD Audio Connector (Molex, 501331- 10 SYNC HD Audio 48 kHz Fixed Rate Sample Sync 1207) 11 HDA_VIO HD Audio Bus IO Level Voltage (3.3 V) 12 GND Ground 3.5.2.13 USB2.0 Header Connector (J58, J59, J60) Shrouded 1.00 mm header with friction lock used to connect MPL AGs USB 2.0 adapter module. Pin Signal Signal Description Pin Assignment 1 VCC6/7/8 USB Power Port 6/7/8 2 P6/7/8- USB 2.0 Port 6/7/8 Balanced Data Line - 3 P6/7/8+ USB 2.0 Port 6/7/8 Balanced Data Line + 4 GND Ground 1 4

Figure 46: USB2.0 Header Connector (Molex 501331-0407)

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3.5.2.14 Reset & Power Button Connector (J7) Shrouded 2.54 mm header with latch used to connect power- and reset buttons. Pin Signal Signal Description Pin Assignment 1 PWRBTN# Power Button 2 RSTBTN# Reset Button 2 4 3 GND Ground 4 GND Ground 1 3

Figure 47: Reset & Power Button Connector (Samtec, IPL1-102-02-S-D)

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3.5.2.15 PCI/104-Express Interface Type 1 Connector (J2, PCIe Part) For detailed information please refer to the PCI/104-Express Specification, Rev. 2.01. Pin Signal Signal Description Pin Assignment CPP1, CPP2 +5V +5 V System Voltage CPP3 (+12V) +12 V System Voltage *1

9, 10, 15, 16, 21, 22, 27, GND System Ground 28, 33, 34, 55, 56, 61, 62, 67, 68, 73, 74, 79, 80 ,85, 86, 91, 92, 97, 98, 103, 104, 107, 108, 113, 114, 119, 120, 125, 126, 131, 132, 137, 138, 143, 144, 149, 150, 155, 156 1 USB_OC# USB Port 12/13 Over Current 2 PE_RST# PCI Express Bus Reset 3, 4 +3.3V +3.3 V System Voltage 1 2 5, 7 USB_1+/- USB 2.0 Port 13 Balanced Data Line 6, 8 USB_0+/- USB 2.0 Port 12 Balanced Data Line 11, 13 PEx1_1Tp/n PCI Express x1 Lane Port 1 Transmit CPP1 12, 14 PEx1_0Tp/n PCI Express x1 Lane Port 0 Transmit 17, 19 PEx1_2Tp/n PCI Express x1 Lane Port 2 Transmit 18, 20 PEx1_3Tp/n PCI Express x1 Lane Port 3 Transmit 51 52 23, 25 PEx1_1Rp/n PCI Express x1 Lane Port 1 Receive 24, 26 PEx1_0Rp/n PCI Express x1 Lane Port 0 Receive 53 54 29, 31 PEx1_2Rp/n PCI Express x1 Lane Port 2 Receive 30, 32 PEx1_3Rp/n PCI Express x1 Lane Port 3 Receive CPP2 35, 37 PEx1_1Clkp/n PCI Express x1 Lane Port 1 Clock 36, 38 PEx1_0Clkp/n PCI Express x1 Lane Port 0 Clock 39, 40 +5V_SB +5V Standby Voltage (Active in ATX S5 State) 41, 43 PEx1_2Clkp/n PCI Express x1 Lane Port 2 Clock 103 104 42, 44 PEx1_3Clkp/n PCI Express x1 Lane Port 3 Clock 45 GND (DIR) Ground, Indicates that the PCIe Connector is 105 106 on the Top Side of the PIP PCB 46 PWRGOOD Power Good CPP3 47, 49, 51 SMBus SM Bus Data, Clock and Alert 48, 50 PEx16_Clkp/n PCI Express x16 Lane Clock (PEG Port) 52 PSON# Not Connected 155 156 53 WAKE# PCI Express Bus Wake 54 PEG_ENA# PCI Express Graphics (PEG) Device Enable Figure 48: PCI/104-Express 57, 58, 59, 60, 63, 64, PEx16_xTp/n PCI Express x16 Lane Transmit (PEG Port) Connector (Samtec, ASP-129637- 65, 66, 69, 70 ,71, 72, 03) 75, 76, 77, 78, 81, 82, 83, 84, 87, 88, 89, 90, 93, 94, 95, 96, 99, 100, 101, 102 105, 106 SDVO SDVO not used (100k Pull Down) 109,110, 111, 112, 115, PEx16_xRp/n PCI Express x16 Lane Receive (PEG Port) 116, 117, 118, 121, 122, 123, 124, 127, 128, 129, 130, 133, 134, 135, 136, 139, 140, 141, 142, 145, 146, 147, 148, 151, 152, 153, 154 Notes: *1: +12 V is only available if supplied to the Internal Power Connector 1 (J36) or the PCI/104-Express Power Connector (J52) from a power supply (please see chapter 3.5.1.3.4 Power Input Circuit and 3.7 SYSTEM-VOLTAGES SUPPLIED BY THE PIP).

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3.5.2.16 PCI/104-Express Interface Connector (J3, PCI Part) For detailed information please refer to the PCI/104-Express Specification, Rev. 2.01. Pin A B C D Pin Assignment 1 GND +5V_SB +5V AD0 *2 2 VIO AD2 AD1 +5V 3 AD5 GND AD4 AD3 4 C/BE0 AD7 GND AD6 5 GND AD9 AD8 GND ABCD *2 1 6 AD11 VIO AD10 M66EN 7 AD14 AD13 GND AD12 8 +3.3V C/BE1 AD15 +3.3V 9 SERR GND Not Connected PAR 10 GND PERR +3.3V Not Connected 11 STOP +3.3V LOCK GND 12 +3.3V TRDY GND DEVSEL 13 FRAME GND IRDY +3.3V 14 GND AD16 +3.3V C/BE2 15 AD18 +3.3V AD17 GND 16 AD21 AD20 GND AD19 17 +3.3V AD23 AD22 +3.3V 18 IDSEL0 GND IDSEL1 IDSEL2 *2 19 AD24 C/BE3 VIO IDSEL3 20 GND AD26 AD25 GND 21 AD29 +5V AD28 AD27 30 22 +5V AD30 GND AD31 *2 23 REQ0 GND REQ1 VIO Figure 49: PC/104+ Connector 24 GND REQ2 +5V GNT0 (Samtec, ESQT-130-03-MQ-368) *2 25 GNT1 VIO GNT2 GND 26 +5V CLK0 GND CLK1 27 CLK2 +5V CLK3 GND 28 GND INTD +5V RST 29 (+12V) *1 INTA INTB INTC 30 (-12V) *1 REQ3 GNT3 GND Notes: *1: -12 V and +12 V are only available if supplied to the Internal Power Connector 1 (J36) or the PCI/104-Express Power Connector (J52) from a power supply (please see chapter 3.5.1.3.4 Power Input Circuit and 3.7 SYSTEM-VOLTAGES SUPPLIED BY THE PIP). *2: The PC/104-PLUS IO-voltage can be set to +3.3 V or to +5.0 V with the DIP Switch 3 (please see chapter 3.4.3). 3.5.2.17 PCI/104-Express Power Connector (J52) Shrouded 2.54 mm header with latch. For a schematic diagram of all the PIP power connectors please see chapter 3.5.1.3.4. Pin Signal Description Pin Assignment 1 -12V -12 V System Voltage 2 GND Ground 1 3 GND Ground 4 +12V +12 V System Voltage 5 +12V +12 V System Voltage 5

Figure 50: PCI/104-Express Power Connector (Samtec, IPL1-105-02-L-S-K)

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3.5.2.18 Internal TTL Level Serial Port 3 (J68) and 4 (J69) Connectors Serial port 3 and 4 TTL level signals are available at 2 mm headers. Pin Signal Description Pin Assignment 1 DCDn Carrier Detect 2 DSRn Data Set Ready 3 RXD Receive Data 11 1 4 RTSn Request to Send 5 TXD Transmit Data 6 CTSn Clear to Send 7 DTRn Data Terminal Ready 8 RIn Ring Indicator 12 2 9 GND Ground 10 +5V +5 V System Voltage Figure 51: TTL Level Serial Port Connector (Fischer, 11 CONF0 SLY-2-085-12G) Module Identification 12 CONF1 3.5.2.19 mPCIe Full-Mini Card Socket 1 Supports mPCIe Full-Mini Card modules according to PCI Express Mini Card Electromechanical Specification v1.2. Pin Signal Pin Signal Pin Assignment 1 WAKE# 2 +3.3V_SB 3 Not Connected 4 GND 5 Not Connected 6 +1.5V 7 CLKREQ# 8 SIM1_PWR 9 GND 10 SIM1_DATA 11 REFCLK- 12 SIM1_CLK 13 REFCLK+ 14 SIM1_RSET 2 52 15 GND 16 SIM1_VPP 17 Not Connected 18 GND 19 Not Connected 20 W_DISABLE1# 21 GND 22 PERST# 23 PERn 24 +3.3V_SB 25 PERp 26 GND 27 GND 28 +1.5V 29 GND 30 Not Connected 31 PETn 32 Not Connected 1 51 33 PETp 34 GND Figure 52: mPCIe Full-Mini Card Socket Connector 35 GND 36 USB_D10- (JAE, MM60-52B1-E1-R650) 37 GND 38 USB_D10+ 39 +3.3V_SB 40 GND 41 +3.3V_SB 42 LED_WWAN# 43 GND 44 LED_WLAN# 45 Not Connected 46 LED_WPAN# 47 Not Connected 48 +1.5V 49 Not Connected 50 GND 51 Not Connected 52 +3.3V_SB 3.5.2.20 mPCIe Full-Mini Card Socket 1 WLAN Disable Connector (J38) The mPCIe Socket 1 WLAN Disable Signal is available at a solder pad. Pin Signal Description Pin Assignment 1 GND Ground 2 W_DISABLE1# mPCIe Socket 1 WLAN Disable Signal (Connect to GND for Disabling) 2 1

Figure 53: WLAN Disable Solder Pads

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3.5.2.21 mPCIe / mSATA Full-Mini Card Combo Socket 2 Supports mPCIe Full-Mini Card modules according to PCI Express Mini Card Electromechanical Specification v1.2 and mSATA Full-Mini Card modules according to Serial ATA Specification Revision 3.1. Pin Signal Pin Signal Pin Assignment 1 WAKE# 2 +3.3V_SB 3 Not Connected 4 GND 5 Not Connected 6 +1.5V 7 CLKREQ# 8 SIM1_PWR 9 GND 10 SIM1_DATA 11 REFCLK- 12 SIM1_CLK 13 REFCLK+ 14 SIM1_RSET 2 52 15 GND 16 SIM1_VPP 17 Not Connected 18 GND 19 Not Connected 20 W_DISABLE2# 21 CARD_DETECT# 22 PERST# 23 PERn / SATA_RX5p 24 +3.3V_SB 25 PERp / SATA_RX5n 26 GND 27 GND 28 +1.5V 29 GND 30 Not Connected 31 PETn / SATA_TX5n 32 Not Connected 1 51 33 PETp / SATA_TX5p 34 GND Figure 54: mPCIe / mSATA Full-Mini Card Combo 35 GND 36 USB_D11- Socket Connector (JAE, MM60-52B1-E1-R650) 37 GND 38 USB_D11+ 39 +3.3V_SB 40 GND 41 +3.3V_SB 42 LED_WWAN# 43 mSATA_SELECT 44 LED_WLAN# 45 Not Connected 46 LED_WPAN# 47 Not Connected 48 +1.5V 49 Not Connected 50 GND 51 Not Connected 52 +3.3V_SB 3.5.2.22 mPCIe / mSATA Full-Mini Card Combo Socket 2 WLAN Disable Connector (J70) The mPCIe socket 2 WLAN Disable Signal is available at a solder pad. Pin Signal Description Pin Assignment 1 GND Ground 2 W_DISABLE2# mPCIe Socket 2 WLAN Disable Signal (Connect to GND for Disabling) 2 1

Figure 55: WLAN Disable Solder Pads

3.5.2.23 Fan 1 and Fan 2 Connectors (J2000, J2001) This connector is reserved for future MPL system expansion. Pin Signal Description Pin Assignment 1 PWM1/2 Fan 1 / 2 Speed Control 2 FANTACH1/2 Fan 1 / 2 Tachometer Signal 3 +5V +5 V System Voltage 6 4 GND Ground 5 REMOTE1/2+ Remote Thermal Diode 1 / 2 Anode 1 6 REMOTE1/2- Remote Thermal Diode 1 / 2 Kathode

Figure 56: Fan 1 and Fan 2 Connectors (Molex, 501331-0607)

3.5.2.24 IPT700 Connector (J19) This connector is reserved for MPL test purpose. 3.5.2.25 LPC Bus Expansion Connector (J7) This connector is reserved for MPL test purpose.

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3.5.2.26 JTAG Port Connector (J78) This connector is reserved for MPL production purpose. 3.5.2.27 SPI Port Connector (J6) This connector is reserved for MPL production purpose.

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3.6 MODULE SOCKETS

3.6.1 MEMORY MODULE

3.6.1.1 Electrical and Mechanical Requirements A memory module socket with JEDEC standard layout supports DDR3-1600 (PC3-12800) 204 pin SO-DIMM memory modules with up to 8 GiB capacity (4 Gib chips). The memory modules listed bellow are tested and approved. Regarding the special environmental conditions the PIP is normally used, MPL AG recommends to use low power industrial type memory modules. It is the customers responsibility that memory modules supplied by third party vendors meet the above stated requirements. MPL AG will not be liable for memory modules that are purchased from third party vendors and don’t work in the PIP. Module Manufacturer Part Number Chip Manufacturer Capacity Corsair CMSX4GX3M1A1600C9 Corsair 4 GiB Corsair CMSX8GX3M1A1600C10 Corsair 8 GiB Kingston KHX1600C9S3K2/8GX Kingston 4 GiB

3.6.1.2 Mounting the Memory Module Please be careful with the bare memory module. Electrostatic discharge is a destructive issue to all of the electronic components on it.

Figure 57: Mounting The Memory Module

3.6.2 RS232 AND RS422 / RS485 INTERFACE MODULES The serial port 3 and 4 (please see chapter 3.5.2.18) can be equipped with MPL AGs SerifV modules (optional). This modules adds either RS232 or RS485 (half duplex) / RS422 (full duplex) support. For more information please see the SerifV User Manual.

3.6.3 PCI/104-EXPRESS MODULES Please follow the appropriate module user manuals for installing and setup the PCI/104-Express modules.

3.6.4 mPCIe AND mSATA MODULES There are a mPCIe Full-Mini Card socket and a mPCIe / mSATA Full-Mini Card combo socket, both with SIM card support, available to expand the PIP with a mSATA Solid State Disk or various IO interfaces (like LAN, WLAN, GSM, GPRS, UMTS, DVB-T, Frame Grabber, CAN, IEEE1394 A+B, .. ). Please follow the appropriate module user manuals for installing and setup the several add-on modules.

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3.7 SYSTEM-VOLTAGES SUPPLIED BY THE PIP The PIP has the possibility to supply -12 V, +3.3 V(_Standby), +5 V(_Standby) and +12 V to several connectors on the PIP PCB. But there are some specialties to pay attention to about this voltages: • -12 V and +12 V are not generated by the PIP itself. • There is a limited current available on all the supplied system voltages. • These voltages are not fused on the internal connectors, so a short circuit may cause serious damage to the PIP PCB or its components.

3.7.1 -12 V AND +12 V -12 V and +12 V must be generated by an additional power supply, that supplies these voltages to the internal power connectors J36 or J52. You can use VIN (J36 pin 1-3) for feeding and 5 V (J37 pin 1) for switching on and off this additional power supply. The maximum currents allowed for all loads on these voltages are: Maximum current Voltage Possible loads allowed for all loads -12 V - PCI/104-Express PCI Part (J3) 2 A +12 V - PCI/104-Express PCIe Part (J2) 3.5 A - PCI/104-Express PCI Part (J3)

3.7.2 +3.3 V STANDBY, +3.3 V, +5 V STANDBY AND +5 V On the PIP there is one switching regulator that supplies power to the +3.3 V_SB power rail and via a MOSFET switch it supplies power to the +3.3 V power rail also. The same at +5 V, one switching regulator for both the +5.0 V_SB and the +5.0 V power rail. Each switching regulator supplies maximum 7 A to its appropriate 3.3 V or 5.0 V loads. So each load added to the +3.3 V and the +3.3 V_SB or to the +5.0 V and the +5.0 V_SB power rail must be accumulated and the total amount of used current must not exceed 7 A: Maximum current Voltage Possible loads allowed for all loads +3.3V_SB - PCIe / mSATA Full-Mini Card Combo Socket (J32) 7 A - PCIe Mini Card Socket (J33) +3.3V - PCI/104-Express PCIe Part (J2) - PCI/104-Express PCI Part (J3) - LVDS flat panel (J14) - Display Port (J18) - Internal Power (J37) - HD Audio (J43) - PCIe external cabling (J51) - SATA Power 1 & 2 (J75, J76) +5.0V_SB - PCI/104-Express PCIe Part (J2) 7 A - PCI/104-Express PCI Part (J3) +5.0V - DVI-I (J16) - Keyboard / Mouse PS/2 (J49) - PCI/104-Express PCIe Part (J2) - PCI/104-Express PCI Part (J3) - Internal Power (J37) - HD Audio (J43) - SATA Power 1 & 2 (J75, J76) - LVDS flat panel (J14) - Backlight Inverter (J15) - USB (J4, J8, J9, J58, J59, J60)

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4 THEORY OF OPERATION

4.1 BLOCK DIAGRAM

PCIe RJ45 RJ45 9 pin DSUB PS/2 Connector Connector Connector Connectors Connector s e c a f r t t ) e t e e e n n n s I r r

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DVI-I DP RJ45 RJ45 3x2 USB eSATAp Connector Connector Connector Connector Connectors Connector

Figure 58: Complete PIP Block Diagram Note: ● There are several PIP variants available. Please refer to the ordering information list in chapter 1.8 to see all the appropriate features.

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4.2 STATUS INDICATORS The PIP provides 15 status indicator LEDs at the case cover, giving you visual information about the actual operating status. Indicator LED Meaning Power LED Dark: PIP in ACPI power state G3 (Mechanical OFF) Yellow: PIP in ACPI power state S5 (Soft Off) Green: PIP in ACPI power state S0 (Working) Green / yellow blinking: CPU temperature > 100 °C Yellow / red blinking: PIP in ACPI power state S5, because CPU temperature was > 125 °C (immediate shutdown for CPU thermal protection) *1 Reset LED Red: PIP in reset state Red blinking: Power failure detected, please turn off the power supply feeding the PIP and remove the power failure issue User [1..2] LED Dark, Green, Red, Yellow: Free user programmable status indicators (see chapter 5.1.6) LAN [1..4] Dark: No link Activity LED Green: Link detected Green blinking: Link with activity LAN [1..4] Dark: No link or 10 Mb/s link Speed LED Green: 100 Mb/s link Yellow: 1 Gb/s link HDD LED Green: Access to any connected SATA device mPCIe [2..1] Green: mPCIe Module is powered and ready to work Status LED Green slowly blinking: mPCIe Module is connecting to a network Green blinking: mPCIe Module with link activity Note: *1: Please first let the PIP cool down and then control the cooling system against any defects. For starting the PIP after an immediate shutdown please press the power button once. Solely cycling the power input does not work.

4.3 BATTERY CIRCUIT

Battery type: Renata CR2032 3 V / 230 mAh Lithium Coin Cell (20.0 x 3.2 mm) An on board battery provides power to the Real Time Clock (RTC) and the CMOS RAM circuit. For changing the battery please follow the steps below: ● Remove the 6 screws to open the right side panel.

Figure 59: Removing the 6 screws ● Pull the battery out of its socket and replace it with the new one.

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4.4 RS485 / RS422 INTERFACES When using the optional RS485 / RS422 module SerifV-2 with a half-duplex interface (using a 2-wire connection) then it is necessary to control the transmit driver enable. This is automatically done by the UART with the RTS signal, but only if it is correctly enabled in the BIOS setup (please refer to the PIP3x System BIOS User Manual).

4.5 WATCHDOG TIMER The PIP uses the SCH3114 Super-IO watchdog timer with a programmable time-out from one to 255 minutes with a one minute resolution, or from one to 255 seconds with a one second resolution. The watchdog timer do a system reset if the timeout has expired. OS drivers are available at the MPL AG homepage, please refer to chap. 5.3DEVICE DRIVERS.

4.6 TEMPERATURE SENSORS For monitoring the system health there are several temperature sensors available at the PIP. Temperature Sensor Type Interface and Address CPU, individual core Intel CPU Digital Thermal Sensors (DTS) CPU MSR register block Memory, on board ADT7408 (compatible to JEDEC JC-42.4 spec) SMBus: Addr = $18 (7 bit) Memory, SO-DIMM module Type and availability depends on memory module SMBus: Addr = $1a (7 bit) Motherboard, near Ethernet controllers LM75 SMBus: Addr = $48 (7 bit) Motherboard, at Super IO chip SCH3114 SIO Hardware Monitor SIO HW-monitor register block

4.7 EARTHING AND GALVANIC ISOLATION The PIP is designed to support different earthing schemes. Please refer to the electrical schematics below, to understand the different possibilities. In this chapter it is assumed that the PIP is well earthed over its DIN rail for accurate ESD and EMC behavior. J35 1 2 Power Input 3 Extension 4 Connector External Power

Connector VIN_CON VIN_FLT J21 FUSE 6.3A T 1 Load Dump Input Filter and VIN 2 Protection and ESD Protection 3 Filter 0 Ohm 0 Ohm

GND GND_CON GND_IN J36 CASE_EARTH 1 VIN 2 VIN 3 VIN 4 Internal Power VCC_+12V +12V 5 IGN, RST-, GND Connector 1 6 GND PWR-BTN 7 GND 8 Connector GND J53 to Ignition Signal Logic GND 1 J52 2 1 3 to Power Button Logic VCC_-12V -12V 2 4 GND 3 PCI/104-Express to Reset Button Logic GND GND 4 GND_CON VCC_+12V +12V Power Connector 5 +12V

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4.7.1 DESKTOP PC EARTHING SCHEME (PIP DEFAULT) The Power Input, the housing and all the interfaces are referenced to CASE_EARTH. That means GND_CON, GND_IN and GND are shorted to CASE_EARTH. This earthing scheme is Desktop PC compatible and is the default PIP earthing scheme. Pros Cons • Everything is as normal as with a desktop PC. • Ground loops are possible. • Standard PC periphery can be used without constraints. • A wrong polarized earthed power supply or one with a potential difference between earth and its negative pole induces a short circuit current via GND_CON to CASE_EARTH and on earth back to the power supply. • This may damage the PIP GND_CON → CASE_EARTH path.

4.7.2 GALVANICALLY ISOLATED HOUSING (OPTIONAL) With this earthing scheme the connection between CASE_EARTH and GND_CON is replaced with a 10 MΩ resistor. Pros Cons • The ground loop “power supply ↔ PIP” is opened, no • It is easily overlooked that external PC hardware like USB current flow on earth. flash drives or PC monitors often short again the • A wrong polarized earthed power supply or one with a connection between CASE_EARTH and the ground potential difference between earth and its negative pole (GND) pins of the appropriate interface connectors (USB, doesn't damage the PIP (if the ground loop isn't closed DVI, …). again with external hardware). • Then all the ground loop current (e.g. from a wrong polarized earthed power supply) flows through the GND and signal pins of the appropriate interface connector and through the external connected hardware to earth and back to the power supply. • A wrong polarized high output power supply then may damage the external hardware and the corresponding PIP interface.

4.7.3 GALVANICALLY ISOLATED HOUSING AND POWER INPUT (OPTIONAL) With this earthing scheme the connection between CASE_EARTH and GND_CON is replaced with a 10 MΩ resistor. Additionally, the connection between GND_IN and GND and the 6.3 A fuse is replaced with a galvanically isolated DC / DC converter. Pros Cons • The ground loop “power supply ↔ PIP” is opened two • Also with this configuration ground loops are possible. times, no current flow on earth. • External PC hardware may short the connection between • A wrong polarized earthed power supply doesn't damage CASE_EARTH and the GND pins of the appropriate the PIP. interface connector. • An electrical potential difference between the power • Also shielded cables like some Ethernet cables may short supply and the PIP doesn't damage the PIP or possibly CASE_EARTH to a far away earthed Ethernet switch. connected external PC hardware.

4.7.4 CONCLUSION If the PIP is used in a wide branched system of power supply, external connected devices or Ethernet lines it is important to understand where closed ground loops are, where voltages can be coupled into this system, where an electrical potential difference may occur and what may happen if something goes wrong or is wrongly connected. In this regard at risk are PIPs, which are mounted near heavy electrical loads, near electrical drives, at vehicles or at wide branched industrial facilities.

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5 SOFTWARE

5.1 PIP EXTENSION REGISTER SET

5.1.1 OVERVIEW

IO-Address Function Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Serial Ports $800 Status Reserved Reserved SER4_STS1 SER4_STS0 Reserved Reserved SER3_STS1 SER3_STS0 Register

Boot LED Reserved Reserved Reserved Reserved Reserved Reserved BLED_RD BLED_GN $801 Register

SATA Power Reserved Reserved Reserved Reserved SATA_PEN3 SATA_PEN2 SATA_PEN1 SATA_PEN0 $802 Register

$803 RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

$804 RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

$805 RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

$806 RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

$807 RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

ACPI BIOS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $808 scratch (do not (do not (do not (do not (do not (do not (do not (do not Register modify) modify) modify) modify) modify) modify) modify) modify) User LED $809 Control Reserved Reserved Reserved Reserved ULED2_RD ULED2_GN ULED1_RD ULED1_GN Register

PIP Status BR_UP BR_DN WLAN2_DIS WLAN1_DIS NIC4_DIS NIC3_DIS NIC2_DIS NIC1_DIS $80A Register 1

PIP Status DSW4_1 DSW4_2 DSW4_3 DSW4_4 DSW4_5 DSW4_6 DSW4_7 DSW4_8 $80B Register 2

$80C RESERVED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

PIP PCB $80D Revision Reserved Reserved Reserved Reserved PCB_REV3 PCB_REV2 PCB_REV1 PCB_REV0 Register PLD Code $80E ID PLD_ID7 PLD_ID6 PLD_ID5 PLD_ID4 PLD_ID3 PLD_ID2 PLD_ID1 PLD_ID0 Register PLD Code $80F Revision PLD_REV7 PLD_REV6 PLD_REV5 PLD_REV4 PLD_REV3 PLD_REV2 PLD_REV1 PLD_REV0 Register

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5.1.2 SERIAL PORTS STATUS REGISTER Address: IO 800h Default Value: 00xx'00xxb Access: Read only Bit Access Default Value Description 7:6 RO 00b Reserved 5:4 RO xxb SER4_STS[1..0]: These bits report the serial port 4 interface type. Encoding Description 00b Reserved 01b RS232 10b RS422 / RS485 11b Interface not used 3:2 RO 00b Reserved 1:0 RO xxb SER3_STS[1..0]: These bits report the serial port 3 interface type. Encoding Description 00b Reserved 01b RS232 10b RS422 / RS485 11b Interface not used

5.1.3 BOOT LED REGISTER Address: IO 801h Default Value: 00h Access: Read only, Read / Write Bit Access Default Value Description 7:2 RO 0000'00b Reserved 1:0 RD / WR 00b BLED_RD/GN: These bits define the Boot LED status. Encoding Description 00b Boot LED Off 01b Boot LED lights green 10b Boot LED lights red 11b Boot LED lights yellow (green and red)

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5.1.4 SATA POWER REGISTER Address: IO 802h Default Value: 00h Access: Read only, Read / Write Bit Access Default Value Description 7:4 RO 0h Reserved 3 RD / WR 0b SATA_PEN3: This bit defines the SATA port 3 power state. Encoding Description 0b +3.3V/+5V_SATA3 Power Off 1b +3.3V/+5V_SATA3 Power On 2 RD / WR 0b SATA_PEN2: This bit defines the SATA port 2 power state. Encoding Description 0b +3.3V/+5V_SATA2 Power Off 1b +3.3V/+5V_SATA2 Power On 1 RD / WR 0b SATA_PEN1: This bit defines the SATA port 1 power state. Encoding Description 0b +3.3V/+5V_SATA1 Power Off 1b +3.3V/+5V_SATA1 Power On 0 RD / WR 0b SATA_PEN0: This bit defines the SATA port 0 power state. Encoding Description 0b +3.3V/+5V_SATA0 Power Off 1b +3.3V/+5V_SATA0 Power On

5.1.5 ACPI BIOS SCRATCH REGISTER Address: IO 808h Default Value: 00h Access: Read / Write Bit Access Default Value Description 7:0 RD / WR 00h Reserved Used by the PIP BIOS. Do not modify this register.

5.1.6 USER LED REGISTER Address: IO 809h Default Value: 00h Access: Read only, Read / Write Bit Access Default Value Description 7:4 RO 0000b Reserved 3:2 RD / WR 00b USER_LED2: These bits define the User LED2 status. Encoding Description 00b User LED2 Off 01b User LED2 lights green 10b User LED2 lights red 11b User LED2 lights yellow (green and red) 1:0 RD / WR 00b USER_LED1: These bits define the User LED1 status. Encoding Description 00b User LED1 Off 01b User LED1 lights green 10b User LED1 lights red 11b User LED1 lights yellow (green and red)

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5.1.7 PIP STATUS REGISTER 1 Address: IO 80Ah Default Value: xxh Access: Read only Bit Access Default Value Description 7 RO xb BR_UP: Used by the PIP BIOS. Increase the panel backlight brightness by Panel Dimming Connector (J24) pin 1. Encoding Description 0b Increase the Panel Backlight Brightness 1b No Action 6 RO xb BR_DN: Used by the PIP BIOS. Decrease the panel backlight brightness by Panel Dimming Connector (J24) pin 2. Encoding Description 0b Decrease the Panel Backlight Brightness 1b No Action 5 RO xb WLAN2_DIS: This bit reports the mPCIe Socket 2 radio operation disable signal set by the switch connected to J70. Encoding Description 0b mPCIe Socket 2 Radio Operation Disabled 1b Normal Operation 4 RO xb WLAN1_DIS: This bit reports the mPCIe Socket 1 radio operation disable signal set by the switch connected to J38. Encoding Description 0b mPCIe Socket 1 Radio Operation Disabled 1b Normal Operation 3 RO xb NIC4_DIS: This bit reports the DIP switch S2-5 status. Encoding Description 0b NIC4 Controller Disabled 1b NIC4 Controller Normal Operation 2 RO xb NIC3_DIS: This bit reports the DIP switch S2-6 status. Encoding Description 0b NIC3 Controller Disabled 1b NIC3 Controller Normal Operation 1 RO xb NIC2_DIS: This bit reports the DIP switch S2-7 status. Encoding Description 0b NIC2 Controller Disabled 1b NIC2 Controller Normal Operation 0 RO xb NIC1_DIS: This bit reports the DIP switch S2-8 status. Encoding Description 0b NIC1 Controller Disabled 1b NIC1 Controller Normal Operation

5.1.8 PIP STATUS REGISTER 2 Address: IO 80Bh Default Value: xxh Access: Read only Bit Access Default Value Description 7:0 RO xxh DSW4[1..8]: These bits report the LVDS port (LCD panel) settings tuned by the DIP switch S4.

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5.1.9 PIP PCB REVISION REGISTER Address: IO 80Dh Default Value: xxh Access: Read only Bit Access Default Value Description 7:0 RO xxh PCB_REV[7..0]: These bits report the PIP3x PCB revision. Encoding Description 00h PCB Rev. A 01h PCB Rev. B 02h PCB Rev. C ......

5.1.10 PLD CODE ID REGISTER Address: IO 80Eh Default Value: xxh Access: Read only Bit Access Default Value Description 7:0 RO xxh PLD_ID[7..0]: These bits report the PLD code ID. Encoding Description 00h PLD Code ID P00 01h PLD Code ID P01 02h PLD Code ID P02 ......

5.1.11 PLD CODE REVISION REGISTER Address: IO 80Fh Default Value: 0xh Access: Read only Bit Access Default Value Description 7:0 RO xxh PLD_REV[7..0]: These bits report the PLD code revision. Encoding Description 00h PLD Code Revision V00 01h PLD Code ID V01 02h PLD Code ID V02 ......

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5.2 BIOS BIOS upgrading is easily possible. Please refer to the PIP3x System BIOS User Manual for additional information. The latest BIOS version is available at the MPL AG homepage: http://www.mpl.ch/t24e3.html

5.3 DEVICE DRIVERS All the drivers are available at the MPL AG homepage: http://www.mpl.ch/t24e3.html

5.4 TOOLS There are different hardware monitoring features that can be reported with several freeware tools: ● CoreTemp (CPU monitor): http://www.alcpu.com/CoreTemp/

● Open Hardware Monitor (CPU-, Memory- and HD drive monitor): http://openhardwaremonitor.org/

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6 COPYRIGHT Copyright © 2013 by MPL AG Elektronikunternehmen. All rights are reserved. Reproduction of this document in part or whole, by any means is prohibited, without written permission from MPL AG Elektronikunternehmen.

7 DISCLAIMER MPL AG has fully tested the PIPs and reviewed the documentation. However, MPL AG makes no warranty or representation, either expressed, or implied, with respect to this product, its quality, performance, merchantability, or fitness for a particular purpose. In no event will MPL AG be liable for direct, indirect, special, incidental, or consequential damages resulting from any defect in the product or its documentation, even if advised of the possibility of such damages. In particular MPL AG shall have no liability for any parts connected to this product. MPL AG reserves the right to make changes to any product herein to improve reliability, function or design.

8 TRADEMARKS Brand or product names are trademarks and registered trademarks of their respective holders.

9 SUPPORT

9.1 FAQs Please have a look at the homepage www.mpl.ch/t2400.html. In the menu at the left hand side you will find FAQ's for each available PIP.

9.2 SERIAL NUMBER AND REVISION When contacting MPL Support it is important that you declare the PIP type, the serial number with revision and the BIOS number. Please have a look at the label on the top of the PIP housing for this.

Type: S/N: 21365 [A] PIP 31-1 BIOS: MEV-10129-001 Rating: 8 VDC - 36 VDC / 6.3 AT Class 2 Power Supply only Environment: -20 °C - +60 °C Enclosure Type 1

LAN1 MAC: 00.60.C2.1C.00.0C LAN3 MAC: 00.60.C2.1C.00.0E LAN2 MAC: 00.60.C2.1C.00.0D LAN4 MAC: 00.60.C2.1C.00.0F

Figure 60: PIP Label

9.3 CONTACTING MPL AG In case of general information questions please feel free to contact MPL AG at the homepage (www.mpl.ch) or per email ([email protected]). In case of sales information questions please send your email to [email protected]. If you have a technical problem with a PIP, first please carefully read the BIOS user manual, this manual and the FAQs at the homepage. If you can’t solve the problem on your own, you can contact MPL AG for technical support per email at [email protected].

MPL AG local Distributor: