A Method for Producing an Organic Field Effect Transistor and an Organic Field Effect Transistor

(19) TZZ _¥¥_T

(11) EP 2 797 133 A1

(12) EUROPEAN PATENT APPLICATION

(43) Date of publication: (51) Int Cl.: 29.10.2014 Bulletin 2014/44 H01L 51/05 (2006.01) H01L 51/10 (2006.01) H01L 51/52 (2006.01) (21) Application number: 13164959.2

(22) Date of filing: 23.04.2013

(84) Designated Contracting States: • Kleemann, Hans AL AT BE BG CH CY CZ DE DK EE ES FI FR GB 01187 Dresden (DE) GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO • Lüssem, Björn PL PT RO RS SE SI SK SM TR 01127 Dresden (DE) Designated Extension States: •Leo,Karl BA ME 01219 Dresden (DE)

(71) Applicants: (74) Representative: Bittner, Thomas L. • Novaled GmbH Boehmert & Boehmert 01307 Dresden (DE) Anwaltspartnerschaft mbB • Technische Universität Dresden Patentanwälte Rechtsanwälte 01062 Dresden (DE) Pettenkoferstrasse 20-22 80336 München (DE) (72) Inventors: •Günther,Alrun 01159 Dresden (DE)

(54) A method for producing an organic field effect transistor and an organic field effect transistor

(57) The present disclosure relates to a method for producing an organic field effect transistor, the method comprising steps of providing a gate electrode (1) and a gate insulator (2) assigned to the gate electrode (1) for electrical insulation on a substrate, depositing a first organic semiconducting layer (3) on the gate insulator (2), generating a first electrode (4) and an electrode insulator (5) assigned to the first electrode (4) for electrical insulation, depositing a second organic semiconducting layer (6) on the first organic semiconducting layer (3) and the electrode insulator (5), and generating a second electrode (7), wherein the method further comprises at least one of the following steps generating a first doping material layer (13) on the first organic semiconducting layer (3) prior to generating the first electrode (4) and the electrode insulator (5) such that the first electrode (4) with the electrode insulator (5) are generated at least partially on the first doping material layer (13), and generating a second doping material layer (14) on the second organic semiconducting layer (6) prior to generating the second electrode (7) such that the second electrode (7) is generated at least partially on the second doping material layer (14). Furthermore, an organic field effect transistor is provided. EP 2 797 133 A1

Printed by Jouve, 75001 PARIS (FR) 1 EP 2 797 133 A1 2

Description porting layer are arranged on the semiconducting layer. Further, the transistor comprises an emitting layer and a [0001] The invention relates to a method for producing drain electrode. anorganic field effect transistorand an organic field effect [0007] There is a need to provide a transistor design transistor. 5 which allows high current densities in the device and which can be produced in an easy and controllable man- Background of the invention ner.

[0002] For a realization of flexible and electronic com- Summary of the invention ponents based on organic semiconducting elements it is 10 necessary to develop capable and robust organic tran- [0008] It is the object of the invention to provide a meth- sistors. A promising approach is provided by vertical or- od for producing an organic field effect transistor and an ganic field effect transistors (VOFETs). organic field effect transistor, wherein the organic field [0003] A VOFET (as field effect transistors in general) effect transistor has a high current density. is formed with three electrodes, namely a gate electrode, 15 [0009] This object is solved by the method according a source electrode and a drain electrode. In a VOFET, to the independent claim 1 and the organic field effect the source electrode and the drain electrode are con- transistor according to the independent claim 12. Advan- nected with each other by an organic semiconductor. The tageous embodiments of the invention are the subject of gate electrode is separated from the source electrode dependent claims. and the drain electrode by an insulator. The elements of 20 [0010] According to one aspect of the invention, a the VOFET are formed as a stack on a substrate, wherein method for producing an organic field effect transistor is the stack has one of the following sequences of layers: provided. The method comprises steps of providing a substrate / gate electrode / insulator / source electrode / gate electrode and a gate insulator assigned to the gate drain electrode or substrate / drain electrode / source electrode for electrical insulation on a substrate, depos- electrode / insulator / gate electrode. The organic semi- 25 iting a first organic semiconducting layer on the gate in- conductor is always arranged between the source elec- sulator, generating a first electrode and an electrode in- trode and the drain electrode. Additionally, it can be ar- sulator assigned to the first electrode for electrical insu- ranged between the insulator and the source electrode. lation, depositing a second organic semiconducting layer Two methods are known for producing a VOFET: self- on the first organic semiconducting layer and the elec- organization of the materials and technical structuring, 30 trode insulator, and generating a second electrode. Fur- for example with a shadow mask. ther, the method comprises at least one of the following [0004] The document WO 2010/113163 A1 discloses steps: generating a first doping material layer on the first a vertical organic field effect transistor and a method for organic semiconducting layer prior to generating the first producing the same. The transistor comprises a pat- electrode and the electrode insulator such that the first terned electrode structure which is enclosed between a 35 electrode with the electrode insulator are generated at dielectriclayer and an activeelement. The activeelement least partially on the first doping material layer, and gen- is either an organic semiconductor or an amorphous erating a second doping material layer on the second semiconductor. The electrode structure is patterned by organic semiconducting layer prior to generating the sec- using a block copolymer material as a patterning mask. ond electrode such that the second electrode is gener- Hereby, the thickness of the patterned layer and lateral 40 ated at least partially on the second doping material layer. feature size can be selected. [0011] According to another aspect of the invention, [0005] A method for forming an organic device having an organic field effect transistor is provided, comprising a patterned conductive layer is disclosed in document a first electrode and a second electrode, the electrodes WO 2011/139774. The method comprises the steps of providing a source electrode and a drain electrode, a depositing an organic layer on a substrate and coating 45 gate electrode, a gate insulator provided between the the organic layer with a photoresist solution to form a gate electrode and the first electrode, an electrode insu- photo-patternable layer. The photoresist solution in- lator providedbetween thefirst and the secondelectrode, cludes a fluorinated photoresist material and a fluorinated a first organic semiconducting layer provided between solvent. Selected portions of the photo-patternable layer the gate insulator and the first electrode, a second or- are radiated to form a pattern. A conductive layer is coat- 50 ganic semiconducting layer provided between the first ed over the organic layer. A portion of the conductive organic semiconducting layer and the second electrode, layer is removed to form a patterned conductive layer. and at least one of the following layers: a first doping [0006] K. Nakamura et al., Applied Physics Letters Vol. material layer which is provided between the first elec- 89, page 103525 (2006) discloses an organic light emit- trode and the first organic semiconducting layer and ting transistor. A gate electrode is arranged on a sub- 55 which is at least partially in direct contact with the first strate and covered by a gate insulating layer. A semicon- electrode, and a second doping material layer which is ducting layer is coated on the gate insulating layer. A provided between the second electrode and the second source electrode, an insulating layer, and a hole trans- organic semiconducting layer and which is at least par-

2 3 EP 2 797 133 A1 4 tially in direct contact with the second electrode. The first doping material layer, respectively. and second organic semiconducting layers can be con- [0017] VOFETs in general have an asymmetric re- figured to transport charge carriers of the same type, sponse for positive and negative Drain-Source voltages namely holes and electrons. Alternatively or in addition, VSD caused by the different electrical field from the gate the first and second organic semiconducting layers can 5 electrode to the source and drain electrodes, due to the be configured to transport both carrier types, namely different distances of the source and drain electrodes to holes and electrons. the gate insulator. It was found that by using a first doping [0012] The invention refers to a vertical transistor de- material layer between the source electrode and the first sign. The first and second electrode each provides a con- semiconducting layer and / or a second doping material tact for applying a voltage to the transistor. The gate elec- 10 layer between the drain electrode and the second organic trode provides a contact for controlling the state of the semiconducting layer, respectively, it is possible to con- transistor. By the electrode insulator a parallel resistance trol the asymmetry. Preferably, the first and / or second of the transistor is reduced and the ratio between the doping material layers have a thickness of less than 5 current in an ON-state and the current in an OFF-state nm, respectively. is increased. 15 [0018] In a hole transport layer (HTL) the mobility of [0013] In an exemplary embodiment the method com- holes is larger than the mobility of electrons. In an elec- prises steps of providing a gate electrode and a gate tron transport layer (ETL) the mobility of electrons is larg- insulator assigned to the gate electrode for electrical in- er than the mobility of holes. sulation on a substrate, depositing a first organic semi- [0019] The first and second organic semiconducting conducting layer on the gate insulator, generating a first 20 layers are generated in separated steps. At least one of doping material layer on the first organic semiconducting, the first and second organic semiconducting layers may generating a first electrode and an electrode insulator be made completely of a matrix material. There is a junc- assigned to the first electrode for electrical insulation at tion at the interface of one of the first or second electrode least partially on the first doping material layer, depositing to the organic semiconducting material, namely a a second organic semiconducting layer on the first or- 25 Schottky barrier. The junction depends on the polarity of ganic semiconducting layer and the electrode insulator, the electrode (acting as source electrode or drain elec- and generating a second electrode on the second sem- trode). The Schottky barrier is modulated by the field from iconducting layer. the gate insulator. An injection barrier only forms if the [0014] In another embodiment the method comprises material of the adjacent organic semiconducting layer is steps of providing a gate electrode and a gate insulator 30 not doped, and free of an injection layer. The path be- assigned to the gate electrode for electrical insulation on tween the first electrode and the second electrode is a substrate, depositing a first organic semiconducting mainly for transport only in this case. layer on the gate insulator, generating a first electrode [0020] Alternatively, at least one of the first or second and an electrode insulator assigned to the first electrode organic semiconducting layer is doped which reduces for electrical insulation on the first semiconducting layer, 35 asymmetric properties of the transistor. A doped layer depositing a second organic semiconducting layer on the comprises a matrix material and at least one dopant. The first organic semiconducting layer and the electrode in- doped layer may be made of the matrix material and one sulator, generating a second doping material layer on the dopant, preferentially of more than 90 % (mol) of the ma- second organic semiconducting layer, and generating a trix material, even more preferable of more than 95mol%. second electrode at least partially on the second doping 40 If one or both of the organic semiconducting layers is material layer. doped, the first and second organic semiconducting lay- [0015] In an alternative embodiment the method com- ers preferentially comprise matrix materials configured prises steps of providing a gate electrode and a gate to transport the same type of charge carriers. It is even insulator assigned to the gate electrode for electrical in- more preferred that the organic matrix material of both sulation on a substrate, depositing a first organic semi- 45 layers is the same material. conducting layer on the gate insulator, generating a first [0021] Preferentially, all organic semiconducting ma- doping material layer on the first organic semiconducting terials have singlet excitation energies equal or smaller layer, generating a first electrode and an electrode insu- than 2eV, preferably smaller than 1.85 eV, and/or the lator assigned to the first electrode for electrical insulation singlet transition is forbidden. The singlet excitation en- at least partially on the first doping material layer, depos- 50 ergy is calculated from the photon energy of the wave- iting a second organic semiconducting layer on the first length of the absorption peak (maximum of the singlet organic semiconducting layer and the electrode insula- peak), which implies that the emission is smaller than tor, generating a second doping material layer on the 1.83eV plus the binding energy, which is typically in the second organic semiconducting layer, and generating a infrared. Thus, the materials do not emit visible light. second electrode at least partially on the second doping 55 [0022] In one embodiment of the method at least one material layer. of the step of generating the first electrode and the elec- [0016] The first and second electrode may be gener- trode insulator, the step of generating the first doping ated such that they completely cover the first and second material layer, the step of generating the second elec-

3 5 EP 2 797 133 A1 6 trode and the step of generating the second doping ma- organic semiconducting layers comprise the same or- terial layer comprises a step of photo-lithographic struc- ganic matrix material. At least one of the first and second turing on the first and the second organic semiconducting organic semiconducting layers may be made of the or- layer, respectively. It is known to produce VOFETs using ganic matrix material. The first and / or second organic shadow masking. These VOFETs have a small specific 5 semiconducting layer can be formed by vacuum or solu- edge length. With photo-lithographic structuring the edge tion processing. length can be maximized while using a technical well [0028] Alternatively or in addition, in an embodiment controllableprocedure. A high performance device ispro- of the method, the first electrode is generated with first vided without requiring sophisticated lithography equip- sub-electrode portions and the second electrode is gen- ment. Common equipment with resolution and alignment 10 erated with second sub-electrode portions, the plurality registry of about 1 mm is more than sufficient to produce of sub-electrode portions being arranged in separated the transistor. Preferably, the first and / or second doping groups of overlapping sub-electrode portions, wherein material layers are generated after applying the photo- each of the separated groups of overlapping sub-elec- lithographic mask but before depositing the first and sec- trode portions is generated with at least one first sub- ond electrode, respectively. By this, doping may be re- 15 electrode portion overlapping with at least one second stricted to areas attached to the respective contact ma- sub-electrode portion. The sub-electrode portions of both terials. In principle, this may be realized by a shadow electrodes have a correspondence; either a one-to-one masking process. correspondence if the overlap area is larger than the non- [0023] In a preferred embodiment, the first doping ma- overlapping area, or a one-to-one or a one-to-two neigh- terial layer and / or the second doping material layer are 20 boring (where the end can be even or odd) if the overlap generated by physical vapour deposition, in particular by area is smaller than the non-overlapping area. In the first thermal evaporation. Hereby, the step of generating the case, the width of the sub-electrode of the second elec- first and / or second doping material layer can be inte- trode is preferentially larger than the width of sub-elec- grated in known production processes in a simple man- trode of the sub-electrode of the first electrode. ner. 25 [0029] Preferentially, the sub-electrodes portions of [0024] In anotherembodiment, the firstdoping material both electrodes are arranged parallel to each other. Here- layer and / or the second doping material layer are made by, the optimum of lowest capacitance while keeping the of a pure electrical dopant material, respectively. The first series resistance low is provided. doping material layer and the second doping material [0030] In a further embodiment, the first doping mate- layer can be made of the same pure electrical dopant 30 rial layer is generated such that the first sub-electrode material. Alternatively, both doping material layers can portions are at least partially in direct contact with the be made of different pure electrical dopant materials. first doping material layer and / or the second doping [0025] In an alternative embodiment the first doping material layer is generated such that the second sub- material layer and / or the second doping material layer electrode portions are at least partially in direct contact comprise a matrix material including an electrical dopant 35 with the second doping material layer. Preferably, the material, respectively. The first doping material layer and first and / or second sub-electrode portions cover the first the second doping material layer can comprise the same and / or second doping material layers completely, re- matrix material including the same electrical dopant ma- spectively. terial. Alternatively, both doping material layers can com- [0031] In a preferred embodiment, the step of gener- prise the same matrix material including different electri- 40 ating the first electrode and the electrode insulator com- cal dopant materials. In another alternative, both doping prises steps of depositing a first photoresist layer on the material layers can comprise different matrix materials first organic semiconducting layer and / or on the first with either the same or different electrical dopant mate- doping material layer, if applicable, defining an electrode rials. In a layer comprising a matrix material and an elec- area for the first electrode by patterning the first photore- trical dopant material, the dopant material may exist in a 45 sist layer, thereby providing a first photoresist pattern, ratio of less than 5mol% in the layer, preferably less than depositing a first conductive layer on the first photoresist 2mol%. The matrix materials used in the first and second pattern, depositing an insulating layer on the first con- doping materiallayers canbe the same orcan be different ductive layer, and removing the first photoresist pattern from the first and second organic semiconducting layer. in a lift-off process, thereby generating the first electrode If they are different they may have a lower mobility. 50 and the electrode insulator. [0026] The dopants used for generating the first and [0032] In still a further embodiment, the step of gener- second doping material layer, either as pure dopant ma- ating the second electrode comprises steps of depositing terial or in a matrix/dopant system, can be small organic a second photoresist layer on the first organic semicon- molecules. The matrix material can be an organic sem- ducting layer, on the electrode insulator, and on the sec- iconducting material. The thickness of the first and / or 55 ond doping material layer, if applicable, defining an elec- second doping material layer is preferably less than 2.5 trode area for the second electrode by patterning the sec- nm, more preferably equal to or less than 1 nm. ond photoresist layer, thereby providing a second pho- [0027] In a preferred embodiment, the first and second toresist pattern, depositing a second unpatterned organic

4 7 EP 2 797 133 A1 8 semiconducting layer on the second photoresist pattern, light does not affect the performance of the transistor. depositing a second conductive layer on the second un- [0041] According to a further embodiment, at least one patterned organic semiconducting layer, and removing electrode selected from the following group is made of a the second photoresist pattern in a lift-off process, there- metal material: the first electrode, the second electrode, by generating the second organic semiconducting layer 5 and the gate electrode. The metal material may be gold and the second electrode. Alternatively, the deposition or aluminum. Electrodes made of a metal material have of the second electrode can be made after removing the a low resistance while a high power with a high frequency patterned second photoresist layer. may be applied. [0033] For generating the first electrode and / or the [0042] The dopant material is preferably an electrical second electrode patterning may involve curing a portion 10 dopant. Electrical dopants are classified in p-dopants and and removing an uncured portion. The first photoresist n-dopants. Electrical doping is well known in the field, layer and / or the second photoresist layer can be formed exemplary literature references are Gao et al, Appl. Phys. as a double layer. The steps involving deposition, pat- Lett. V.79, p.4040 (2001), Blochwitz et al, Appl. Phys. terning and removing of the first and / or second photore- Lett. V.73, p.729 (1998), D’Andrade et al. App. Phys. Let. sist layer can be done under normal or under an inert 15 V.83, p. 3858 (2003), Walzer et al. Chem. Rev. V. 107, gas atmosphere. The first and / or second photoresist p.1233 (2007), US2005040390A1, US2009179189A. layer may be removed by an additional step of plasma Exemplary p-dopants are: tetrafluoro-tetracyanoqui- etching. nonedimethane (F4TCNQ); 2,2’-(perfluoronaphthalene- [0034] In a preferred embodiment of the invention, the 2,6-diylidene) dimalononitrile (F6TCNNQ); 2,2’,2"-(cy- first electrode is provided with first sub-electrode portions 20 clopropane-1,2,3-triylidene)tris(2-(p-cyanotetrafluor- and the second electrode is provided with second sub- ophenyl)acetonitrile). Preferred compounds are organic electrode portions, the plurality of sub-electrode portions molecules containing cyano groups. Exemplary n-do- being arranged in separated groups of overlapping sub- pants are: acridine orange base (AOB); tetrakis electrode portions, wherein each of the separated groups (1,3,4,6,7,8 - hexahydro - 2H - pyrimido [1,2 - a] pyrimid- of overlapping sub-electrode portions comprises at least 25 inato) ditungsten (II) (W2(hpp)4); 3,6-bis-(dimethyl ami- one first sub-electrode portion overlapping with at least no)-acridine; bis(ethylene-dithio) tetrathiafulvalene one second sub-electrode portion. The first and second (BEDT-TTF); oxocarbon; pseudooxocarbonderivatives. semiconducting layers may or may not comprise the [0043] According to another embodiment, an electron- same organic matrix material. If this embodiment is im- ic switching device comprising an organic field effect tran- plemented it is not necessary that the first and second 30 sistor is provided. organic semiconducting material comprise the same or- [0044] It is preferred that the first electrode, the second ganic matrix material. Each of the at least one first sub- electrode, and the electrode insulator are not permeable. electrode portion and the at least one second sub-elec- The first and second electrode as well as the electrode trode portion is separated from a respective adjacent insulator shall preferably be thick enough to form closed sub-electrode portion. Further, the at least one first sub- 35 layers. Preferentially, first and second electrode as well electrode portion and the at least one second sub-elec- as the electrode insulator are not interrupted or perforat- trode portion may have different widths. ed or randomly interrupted, but rather lithographically [0035] According to a preferred embodiment, a current patterned. Also, the electrode insulator does not allow path formed between the first and second electrodes via any substantial tunneling of charge carriers through it the first and second organic semiconducting layers is un- 40 under normal operating conditions. ipolar. Thus, the current through the layers is provided [0045] Several advantages are provided, for instance by only one type of charge carriers, namely electrons or the process allows for a reduction of overlap capacitanc- holes. es. Injection can be easily improved. Higher current den- [0036] In one preferred embodiment, the first and sec- sities are possible even at higher frequencies. In some ond organic semiconducting layers are made of a small 45 embodiments, the high current can be further increased molecule material. in asymmetrical devices by doping at least one of the [0037] In one preferred embodiment, the first and sec- contacts. The two photoresist layers comprising fluori- ond organic semiconducting layers are made of polymer- nated photoresist and/or conventional (non-fluorinated) ic materials. photoresist allows the precise and robust photolitho- [0038] In another preferred embodiment, the first and 50 graphic patterningof completely different types oforganic second organic semiconducting layers are in direct con- semiconducting materials without considerable affecting tact to each other. the organic semiconducting material. It enables the fab- [0039] According to a preferred embodiment, the sec- rication of complementary circuits (using n- and p-chan- ond organic semiconducting layer is provided between nel transistors). Also transistors can easily be made with the electrode insulator and the second electrode. 55 gain of 10 times, 20 times or higher than conventional [0040] In still a further embodiment, the second elec- planar field effect transistors having high on/off ratio of trode and at least one of the gate electrode and the first more than 105. electrode are opaque for light. This ensures that ambient [0046] Preferred p-type semiconductors for the first

5 9 EP 2 797 133 A1 10 and the second semiconducting layer and the first and comprise: second doping material layer (if provided as matt-ix/dopant system) are: pentacene, dinaphthothienothiophene - depositing the fluorin based photoresist over the (DNTT), further DNTT derivatives such as C10-DNTT (in semiconducting layer; general Cx-DNTT), Metal-Phthalocyanines 5 (Zn-- depositing the (non-fluorine based) photoresist over Pc,CuPc), perylenes such as Diindenoperylenes (DIP), the fluorin based photoresist layer; Tetrapropyl-tetraphenyl-diindenoperylene (P4-PH4- - illuminating (exposing) the fluorin and the non-fluorin DIP). Preferred n-type semiconductors for the first and based photoresit layer; the second semiconducting layer and the first and second - developing the non-fluorine based photoresist pat- doping material layer (if provided as matrix/dopant sys- 10 ter; tem) are: C60, C70, ZnPc, CuPc, F16CuPc, F4CuPc, - developing the fluorine based photoresist pattern; Diindenoperylenes (DIP). The matrix material in a doped - depositing an additional organic or inorganic layer layer can for example also be triphenyl-diamine (TPD), on top of the then patterned photoresist layer; 3-(N-Maleimidopropionyl)-biocytin (MPB), athophenan- - patterning the additional organic or inorganic layer throline (BPHEN), 2,4,7,9-tetraphenyl-1,10-phenanthro- 15 by lift-off of the fluorin based and non-fluorine based line (TPHEN), perylene-3,4,9,10-tetracarboxylie- photoresist. 3,4,9,10-dianhydride (PTCDA), naphthalene tetracar- boxylic acid di-anhydride (NTCDA) etc. Further, the ma- [0051] All steps can be done at atmospheric pressure. trix material can be a polymer, for example p-type materials like poly(3-hexylthiophen-2,5-diyl) (P3HT), DIPs- 20 Description of preferred embodiments of the invention pentacene, poly[2,5-bis(3-alkylthiophen-2-yl)thieno(3,2- b)thiophene] (PBTTT) or n-type materials like poly [0052] In the following the invention will be described {[N,N9-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(di- in further detail, by way of example, with reference to carboximide)-2,6-diyl]-alt-5,59-(2,29-bithiophene)} different embodiments. In the figures show: (P(NDI2OD-T2). 25 [0047] In another embodiment of the invention, a circuit Fig. 1 a schematic representation of a vertical organic is provided comprising: field effect transistor, Fig. 2 a schematic representation of another vertical - at least a n-type VOFET comprising a n-type material organic field effect transistor, and 30 Fig. 3 a schematic representation of a further vertical - at least a p-type VOFET comprising a p-type mate- organic field effect transistor, rial. Fig. 4 a schematic representation of an electrode configuration, [0048] Preferentially, the first and the second organic Fig. 5 a transfer characteristic line of a common ver- semiconducting layers consist each of one kind of sem- 35 tical organic field effect transistor, and iconducting material. Alternatively or in addition, layers Fig. 6 a transfer characteristic line of a common ver- forming the electrodes can be shared between the n-type tical organic field effect transistor according to and p-type VOFET. The polarity ot the VOFET may only the embodiment shown in Fig. 1. be chosen by the polarity of the dopant (p or n). In this case the DSC material of p- or n-type VOFET may then 40 [0053] Fig. 1 shows a schematic representation of a be the same. vertical organic field effect transistor which comprises [0049] For materials which growth layers with high several layers. The transistor comprises a gate electrode roughness (e.g. the roughness is of the order of the layer (1) on which a gate insulator (2) is deposited. A first or- thickness itself), such as pentacene, it is preferred to ganic semiconducting layer (3) is arranged on the gate keep the layers thin, preferably thinner than 60 nm, more 45 insulator (2). Further, a first electrode (4), an electrode preferably thinner than 40 nm. That ensures a good proc- insulator (5) and a second organic semiconducting layer essability. One aspect of the invention is to provide a dual (6) are provided. The first electrode (4) is arranged on a layer photoresist and a method using a dual layer pho- first doping material layer (13). A second electrode (7) is toresist for patterning organic semiconducting materials. arranged on a second doping material layer (14). The The dual layer photoresist is applied over a layer of an 50 transistor may be arranged on a substrate (not shown). organicsemiconducting material.The dual layer photore- [0054] Fig. 2 shows a schematic representation of an- sist consists of a layer of fluorine based photoresist, other transistor design. The transistor comprises also the which contacts the organic semiconducting material to gate electrode (1) with the gate insulator (2). The first be patterned, and a non-fluorine based photoresist. With organic semiconducting layer (3) is arranged on the gate that combination, it is possible to pattern the most differ- 55 insulator (2). The first electrode (4) is arranged on the ent kinds of organic semiconducting materials; non lim- first doping material layer (13). Further, the electrode in- iting examples are pentacene, C60, ZnPc, etc. sulator (5) and the second organic semiconducting layer [0050] The photolitographic patterning procedure may (6) are provided. On top of the transistor the second elec-

6 11 EP 2 797 133 A1 12 trode (7) is arranged on the second organic semicon- steps before the first organic semiconducting layer (3) is ducting layer (6). applied. Also the oxide layers and other gate dielectric [0055] Fig. 3 shows a schematic representation of a layers may be overcoated by an organic material, e.g. further vertical organic field effect transistor comprising SAM described in US 7,202,547 and US 7,208,782. Af- the gate electrode (1) with the gate insulator (2). Further, 5 terwards, a first photoresist layer is deposited on the first the first organic semiconducting layer (3), the first elec- organic semiconducting layer (3). The first photoresist trode (4) and the electrode insulator (5) are provided. layer comprises a special lacquer for protecting the or- The second doping material layer (14) is arranged on the ganic material of the first organic semiconducting layer second organic semiconducting layer (6). Finally, the (3). After illuminating and processing (patterning by re- second electrode (7) is provided. 10 moving the uncured portion) the first photoresist layer, [0056] Fig. 4 shows a schematic representation of an the first doping material layer (13) is deposited, for ex- electrode configuration. The first electrode (4) is provided ample by thermal evaporation. Then, a gold layer is vapor with first sub-electrode portions (8) and the second elec- deposited to provide the first (source) electrode (4). In a trode (7) is provided with second sub-electrode portions next step, the electrode insulator (5) is deposited. For (9). The plurality of sub-electrode portions (8, 9) are ar- 15 example, insulation is provided by a silicon dioxide layer ranged in separated groups of overlapping sub-electrode that is deposited on the first electrode (4) by magnetron portions (10). Each of the separated groups of overlap- sputtering. Non required parts of the first photoresist lay- ping sub-electrode portions (10) comprises at least one er, the first doping material layer (13), the first electrode first sub-electrode portion (8) overlapping with at least (4) and the electrode insulator (5) are removed in a lift- one second sub-electrode portion (9). The width (11) of 20 off process. A second photoresist layer is deposited, il- the first sub-electrode portions (8) is optimized to be as luminated and processed for structuring the second elec- small as possible to obtain the lowest possible capaci- trode (7). The second organic semiconducting layer (6) tance between the first and second electrode (4, 7) but which preferentially comprises the same matrix material large enough to collect the current which is limited by the as the first organic semiconducting layer (3) is deposited mobility of the charge carriers. Preferable ranges are be- 25 on the second photoresist layer. On the second organic tween 100m m and 1 mm or between 50 mm and 1 mm semiconducting layer (6) the second doping material lay- or between 20 and 0.5 mm A width (12) of the second er (14) is deposited. Following, the second (drain) elec- sub-electrode portions (9) is larger than the width (11) trode (7) is deposited on the second doping material layer and is optimized for lowest capacitance (source-drain ca- (14).Finally, non-requiredparts of the second photoresist pacitance) while large enough to not considerably limit 30 layer, the second organic semiconducting layer (6), the the current. Preferentially, portions (4.1) and (7.1) do not second doping material layer (14) and the second elec- overlap. Preferable ranges are also between 100 mm and trode (7) are removed in a lift-off process, defining layers 1 mm or between 50 mm and 1 mm or between 20 and (6), (7) and (14). The first and second organic semicon- 0.5 mm Preferentially, the sub-electrode portions (8, 9) ducting layer (3, 6) may be either electron transport lay- 35 are parallel to the each other (intra and inter-electrodes ers, comprising C 60,for example,or holetransport layers, parallelism), because that leads to the lowest series re- comprising pentacene, for example. sistance and highest overlap length (active area). The [0058] In one example, an n-Si wafer with a 25nm thick first and second sub-electrode portions (8, 9) can be at Al2O3layer (by ALD from Namlab) is used as substrate least partially arranged on the first and second doping and gate electrode and gate insulator. The wafer is material layer, respectively (not shown). 40 cleaned with isopropanol (IPA) in a supersonic bath for [0057] Following, a method for producing a transistor 5min and further ozone plasma etching for 10min. The is disclosed. At first, a gate electrode (1) made of silicon wafer is dipped in a solution of HMDS (Hexamethyldis- (serving at the same time as substrate) is provided which ilazane) for 30min for enhancing adherence of the organ- also serves as a substrate for following layers. Typical ic layer (this step is optional) with further spin rinsing IPA substrate materials are silicon, glass, polyethylene, other 45 (1000rpm, 30s). 25 nm of Pentacene is deposited on the common polymers for foils, gate materials: ITO, Pe- Al2O3 side, onto which a 1 mm thick layer of Ortho 310 dot:PSS, Al, all air stable metals like Mo, Ta, Ag, Au, Cu, from Orthogonal Inc. is spin coated at 30s, and 3000rpm. Al, Pa, Pl, carbon nanotubes, graphene. The gate elec- A second coating of Ma P 1210 from micro resist (30s, trode (1) may be doped. The gate electrode (1) is covered 3000rpm) follows on top of the Ortho 310 layer, forming with the gate insulator (2) which is applied to the gate 50 a double layer photo resists. Both photoresist are proc- electrode (1). The gate insulator (2) may be formed from essed under yellow light (lithography room), at 22°C. The a metal oxide, for example SiO2, Al2O3 and HfO2. The sample rests for 10 min under yellow light (lithography metal oxide can be evaporated by vacuum thermal evap- room), 22°C. oration (VTE), sputtered or deposited using atomic layer [0059] Using a mask aligner (finger grid, finger length deposition (ALD). Alternatively, the gate insulator (2) can 55 200 mm, lateral dimensions are 30 and 50mm), sample be made from a polymer like PVA, PVP or Cytop. Poly- is exposed (e.g. to a Mercury lamp i-line (365nm), dose mers can be printed, coated, dipped or evaporated. The 35mJ/cmF) for forming the source electrode for time=0.6s surface of the gate insulator (2) is cleaned in several and developed under yellow light (lithography room) at

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22°C in an aqueous solution of NaOH for 17s (NaOH for electrical insulation, solution as ordered from supplier (micro-resist) under the - depositing a second organic semiconducting acronym ma-D 331) for patterning the upper photoresist layer (6) on the first organic semiconducting lay- layer. er (3) and the electrode insulator (5), and [0060] Afterwards, the sample is dipped into HFE 7300 5 - generating a second electrode (7), for 3 minutes and 30 seconds with posterior rinsing in HFE7300 for 30 s (solvents from Orthogonal Inc.) for pat- wherein the method further comprises at least one terning the lower photoresist layer. of the following steps: [0061] A 1nm thick layer of F6TCNNQ is deposited by thermal evaporation serving as first doping material layer 10 - generating a first doping material layer (13) on for improving charge carrier injection. the first organic semiconducting layer (3) prior [0062] A 50nm thick layer of Au is deposited as first to generating the first electrode (4) and the elec- electrode using VTE. A 200 nm thick layer of HfO2 is trode insulator (5) such that the first electrode deposited by RF-sputtering. The patterning of the (4) with the electrode insulator (5) are generated Au/HfO2 is done by Lift-Off in HFE 7300 for 12h in a15 at least partially on the first doping material layer glovebox with nitrogen gas. (13), and [0063] A second photolithographic step follows, with - generating a second doping material layer (14) the spin coating of Ortho 310 at 30s and 3000rpm, and on the second organic semiconducting layer (6) posterior coating of Ma - P 1210 at 30s and 3000rpm prior to generating the second electrode (7) such (Yellow light, 22°C). The sample rests for 10 min. Again, 20 that the second electrode (7) is generated at using a mask aligner, the photoresist is exposed for 0.6s least partially on the second doping material lay- (Mercury lamp i-line (365nm), dose 35mJ/cm 2, finger grid er (14). (finger grid, finger length 200 mm, lateral dimensions are 30 and 50mm). The developing occurs in a solution of 2. The method according to claim 1, wherein at least NaOH (NaOH as ordered from supplier under the acro- 25 one of the step of generating the first electrode (4) nym ma-D 331, yellow light (lithography room), 22°C). and the electrode insulator (5), the step of generating The undeveloped photoresist is removed by dipping into the first doping material layer (13), the step of gen- HFE 7300 (3min 30s) and subsequent rinsing in HFE erating the second electrode (7) and the step of gen- 7300 for 30 s (solvents from Orthogonal Inc.). erating the second doping material layer (14) com- [0064] A 25 nm thick layer of Pentacene is deposited 30 prises a step of photo-lithographic structuring on the (VTE) on top, followed by a 1 nm thick layer of F6-TCNNQ first and the second organic semiconducting layer and a 50 nm thick layer of Au as second electrode. A lift (3, 6), respectively. off process, in HFE 7300 during 12 h in a glovebox with nitrogen gas (diffuse ambient light, 22°C), patterns the 3. The method according to claim 1 or 2, wherein the pentacene, the F6-TCNNQ and the Au layer. 35 first doping material layer (13) and /or the second [0065] Fig. 5 and6 showcharacteristic details ofa com- doping material layer (14) are generated by physical men VOFET (Fig. 5) and a transistor as shown in Fig. 1 vapour deposition. and described above. In Fig. 6, the current flow is signif- icantly higher than in Fig. 5. The ration between ON-cur- 4. The method according to one of the preceding rent and OFF-current for both transistors is 10 5. It is sur- 40 claims, wherein the first doping material layer (13) prising that the ON-current and OFF-current for both tran- and / or the second doping material layer (14) are sistors are similar despite the fact that the higher amount made of a pure electrical dopant material, respec- of free charge carriers in the VOFET due to doping should tively. increase the OFF-current. 45 5. The method according to one of the preceding claims, wherein the first doping material layer (13) Claims and / or the second doping material layer (14) comprise a matrix material including an electrical dopant 1. A method for producing an organic field effect tran- material, respectively. sistor, the method comprising steps of: 50 6. The method according to claim 5, wherein the matrix - providing a gate electrode (1) and a gate insu- material is an organic semiconducting material. lator (2) assigned to the gate electrode (1) for electrical insulation on a substrate, 7. The method according to one of the preceding - depositing a first organic semiconducting layer 55 claims, wherein the first and second organic semi- (3) on the gate insulator (2), conducting layers (3, 6) comprise the same organic - generating a first electrode (4) and an electrode matrix material. insulator (5) assigned to the first electrode (4)

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8. The method according to one of the preceding - removing the second photoresist pattern in a claims, wherein the first electrode (4) is generated lift-off process, thereby generating the second with first sub-electrode portions (8) and the second organic semiconducting layer (6) and the sec- electrode (7) is generated with second sub-electrode ond electrode (7). portions (9), the plurality of sub-electrode portions 5 (8, 9) being arranged in separated groups of over- 12. An organic field effect transistor, comprising: lapping sub-electrode portions (10), wherein each of the separated groups of overlapping sub-electrode - a first electrode (4) and a second electrode (7), portions (10) is generated with at least one first sub- the electrodes providing a source electrode and electrode portion (8) overlapping with at least one 10 a drain electrode, second sub-electrode portion (9). - a gate electrode (1), - a gate insulator (2) provided between the gate 9. The method according to claim 8, wherein the first electrode (1) and the first electrode (4), doping material layer (13) is generated such that the - an electrode insulator (5) provided between first sub-electrode portions (8) are at least partially 15 the first and the second electrode (4, 7), in direct contact with the first doping material layer - a first organic semiconducting layer (3) provid- (13) and / or the second doping material layer (14) ed between the gate insulator (2) and the first is generated such that the second sub-electrode por- electrode (4), tions (9) are at least partially in direct contact with - a second organic semiconducting layer (6) pro- the second doping material layer (14). 20 vided between the first organic semiconducting layer (3) and the second electrode (7), and 10. The method according to one of the preceding claims, wherein the step of generating the first elec- at least one of the following layers: trode (4) and the electrode insulator (5) comprises steps of: 25 - a first doping material layer (13) which is provided between the first electrode (4) and the first - depositing a first photoresist layer on the first organic semiconducting layer (3) and which is organic semiconducting layer (3) and /or on the at least partially in direct contact with the first first doping material layer (13), if applicable, electrode (4), and - defining an electrode area for the first electrode 30 - a second doping material layer (14) which is (4)by patterningthe firstphotoresist layer, there- provided between the second electrode (7) and by providing a first photoresist pattern, the second organic semiconducting layer (6) - depositing a first conductive layer on the first and which is at least partially in direct contact photoresist pattern, with the second electrode (7). - depositing an insulating layer on the first con- 35 ductive layer, and 13. Transistor according to claim 12, wherein the first - removing the first photoresist pattern in a lift- and second organic semiconducting layers (3, 6) are off process, thereby generating the first elec- configured to transport charge carriers of the same trode (4) and the electrode insulator (5). type, namely holes and electrons. 40 11. The method according to one of the preceding 14. Transistor according to claim 12 or 13, wherein the claims, wherein the step of generating the second first electrode (4) is provided with first sub-electrode electrode (7) comprises steps of: portions (8) and the second electrode (7) is provided with second sub-electrode portions (9), the plurality - depositing a second photoresist layer on the 45 of sub-electrode portions (8, 9) being arranged in first organic semiconducting layer (3), on the separated groups of overlapping sub-electrode por- electrode insulator (5), and on the second dop- tions (10), wherein each of the separated groups of ing material layer (14), if applicable, overlapping sub-electrode portions (10) comprises - defining an electrode area for the second elec- at least one first sub-electrode portion (8) overlap- trode (7) by patterning the second photoresist 50 ping with at least one second sub-electrode portion layer, thereby providing a second photoresist (9). pattern, - depositing a second unpatterned organic sem- 15. Transistor according to claim 14, wherein the first iconducting layer on the second photoresist pat- doping material layer (13) is at least partially in direct tern, 55 contact with the first sub-electrode portions (8) and - depositing a second conductive layer on the / or the second doping material layer (14) is at least second unpatterned organic semiconducting partially in direct contact with the second sub-elec- layer, and trode portions (9).

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16. Electronic switching device, comprising an organic field effect transistor according to one of the claims 12 to 15.

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• WO 2010113163 A1 [0004] • US 2009179189 A [0042] • WO 2011139774 A [0005] • US 7202547 B [0057] • US 2005040390 A1 [0042] • US 7208782 B [0057]

Non-patent literature cited in the description

• K. NAKAMURA et al. Applied Physics Letters, 2006, • D’ANDRADE et al. App. Phys. Let., 2003, vol. 83, vol. 89, 103525 [0006] 3858 [0042] • GAO et al. Appl. Phys. Lett., 2001, vol. 79, 4040 • WALZER et al. Chem. Rev., 2007, vol. 107, 1233 [0042] [0042] • BLOCHWITZ et al. Appl. Phys. Lett., 1998, vol. 73, 729 [0042]