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Product Assurance Technology for Custom LSI/VLS! Electronics Report for Period: October 1982 September 1984 JPL PUBLICATION 85-76 [N_SA-CR- 177167) PRO£UCT _SSU_NCE N86-29255 IECHNOLOGY FOR C_F_OM ISI/_ISI F IEC_RONICS THRU _xternal _eport, Cot. 1982- Se_. 1984 ._Jet N86-29265 P[opulsion La£.) 218 _ CSCL 14D Unclas G3/38 43197 Product Assurance Technology for Custom LSI/VLS! Electronics Report for Period: October 1982 September 1984 M.G. Buehler B.R. Blaes G.A. Jennings B.T. Moore R.H. Nixon C.A. Pina H.R. Sayah M.W. Sievers N.F. Stahlberg June 1'985 Prepared for National Aeronautics and Space Administration, Defense Advanced Research Projects Agency, and 2,,. U.S. Department of Defense / by Jet Propulsion Laboratory California Institute of Technology Pasadena, California JPL PUBLICATION 85-76 Product Assurance Technology for Custom LSI/VLSI Electronics Report for Period: October 1982 - September 1984 M.G. Buehler B.R. Blaes G.A. Jennings B.T. Moore R.H. Nixon C.A. Pina H.R. Sayah M.W. Sievers N.F. Stahlberg June 1985 Prepared for National Aeronautics and Space Administration, Defense Advanced Research Projects Agency, and U.S. Department of Defense by Jet Propulsion Laboratory California Institute of Technology Pasadena, California The research described in this publication was carried out by the Jet Propul- sion Laboratory, California Institute of Technology, and was sponsored by the Defense Advanced Research Projects Agency, the U.S. Department of Defense, and the National Aeronautics and Space Administration. ABSTRACT The work described in this report represents the collaborative efforts of integrated-circuit (IC) parts specialists, device physicists, test-chip engineers, and fault-tolerant-circuit designers. Their efforts were focused on developing the technology for obtaining custom ICs from CMOS-bulksilicon foundries using a universal set of layout rules. In pursuit of this goal the technical efforts were guided by the requirement to develop a 3-pm CMOStest chip for the CombinedRelease and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits for characterizing the space- radiation-induced shifts in CMOStransistor parameters and inverter propaga- tion delays, and for characterizing the single-event-upset (SEU) rates of static randomaccess memories (SRMs). The development employed all the ele- ments required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification. The technical accomplishments of this effort include: (a) A critical review of the military IC qualification standards. The review indicated that many of these standards are not applicable to the procurement of custom ICs. (b) An assessment of the test time and area required by CMOS-bulk test structures that are to be included in parameter extraction and yield analysis test chips. (c) The development of a MOSFET parameter extraction procedure, called JMOSFIT, which allows the extraction of physically meaningful parameters for a SPICE-like circuit simulator. (d) The fault modeling of pinhole-array-capacitor defects in terms of a gate-to-silicon resistive short that terminates in an n-diffusion pocket in the silicon. (e) The time response analysis of CMOS gates (inverters, NAN, s, NORs, and flip-flops) for various resistive shorts which indicates the resistive values needed to cause a faulty response. (f) The development of a CMOS-bulk test chip for CRRES. iii CO_E_S . INTRODUCTION • • . • . • . • • • • • . • • • . I-i i.i OVERVIEW ........................ I-I 1.2 REFERENCES ....................... 1-2 TECHNICAL ACCOMPLISHMENTS .................... 2-1 WAFER ACCEPTANCE PROCEDURES ................... 2-2 2.1.1. Basis for Evaluation of Current Qualification Procedures ....................... 2-2 2.1.2. Review and Evaluation of Military Qualification Procedures ....................... 2-4 2.1.3. Conclusions ...................... 2-21 2.1.4. Prototype Wafer Acceptance Requirements ........ 2-22 2.1.5. References ....................... 2-27 2.2. TEST CHIPS ........................... 2-30 2.2.1. CMOS-Bulk Critical Parameter Set ............ 2-31 2.2.2. Catalog of CMOS Critical Parameters and Test Structures .................... 2-36 2.3. TEST STRUCTURES ......................... 2-45 2.3.1 ................. = ^- r zNttoz_ nLL_y _tuL -9--AA,_ 2.3.2. Contact-Resistance Process Cliff ............ 2-63 2.3.3. Addressable Inverter Matrix .............. 2-68 2.3.4. Reliability Analysis .................. 2-77 2.3.5. Inverter Noise Margin Analysis ............. 2-94 2.3.6. JMOSFIT--A M0SFET Parameter Extractor with Geometry-Dependent Terms ............... 2-101 2._. TEST CHIP METHODOLOGY ...................... 2-142 2.4.1. 1.2-pm CMOS Technology ................. 2-143 2.4.2. 3-pm CMOS Technology .................. 2-144 2.4.3. 3-pm CMOS-Bulk Test Chips ............... 2-146 v PRECEDING PAGE BLANK rqOT F_.__,;,,I!.I_ 2.4.4. Test Chip Assembler and Test Program Generator ..... 2-153 2.4.5. Statistical Analysis Package Capability ........ 2-154 2.5. FAULT MODELS .......................... 2-159 2.5.1. Open-Gate Transistors and Faulted Gates ........ 2-160 2.5.2. MOS Integrated Circuit Fault Modeling ......... 2-165 2-206 2.6. CRRES CHIP ........................... 2.6.1. Random Access Memory (RAM) ............... 2-207 2.6.2. Transistor Matrix ................... 2-208 2.6.3. Timing Sampler and Ring Oscillator ........... 2-210 2.6.4. Chip Fabrication History ................ 2-214 2.6.5. Chip Requirements and Plans for CRRES ......... 2-214 2.6.6. References ....................... 2-215 3-1 . DISCUSSION AND PLANS ...................... 3.1 OVERVIEW ........................ 3-1 3.2 REFERENCES ....................... 3-2 vi Figures 2.1-1. Wafer acceptance flow diagram .............. 2-29 2.2.1-1. Test structures for checking various CMOS-bulk layout rules ....................... 2-33 2.3.1-1. Transistor-level description of the Pinhole Array Capacitor ........................ 2-49 2.3.1-2. Poly-bulk shorts for an n-channel Pinhole Array Capacitor fabricated with a 1.2-pm CMOS process ..... 2-50 2.3.1-3. Poly-bulk shorts for a p-channel Pinhole Array Capacitor fabricated with a 1.2-pm CMOS process .... 2-51 2.3.1-4. Origin of oxide pinholes in a CMOS local oxidation process where silicon nitride is used to define the thin oxide regions .................. 2-52 2.3.1-5. Two types of Pinhole Array Capacitor defects ....... 2-53 2.3.2-1. Metal-n-diffusion contact-resistance process cliff .... 2-65 2.3.2-2. Metal-p-diffusion contact-resistance process cliff .... 2-65 2.3.2-3. Metal-n-poly contact-resistance process cliff ...... 2-66 2.3.2-4. Metal-p-poly contact-resistance process cliff ...... 2-66 2.3.4-1. Electrical test of radiation hardness .......... 2-84 2.3.4-2. C-V shift vs injection .................. 2-85 2.3.4-3. Comparison of radiation vs _q injection ......... 2-86 2.3.4-4. Impact ionization measurements apparatus ......... 2-87 2.3.4-5. Impact ionization coefficient for electrons ....... 2-88 2.3.4-6. Hot-electron effects for an n-channel transistor biased in a conducting state ............... 2-89 2.3.4-7. Isu b and IG as functions of the gate voltage V G ..... 2-90 2.3.4-8. Hot-electron effects measurement apparatus ........ 2-91 2.3.4-9. TDDB test structures ................... 2-92 2.3.4-10. TDDB test chip ...................... 2-93 2.3.5-1. The number of inverters per circuit where the probability is 50 percent that all the inverters are with the design window, 2_M, and centered within X2 of the d_ign center_ Mc, for G = infinity ...... 2-96 vii 2.3.5-2. Inverter noise margin as derived from the maximum square method and illustrated for four cases ....... 2-97 2.3.5-3. Inverter noise margin dependence on the inverter threshold voltage and gain ................ 2-98 MOSFET dimensional definitions .............. 2-124 MOSFET short-channel effect due to source and drain bulk charge stealing (cross-hatched regions) .... 2-125 2.3.6-3a. MOSFET narrow-channel effect where additional bulk charge (cross-hatched regions) appears beneath the gate with the conventional oxide process . 2-126 2.3.6-3b. MOSFET narrow-channel effect where additional bulk charge (cross-hatched regions) appears beneath the gate with the recessed oxide process ..... 2-126 2.3.6-4. Graphical representation of the channel carrier velocity dependence on electric field .......... 2-127 MOSFET with source and drain series resistance ...... 2-128 The transistor channel width-length plane where the relative threshold voltage values expected from classical short and narrow channel effects are indicated within the boxes for the four transistors used in the 1.2-pm parameter extraction 2-128 2.3.6-7. Individual fitting of four 1.2-pm CMOS n-channel transistor drain current curves for VB = 0 ........ 2-129 2.3.6-8. Individual fitting of four 1.2-pm CMOS n-channel transistor drain current curves for VB = -2.5 volts 2-130 2.3.6-9. Global fitting of four 1.2-pm CMOS n-channel transistor drain current curves for VB = 0 ........ 2-131 2.3.6-10. Global fitting of four 1.2-pm CMOS n-channel transistor drain current curves for VB = -2.5 volts 2-132 2.4.3-1. Test chip CM5031 (area = 6.0 mm x 6.4 mm) ........ 2-148 2.4.3-2. Test chip CM5041 (area = 7.2 mm x 8.0 mm) ........ 2-149 2.4.5-1. Sheet resistance (ohms/square) wafer map for n + poly layer measured from a split-cross-bridge resistor .... 2-157 2.4.5-2. Logarithmic wafer map for the data shown in Figure 2.4.5-I ...................... 2-158 2.5.1-1. Layout of the addressable NAND gate matrix, a normal gate, and a gate with an open pull-up transistor ........ 2-161 viii 2.5.2-1. Inverter ......................... 2-175 2.5.2-2. NORgate ......................... 2-175 2.5.2-3. NANDgate ........................ 2-176 2.5.2-4. Static flip-flop ....................
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