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Fibre Channel Interface
Fibre Channel Interface Fibre Channel Interface ©2006, Seagate Technology LLC All rights reserved Publication number: 100293070, Rev. A March 2006 Seagate and Seagate Technology are registered trademarks of Seagate Technology LLC. SeaTools, SeaFONE, SeaBOARD, SeaTDD, and the Wave logo are either registered trade- marks or trademarks of Seagate Technology LLC. Other product names are registered trade- marks or trademarks of their owners. Seagate reserves the right to change, without notice, product offerings or specifications. No part of this publication may be reproduced in any form without written permission of Seagate Technol- ogy LLC. Revision status summary sheet Revision Date Writer/Engineer Sheets Affected A 03/08/06 C. Chalupa/J. Coomes All iv Fibre Channel Interface Manual, Rev. A Contents 1.0 Contents . i 2.0 Publication overview . 1 2.1 Acknowledgements . 1 2.2 How to use this manual . 1 2.3 General interface description. 2 3.0 Introduction to Fibre Channel . 3 3.1 General information . 3 3.2 Channels vs. networks . 4 3.3 The advantages of Fibre Channel . 4 4.0 Fibre Channel standards . 5 4.1 General information . 6 4.1.1 Description of Fibre Channel levels . 6 4.1.1.1 FC-0 . .6 4.1.1.2 FC-1 . .6 4.1.1.3 FC-1.5 . .6 4.1.1.4 FC-2 . .6 4.1.1.5 FC-3 . .6 4.1.1.6 FC-4 . .7 4.1.2 Relationship between the levels. 7 4.1.3 Topology standards . 7 4.1.4 FC Implementation Guide (FC-IG) . 7 4.1.5 Applicable Documents . -
AMD Opteron™ Shared Memory MP Systems Ardsher Ahmed Pat Conway Bill Hughes Fred Weber Agenda
AMD Opteron™ Shared Memory MP Systems Ardsher Ahmed Pat Conway Bill Hughes Fred Weber Agenda • Glueless MP systems • MP system configurations • Cache coherence protocol • 2-, 4-, and 8-way MP system topologies • Beyond 8-way MP systems September 22, 2002 Hot Chips 14 2 AMD Opteron™ Processor Architecture DRAM 5.3 GB/s 128-bit MCT CPU SRQ XBAR HT HT HT 3.2 GB/s per direction 3.2 GB/s per direction @ 0+]'DWD5DWH @ 0+]'DWD5DWH 3.2 GB/s per direction @ 0+]'DWD5DWH HT = HyperTransport™ technology September 22, 2002 Hot Chips 14 3 Glueless MP System DRAM DRAM MCT CPU MCT CPU SRQ SRQ non-Coherent HyperTransport™ Link XBAR XBAR HT I/O I/O I/O HT cHT cHT cHT cHT Coherent HyperTransport ™ cHT cHT I/O I/O HT HT cHT cHT XBAR XBAR CPU MCT CPU MCT SRQ SRQ HT = HyperTransport™ technology DRAM DRAM September 22, 2002 Hot Chips 14 4 MP Architecture • Programming model of memory is effectively SMP – Physical address space is flat and fully coherent – Far to near memory latency ratio in a 4P system is designed to be < 1.4 – Latency difference between remote and local memory is comparable to the difference between a DRAM page hit and a DRAM page conflict – DRAM locations can be contiguous or interleaved – No processor affinity or NUMA tuning required • MP support designed in from the beginning – Lower overall chip count results in outstanding system reliability – Memory Controller and XBAR operate at the processor frequency – Memory subsystem scale with frequency improvements September 22, 2002 Hot Chips 14 5 MP Architecture (contd.) • Integrated Memory Controller -
Architecture and Application of Infortrend Infiniband Design
Architecture and Application of Infortrend InfiniBand Design Application Note Version: 1.3 Updated: October, 2018 Abstract: Focusing on the architecture and application of InfiniBand technology, this document introduces the architecture, application scenarios and highlights of the Infortrend InfiniBand host module design. Infortrend InfiniBand Host Module Design Contents Contents ............................................................................................................................................. 2 What is InfiniBand .............................................................................................................................. 3 Overview and Background .................................................................................................... 3 Basics of InfiniBand .............................................................................................................. 3 Hardware ....................................................................................................................... 3 Architecture ................................................................................................................... 4 Application Scenarios for HPC ............................................................................................................. 5 Current Limitation .............................................................................................................................. 6 Infortrend InfiniBand Host Board Design ............................................................................................ -
Towards User-Tailored Creative Applications of Concatenative Synthesis in Electronic Dance Music
MUME 2016 - The Fourth International Workshop on Musical Metacreation, ISBN #978-0-86491-397-5 Towards User-Tailored Creative Applications of Concatenative Synthesis in Electronic Dance Music Carthach´ O´ Nuanain,´ Sergi Jorda,` Perfecto Herrera Music Technology Group Universitat Pompeu Fabra Barcelona [email protected] Abstract speech synthesis (Hunt and Black 1996), where the descrip- tions need to be extremely accurate in producing effective The ecosystem of concatenative synthesis systems is reconstructions of natural speech. Music tends to be a bit large, diverse and oftentimes esoteric. In this article, more forgiving. Indeed, depending on the goals of the com- we examine many of its key works, attempting to poser, accuracy is not always the intended thought in mind. summarise, compare and categorise their characteristic traits. We observe that many existing systems have not Informally, we begin with some music, we deconstruct it, taken into account any user other than the designer of we describe it symbolically using some numerical descrip- the system. Subsequently we position our own imple- tors and then put it back together in some new form. It is mentation in this ecosystem as geared specifically with related to granular synthesis (Roads 2004), but operates on electronic dance music producers in mind. Through in- longer, more descriptive orders of scale. tensive discussion with producers and commercial mu- In the next section we present a summary of many of the sic software practitioners we summarise their reactions, concatenative synthesisers presented in the literature. Some responses and impressions to the usability and musical- are scarcely described, some are fully-formed commercial ity of this approach to music creation. -
Chapter 6 MIDI, SCSI, and Sample Dumps
MIDI, SCSI, and Sample Dumps SCSI Guidelines Chapter 6 MIDI, SCSI, and Sample Dumps SCSI Guidelines The following sections contain information on using SCSI with the K2600, as well as speciÞc sections dealing with the Mac and the K2600. Disk Size Restrictions The K2600 accepts hard disks with up to 2 gigabytes of storage capacity. If you attach an unformatted disk that is larger than 2 gigabytes, the K2600 will still be able to format it, but only as a 2 gigabyte disk. If you attach a formatted disk larger than 2 gigabytes, the K2600 will not be able to work with it; you could reformat the disk, but thisÑof courseÑwould erase the disk entirely. Configuring a SCSI Chain Here are some basic guidelines to follow when conÞguring a SCSI chain: 1. According to the SCSI SpeciÞcation, the maximum SCSI cable length is 6 meters (19.69 feet). You should limit the total length of all SCSI cables connecting external SCSI devices with Kurzweil products to 17 feet (5.2 meters). To calculate the total SCSI cable length, add the lengths of all SCSI cables, plus eight inches for every external SCSI device connected. No single cable length in the chain should exceed eight feet. 2. The Þrst and last devices in the chain must be terminated. There is a single exception to this rule, however. A K2600 with an internal hard drive and no external SCSI devices attached should have its termination disabled. If you later add an external device to the K2600Õs SCSI chain, you must enable the K2600Õs termination at that time. -
Application Note 904 an Introduction to the Differential SCSI Interface
DS36954 Application Note 904 An Introduction to the Differential SCSI Interface Literature Number: SNLA033 An Introduction to the Differential SCSI Interface AN-904 National Semiconductor An Introduction to the Application Note 904 John Goldie Differential SCSI Interface August 1993 OVERVIEW different devices to be connected to the same daisy chained The scope of this application note is to provide an introduc- cable (SCSI-1 and 2 allows up to eight devices while the pro- tion to the SCSI Parallel Interface and insight into the differ- posed SCSI-3 standard will allow up to 32 devices). A typical ential option specified by the SCSI standards. This applica- SCSI bus configuration is shown in Figure 1. tion covers the following topics: WHY DIFFERENTIAL SCSI? • The SCSI Interface In comparison to single-ended SCSI, differential SCSI costs • Why Differential SCSI? more and has additional power and PC board space require- • The SCSI Bus ments. However, the gained benefits are well worth the addi- • SCSI Bus States tional IC cost, PCB space, and required power in many appli- • SCSI Options: Fast and Wide cations. Differential SCSI provides the following benefits over single-ended SCSI: • The SCSI Termination • Reliable High Transfer Rates — easily capable of operat- • SCSI Controller Requirements ing at 10MT/s (Fast SCSI) without special attention to termi- • Summary of SCSI Standards nations. Even higher data rates are currently being standard- • References/Standards ized (FAST-20 @ 20MT/s). The companion Application Note (AN-905) focuses on the THE SCSI INTERFACE features of National’s new RS-485 hex transceiver. The The Small Computer System Interface is an ANSI (American DS36BC956 specifically designed for use in differential SCSI National Standards Institute) interface standard defining a applications is also optimal for use in other high speed, par- peer to peer generic input/output bus (I/O bus). -
Serial Attached SCSI (SAS) Interface Manual
Users Guide Serial Attached SCSI (SAS) Interface Manual Users Guide Serial Attached SCSI (SAS) Interface Manual ©2003, 2004, 2005, 2006 Seagate Technology LLC All rights reserved Publication number: 100293071, Rev. B May 2006 Seagate, Seagate Technology, and the Seagate logo are registered trademarks of Seagate Technology LLC. SeaTools, SeaFAX, SeaFONE, SeaBOARD, and SeaTDD are either registered trademarks or trade- marks of Seagate Technology LLC. Other product names are registered trademarks or trademarks of their owners. Seagate reserves the right to change, without notice, product offerings or specifications. No part of this publication may be reproduced in any form without written permission of Seagate Technology LLC. Revision status summary sheet Revision Date Writers/Engineers Notes Rev. A 11/11/04 J. Coomes Initial release. Rev. B 05/07/06 C. Chalupa, J. Coomes, G. Houlder All. Contents 1.0 Interface requirements. 1 1.1 Acknowledgements . 1 1.2 How to use this interface manual . 1 1.2.1 Scope . 2 1.2.2 Applicable specifications . 2 1.2.3 Other references . 3 1.3 General interface description. 3 1.3.1 Introduction to Serial Attached SCSI Interface (SAS) . 3 1.3.2 The SAS interface . 3 1.3.3 Glossary . 5 1.3.4 Keywords . 16 1.4 Physical interface characteristics. 17 1.5 Bit and byte ordering . 17 2.0 General . 19 2.1 Architecture . 19 2.1.1 Architecture overview . 19 2.1.2 Physical links and phys . 19 2.1.3 Ports (narrow ports and wide ports) . 20 2.1.4 SAS devices . 21 2.1.5 Expander devices (edge expander devices and fanout expander devices) . -
EMC’S Perspective: a Look Forward
The Performance Impact of NVM Express and NVM Express over Fabrics PRESENTATION TITLE GOES HERE Live: November 13, 2014 Presented by experts from Cisco, EMC and Intel Webcast Presenters J Metz, R&D Engineer for the Office of the CTO, Cisco Amber Huffman, Senior Principal Engineer, Intel Steve Sardella , Distinguished Engineer, EMC Dave Minturn, Storage Architect, Intel SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA unless otherwise noted. Member companies and individual members may use this material in presentations and literature under the following conditions: Any slide or slides used must be reproduced in their entirety without modification The SNIA must be acknowledged as the source of any material used in the body of any document containing material from these presentations. This presentation is a project of the SNIA Education Committee. Neither the author nor the presenter is an attorney and nothing in this presentation is intended to be, or should be construed as legal advice or an opinion of counsel. If you need legal advice or a legal opinion please contact your attorney. The information presented herein represents the author's personal opinion and current understanding of the relevant issues involved. The author, the presenter, and the SNIA do not assume any responsibility or liability for damages arising out of any reliance on or use of this information. NO WARRANTIES, EXPRESS OR IMPLIED. USE AT YOUR OWN RISK. 3 What This Presentation Is A discussion of a new way of talking to Non-Volatile -
SCSI Interface Hard Disk Drives Stock Nos
SCSI Interface Hard Disk Drives Stock Nos. 192-0472 and 192-0488 Installation Orientation Figure 1. The drive may be installed in one of three orientations; either PCB down or on either edge. Inclination from vertical or horizontal should not exceed 5¡. Mounting screw fixing Figure 2. When the mounting screw holes on the side of the drive are used, then use only the two pairs of outer holes. Do not use the centre holes in conjunction with only one of the outer holes. The screw must not penetrate the drive by more than 4 millimetres. Grounding Sufficient grounding will be provided for correct operation when the drive is screwed into an electrically grounded frame. Cooling Figure 3. Allow space above and below the drive to provide for adequate air flow. Fan cooling is recommended. The disk enclosure temperature, measured at top centre, should A never exceed 60¡C. Termination A. Temperature measurement point A terminating resistor should be installed at both ends of the SCSI bus. When shipped from the factory, this drive is terminated. If the drive is to be used in the middle of the SCSI cable with other terminated devices at the ends, or if external termination is to be used, then the terminating resistor pack on the drive must be removed. Signal Pin Pin Signal GROUND 1 2 -DB0 GROUND 3 4 -DB1 GROUND 5 6 -DB2 GROUND 7 8 -DB3 GROUND 9 10 -DB4 GROUND 11 12 -DB5 GROUND 13 14 -DB6 GROUND 15 16 -DB7 GROUND 17 18 -DBP GROUND 19 20 GROUND GROUND 21 22 GROUND Reserved 23 24 Reserved Open 25 26 TERMPWR Reserved 27 28 Reserved GROUND 29 30 GROUND -
Troubleshooting the DM-80-R and SCSI Drives
® Supplemental S-760 Clinic ®ÂØÒňΠNotes May 10, 1996 “The Roland S-760 Demystified” AS SEEN IN KEYBOARD MAGAZINE The S-760 Digital Sampler is probably one of the most complex musical instruments Roland has ever designed. Because of this, sampler novices and in some cases hardcore sampler users find the S-760 difficult to grasp. Unfortunately for the new user, the manual that comes with the S-760 is more for reference than for basic instruction. So a lot of musicians who are new to Roland’s architecture are likely to be confused by the rudiments of Roland samplers and miss out on the S-760’s power and flexibility. Even though the S-760 can be used from the front panel, its real muscle comes from the CRT and mouse interface. In this article I’ve focused on using this more than the front panel. If you don’t have the OP-760 option board, don’t panic: We’ll cover some front-panel editing as well. 700 Series Architecture Before we can get into instructions on how to use the S-760, it is crucial that you get an idea of the Roland Sampler architecture. As on all samplers, the most basic unit in the S-760’s architecture is the sample. A sample on the S-760 can not be played multimbrally over MIDI until it is placed into a Partial, that Partial is assigned to a Patch, and the Patch is assigned to a part in a Performance. Luckily there are some shortcuts to creating Patches and Performances, as we’ll see. -
Comparing Fibre Channel, Serial Attached SCSI (SAS) and Serial ATA (SATA)
Comparing Fibre Channel, Serial Attached SCSI (SAS) and Serial ATA (SATA) by Allen Hin Wing Lam Bachelor ofElectrical Engineering Carleton University 1996 PROJECT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF ENGINEERING In the School ofEngineering Science © Allen Hin Wing Lam 2009 SIMON FRASER UNIVERSITY Fall 2009 All rights reserved. However, in accordance with the Copyright Act ofCanada, this work may be reproduced, without authorization, under the conditions for Fair Dealing. Therefore, limited reproduction ofthis work for the purposes ofprivate study, research, criticism, review and news reporting is likely to be in accordance with the law, particularly ifcited appropriately. Approval Name: Allen Hin Wing Lam Degree: Master ofEngineering Title ofProject: Comparing Fibre Channel, Serial Attached SCSI (SAS) and Serial ATA (SATA) Examining Committee: Chair: Dr. Daniel Lee Chair ofCommittee Associate Professor, School ofEngineering Science Simon Fraser University Dr. Stephen Hardy Senior Supervisor Professor, School ofEngineering Science Simon Fraser University Jim Younger Manager, Product Engineering PMC- Sierra, Inc. Date ofDefence/Approval r 11 SIMON FRASER UNIVERSITY LIBRARY Declaration of Partial Copyright Licence The author, whose copyright is declared on the title page of this work, has granted to Simon Fraser University the right to lend this thesis, project or extended essay to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response -
Connecting Time and Timbre Computational Methods for Generative Rhythmic Loops Insymbolic and Signal Domainspdfauthor
Connecting Time and Timbre: Computational Methods for Generative Rhythmic Loops in Symbolic and Signal Domains Cárthach Ó Nuanáin TESI DOCTORAL UPF / 2017 Thesis Director: Dr. Sergi Jordà Music Technology Group Dept. of Information and Communication Technologies Universitat Pompeu Fabra, Barcelona, Spain Dissertation submitted to the Department of Information and Communication Tech- nologies of Universitat Pompeu Fabra in partial fulfillment of the requirements for the degree of DOCTOR PER LA UNIVERSITAT POMPEU FABRA Copyright c 2017 by Cárthach Ó Nuanáin Licensed under Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 Music Technology Group (http://mtg.upf.edu), Department of Information and Communication Tech- nologies (http://www.upf.edu/dtic), Universitat Pompeu Fabra (http://www.upf.edu), Barcelona, Spain. III Do mo mháthair, Marian. V This thesis was conducted carried out at the Music Technology Group (MTG) of Universitat Pompeu Fabra in Barcelona, Spain, from Oct. 2013 to Nov. 2017. It was supervised by Dr. Sergi Jordà and Mr. Perfecto Herrera. Work in several parts of this thesis was carried out in collaboration with the GiantSteps team at the Music Technology Group in UPF as well as other members of the project consortium. Our work has been gratefully supported by the Department of Information and Com- munication Technologies (DTIC) PhD fellowship (2013-17), Universitat Pompeu Fabra, and the European Research Council under the European Union’s Seventh Framework Program, as part of the GiantSteps project ((FP7-ICT-2013-10 Grant agreement no. 610591). Acknowledgments First and foremost I wish to thank my advisors and mentors Sergi Jordà and Perfecto Herrera. Thanks to Sergi for meeting me in Belfast many moons ago and bringing me to Barcelona.