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Efficient Implementation of Elliptic Curve Cryptography in Reconfigurable Hardware

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Efficient Implementation of Elliptic Curve Cryptography in Reconfigurable Hardware EFFICIENT IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOGRAPHY IN RECONFIGURABLE HARDWARE by E-JEN LIEN Submitted in partial fulfillment of the requirements for the degree of Master of Science Thesis Advisor: Dr. Swarup Bhunia Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY May, 2012 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of _____________________________________________________E-Jen Lien candidate for the ______________________degreeMaster of Science *. Swarup Bhunia (signed)_______________________________________________ (chair of the committee) Christos Papachristou ________________________________________________ Frank Merat ________________________________________________ ________________________________________________ ________________________________________________ ________________________________________________ (date) _______________________03/19/2012 *We also certify that written approval has been obtained for any proprietary material contained therein. To my family ⋯ Contents List of Tables iii List of Figures v Acknowledgements vi List of Abbreviations vii Abstract viii 1 Introduction 1 1.1 Research objectives . .1 1.2 Thesis Outline . .3 1.3 Contributions . .4 2 Background and Motivation 6 2.1 MBC Architecture . .6 2.2 Application Mapping to MBC . .7 2.3 FPGA . .9 2.4 Mathematical Preliminary . 10 2.5 Elliptic Curve Cryptography . 10 2.6 Motivation . 16 i 3 Design Principles and Methodology 18 3.1 Curves over Prime Field . 18 3.2 Curves over Binary Field . 25 3.3 Software Code for ECC . 31 3.4 RTL code for FPGA design . 31 3.5 Input Data Flow Graph (DFG) for MBC . 31 4 Implementation of ECC 32 4.1 Software Implementation . 32 4.1.1 Prime Field . 33 4.1.2 Binary Field . 34 4.2 Implementation in FPGA . 35 4.2.1 Prime Field . 36 4.2.2 Binary Field . 40 4.3 Implementation in MBC . 44 4.3.1 Prime Field . 45 4.3.2 Binary Field . 47 5 Test Results 48 5.1 Test Patterns and Methodology . 49 5.2 Test Results . 50 6 Conclusion and Future Work 56 A Simulation Results 58 A.1 Prime field . 58 A.2 Binary field . 59 Bibliography 61 ii List of Tables 2.1 Instruction set . .8 5.1 Number of each operation from the data provided by NIST . 50 5.2 Number of each operation in GF (p) from the data provided by NIST 50 5.3 Number of each operation in GF (2m) from the data provided by NIST 50 5.4 Power, Performance and Size Comparison . 50 5.5 The Comparison of 192 bit Point Multiplication in different Paper . 54 5.6 The Comparison of 192 bit Scalar Multiplication in different Paper . 54 5.7 The Comparison of Point Multiplication in different Papers . 55 iii List of Figures 1.1 2011 ITRS ASIC Scaling trend prediction . .2 2.1 Memory Logic Block Diagram . .7 3.1 Squaring in Binary Field . 31 4.1 ECC hardware addition module . 36 4.2 ECC hardware subtraction module . 37 4.3 ECC hardware Montgomery module . 38 4.4 ECC hardware Inversion module . 39 4.5 ECC hardware Point Addition module . 40 4.6 ECC hardware Point Doubling module . 41 4.7 ECC hardware kp module . 42 4.8 ECC hardware Right-to-left Shift-and-Add Multiply module . 42 4.9 Modified ECC hardware Right-to-left Shift-and-Add Multiply module 43 4.10 ECC hardware inversion module in GF (2m).............. 44 4.11 ECC hardware Itoh-Tsujii inversion module . 44 4.12 ECC hardware Point Addition module in GF (2m)........... 45 4.13 ECC hardware Point Doubling module in GF (2m)........... 46 5.1 Energy comparison in prime field . 51 5.2 Energy comparison in binary field . 52 5.3 Energy comparison in all fields . 52 iv 5.4 Performance comparison in prime field . 53 5.5 Performance comparison in binary field . 53 5.6 Performance comparison in all fields . 54 A.1 Functional simulation of ECC scalar multiplication in GF (p)..... 58 A.2 Functional simulation of ECC scalar multiplication in GF (2m).... 59 A.3 ECC scalar multiplication (with Itoh-Tsujii) in GF (2m)........ 60 v Acknowledgements There are so many people I have to express my thanks sincerely. First, I want to thank my family. My parents gave me a lot of support when I needed. My wife and daughter always cheered me up and boosted my confidence. My younger brother takes care of my parents and deals with a lot of things for me. Secondly, I want to express my sincere gratitude to my advisor - Dr. Swarup Bhunia. From my advisor, I learnt the passion of work and the attitude towards research. I also want to show my heartfelt appreciation to Professor Christos Papachristou and Professor Francis Merat for serving as my thesis committee members. Finally, I want to give my thanks to all members in the nanoscape laboratory whose advice continously helped me to improve my work. vi List of Abbreviations ACP Average CPU Power ANSI American National Standards Institute ASIC Application Specific Integrated Circuit CPU Central Processing Unit DFG Data Flow Graph ECC Elliptic Curve Cryptography FPGA Field Programmable Gate Array FSM Finite State Machine IC Integrated Circuit ITRS International Technology Roadmap for Semiconductors LUT Look-Up Table MBC Memory Based Computing MLB Memory Based Logic Block MSB Most Significant Bit NIST National Institute of Standards and Technology RSA Rivest-Shamir-Adleman TDP Thermal Design Power VLSI Very Large Scale Integration vii Efficient Implementation of Elliptic Curve Cryptography in Reconfigurable Hardware Abstract by E-JEN LIEN Elliptic curve cryptography (ECC) has emerged as a promising public-key cryp- tography approach for data protection. It is based on the algebraic structure of elliptic curves over finite fields. Although ECC provides high level of information security, it involves computationally intensive encryption/decryption process, which negatively affects its performance and energy-efficiency. Software implementation of ECC is often not amenable for resource-constrained embedded applications. Alternatively, hardware implementation of ECC has been investigated V in both application spe- cific integrated circuit(ASIC) and field programmable gate array (FPGA) platforms V in order to achieve desired performance and energy efficiency. Hardware recon- figurable computing platforms such as FPGAs are particularly attractive platform for hardware acceleration of ECC for diverse applications, since they involve signif- icantly less design cost and time than ASIC. In this work, we investigate efficient implementation of ECC in reconfigurable hardware platforms. In particular, we fo- cus on implementing different ECC encryption algorithms in FPGA and a promising memory array based reconfigurable computing framework, referred to as MBC. MBC leverages the benefit of nanoscale memory, namely, high bandwidth, large density and small wire delay to drastically reduce the overhead of programmable interconnects. We evaluate the performance and energy efficiency of these platforms and compare those with a purely software implementation. We use the pseudo-random curve in the prime field and Koblitz curve in the binary field to do the ECC scalar multiplica- viii tion operation. We perform functional validation with data that is recommended by NIST. Simulation results show that in general, MBC provides better energy efficiency than FPGA while FPGA provides better latency. ix Chapter 1 Introduction In this chapter, we describe the research objectives, contribution of the thesis and outline of the thesis. 1.1 Research objectives Energy efficiency during computation has emerged as a major design parameter in diverse applications and computing platforms [1][2][3][4][5][6][7][8]. According to the 2011 report from the International Technology Roadmap for Semiconductors (ITRS), the technology scaling trend for application specific integrated circuit (ASIC) can be depicted by Figure 1.1. It shows that although technology scaling provides consistent exponential improvement (following Moores law) in integration density, operating power is not scaling as desired. Consequently, addressing the power issue at circuit, architecture and application mapping level has been a major research area in the nanoscale technology regime. The energy issue can be more prominent for many compute-intensive tasks. Conven- tional software implementations of these tasks can be too power hungry or can be too slow to meet the requirements for many real-time and embedded applications. There is a growing trend to map these complex compute-intensive applications in 1 reconfigurable hardware, such as field programmable gate array (FPGA). FPGA is an attractive computing platform since it can drastically reduce the hardware de- velopment/test cost and time. Alternative reconfigurable hardware platform such as memory based computing (MBC) platforms [9] [10] are also very promising at nanoscale technology. MBC platform relies on a dense two-dimensional memory ar- ray to perform computing in a spatio-temporal manner. Applications are decomposed into partitions, which can potentially be mapped as large look-up table (LUT) in the memory and a function can be evaluated by accessing the LUT contents over multiple cycles. Multiple MLB interacts in spatial manner to perform complex operation. The objective of the research presented in this thesis is to explore implementation of elliptic curve cryptography (ECC) algorithm in reconfigurable hardware and evaluate their performance and energy efficiency. In order to analyze potential benefit over traditional software-based implementation, we also compare these design parameters with an alternative implementation in software. We study different variants of ECC algorithms proposed in earlier works and analyze the relative merits and demerits of these algorithms in three alternative platforms. Figure 1.1: 2011 ITRS ASIC Scaling trend prediction 2 1.2 Thesis Outline From inception to completion, this thesis is dedicated in analyzing and evaluating the power, performance and resource usage (referred to as size) of Elliptic Curve Cryptography (ECC) among three different platforms, namely CPU, FPGA and MBC respectively. In chapter one, we will describe the research objectives and contribution of our work. The background and motivation will be mentioned in chapter two. Here we will introduce the hardware descriptions of the different platforms on which ECC is being mapped.
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