Internships at Philips Research Leuven

PHILIPS RESEARCH LEUVEN

Internships at Philips Research Leuven - 2003

Philips Research Leuven is a research division of Philips Electronics, located in the city of Leuven, Belgium. Its research activities comprise investigations into future silicon technologies, as needed for the development of integrated circuits and silicon devices in the Philips Semiconductors product division. During the internship, students will participate in project teams, working on dedicated subjects related to the simulation, fabrication and/or characterization of novel silicon devices and applications. A list of available positions is given below.

Duration of internship: 6 months or longer, ending with a written report and presentation (English) Curriculum: background in Electrical Engineering or Physics preferred Language: fluent in English Allowance: students will receive a fixed monthly allowance to compensate for rental and living expenses

Contact person: Peter Stolk, Department Head Philips Research Leuven E-mail: [email protected] Phone: +32-16-288324

INTERNSHIPS AT PHILIPS RESEARCH LEUVEN (BELGIUM) - 2003 PHILIPS RESEARCH LEUVEN

1. Characterization and modeling of flash memory devices Supervisor: Frans Widdershoven

At Philips Research Leuven we are doing research on embedded floating gate flash memories. An information bit is stored as a charge packet on the floating gate of a MOS transistor. The floating gate is coupled capacitively to a control gate that is used to program/erase the floating gate transistor. An access transistor is connected in series with the floating gate transistor to select it in an array of equivalent devices (the memory array). To make the 2-transistor memory cell as small as possible the 2 transistors are merged into a single compact device. Such a compact 2-transistor memory cell puts a challenge to electrical characterization and modeling. Separating the contributions of the various interacting cell parts to the overall cell characteristic requires extension of the standard characterization and modeling approach for conventional MOS transistors. The student will participate in this work by focussing on a dedicated characterization and modeling topic that makes up a self-contained task. Close interaction with the other project team members will provide a unique opportunity to discover the world of flash memory devices and to give valuable feedback to the project.

2. Characterization of MOSFETs with High-K Gate Dielectrics Supervisor: Chris Rittersma

In this internship, you will evaluate electrical properties of sub-65nm NMOSFETs with high-k dielectrics. This internship requires basic knowledge and understanding of MOSFETs and familiarity with semiconductor technology in general.

In advanced CMOS technologies, gate lengths are scaled well-below 70nm. If SiO2 were to be used as a gate dielectric, gate leakage currents would become a serious problem.

In order to reduce the gate leakage and maintain good threshold voltage control, the SiO2 gate dielectric is replaced by what is known as a high-k dielectric, i.e. a dielectric with a permittivity higher than 3.9. Typical materials are Hf-based oxides, e.g. HfO2 and HfAlO. Because of the higher k-value, the physical thickness of these high-k dielectrics can be larger than that of SiO2 at the same capacitance/unit area. Although this reduces the gate leakage current, there are many other materials’ issues influencing the transistor performance, e.g. fixed charge and interface traps. It will be your task to identify the impact of these and other material’s properties on the device performance.

3. Double-Gate MOSFET transistors device modeling with ultra-thin Si layers Supervisor: Youri Ponomarev

It is quite clear that sub-35nm CMOS technology (in production in 2007 and beyond) will have to look quite different from the standard planar CMOS. The requirement of minimal short-channel effects coupled to high performance requirements with ever decreasing supply voltage now looks impossible to achieve. The only way for Si MOSFET's to progress beyond that point is to use a double-gate architecture, which comprises ultimate control of two self-aligned gates over a thin Si body sandwiched between them. It is believed that such devices should push the limits of scaling for Si down to ~10nm gate lengths. Feasibility study of manufacturable double-gate devices is carried out in this part of the project. Final goal of this 6-9 month internship is to find physical models reliable enough to be used in combined process/device modeling software to predict electrical device behavior after real-life processing. The student will be involved in all stages of the study: literature survey, data acquisition, analysis and interpretation.

4. Metal gate electrodes for advanced devices Supervisor: Rob Lander

MOS transistors for future integrated circuits may require one or more metals to replace the current polycrystalline Si gate electrodes. This is in order to continue the scaling down of device dimensions and to further improve the device performance. Furthermore, a metal gate may be required because it is more stable in contact with the new generation of “high- k” gate dielectrics that will replace SiO2. Our understanding of these new metal-high-k combinations is developing rapidly and Philips has access to the most advanced deposition and characterization techniques available anywhere in the industry.

4.1 Metal workfunction stability There remain several obstacles to the incorporation of these new material combinations into commercial processes. Of major concern is the dependence of the metal workfunction upon deposition technique and subsequent variations during thermal processing. The MOSFET threshold voltage is directly proportional to the metal workfunction and so this is a critical parameter which must be highly stable and reproduceable. The project will involve electrical characterization of as-deposited and annealed gate stacks, using capacitance-voltage techniques, and the results will be combined with materials studies in order to identify the areas of concern and to obtain a better understanding of the physical causes.

4.2 Metal alloys for gate electrodes in sub-30nm length MOSFETs A metal offers several advantages over poly-Si as a gate electrode but a significant disadvantage is that the workfunction cannot be controlled by such a simple means as dopant implantation. PMOSFETs and NMOSFETs require gate electrodes with different workfunctions in order to achieve suitable threshold voltages for both types of transistor. New alloying techniques are being developed by Philips to control the workfunction of these metal gates. This project will involve the study of these new alloys and their potential for application in future deep-sub-micron CMOS processes. Capacitance-voltage measurements will be used to measure the metal gate workfunction and gate dielectric quality and the results will be related to the process conditions and physical measurements of the chemical composition.

5. Analogue and digital characterization of CMOS technologies Supervisor: Celine Detcheverry

Philips in collaboration with ST Microelectronics and Motorola works on the development of the latest CMOS technologies. MOS (Metal Oxide Semiconductor) silicon transistors with channel length down to 50 nm are processed and optimised. The driving applications of such CMOS technologies are low voltage digital applications. But as the active dimensions of the devices decrease for each new generation, their speed increases. Typical cut-off frequency of submicron MOS transistors are competing with the cut-off frequency of bipolar transistors (typically 50GHz or higher). Hence, the increasing demand for integrating mixed signal and digital functions on a single chip* calls for dedicated optimisation and characterisation of the analogue behaviour of those devices. The main goal of the training period will be to characterise and understand the digital and analogue performances of transistors processed with process modification splits. The physics of electromagnetic waves and all the electronic aspects of a MOS transistor are involved in this work, which makes the subject challenging and extremely rewarding.

After the internship, the student is asked to deliver a report (in English) to Philips Research.

*An example of such integrated solution is the so called Bluetooth application.

6. Electrical characterization of RF transistors Supervisor: Peter Magnee

In the Advanced BiCMOS program at Philips Research Leuven SiGeC Heterojunction Bipolar Transistors are studied. The devices are scaled down aggressively both vertically and laterally, in search for ever faster devices (well beyond 100GHz). In order to improve on Radio Frequency performance by process-technology variations, extensive characterisation is required. Especially the extraction of the various contributions to parasitic series resistances and capacitances is crucial for the further improvement of the HBT devices. An internship position is available to join the electrical characterisation, where the aim will be to clarify the link between one or two specific major parasitics and the process technology.

7. Determination of the electron mobility in an accumulation layer of a trench gate Supervisor: Erwin Hijzen

In many applications the power loss in (n-type) power trench MOSFETs is mainly determined by on-resistance. This resistance can be split into several contributions such as the channel resistance and the drift resistance. In the channel resistance the inversion layer mobility is important. Both theory and experiments show that this mobility depends a.o. the orientation of the trench.

Another contribution of the on-resistance is the electron mobility in the accumulation layer of a trench gate. So far, in the literature no data have been found about this mobility for different orientations. Consequently, several questions arise such as how does this mobility behave with respect to the electric field, can it be compared with the mobility in the inversion layer, or is there any evidence of the orientation dependence.

In order to answer these questions measurements should be performed with special test structures. Recently, an experimental setup has been explored for the determination of the inversion layer mobility for different temperatures, doping concentrations and trench orientations. The main work is to use this setup for answering all these questions.

8. Gate oxide integrity study of TrenchMOS transistors Supervisor: Erwin Hijzen

Because of the demand for reduction of the on-state resistance of TrenchMOS transistors, to reduce power loss to a minimum, the dimensions of these devices are continuously being scaled down. This implies a reduction in cell pitch and trench width. But also in the vertical direction downscaling is important, resulting in optimisation of doping profiles and trench depths.

To realise this new fabrication concepts are being implemented. This results in more so- called self-aligned processing to reduce the cell pitch and trench width. For the doping profile optimisation the thermal budget of these processes is reduced to a minimum. The influence of these new processes on the gate oxide quality is, however, unknown, and needs to be examined.

Since the methods to evaluate gate oxide integrity in TrenchMOS technology are unexploited at this moment, the student will have to transfer and adapt CMOS approaches. Next, gate oxide integrity studies will have to be performed on devices fabricated with different processes, after which suggestions for improvement, if necessary, should be formulated.

9. Gate resistance study of TrenchMOS transistors Supervisor: Erwin Hijzen

Because of the demand for reduction of the on-state resistance of TrenchMOS transistors, to reduce power loss to a minimum, the dimensions of these devices are continuously being scaled down. This implies a reduction in cell pitch and trench width. To realise this new fabrication concepts are being implemented. This results in more so-called self-aligned processing to reduce the cell pitch and trench width. Reducing the trench width, however, has a disadvantage. The (poly-Si) gate resistance will increase. For fast switching applications this will hamper the on- and off-switching of the device, causing significant power loss. It is yet unknown how the gate resistance will increase with decreasing trench width, since many parameters might influence this. The effect of the poly-Si grainsize, for instance, is unknown. Silicidation of the gate might be a solution for reducing gate resistance, but it is known from CMOS processing that also for silicides the gate resistance is not a linear function of the gate width.

The student will evaluate the effect of trench width reduction on the gate resistance, preferably for both unsilicided and silicided gates. For this purpose measurement structures are already present on existing device wafers. The data gathered will be used to optimise gate processing for TrenchMOS transistors.

INTERNSHIPS AT PHILIPS RESEARCH LEUVEN (BELGIUM) - 2003