On-Line Supplementary Information For

On-line Supplementary Information for

Alternative interpretations for decreasing voltage with increasing charge in

ferroelectric capacitors

Seul Ji Song1, Yu Jin Kim1, Min Hyuk Park1, Young Hwan Lee1, Han Joon Kim1, Taehwan

Moon1, Keum Do Kim1, Jung-Hae Choi2, Zhihui Chen3, Anquan Jiang3, and Cheol Seong

Hwang1

1 Department of Material Science & Engineering and Inter university Semiconductor Research Center,

Seoul National University, Seoul 151-744, Republic of Korea

2 Electronic Materials Research Center, Korea Institute of Science and Technology, Seoul 136-791,

Republic of Korea

3 State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, Shanghai

200433, China

I. Positive capacitor model of FE capacitor during switching

Although this was already briefly explained in main text, much more detailed discussions are given here. Also, combined graphs in Fig. 1 of the main text are placed separately in Fig. S1 for clarity. The interpretation of the FE film behavior during FE switching using an increasing capacitor model is proved by a quantitative simulation using a PSPICE simulation package. The justification for considering FE capacitor as a positive capacitor during the FE switching was provided in the main text. In order to do this, the circuit simulation is designed as described in Fig. S1a. The other parameters, such as the applied voltage pulse (VP), series resistor (RS) and parasitic capacitor (Cpara), are fixed to examine the switching transient pulse signal for the specific case shown in Ref.6 of the main text. The time variant capacitor charging current is simulated by the implementation of eq. (1).

dq(t) d(C (t)v(t)) dv(t) dC (t) i (t) = = var = C (t) + v(t) var eq. (1) C dt dt var dt dt

The voltage across the Cvar (between node 1(N1) and node 2(N2) in Fig.S1a) is sampled by EVALUE part (Ecap_var) of library abm.slb. Then, the derivative of this voltage is multiplied by an external voltage source (Vcap_var(t)), directly representing the capacitance value (Cvar(t)) according to the rule of

1F=1V. Also the derivative of Vcap_var is multiplied by the sampling voltage. Thus, the capacitive charging current (iC) flowing in between N1 and N2 can, then, be calculated by adding these two contributions and converting to a current with GSUM of library analog.slb. The detail of netlist of

PSPICE simulation for a time variant capacitor model is shown below.

*Analysis directives: .TRAN 0 80us 0 200n .INC "..\SCHEMATIC1.net" V_Vpulse1 Node1, 0 +PULSE 0 5.4 2u 0.5u 10n 60u // input pulse conditions

R_RS Node1, Node2, 50k // external series resistor C_Cpara Node2, 0, 60p R_rho Node3, Node4, 5k

E_E_cap_var Node4, 0, VALUE { V(Node4, 0) }

// read the voltage across the Cvar (=Vin) V_V_cap_var Node6, 0 PWL + FILE "D:\Cmodel\C_1.txt" // time varying capacitance according to model X_DIFFER1 Node4, Node5, SCHEMATIC1_DIFFER1 E_MULT1 Node8, 0, VALUE {V(Node6)*V(Node5)} X_DIFFER2 Node6, Node7, SCHEMATIC1_DIFFER2 E_MULT2 Node9, 0, VALUE {V(Node4)*V(Node7)} E_SUM1 Node10, 0 VALUE {V(Node9)+V(Node8)} G_G_cap_var Node3, 0, Node10, 0, 1

// convert to current (iC)

d Here, the FE capacitor has a dielectric capacitance (CF ) of 10 pF, and parallel parasitic capacitance

(CP) of the circuit was 60 pF. The parallel CF/CP are connected to the voltage source via the serial resistor, R, of which the resistance is 50 kΩ, where CF represents the FE capacitor. It is noted that ρ (5 kΩ) is involved in the circuit, which was assumed to remain constant during the entire switching period. In the in-series resistor model in the following section, ρ is replaced with R i(t). The voltage of the node between R and CF/CP - ρ is monitored by an oscilloscope (OSC) with high input impedance

(10 MΩ) during the positive voltage pulse application (5.4 V, 60 μs) to the circuit. Before this 5.4V pulse application, the circuit was originally negatively charged by a previous negative voltage pulse.

d f f CF equals to CF + CF , where CF represents the capacitive contribution when the polarization of the

d f FE switches. Compared to CP, CF can be ignored. In this case, CF must be a function of time because it represents the movement of compensating charges, which is controlled by the nucleation and sideway motion of the reverse domains, and this takes time. The simulation results of the exponential

f 10 form of CF (t) within the domain nucleation model (Komogolov-Avrami-Ishibashi (KAI)) are described in the main text. The original KAI model only describes evolution of the volumetric portion of the reverse domains as a function of time. As described in the main text, however, this can be used to estimate the increase in positive capacitance assuming that the reverse domains have a columnar structure, i. e. reverse domains penetrate through the FE film thickness, and their cross-section area increases with time according to the KAI formalism. In this case, the PSPICE simulation shows highly intriguing results as shown in Fig. S1c. Up to t0 after the positive voltage pulse was applied,

d f f there was a simple capacitive charging of CF , CF , and CP. At t0, the CF started switching (up- polarization changes to down-polarization) meaning that the negative charges accumulated on the top electrode, which were retained up to t0 even when the applied voltage bias was previously positively changed, started draining away towards the voltage source (positive charges on the counter electrode were drained off to ground) and positive charges started accumulating. There could be two sources for

f such positive charges accumulating on the top electrode of the C F : charges from the voltage source via R and charges from the CP which have been accumulated from the time, t=0 to t0. Under this

f circumstance, the estimated node voltage, VF, could decrease until the charging of the CF is completed while the voltage source keeps supplying the circuit with positive charges. Hence, iR is positive and

d f thus, QF (= QF + QF ) keeps increasing. The fitting of the experimental data using this model was already better than what Khan et al. presented using the LK model to formulate the capacitive response of the PZT capacitor (Fig. 4 of Ref. 6.) It inevitably results in the NC type behavior while the authors of the present work used capacitance values that are reasonably changing over time (C(t)) within the positive value regime. The authors noted that the estimated coercive voltage (Vc) according to the LK formalism in Fig. 4 of Ref. 6 is as high as ~10 V, while the experimentally observed Vc was

~3.7 – 3.1V. Such discrepancy might be an indication that the switching has occurred along the path 2 in Fig. 1a of main text, which does not involve the NC effect. Figures S2d shows the variations in iR. Figure S1. a, Schematic of equivalent circuit for the PSPICE simulation. Simulation parameters, such as VP, R, CP and ρ, are referred to the experiment setup in Ref.6. b, Change in capacitance of a

f f 3 f FE film with time. CF (t) was assumed as a function of CF (t∞)(1-exp(-((t-t0)/τ) )+CF (t=0) for the switching time. c, and d, PSPICE simulation result for the variation of the voltage across the C F (VF) and current flowing through the R (iR) during the switching time.

II. In-series resistance model of FE capacitor during switching

The important concept for this in-series resistor model is that any actual FE capacitor is almost always accompanied with in-series resistance component (Ri), which could be an interfacial dead-layer or any other non-FE layer. In Ref. 6, Khan et al., took this into account by introducing an internal resistor (ρ), which is identical to the Ri in this circuit model. In their interpretation of VF↓QF↑ behavior of the circuit, the voltage on the actual FE layer (Vint) was assumed to decrease during the FE switching according to the LK formalism, which resulted in the increase of the voltage and the current across R. Here, the estimated voltage (VF) is applied to Ri (VRi) and Vint (VF = VRi + Vint). Therefore, if either voltage, i. e. VRi or Vint, decreases with time during the FE switching, the decreased voltage must be added to the external R, and iR must increase accordingly. In this in-series resistor model, the authors consider that VRi decreases while Vint remains at a coercive voltage (Vc) of a genuine FE layer, which is consistent with the general view of the FE switching in many FE thin film and bulk systems. The case where Vint decreases with time due to the increase of “positive” capacitance of the FE layer is discussed in the previous section. The decrease in VRi coincides with the degradation of Ri value with time, which can be induced by the charge accumulation across the interfacial layer during the FE switching time. As the charge flow is limited by the presence of high R in the circuit, the initial voltage over Ri is small. The FE switching is also retarded due to the lack of compensating charge flow at the FE film surface although the Vc is applied. As time elapses, the increasing accumulated charges on the interfacial layer increase the voltage across that layer, and Ri decreases rapidly, which then indeed allows the FE switching to occur. The contact between the electrode and the interfacial layer could be Schottky-like or Ohmic, and the carrier injection could be space-charge limited current due to very thin thickness of the interfacial layer. For this case, the work by Many and Rakavy, 11 can be referenced. If such current transient originates from the oxygen motion, the work by Meyer, et al. 12 can be referenced. However, in this work, the Ri degradation is assumed to be soft breakdown-like, as in many dielectrics, which was also assumed by Jiang et al., in recent work on a single crystal LiNbO 3 thin film.13

To demonstrate the equivalent circuit modeling for ferroelectric switching in pulse switching mode, the internal resistance of ferroelectric is taken as a time variable resistor in PSPICS simulation. The

EVALUE part (E_R_var) translates the reading current (iR_var(t)) across the internal resistor (Rvar(t)) to voltage, which is referred to the controlling voltage generator (VR_var(t)), by multiplying the reading current (iR_var(t)) by Rvar(t) according to Ohm’s law. Here, VR_var(t) directly represent the resistance of

β internal resistor. In this case, Ri(t) can be described as Ri(0)exp(-t/τd) , where Ri(0) is the initial resistance and β is a constant describing abruptness of the breakdown which is taken as 1 for simplicity in this work. τd is the dielectric breakdown time. The abrupt degradation of Ri at a certain time (τd) induces an abrupt decrease in VRi, while the voltage across the FE layer still remains at Vc.

Hence, the node voltage (VF) decreases temporarily and soon becomes identical to Vc. It has to be noted that this Vc is generally higher than the Vc estimated from the standard P-V measurement due to the high frequency of the pulse switching test. For this characteristic of ferroelectric capacitor, another

EVALUE part (Eferro) restricts the applied voltage across the capacitor to Vc, when the applied voltage becomes higher than Vc. The netlist of PSPICE simulation is described in below.

*Analysis directives: .TRAN 0 80us 0 200n .INC "..\SCHEMATIC2.net" V_Vpulse1 Node1, 0 +PULSE 0 5.4 2u 0.5u 10n 60u // input pulse conditions

R_RS Node1, Node2, 50k // external series resistor C_Cpara Node2, 0, 60p

E_Rvar Node4, Node5, VALUE {V(Node6, 0)*I(V_Vread)}

// convert to voltage (= iC*Rvar); internal resistance V_V_R_var Node6, 0 PWL + FILE "D:\Rmodel\R_1.txt" // time varying resistance ~exp(-t/τ) V_Vread Node3, Node4, DC 0Vdc, AC 0Vac

// read the current through the Rvar (= iR_var)

E_E_ferro Node5, 0, VALUE {(Node5, 0), IF(V(Node5, 0)>Vc, Vc)}

// Vc is defined as 3.1V V_V_ferro Node6, 0 PWL + FILE "D:\Cmodel\C_1.txt" X_DIFFER1 Node5, Node6, SCHEMATIC1_DIFFER1 E_MULT1 Node9, 0, VALUE {V(Node6)*V(Node5)} X_DIFFER2 Node7, Node8, SCHEMATIC1_DIFFER2 E_MULT2 Node10, 0, VALUE {V(Node5)*V(Node8)} E_SUM1 Node11, 0 VALUE {V(Node10)+V(Node9)} G_G_ferro Node5, 0, Node11, 0, 1 In the meantime, the current across R increases rapidly as the amount of decreased voltage over the R i is now dumped to R, letting switching current increase. This is well consistent with the observed

VF↓QF↑ behavior, and also with the portion of P-V loop where V decreases while P increases (Fig. 4 of Ref. 6, and Fig. 3 of the main text). Again, in this case, the decrease in V F is due to the decrease in

VRi, not Vint. After the FE switching is completed, most of input voltage becomes to be applied over the FE layer and switching current decays rapidly. Under this circumstance, the R i(t) will increase

β with time again according to the identical time dependency; Ri(t1)exp((t-t1)/τd) , where t1 is the time when VF shows the minimum, and β is also taken to be 1. Figure 1c and d of main text showed that this model can precisely fit the experimental data over the entire experimental time region.

III. Detailed information epitaxial BTO film on SRO electrode/DSO substrate

Highly epitaxial BTO (BaTiO3)/ SRO (SrRuO3) bilayer was grown along (001) orientation on (110)

DSO (DyScO3) substrate by pulsed laser deposition. The structural data of 150nm-BTO/100nm-

SRO/DSO structure are shown in elsewhere (figure S3 and S4a of Ref. 15).15 Figures S2a and b show the high-resolution transmission electron microscopy images of the cross section of the sample, where a, and b correspond to the DSO/SRO, and SRO/BTO interfaces, respectively. HRTEM confirmed the high quality of the thin films. Figure S2. High-resolution transmission electron microscopy images of the cross section of the (a)

SRO/DSO, and (b) SRO/BTO interfaces.

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