Structural Modeling of a JK Flip-Flop

Laboratory Experiment #2: Structural Modeling of a JK Flip-Flop

Ari Mahpour ECE 526 Lab In this laboratory session we were to design and build a JK Flip-Flop using primitive gates. This was no ordinary JK Flip-flop since it also consisted of an active low Set and Reset function (along with the K input also being active low). The gates that we used were ANDs, NANDs, and NOR gates. Testing started to get quite difficult because of the delay (a major factor that must be taken into account). The delay caused the readability to be much more difficult and sometimes prevented certain functions from working. The longest delay (critical path) throughout the circuit was 3 + 5 + 8 + 15 = 31ns. This meant that the clocking had to be set for every 31ns minimum. Just to be careful, the clock in this test bench was set to 40ns every positive edge and 40ns every negative edge (a total of 80ns per clock cycle).

Another important factor that must be taken into account is regarding the direct input set and reset. Their purpose it to clear or set Q and Qb. If Q or Qb was not set (i.e. the initial ON switch to the circuit) then we can perform a reset and initialize our circuit to the proper manner (since all gates were dependent on Q and Qb). We also did not have to wait for the clock pulse to generate a Q and Qb value.

Since these are direct inputs they work regardless of the clock or not.

Test Strategy: The purpose of this lab is to observe the functionality of a JK Flip-Flop with set and reset inputs. An exhaustive test is not necessary since we are only required to observe the behavior of such a device. We have eight test cases that are required to test: Asynchronous Set, Asynchronous

Reset, Indeterminate, Load 0 (reset), Load 1 (set), Hold (ncng), Toggle, and Hold (ncng) on a non-positive edge. To test these values we first had to set everything to zero (which includes Q and Qb) so we ran the

Asynchronous Reset function. As stated earlier, this function comes in quite handy when turning on the device (since we will automatically start with arbitrary “x” values which the computer cannot use to simulate). The Reset and Set were now set to 1 which caused the functions to turn off. From here on we were dealing with the JK inputs only. The next test was to test the toggle. This, in effect, would switch our Q to Qb and Qb to Q

(essentially invert the outputs). Once we did that we would perform the next test, a Load 0 (reset) function which would perform the same function as a normal direct input set but through the JK inputs and completely dependent on the clock pulse. As specified, this and the rest of the JK input test functions had to be set before the clock’s positive edge. The test bench’s code specifies that a CP value of 0 was set when setting all the JK inputs and then the clock’s positive edge (CP=1) ran. The next test,

Load 1, would set the Q value to 1, once again, and the Qb to 0. The next test, Hold, would keep the previous Q and Qb by reading in the JK inputs. The indeterminate test was next which should potentially give us a 1 output for Q and Qb. The next test, Asynchronous Set would bring us back to a Q=1 and Qb=0

(resulting in Qb lowering and Q staying the same). The last test, which was the second Hold, was performed but this time on a non-positive edge which means it was done when the clock pulse was set to 0. This was suppose to hold the previous values of Q and Qb. Finally, we let the clock run in order to catch up on a delays that might be factored in.

Another test bench was performed in the same manner but the clock pulse was set to a 25% duty cycle, which is known as a Short positive pulse. The code for the text bench was exactly the same as the regular 50% clock pulse except for one case. When CP was set to zero it was performed every 60 time units (#60) and when it was set to one it was performed every 20 time units (#20). This resulted in a clock pulse ratio of 20 to 80 which is translated to 25%. Other text displaying functions were tested throughout the simulation such as: $monitor, $display, $write, and $strobe.

Results: This laboratory exercise’s outcome was a success. The Asynchronous Reset worked like a charm and laid the way for the rest of the tests to work properly. Prior to running an Asynchronous

Reset, the simulation runs did not function properly and Q and Qb outputs did not resemble anything like a JK Flip-Flop. Once the Asynchronous Reset was performed the next test, Toggle, was put to test.

The Q and Qb outputs did, indeed, invert and the toggle was successful. The Load 0 (reset) brought the Q output back to 0 and the Qb to 1. The Load 1 performed the set function via the clock pulse and JK inputs which resulted in Q becoming 1 and Qb going back to 0. The next test, Hold (ncng) performed well but was short lived since the test after that, Indeterminate, used direct inputs. Instead of waiting for the clock’s positive edge to run, the Q and Qb outputs set to 1 before the Hold (ncng) could complete a full cycle. The Asynchronous set was tested and was also unaffected by the clock’s edge which meant that Q was kept at 1 and Qb moved back to Q’s inverted value, 0. The last test was to see if the Hold

(ncng) function would work on a non-positive edge. This test also worked since it managed to keep the previous output constant without a gap or distruption. The short positive pulse test performed exactly like the previously stated test without any inconsistencies (see graph for details).

Conclusion: The most important part of this laboratory exercise was to observe the behavior of the JK Flip-Flop through the SimVision software. It was to give us a background on how to really examine a circuits behavior by observing its input and out signals. Sometimes is can be difficult remembering the behavior of these circuits so it is important to look back on notes or books from previous courses. Even in the industry today people don’t know the behavior of every possible circuit and for that we have so many resources both on paper and digitally. In the future labs we will eliminate the use of primitive gates so testing thebehavior can potentially be easier or more difficult (depending on the circuit that is coded/built). I hereby attest that this lab report is entirely my own work. I have not copied either code or text from anyone, nor have I allowed or will allow anyone to copy my work.

Name (printed): ______

Name (signed): ______

Date: ______SimVision - Test Bench (Symmetiric Clock with 50% Duty Cycle)

SimVision - Test Bench (Symmetiric Clock with 25% Duty Cycle)