Computing of the Future Consortium s1

Computing of the Future

Energy-Efficient Large-Scale High-Performance Computing

Place: Crowne Plaza Hotel, San Francisco Airport Date: February 29, 2008 Time: 8:00 am- 8:00 pm

What will Computing be like in 20 years? What is the future beyond the end of the current roadmap for CMOS microprocessors? The phenomenal advances in computing technology over the past two decades were enabled by Dennard scaling, whereby the exponential improvements in power efficiency and performance and cost-effectiveness of silicon technology tracked Moore’s Law improvements in integrating more devices on each chip. As we approach atomic scale lithography, the end of Dennard scaling puts future growth of the computing industry in jeopardy. Multicore has provided a temporary respite from stagnation of CPU clock frequencies, but creates daunting challenges to programmability, and drives today’s system architectures towards extreme levels of unbalanced communication-to-computation ratios! This workshop will promote discussions on a comprehensive strategy that directly addresses the challenges of power-density, bandwidth limits, programmability, and interconnect technologies. One of the central goals of the workshop is to discuss methods to eliminate the growing system imbalance performance gap by creating a new computing platform where bandwidth is uniformly plentiful across the entire system and is not traded off the power budget. A system with such uniform system-wide bandwidth offers significantly simpler optimization strategies for software architects that address many of the programmability concerns for multicore chips and massively parallel computing platforms. Addressing the three key areas of energy consumption, bandwidth scaling, and programmability will enable continued exponential improvements in power-efficiency, performance, and cost-effectiveness that drive the computing industry for the next 20 years.

This workshop addresses key opportunities and challenges of Future Computing, in the architecture, nanotechnologies, interconnection, and systems areas.

Topics

 Applications and Architectures of Future Computing Systems  Nanotechnologies beyond CMOS (nanophotonics, nanoelectronics, nanomagnetics)  Novel Interconnection

Organizing Institutions: Center for Information Technology in the Interest of Society (CITRIS) Columbia University Cornell University Lawrence Berkeley National Laboratory University of California, Berkeley University of California, Davis Stanford University

Cooperating Organizations: HP, Hitachi, Intel, Lawrence Berkeley National Laboratory, NEC, Samsung Format

The workshop will be for one entire day (including lunch and dinner) on February 29, 2008, featuring presentations by key contributors to the field in intermixed with working sessions to create a group consensus of promising future directions. The workshop will produce a report suitable for use by decision makers and technologists.

Co-Chairs: Venkatesh Akella (UC Davis), Keren Bergman (Cornell University), Horst Simon (Lawrence Berkeley National Laboratory), S. J. Ben Yoo (UC Davis) Agenda (Tentative)

February 29, Friday, 2008

Friday, February 29 Day: 7:30 amBreakfast 8:15 amRegistration 9:00 amWorkshop Introduction, Overview, and Goals S. J. Ben Yoo, UC Davis 9:30 amResults from the Zettaflops Workshop 2007 Erik P. DeBenedictis, Sandia National Labs 10:00 amTera-scale Computing - motivation and challenges Jerry Bautista, Intel 10:30 amBreak 11:00 amApplications and Architectures to Harness Exaflops John Shalf, LBL 11:30 amThe Future Evolution of High-Performance Microprocessors Norm Jouppi, HP Labs 12:00 NoonOptical Interconnects David A. B. Miller, Stanford 12:30 pmLunch 1:30 pm Nano-Photonic Interconnection Networks for Chip-Multiprocessor Computing Systems Keren Bergman, Columbia Univ. 2:00 pmIntraChip Optical Networks for a Future Supercomputer-on-a-Chip Jeffrey Kash, IBM Research 2:30 pmNanoscale waveguides, metallic slots, and switches Shanhui Fan, Stanford Univ. 2:45 pmNanowires: Massively Parallel Interconnects Saif Islam, UC Davis 3:00 pmNSA’s Center for Excellence in Computing and ACS Programs David Bifang, Department of Defense Lance Janeckis, Institute of Defence Analysis 3:20 pmBreak 3:50 pmDiscussions: Computing of the Future Moderated by S. J. Ben Yoo, UC Davis 5:30 pmSocial 6:00 pm Dinner Banquet ~8:00 pm March 1, Saturday 2008 (Optional Lab Tour: Please indicate your interest in your registration or contact Sonia Rivera)

Day:Saturday, March 1, 2008 8:00 amDepart Crowne Plaza SFO 9:30 amArrive at UC Davis Campus 9:40 amNorthern California Nanotechnology Center Tour Frank Yaghmaie, UC Davis 10:00 am167-core ASAP II chip demo Bevan Baas, UC Davis 10:20 amNano-wire device demo Saif Islam, UCDavis 10:35 amPhotonic Integrated System-on-a-Chip tour S. J. Ben Yoo, UCDavis 10:50 amSpintronic Devices tour Kai Liu, UCDavis 11:05 amDepart Davis for Stanford 12:40 pmLunch at Stanford 1:20 pmPlasmonics and Photonic Interconnects (Tentative) TBD 2:20 pmDepart Stanford for Crowne Plaza Hotel, SFO 2:50 pmCrowne Plaza Hotel, SFO Arrival Registration

Participation is by gracious invitation only. Contact [email protected] if you need an invitation. Additional invitations are subject to space availability. Register on line (registration website will open soon at: http://sierra.ece.ucdavis.edu/html/html/workshop.htm )

Note: On-line registration closes February 26, 2008 at 11:59pm (PDT). Registration will still be available at the door. Accommodations Crowne Plaza Hotel 1177 Airport Blvd Burlingame, CA 94010 Phone: 877-252-1558 / 800-411-7275

Sleeping Room Block: The organizers have reserved a block of rooms at $159 + tax per night ($140+tax with Government ID). These rooms have been guaranteed and non-local participants are requested to contact the organizers if they cannot use these arrangements. Please call 800-411-7275 and provide the Group Name: “Computing.”

Check-In/Check-Out: Crowne Plaza respectfully requests a 4:00 pm check-in and a 12 noon check-out. Conference Meals

Breakfast, lunch and dinner will be provided for registered conference attendees on February 29, 2008.

All meals will be served buffet-style in the dining rooms.

Morning and afternoon refreshment breaks will be provided and replenished continually throughout the day.

Driving Directions

From San Francisco International Airport: Take Highway 101 South to Broadway exit. Follow the Airport Boulevard signs and travel east across the overpass. Turn right on Old Bayshore Road and follow straight into the hotel driveway. approximately 1.5 miles

From San Jose Airport: Take Highway 101 North to the Broadway/Burlingame exit. Turn right and follow straight into the hotel driveway approximately 33 miles

From Oakland Airport: Take I-880 South to Highway 92 ( San Mateo Bridge) West to Highway 101 North. Stay on Highway 101 to the Broadway/Burlingame exit. Turn right and follow straight into the hotel driveway. approximately 30 miles Contact Us

For questions regarding the technical program, please contact: S. J. Ben Yoo, [email protected], UC Davis CITRIS Director & General Workshop Chair Phone: (530) 752-7063

For questions regarding conference logistics, please contact: Sonia Rivera, [email protected], UCDavis CITRIS Program Manager, Phone: (530) 752-7007