Faculty of Engineering

FACULTY OF ENGINEERING

MULTIMEDIA UNIVERSITY

LAB SHEET

INTEGRATED VLSI SYSTEMS

EEN4196

TRIMESTER 1 (2011/2012)

VLSI1: Schematic Design Entry, Simulation & Verification VLSI2: SDL Layout Drawing -DRC - LVS – PEX EEN4196: Integrated VLSI Systems

Design Laboratory

1. Objective

To sharpen students’ design skills, which after completing the two lab phases, students will be able to design the basic digital integrated circuit building blocks based on given specifications.

To expose students to the design tools used by the industries in designing digital integrated circuits. During the course of the design labs, students will be going through digital IC circuits design flow, from the initial design to final verification.

At the completion of the design project, students should be able to:

 understand how the logic gates are constructed out of transistors.  Measure the circuit parameters such as propagation delay and power consumption.  understand and apply low-power high-performance design techniques in their design.  draw the layout of a small IC block, including the routing.  understand and apply advanced layout techniques to minimize the effects of parasitics, especially on high-speed circuitries.

Programme Outcomes (% of contribution)

 Ability to acquire and apply fundamental principles of science and engineering. - 19%  Capability to communicate effectively. - 5%  Acquisition of technical competence in specialized areas of engineering discipline.- 23%  Ability to identify, formulate and model problems and find engineering solutions based on a system approach.- 22%  Understanding of the importance of sustainability and cost-effectiveness in design and development of engineering solutions. - 20%  Ability to work effectively as an individual, and as a member/leader in a team.. - 5%  Capability and enthusiasm for self-improvement through continuous professional development and life-long learning. - 6%

2 2. Introduction

In the first induction lab (VLSI1), students are asked to go through the process of designing and simulating a CMOS inverter.

In the second induction lab (VLSI2), students will be asked to continue to the second part of the design which are Circuit Layout, Design Rule Check, (DRC) Parasitic Extraction (PEX) & Layout Versus Schematic (LVS) Verification.

The two induction labs will familiarize students with Mentor Graphics as an Electronic Design Automation (EDA) tool package for VLSI design. After going through the labs, students are required to create their own design from a selected topic. Detailed methodology on how to design the system are not given in the lab sheet. Students will have to use their creativity in designing the system, taking into consideration design tradeoffs. This will also sharpen students’ design skills, as engineers are not procedure-followers.

3. Design Task/Expected Outputs

Students are required to design one VLSI circuit building block using CMOS TSMC 0.35-micron technology. After forming a group of at most 3 students, students should choose one of the topics to be proposed on Week 1 of the trimester.

Mentor Graphics should be used to implement and verify the correct functionalities of your design, similar to the 2 walk-through labs.

The circuit and layout must be designed with the following goal(s) in mind: 1. Minimum chip area 2. Minimum transistor count 3. Minimum power dissipation 4. Minimum propagation delay (maximum speed possible)

Before capturing the design using the EDA tool, students must do some homework. This includes reading background theory of the chosen building block. After that, students must hand-analyze the chosen circuit architecture to get maximum performance. Students should come up with their own testing methodology, to prove that the circuit is functional and meet every design specification. Students will have to enter the lab and implement their designs at their own time, and complete the design by the time stipulated by the lecturer.

3 4. Report

After completing the design project, a project report should be submitted by each group. The quality of your report is as important as the quality of your design. One must sell the design by justifying the design decisions and providing all the vital information, while eliminating the unnecessary materials. Organization, conciseness, and completeness are of paramount importance. Remember, a good report is like a good layout: it should perform its function (convey information) in the smallest possible area with the least delay (to the reader) possible. In the report, the following information must be included:

(a) Functional explanation of the design (b) Hand analysis (c) The schematic diagram of the design (d) Layout (e) Input test vectors and expected results (f) Simulation results of the schematic (g) Design methodology and flow (h) Simulation results of the parasitic-extracted layout (i) Design summary on layout size (m  m), transistor count, and maximum delay/maximum frequency, average power consumption, specification, etc. (j) Discussions – analyze the differences among results for hand-analysis, schematic capture and layout. (k) Conclusions

Detailed information on the design project will be given by the lecturer.

4 LAB GUIDE VLSI1: Schematic Design Entry, Simulation & Verification

Create project folder  Before creating a design, you must create a folder storing all the design files.  From the desktop, right click on the mouse and open a terminal window.  At the command shell, make a project directory, and inside the project directory, create another schematic directory as follows: Type: mkdir project then click ENTER. Type: cd project then click ENTER. Type: mkdir schem then click ENTER.

Schematic capture

Setup  To draw schematic, use the Design Architect IC. At the command shell, Type: da then click ENTER  From the menu, choose the ADK Design Kit by keying in “2”. The DA-IC window pops up.  You need to setup the DA-IC Session. Click on the “MGC -> Setup -> Session”, to bring up the setup window.  Check the “Show Palette” option and click “OK”. This will display a schematic palette on the right side of the tool.  Next you should setup the working directory, click on “MGC -> Location map -> Set Working Directory”. At the “Directory path” column, set the working directory to schematic directory just created earlier by keying in (or use the navigator) this path: /newhome/shome/DIC**/project/schem Note: DIC** is your username (e.g. DIC12). Usually, “/newhome/shome/DIC**” appears by default.

Create a schematic sheet  To create a schematic, click on the “Schematic” option at the palette on the right. At the “Component name” column, type in the path to store the schematic, e.g. “/newhome/shome/DIC**/project/schem/inverter”. Click on “Editable” option and click “OK”.  Now you should be able to see the schematic window with grids.

To draw a schematic

5 (a) Insert components  Click on “ADK IC Library” on the palette on the right side. The palette is now changed to “ic library” where there are many components.  For example, if you wish to insert an NMOS transistor, click on the “nmos”, and place the “nmos” in the schematic.  Note: Placed components are automatically selected/highlighted. To unselect, press on “F2”.  Components you need in creating an inverter are: o nmos, pmos, VDD, GND, In and Out  Refer to the following schematic to insert desired components.

 To name a component (nmos and pmos), highlight the component, then right click and select “Name Instance: -> Manual” at the Instance menu.  Key in the new component name in the “New Value” column at the bottom of the window. Name the components as shown (M1, M2).  When done, click “OK”.  Click “OK” at the bottom of the window when done.  Repeat the same procedure for the nmos.

(b)Add wires  Unselect everything by pressing “F2”. To add wire/net, click the right mouse button, in the “ADD” menu, choose “Wire”.  To add a wire between 2 points, click once on the starting point, move the cursor to the other point, and double click.  To exit from this adding wire function, press “Esc”.

6 (c) Name ports/nets  Unselect all first (by pressing “F2”), then select the net (yellow line) to be named by dragging the cursor across the net. The net will be highlighted.  Right click and choose “Name Nets” from the “NET” menu.  Key in the new net name in the “New Value” column at the bottom of the window. Name the nets as shown (input, output).  When done, click “OK”.

Check Schematic  After the schematic is captured, you need to check the schematic to make sure there are no errors on it.  At the main menu, click on File -> Check Schematic.  Check to see if the process passed or failed. Notice that at the bottom of the window, it reads “inverter/schematic/sheet1 passed check”  If schematic check failed, fix the schematic accordingly by referring the log window. Otherwise, the log window can be closed. This can be done by clicking on the middle mouse button and dragging it towards the left and let go.

Generate Symbol  Next is to generate a symbol to represent the design.  Click on Miscellaneous -> Generate Symbol from the main menu.  At the “Generate Symbol” window, choose the options (default) as shown below:  Component Name: newhome/shome/DIC**/project/schem/inverter  Symbol name: inverter  Replace existing? No  Once generated … Edit Symbol  Activate symbol? No  Choose source: Schematic  Schematic Name: schematic  Pin Spacing: 2  Sort Pins? No  Click “OK” when done.  The symbol generated will be seen.  To check the symbol, click on File -> Check Symbol at the main menu.  Check to make sure the symbol passed check at the bottom of the window.  Close the log window. Hold on to the middle mouse button, drag it to the left and let go.  Save the symbol by clicking File -> Save Symbol -> Default.  Notice that once you have save the symbol, one of the pins of the symbol will be highlighted.  Close the symbol window. Hold on to the middle mouse button, drag it to the left and let go.

Save schematic  To save the schematic, click on File -> Save Sheet -> Default or you can also click on the blue diskette tab at the main menu.

7  After saving, you can close the schematic window by holding on to the middle mouse button, dragging it to the left and let go.

Simulation

Creating a testbench  What you need to do next is to create a testbench graphically. This testbench is used to create stimulus to simulate your inverter.  Click on “Schematic” at the palette on the right.  In the “component name” column, change the “inverter” to “inverter_tb”. This is to create another schematic file with the name inverter_tb. Click on “Editable” option and click “OK”.  An empty schematic window pops up. The first thing you need to do is to instantiate your inverter design in the testbench.  Click on “Add Instance” on the palette on your right.  An “Add Instance” window pops up. Select the “inverter” which is the inverter symbol that you have designed earlier.  Click on “OK”.  Move your cursor to place the instance in the schematic sheet.  After placing the inverter, click on “Library”.  Components you need to add to the test bench are:  VDD, DC, GND and PULSE  Refer to the following to insert the components and to connect the wires.

 To modify the DC source, unselect everything first by pressing “F2”.  After that, click on the DC source and it will be highlighted. Then, right click and select “Properties -> Modify Multiple”.  A “Modify Editable Properties” window pops up. On the “DC” column, change value to “5V”. Then, click on “OK”. Notice that “Mag=1V” in the DC source is now changed to “Mag=5V”.

8  To modify the PULSE source, unselect everything. Then, click on PULSE and right click. Select “Properties ->Modify Multiple”.  When the “Modify Editable Properties” window pops up, change the data to the following:  delay: 1ns  initial_value: 0V  INST: I$2 or V1 (or any default name)  period: 50ns  pulse_value: 5V  t_fall: 1ns  t_rise: 1ns  width: 20ns  Click “OK” when done.  To name the nets (input, output), unselect everything first. Select the net to be named and it’ll be highlighted. Right click and select “Name Nets”.  Key in the net name (input or output) in the “Property Value” column at the bottom of the window.  After creating the testbench, you now need to check the schematic of the testbench to make sure it is correct.  To check schematic, click on “File ->Check Schematic” from the main menu.  Once passed, save the schematic by clicking on “File -> Save Sheet ->Default” or the blue diskette tab.

Simulation mode  Click on “Schematic” at the “ic library” palette on your right.  Next, click on arrow key on the “Simulation”  The schematic of the design pops up.  At the palette on your right, click on “Session -> Simulator/Viewer. The “Setup Simulator/Viewer” window pops up. Change the working directory for running simulations to your schematic folder. e.g. /newhome/shome/DIC**/project/schem/inverter_tb Then, in the “Viewer” column, select “Xelga” or “EZwave”. Click “OK” when done.  Click on “Session -> Netlister” at the palette.  A “Setup SPICE Netlister” window pops up. At the “Set Node 0” column, key in “GND VSS”. This tells the netlister that any nodes with the name GND or VSS is the ground. Click “OK” when done.  Click on “Lib/Temp/Inc -> Libraries”. A “Set Library Paths” window pops up. At the “library path” column, key in (or browse) the path “/EDA/Mentor-training- ADK/technology/accusim/tsmc035.mod”. Click “OK” at the bottom of the window.  Click on “Analyses” and a “Setup Simulation Analysis” window pops up. Choose “Transient” and click on “Setup”. A “Setup Transient Analysis” window pops up. Change the stop time to “300ns” and time step to be “1ns”. Click on “OK” for both pop up windows.  Click on “ADK Sim Palette”. Click on “Probes” and select “TRAN” for the Analysis Type. Click “OK”.

9  After setting the probes, you are now ready to run simulation. Go back to the default menu by clicking on “Default Sim Palette”.  If you click on “Netlist”, the tool will generate the spice netlist for your design. However, you can just click on “Run Eldo”. This option will automatically run the netlist option and then simulate.  Take note that 2 window pops up, one to generate the netlist and the other to simulate.  Make sure if your simulation is successfully done. Notice that at the bottom of the window, it reads “Simulation completed successfully”. When simulation is successfully done, you can just hit “ENTER” to close the two pop up windows.  If your simulation fails, end your simulation by clicking “End Sim” and do the corrections on your schematic, before repeating the whole simulation process again.

View simulation result  If your simulation is successfully done, you’ll be able to click on “View waves” on the palette on your right.  Depending on what you’ve checked, either Xelga or EZwave will be invoked.  Check your waveform.

Exiting the Design Architect IC (DA-IC) session  If you are still in the simulation mode, click “End Sim” at the palette on your right.  From the main menu, you can exit by clicking “MGC ->Exit” and you will return to the terminal window. Note: Do not close the terminal window before exiting from the DA-IC session.

10 LAB GUIDE VLSI2: Circuit Layout, DRC, LVS, PEX

Create project folder  Previously, you have created a schem folder for your schematics files. Now you need to create another folder to store layout files.  Open a terminal window, by right clicking the mouse at your desktop. At the command shell, go into your project directory and make a layout directory as follows: Type: cd project then click ENTER. Type: mkdir layout then click ENTER

Create sdl viewpoint from schematic and generate netlist for LVS  The inverter schematic has been drawn in the first lab. Now, you need to create an sdl viewpoint from the schematic.  Open the schematic diagram using the Design Architect IC. From desktop, right click to open a new terminal. At the command prompt, type: “da” and key in option: “2”.  Like what you did in your first lab, setup the working directory. Click on “MGC -> Location map -> Set Working Directory”. At the “Directory path” column, set the working directory to schematic directory: /newhome/shome/DIC**/project/schem Note: DIC** is your username (e.g. DIC12). Usually, “/newhome/shome/DIC**” appears by default.  To open the schematic you’ve created in your previous lab session, click on the “Schematic” option on the palette on your right. At the “Component name” column, type in the path which stored your inverter schematic, e.g. “/newhome/shome/DIC**/project/schem/inverter”. Click on “Editable” option and click “OK”.  Now you should be able to see your inverter.  Next, click on “Simulation” palette  The schematic of the design pops up.  Now, you’ve automatically created an SDL viewpoint to do your layout.  To generate a new netlist to be used in the LVS (Layout Versus Schematic) process, click on “Session -> Netlister” at the palette.  A “Setup SPICE Netlister” window pops up.  This time, choose the “LVS” option in the “Output Type” column.  Check “Wrap Netlist in .subckt” option.  Again make sure the “Set Node 0” is specified: GND VSS  Click “OK” to close the dialog. Then, click on execute “Netlist” at the palette on your right to generate the netlist. The new netlist is then generated.  Note that the tool will inform you that the netlisting completed successfully at the bottom of the window.

11  Exit to the command shell (terminal).

Layout design

Setup  To draw layout, invoke IC Station at the command shell. Type: ic  Choose the ADK Design Kit by keying in “2”.  You need to setup the IC Station. Select “Setup -> New Windows” from the main menu.  Check the “Snap Grid On” option.  Specify the grid setting o Snap: X = 0.05 Y = 0.05 o Minor = 2 Major = 20 o Offset: X = 0 Y = 0 o Drawing cull = 5  Click “OK” when done.  You should now setup the working directory. From the main menu, click on “MGC -> Location map -> Set Working Directory”. Set the working directory to the layout directory just created earlier: /newhome/shome/DIC**/project/layout

Import design from schematic  Since the inverter schematic has been drawn in the first lab, we are going to create an SDL (Schematic Driven Layout).  Click on “Create – SDL” in the “Session” palette on your right.  At the “Logic Source”, select “EDDM Viewpoint” button.  Select the component to be imported by clicking on “Browse…” button at the “Path to Viewpoint” column.  Browse to “/newhome/shome/DIC**/project/schem/inverter/tsmc035a”. Click “OK” to close the browse window.  Specify the “Layout Directory” as “/newhome/shome/DIC**/project/layout”  Specify the “Process Name” as “EDA/Mentor-training- ADK/technology/ic/process/tsmc035”  Specify the “Rules File Name” as “EDA/Mentor-training- ADK/technology/ic/process/tsmc035.rules”.  Click “OK” to proceed.  2 windows will be opened in IC-Station – the schematic and the layout.  Resize the windows so that you can see both of them. A simple way to do this is to select “Setup -> Session” from the main menu and click on “Left Right Tiling”. Click “OK”.  Click on “DLA Layout” at the “IC Palettes” on your right. Then click on “Place -> AutoInst” at the palette.  The SDL will generate the nmos and the pmos. The details of the devices are stated at the bottom of the window when you click on them. To unselect a highlighted device, press “F2”.  To get a better view of the whole layout, you can zoom out the view. This can be done by holding the middle mouse button and make a short stroke movement to upper right.

12  You can see yellow lines connecting the devices. They are called overflows. These are the connections (using metal or poly layer) you need to make.  The devices generated by SDL are instances. This means the device is not flat. Try to peek inside the devices by using the peekdown stroke. Hold the middle mouse button and make this stroke.

 The contacts (yellow squares) inside the nmos/pmos becomes visible.  You won’t be able to edit the nmos/pmos because it is an instance generated based on the schematic.  To unpeek, hold on the middle mouse button and make this stroke.

 The following figure (in the next page) shows a screen shot of what you suppose to get when you peek into the nmos and pmos.

Layout editing  From the main menu, select “Other -> Layers -> Show Layer Palette”. A Show Layer Palette window pops-up. Select the following layers to be added to the layer palette by pressing Ctrl and left mouse button. metal1.port p_well n_well poly metal1

 The layer palette should appear on the top-right side of the window.  Switch the “DLA Layout” session at the palette on your right to “IC Palettes” by clicking on the “Top” icon.  We can now begin drawing the layout.  There are many ways to draw layout, using Expert Edit or Easy Edit. Click on “Expert Edit” in the “IC Palette”.

13  To draw a path (metal or poly), click “PAT+” in the “Expert Edit” palette, then click the layer to draw, eg. metal1, from the menu above the “Expert Edit” palette.  Move your cursor to the starting point of your path in the layout window and click once. An “ADD PA” window appears at the bottom-left. Click on “Options”. The width of the path can be specified here. Enter “3” for width. (which means the width is 3 lambda in size)  Back to the layout window and try placing the path. Click once to make a corner and double click to complete the path.  To unselect highlighted objects, press F2.  Press ESC key to terminate commands that are still active.  You can try using the other commands in the Expert Edit palette. Try COP+ (copy), NOTC+ (notch, add or remove a portion of a polygon), SLI+ (slice), MOV+ (move), MVED+ (move edge), etc.  The Expert Edit commands are listed below: o Select AR+ area GR group ED+ edge o Unselect AL all ED+ edge ALED all edge GR group o Add SH+ add shape CE* add cell PAT+ add path VIA* add via TE* add text DEV* add device PR* add property PAN* add panel PRT* add property text RU+ add ruler LAY set IC layer ASP set aspect WID set path width GRID set grid o Edit COP+ copy MVED+ move edge FIL+ fillet NOTC+ notch FLI+ flip ROT* rotate MOD+ modify centerline SLI+ slice MOV+ move ALGN align STR+ stretch CUT/S+ cut/stretch MEAS* measure PRO protect UNDO undo UNPR unprotect DEL delete Rpt* repeat

 The following figure shows the connections of the inverter layout that you supposed to draw.

14  Make sure you have enough space in between the nmos and pmos in order to be able to place the poly contacts in between them. To move either the nmos or pmos, select either one component, right-click and click on “Edit -> Move -> Vertical”.  To add a poly contact (poly to metal1), place the cursor anywhere in the layout window and type “pc” then press “ENTER”. A poly contact is automatically generated. Select all layers of the poly contact and move it to its respective place.  Add a poly layer (red layer) from the nmos to the poly contact. Repeat for the pmos.  Using Metal 1, connect the outputs together. Metal 1 width should be 3 lambda.  Also connect the poly contacts of the two transistors with Metal 1.  To generate a p-Well contact, type “pwc” and press “ENTER”. The PWC is an instance. To look at layers inside it, unselect all (by pressing F2), use the middle mouse button to perform a stroke on the PWC:

 This will “peek” inside the device. The contacts inside the device become visible. You are not allowed to edit the instance.  To “unpeek”, perform unpeek stroke:  Next, generate the n-well contact. Type “nwc”. Press “ENTER”.  Place the n-well contact and p-well contact accordingly.  Now, place the VDD and GND lines. Use Metal 1 but make the width wider now. Eg 10 lambda. Make sure the Metal 1 covers all of the n-well contact and p-well contact.  The source of the pmos is tied to VDD while nmos goes to GND.  Add the n-well and p-well accordingly to the layout diagram shown.  To label a net, select “TE*” in the palette. In the ADD TE window that comes up, click on “Options”. Select metal1.port, then click OK.

15  In the ADD TE box, enter the net name (eg. VDD) and then click OK.  With the cursor, click at where you want to place the text (eg. VDD metal1 layer). The text must be within the Metal1.  Once the text is placed, you can still edit the text. Place the cursor at the text and press SHIFT-F7. A Change Text dialog appears. The value, height, and justification of the text can be modified.  Repeat the same steps until all VDD, GND, input and output nets are named. Make sure that the names are same as the ones you named in your schematic. Note: select metal1.port layer if the layout metal connection is metal1 layer.  When the layout of your inverter is done, save the cell by clicking on the “blue diskette” tab from the main menu. Note: Whenever you close the layout window and reopen back your layout, you have to press “CTRL-M” (to reserve the cell) before you can do any editing.

Design Rule Check (DRC)  From the main menu, select “Calibre > Run DRC”.  If this is the first time Calibre is invoked, the software will request to specify the Calibre home directory. Browse to “/EDA/ixl_cal_2008.2_33.26”. Then, click “OK”.  The Calibre Interactive window appears. It will ask to Choose Runset File. Click on “OK”. Runset file is a setup file. When Calibre is used, the user needs to specify some settings. User can then save this setup in a runset file, so that the settings can be reused the next time.  In the “Calibre Interactive – hmDRC” window, click on “Rules” tab.  Browse the rules file from “/EDA/Mentor-training-ADK/technology/ic/process” directory and select the file: tsmc035.rules.  Specify the “Calibre-DRC Run Directory” as “/newhome/shome/DIC**/project/layout”.  When the necessary Rules File and Calibre-DRC Run Directory have been specified, the Rules tab turns green.  Click on the “Inputs” tab. Select “DRC(Flat)” option.  All the setup is done now. Click on “Run DRC”.  DRC Summary Report is shown, scroll through to view the report.  Another window shown is the RVE (Result Viewing Environment) window. This window shows DRC errors.  If there is no DRC error, the DRC report will indicate there is 0 DRC Results generated and you’re done.  If there are errors, click on the error to see the details. Double click on the DRC error will highlight the error in layout window.  You can automatically zoom in the DRC error. At the Calibre DRC RVE window, select “Setup->Options” from the main menu. Click on “Zoom cell view to highlights by:”. Enter a number (e.g. 0.7). This is the zoom ratio. Click OK to close. Double click on an error to see the zoom in.  Fix all the DRC errors accordingly.  After editing, save the cell and rerun the DRC. This is done by going back to the Calibre DRC and click on Run DRC again. When prompted to Overwrite Layout File, click OK.

16  As mentioned earlier, runset saves the settings for running Calibre DRC. Save the runset file by selecting “File -> Save Runset As” from the Calibre Interactive’s main menu. You can pecify the runset file as “/newhome/shome/DIC**/project/layout/drc.runset”.  Close the RVE and Calibre DRC windows.  The next time you need to run the DRC on the design, just invoke the Calibre DRC and choose the runset file you saved earlier. All the settings done earlier are preserved.

Layout Versus Schematic (LVS)  We will now proceed to LVS. We will be comparing the netlist from the schematic (which you have generated earlier) and the netlist from the layout (which will be automatically generated).  In IC-Station, invoke Calibre LVS by selecting Calibre -> Run LVS from the main menu. (If needed to specify the Calibre home directory, browse to “/EDA/ixl_cal_2008.2_33.26”)  For Runset, select New Runset.  Click on the “Rules” tab. Specify the Calibre-LVS Rules file as “/EDA/Mentor- training-ADK/technology/ic/process/tsmc035.rules”, which is the same as DRC rules file.  Specify the run directory as “/newhome/shome/DIC**/project/layout”.  Click on the “Inputs” tab. Select “Layout vs Netlist”.  Then click on the “Netlist” tab in the same window. Specify the schematic netlist to be used in LVS. The file should be “/newhome/shome/DIC**/project/schem/inverter/tsmc035a/inverter_tsmc035a.spi ”.  At the “Outputs” tab, check “Generate data for xRC”. This option is needed in the next section for parasitic extraction.  Click on “Run LVS”. Click “OK” when asked to overwrite.  Once completed, the LVS Report and the RVE windows will appear.  Take a look at the LVS Report. If you see a big X, it means there are errors.  The RVE window is useful to debug the layout. Click on an error, an explanation will appear at the bottom pane. To debug, right click near the error and select Highlight Net. The IC-Station will highlight the respective net.  Try fixing all the errors and rerun the LVS by simply click on Run LVS.  After modifying the layout, remember to run DRC again. Make sure your layout is DRC and LVS clean.  Remember to save the LVS runset file similar to the DRC runset file. You can specify the runset file as “/newhome/shome/DIC**/project/layout/lvs.runset.  Close the LVS Report, RVE, and Calibre windows.

17 Parasitic extraction Parasitic extraction is after DRC and LVS checking. The purpose of parasitic extraction is to extract the parasitics (R & C) from the circuit layout.  Make sure that your layout is DRC and LVS clean.  In IC-station, invoke LVS: Calibre -> Run LVS  Add the rules file and run directory  Setup your LVS inputs for layout like you normally do for LVS  Setup your LVS inputs for netlist like you normally do for LVS – specify where your spice files are.  In the output window, click on “Generate data for xRC or xCalibre” tab.  Click on “Run LVS” tab  When your LVS is clean, it will generate a “_tsmc035.rules_” file in the working directory. (the file is needed for RC extraction)  From the IC station menu, Calibre  Run PEX. The PEX screen pops up.  In the “Rules” choose the “_tsmc035.rules_” file that is generated when LVS is clean.  Setup the run directory  Click on the “Inputs” tab. Setup the layout options similarly to what you normally setup for LVS.  Choose “Calibre-xRC” for extraction.  Setup netlist options.  Click on the “Outputs” tab.  Choose “RC” and “Distributed” for extraction type.  Choose the “Names:” as “LAYOUT”  Choose the format as “HSPICE”  Enter a name for the output netlist file e.g. “inv.pex.netlist”  Click on “Run PEX”. This will start RC extraction.

Re-simulate the design with the parasitic data.