Reviewing the Three-Bus System Architecture

THE 8086 HARDWARE

REVIEWING THE THREE-BUS SYSTEM ARCHITECTURE

A microprocessor endlessly follows the sequence:

1. Fetch the next instruction in sequence from memory . 2. Execute the instruction. 3. Go to step 1 .

There are five unique operations or bus cycles possible:

1. Memory read 2. Memory write 3. I/O read 4. I/O write 5. Bus idle (internal operation not requiring access to memory or I/O)

Bus Cycle Timing

Figure 6.1 illustrates bus cycle timing for the four active bus cycle types. Each cycle begins with the output of the memory or I/O port address during the T1 clock cycle. For the 8086 this can be a 20-bit memory address, a 16- bit indirect I/O address (using register DX), or an 8-bit direct I/O address. The parallel lines indicate that some of the lines are assumed to be high and others low. Examining the address lines only, it is not possible to determine if this is a memory or an I/O address. Neither can you tell the direction of the data flow. For this reason a control bus is required. As shown in Fig. 6.1, this bus consists of the four active-low signals

1. MEMR 2. MEMW 3. IOR 4. IOW

FIGURE Read and write bus cycle timing for the 8086 and 8088 microprocessors. Each bus cycle requires four T states.To see how the three buses shown in Fig. 6.1 work together, consider the sequence of events that occur during a memory read bus cycle.

T1. The processor outputs the 20-bit memory address. The data lines are open circuited and all control lines disabled.

T2. The MEMR control line is driven low. The memory unit recognizes this bus cycle as a memory read and prepares to place the addressed byte or word onto the data lines.

T3. The microprocessor configures its data bus lines for input but takes no further action. This state is provided primarily to give the memory time to “look up” the data byte or word .

T4. The microprocessor now expects the data to be on the data bus lines. Therefore it latches the contents of these lines and releases the memory read cont signal. This marks the end of the bus cycle.

The most important point to note is that the microprocessor controls all the bus timing. The memory must be able to supply the selected data byte or word by the time MEMR goes high during the T4 state. If it cannot do so, the CPU will read random information on the data bus lines. This will lead to unpredictable results.

Example 6.1

Describe the contents of the address. data, and control bus lines when the instruction MOV [1000H],BX is executed. Assume that register DS = 09D3H and register BX = 1234H.

Solution The instruction requires a memory write to location 1000H of the data segment. In this case the physical address is 09D30H + l000H = 0AD30H. This 20-bit address will

be placed on the address lines. The control bus signal MEMW will go low during T2 and the data bus will contain 1234H, the contents of register BX. The memory is assumed to latch this data word by the time MEMW returns high in the T4 state.

 Only one control signal can be active at a given time. The processor cannot read from its memory at the same time it is outputting to an I/O device, for example.

1. During an instruction fetch a ______bus cycle is performed. 2. Execution of the instruction OUT DPORT ,AX requires a(n) ______bus cycle. 3. Under what conditions will the 8086 buses be idle? 4. U sing a logic analyzer the three buses of an 8086 microprocessor are recorded at a particular instant. Addres bus: 47000H Control bus: MEMR = 0, MEMW = 1, IOR = 1, IOW = 1 Data bus: F3C0H

Explain the type of bus cycle occurring.

8086 CPU Pin Descriptions

The 8086 has:  20-bit address bus  16-bit data bus  17 pins devoted to control and timing

Time multiplexing : a circuit pin has more than one function. For example the 8086’s 16 pins (labeled AD0 – AD15) serves as address lines during the T1 clock state, but become data lines during T2- T4 state. A special “ demultiplexing” circuit is required to extract the separate data and address lines. Using time multiplexing the pin breakdown becomes  16 data and address pins  4 address (and status) pins  3 power pins  17 control and timing pins

Data bus (AD0-AD15). These 16 pins form the CPU's bidirectional data bus. These lines are valid only during the T2 through T4 clock states. During T1 they hold the low 16 bits of the memory or I/O address.

Address bus (AD0-AD15 and A16/S3-A19/S6). These 20 pins correspond to the CPU's 20-bit address bus and allow the processor to access 1,048,576 unique memory locations. These output lines are valid only during the T1 state, switching to become the data and status lines during the T2- T4 clock states.

Address latch enable (ALE). The signal output on this pin can be used to demultiplex the address, data, and status lines on AD0-AD15, A16/S3- A19/S6, and BHE/S7. Figure 6.3 illustrates the (minimum mode) timing for read and write bus cycles. Every cycle begins with an ALE pulse during the T1 clock state. The 20-bit address is guaranteed to be valid when ALE switches from high to low near the end of T 1. Therefore, this signal can be used to strobe the address into a latch.

Figure Simplified 8086/8088 write bus cycle.

Figure Simplified 8086/8088 read bus cycle.

Memory/IO (M/IO). The 8086 does not output separate memory and I/O read and write signals. Instead, the M/IO signal is output early in the T1 state and identifies the current bus cycle as a memory (M/IO = 1) or I/O (M/ IO = 0) operation.

Read (RD). This active-low output signal indicates that the direction of data flow on the bus is from memory or I/O into the processor. It can be combined with M/IO to form MEMR and IOR control signals. It is output during the T2 state and removed during the T4 state. The memory or I/O device is assumed to have placed the addressed byte or word onto the data lines by the time RD returns high.

Write (WR). This signal is the counterpart of RD and indicates that data is to flow from the CPU to memory or to an I/O device. In either case, the data is output during the T2 state. This gives the memory or I/O plenty of time to latch the data byte or word before WR is removed during T4. The figure shows how RD, WR, and M/IO can be combined to generate a conventional four-line control bus.

Clock (CLK). All events in the microprocessor are synchronized to the system clock

Status (A 16/S3-A19/S6 and BHE/S7). These five status signals are output during states T2- T4. They are intended primarily for diagnostic testing purposes.

Bus high enable (/S7). This signal is multiplexed with the S7 status indicator. It is output only during the T1 state. When BHE is low, it indicates that AD8-AD15 are involved in the data transfer. This can occur for memory or I/O word accesses or when accessing a data byte from an odd address. BHE and A0 are typically used to select even or odd memory banks or I/0 ports.

BHE A0 Action 0 0 Access 16-bit word 0 1 Access odd byte to D8-D15 1 0 Access even byte to D0-D7 1 1 No action

Data transmit/receive (DT/R). This signal is intended to control the direction of data flow through the buffers (if any) connected to the system data bus. When low it indicates a read operation, and when high, a write operation.

Data enable (DEN). This signal is intended to be used with DT/R to enable a set of bidirectional buffers connected to the system data bus. It prevents bus contention (two circuits attempting to drive the same bus line) by disabling the data bus buffers until the T2 state, when the address/data lines no longer hold the memory or I/O address.

Minimum/maximum mode (MN/MX)

RESET When pulsed high this input causes the 8086 to terminate its present activity and perform a reset sequence. The status of the "old" job is lost. RESET is normally used when first starting the system or after a system crash.

TEST This input is used together with the WAIT instruction. If the TEST input is high when the W AIT instruction is encountered, execution of the program is suspended and the CPU enters an idle mode. Only when TEST returns low will execution resume (with the instruction following WAIT). Normally, this input is driven by the 8087. WAIT is then used as a prefix to those 8086 instructions that reference data operated on by the 8087. This prevents the CPU from accessing a memory result before the NDP has finished its calculation .

READY The READY input is sampled on the rising edge of the T2 clock pulse. If this line is found low ("not ready"), an extra T3 state is inserted by the processor. The cycle repeats until the READY input is found high. The READY input is usually driven by a slow-memory device that cannot supply data as fast as required with normal CPU timing .

Interrupts (INTR, NMI, and INTA) INTR and NMI are hardware-initiated interrupt requests that function exactly as software interrupts

Hold and hold acknowledge (HOLD and HLDA). HOLD is an active-high CPU input that causes the processor to open circuit all of its bus lines. This effectively disconnects the CPU from its memory and I/O, allowing a second processor to access these devices. This is referred to as direct memory access (DMA). HLDA acknowledges the DMA request to the DMA controller.

Power and ground (Vcc and GND). The 8086 requires a single +5 V power source and has two ground pins.

CPU state following RESET Flags Clear IP 0000h CS FFFFh DS 0000h SS 0000h ES 0000h Queue Empty