Homework for Chapter 3

[Write your answers on a separate sheet of paper. Copy and paste any tables that you need to complete.] 1. Design a circuit to compute the even parity function, E, on 3 variables, A, B, C. This parity function guarantees that the number of ones in A, B, C, E is always even. a. Build truth table b. Write the corresponding Boolean expression c. Draw the circuit

2. Prove that the lower diagram of Fig 3-4b implements (A AND B) a. Using a truth table b. Using laws of Boolean algebra

3. Implement a circuit that outputs a 1 if the 3-bit input, A, B, C, is less than 3. Use only NAND gates. Show the truth table and the diagram. Hint: first design the circuit as a sum of products, then transform into NAND only.

4. Draw the circuit for the following function: F=(A+B)(A+B’)(A’+B). Then transform it using only NOR gates

5. Implement the even parity function for 3 inputs, A, B, C, using a multiplexer.

6. Draw the logic diagram of a 2-bit encoder, a circuit with four input lines, exactly one of which is high at any instant , and two output lines whose 2-nit binary value tell which input is high. Hint: first draw the truth table (only 4 lines); express the high-order and low order bit separately as an OR of the relevant inputs.

7. Assume that the multiplexer in Fig. 3-11 is to be implemented using: a. Only NAND gates b. Only NOR gates How many gates are necessary in each case?

8. Implement a comparator for two 2-bit numbers A and B using only AND, OR, NOT gates. Hint: Ignore the design of Fig. 3-14. Draw the truth table for the four inputs and one output and design as canonical sum of products. 9. Implement a 2-intput multiplexer using a PLA. Draw the smallest possible PLA necessary. Cross out the fuses that are blown to implement the circuit.

10. Implement a 2-to-4 decoder using a PLA. Draw the smallest possible PLA necessary. Cross out the fuses that are blown to implement the circuit.

11. Using an 8-output demultiplexer, implement a 3-to-8 decoder. Hint: no additional gates are necessary. 12. Using a 4-input multiplexer, implement: a. An OR gate b. An XOR gate c. A NAND gate

13. First modify the shifter circuits shown below to have only 3 inputs and 3 outputs. Then modify this reduced circuit to perform a circular shift. That it, on a right shift the rightmost bit D2 goes to S0, and on a left shift the leftmost bit D0 goes to S2

14. Draw a 4-bit right shifter circuits (not circular) to perform as follows:  When C=0 it shifts the input right by ONE bit  When C=1 it shifts the input right by TWO bits

15. Implement the full adder circuit using a PLA. Hint: Ignore the optimized circuit shown in the book. Use only the truth table and implement the Sum and Carry out as canonical sums of products. 16. Consider the 1-bit ALU shown in the book. Complete the table below by specifying the outputs (Out and Cout) for the various inputs. Assume that both A=1 and B=1.

F0 F1 ENA ENB INVA Cin Out Cout 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0 1

17. Consider again the 1-bit ALU. Complete the table below to implement the desired function. (Note: A’, B’ means 1’s complement; -A means 2’s complement) function F0 F1 ENA ENB INVA Cin A + B A + 1 -A A AND B A A’ B’

18. Consider the 8-bit adder shown below. Complete the table by specifying the output for the various inputs (all in hexadecimal).

A B F INC O 3C 19 0 0 3C 19 1 0 3C 19 2 0 3C 19 3 0 3C 19 3 1 3C 19 2 1

19. Consider a simple SR Latch. Given the values of the two inputs S and R at each time interval t, fill in the corresponding values for the output Q t 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S 0 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 R 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 Q 0

20. The 4x3 memory shown in the book uses 22 AND gates and three OR gates. If the circuit were to be expanded to 256x8, how many of each would be needed?

21. Assume that Q=1 for all flip flops in the following 4x3 memory. In the diagrams below, mark all gates that will be outputting a 1 given the following sets of inputs: CS OE RD A0 A1 (a) 1 1 1 0 1 (b) 1 1 0 0 1 (a)

(b) 22. Referring to the timing diagram for a synchronous bus, suppose that the clock is slowed down to a period of 20 nsec instead of 10 nsec but the timing constraints remained unchanged. How

much time would the memory have to get the data on the bus during T3 after MREQ/RD were asserted?

23. Assume that a block transfer is done using the timing constraints shown for the synchronous bus in the book. How much more bandwidth is obtained by using the block transfer over individual word transfers?