Cpe 471 - Computer Communications I: Systems Analysis

CpE 448: Introduction to VLSI Design Fall 2010 (Either Cpe447 or Cpe448 is Required)

2008-2010 Catalog Data: CPEG 448 - Design and implementation of very large scale integrated circuits. CMOS and BiCMOS technologies, basic topological structure of ICs. Clocking characteristics, resistance, capacitance and power estimation, system level design and implementation issues. Custom layout and verification using CAD tools. Synthesis of designs from VHDL descriptions. Term project will include the design and testing of a custom integrated circuit. 3 lecture hours, 3 semester hours.

Prerequisites: CPEG 315 and EE 348

Textbook : “CMOS VLSI design : A Circuits and Systems Perspective”, by Neil H E Weste, David Harris; Addison-Wesley, 2005

Course Learning Outcomes: Having successfully completed this course, the student should be able to:  Students will be able to design a complete digital VLSI chip ranging from its digital design to its simulations, and CMOS layout.  Students will be able to design CMOS digital circuits and optimize their layout for less delay.  Students will be able to design and simulate complex digital designs in VHDL and Verilog.  Students will be able to estimate the resistance, capacitances in VLSI circuits so that they can optimize delays, and power consumption.  Students will be able to design, layout, simulate and verify actual VLSI circuits using modern tools such as Mentor Graphics.  Students will demonstrate Engineering design skills.  Students will exercise written communication skills in terms of technical writing.  Students will be able to function competently in a related entry-level career.

Topics (by week): o Review of Digital VLSI Circuit Design technologies (1 Week) RTL, DTL, TTL, ECL, NMOS, PMOS, CMOS, and BiCMOS technologies. Digital Gate structures in different technologies, Comparison of different digital circuit technologies based on Noise margins, fanouts, power consumption, rise/fall delays. Identifying characteristics of an ideal digital circuit technology. o MOS transistor theory (1 Week) MOS transistor fundamentals PMOS and NMOS technologies Designing gates and PLAs in NMOS technology. o CMOS technology (1 Week) Pseudo NMOS technology CMOS inverter I/O characteristics, noise margins, fanouts NAND, NOR and logic expressions in CMOS Multiplexers, decoders, latches and Master-Slave flip flops in CMOS o CMOS Fabrication technology (1 Week) N-Well, P-Well and Twin-tub processes Layout design rules in CMOS Layout of simple gates, yield calculations, Prevention against latchup in CMOS. o System Design in CMOS technology (2 Weeks) Layout of adders and flip-flops Layout of a digital system, determining pitch, routing power lines and busses using metal1, metal2. Design, simulation and layout of complex digital VLSI Circuits. o Circuit Characterization and Performance Estimation (3 Weeks) Resistance estimation MOS transistor capacitance and routing capacitance Distributed RC effects, wire length design guide Inductance calculations, delay estimation (rise and Fall delays) Gate delays and body effect minimization CMOS buffer design to optimize delay Power consumption estimation, sizing conductors Charge sharing, scaling of MOS transistor dimensions Complementary CMOS, PseudoNMOS, Clocked CMOS, CVSL, BiCMOS and Dynamic CMOS o Layout of CMOS circuits using Mentor Graphics (2 Weeks) CMOS Layout of digital gates and systems Layout verification using DRC and LVS o SPICE and VHDL simulations using Mentor Graphics (2 Week) o Discussion of example chip design projects (1 Week) Examples of digital VLSI projects, their circuit design, floorplan design, VHDL/Verilog simulations and chip layout. 10. CMOS Testing (if time permits)

Class/Laboratory Schedule: Lectures: 2 sessions per week with duration of 1hr 15min each Lab Sessions: Laboratory work is an integral part of this course. Several laboratory assignments emphasize the practical aspects of the course. Laboratory projects are implemented using Mentor Graphics VLSI design software where students do the actual layout and simulation of the digital VLSI designs. Written reports (using a word processor) are required for all labs. There is a required final project where a complete design of medium sized digital circuit ranging from simulation to complete chip layout is implemented.

Contribution to Criterion 5 Requirements: Engineering Topics 3 credits

Relationship to Program Outcomes: The course objectives help in contributing towards the following program outcomes at a beginner’s level: Program Outcome 4 Techniques/Skills: Larger projects such as chip design and FPGA implementations with simulation and verification tools Program Outcome 10 Diversity/LLL: B/D continuum is used to collect incidental/anecdotal data from representative sample of courses

Prepared by : Dr. Ausif Mahmood Date: June 23