Lab Manual: Synopsys EDA tools.
DR.RAMIN ROOSTA,
EDA-ASIC Laboratory California State University, Northridge
99 Synopsys has a full suite of tools to support high-level design. These tools are used for - - design entry, - source-level performance analysis - validation - implementation ( synthesis) - post-synthesis performance analysis - verification.
This manual deals with the brief descriptions of the design steps and Synopsys tools used to perform those steps.
ASIC Design flow:
1. Define the design requirement: In this step designer has the idea of the design objectives and requirements. Having the clear idea of the function of the design, required setup and clock-to-output times, maximum frequency of operation and the critical paths help the designer chose a design methodology and technology to which the design will be synthesized.
2. Describe the design in VHDL - design entry : Having defined the design objective and requirements, designer describe the design using VHDL code in any text editor such as pico, vi, emacs etc. The key to writing good VHDL code is to think in terms of hardware.
3. Analyze the design: After writing the code, designer analyze the code to check the syntax and semantic errors. Design have to be fixed and modified until it error free.
3. Simulate the source code: After the design has been captured in HDL, it is essential to verify that code matches the required functionality prior to synthesis. This step is called pre- synthesis behavioral simulation of VHDL which is done to validate the functionality of the design. Using simulation tool, this can be performed by simply assigning specific values to input signals, performing simulation runs and viewing the wave-forms in graphical wave view tool. An alternative is to write a test-bench. The test- bench can be considered as an HDL block whose outputs provide the stumuli (test data) for the design to be simulated and comparing the outputs with the expected results.
4. Synthesize the design: Functionally correct design description of the design is now synthesized by synthesis tools. VHDL synthesis tools convert VHDL description of the design to technology-specific netlists. Here designer presents an abstract description of his/her design, specifying the function of the digital circuit, and the synthesis software produces a netlist targeting the specified technology library. The synthesis process consists of two steps - translation and optimization. Translation involves transforming a VHDL description to gates while optimization involves selecting the optimal combination of ASIC technology library cells to achieve the required functionality.
5. Post-Synthesis/Netlist Simulation: After design is synthesized to gate-level netlist, it is simulated again using the simulator. The post-Synthesis simulation enables designer to verify not only the functionality of the design but also the timing, such as setup and hold time, clock-to-output, and register-to-register times. In order to simulate a synthesized gate-level netlist, VHDL simulation models of the technology library are required. If one has the ASIC vendor library for synthesis and the Synopsys Library compiler, the VHDL simulation models can automatically created using Synopsys “liban” utility.
6. Layout: Floorplaning, Place and Route. Tools used to perform different design steps:
1. Pico text editor:
Any text editor can be used to describe the design in VHDL. In CSUN EDA-ASIC Laboratory, pico text editor is available which is user friendly and convenient to use.
Pico text editor can be invoked by entering the following command in UNIX propt: edasunx% pico filename.vhd
2. VHDL Analyzer (vhdlan/gvan):
Translates VHDL code into an intermediate format for the VHDL Simulator use.
You can invoke the VHDL analyzer either by using following command which writes any error message to standard output:
edasunx% vhdlan filename.vhd
or by using the following command which calls vhdlan and if it finds error, displays in the VHDL Error Browser:
edasunx% gvan filename.vhd
You can use the VHDL Error browser to browse error messages from the VHDL Analyzer. When you reach an error, you click a button to invoke a text editor, fix the error and continue the analysis. you repeat this process until no more error exists.
While analyzing, you can create an error listing file selecting -I option with the command:
edasunx% vhdlan -l filename.vhd edasunx% gvan -l filename.vhd If -spc or -spc_elab options are used with vhdlan or gvan, the VHDL analyzer performs synthesis policy checking while it analyzes vhdl design against VHDL subset supported by Synopsys Synthesis tool.
edasunx% vhdlan -spc filename.vhd edasunx% gvan -spc filename.vhd
3. VHDL Simulator (vhdlsim):
This tool is used to perform functional and gate-level simulation to validate the design.
You can invoke VHDL Simulator by entering the following command:
edasunx% vhdlsim filename
VHDL Simulator enables you to: - Start and stop simulation engine. - Apply stimulus to the circuit. - Set breakpoints. - monitor signals and take conditional actions based on their values. - Show the values of registers in dedicated pad windows.
You can enter VHDL Simulation Commands at the VHDL Simulator command line (#). You can also control VHDL Simulator through the VHDL Debugger graphical user interface.
5. VHDL Debugger (vhdldbx):
The VHDL Debugger is a debugging tool for VHDL source code. The VHDL debugger is also the graphical user interface for the VHDL Simulator and it gives access to your source code.
Invoke VHDL Debugger by entering following commands:
edasunx% vhdldbx
The VHDL debugger enables you to find bugs more easily, because you have complete control over both source code and the simulation engine.
When you find a bug, you can fix it without exiting from the VHDL Simulator or the VHDL Debugger by
1. Editing the file that contains bug, 2. Re-analyze the file 3. Resuming the simulation. To simulate a design from VHDL Debugger, you can either
- Select Test bench of that design which specifies and applies stimulus to the design, Run the simulator for certain period and see the generated waves in the Wave Form Viewer by tracing those signals.
or - From VHDL Debugger, you can assign stimulus to INPUTS of the design, RUN Simulator for certain period and see the generated wave in the Wave Form Viewer by selecting commands (assign, trace & RUN) at the simulator prompt (#).
6. Waveform Viwer (waves):
` Provides a Graphical display of Signal values generated during Simulation. You can use the waveform viewer during simulation or afterwards as a stand alone tool.
You can invoke wave form viewer by entering following commands:
edasunx% waves
or from VHDL debugger by selecting `trace' for any signal.
Waveform viwer enables you to display simulation data captured in a trace data file either during of after the simulation.
7. Design Analyzer:
Design Analyzer is the graphical interface to the Synopsys family of synthesis tools.
Invoke Design Analyzer by entering following command:
edasunx% design_analyzer
Design Analyzer provides menu-driven access to most features of the Synopsys family of synthesis tools. It allows you to do the following:
Set system variable values, such as the technology library name that you want. Read and write designs in multiple formats, such as EDIF, netlist, PLA, Verilog, VHDL and equation. Set Constraints and attributes graphically on designs, cells, pins, nets, buses and clocks. View hierarchical design through level of hierarchy Synthesize and Optimize digital circuits. Generate, view and plot schematics. Highlight paths in the schematic. Generate a variety of reports.
One of the Design Analyzer menu selections (Setup/Command Window) creates a Command Window that provides access to all commands through the command line interface. Design Analyzer's Command Window shows the command-line interface. All commands and reports generated by menu selections are echoed in the command Window. You can type design Compiler (dc shell) commands in the command entry box.
To bring up the Command Window, select setup -> Command Window.
Design Analyzer Menu Bar
The Design Analyzer menu bar contains the names of the eight primary menus:
Menu Bar
- Setup:
Accesses several dialog boxes that describe Design Analyzer, set default values and variables, get and give up tool licenses (for Network Licensing users). execute scripts and display a command-line interface window.
- File:
Edits the hierarchy and can delete designs and constraints.
- View:
Controls the appearance of displayed schematics.
- Attributes:
Sets attribute values for selected objects.
- Analysis:
Links a design to its sub-designs and libraries, check a design for errors, run the timing analyzer, highlight timing paths, show HDL text from selected objects, and creates and displays reports about a compiled design. - Tools:
Calls up Design Optimization, FSM compilation, FPGA Compiler, or Test Synthesis.
- Help:
Calls up the design Analyzer Help menu. You can browse a brief summary about the tool or retrieve command information.
Some of the menu selections from Design Analyzer in Design Cycle:
Here are the objectives and descriptions of some menu selections from Design Analyzer we'll use in our design cycle:
Read the Design:
Selection File -> Read is used to read in one or more design description files.
Type file names in File Name(s) text box. You can also choose file names by clicking through directories and then clicking on the displayed name. In File Format option, you must select the appropriate output format from the option menu. Then click OK to read in the chosen File Name in the Current File Format.
View the Design :
The three view buttons, Hierarchy View button, the Symbol View Button and the Schematic View button, displays the corresponding view of the current design.
Design Optimization :
The selection Tools -> Design Optimization compiles the current design.
Click OK to compile the current design using displayed options. Click Cancel to remove this dialog box.
Map Design: Turn on the Map Design option to map the circuit to the current technology library during compilation.
More Map Options: Using this, you can set additional mapping options for compile command.
Verify Design: Turn on the Verify design toggle button to verify that the logical behavior of the circuit is the same before and after the compilation. Verify Effort: Choose the verification effort level you want to enable. The Verify Effort radio buttons are available when the Verify Design toggle buttons is enabled.
Allow Boundary Optimization: Turn on the Allow Boundary Optimization toggle button to allow boundary optimization during compilation.
Execute in: Define whether the compile command is to be run in foreground or in the background.
Analyze the Design:
The selection File -> Analyze reads in an HDL source file (VHDL or Verilog) and creates HDL library objects. After you make a change to an HDL source file, use analyze to read in the file and check for errors from Design Analyzer.
The top portion of the Analyze File dialog box looks like the File -> Read dialog , box. However, the File Format switch
allows you to select only VHDL and Verilog files you want to analyze.
In the lower half of the dialog box, select the HDL library for the analyze command. The work library is the default. The space beneath the library field is a list of available design libraries.
When you click on OK, a report output windows appears and displays messages generated by analyze.
Report Windows and Design Report:
Report windows display HDL input reports, compilation reports, design reports, etc.
Following is a partial list of menu selections that create report windows with the indicated window names:
Analysis -> Link Design (Link Report) File -> Read (Verilog or VHDL) Tools -> Design Optimization (Compile Log) Tools -> Test Synthesis -> Create Vectors (Create Test Vectors)
Report Dialog Box:
Selection Analysis -> Report displayes Report dialog box which generates and displays various reports in Report window for the current design
Save the Design:
The selection File -> Save is available when you have selected or are viewing a design. This selection saves the current design in Synopsys internal database (db) format as a file named design_name.db.
Plot the Design:
Use selection File -> Plot to write a design symbol view or part or all of the selected design's schematics to a file or printer in Postscript format.
8. Synopsys Design Compiler:
Design Analyzer (discussed above) is the graphical front end of the Synopsys synthesis tool. Design Compiler or DC-shell is the command line interface for the same synthesis tool. In most cases,designer begins using the graphical front end, and once they are comfortable with the commands and the Design Compiler terminology, they prefer to use the command line (dc_shell) interface. At that stage Design Analyzer is generally used only to view schematics and their critical paths.The Design Compiler command line interface can be invoked by the following command;
edasunx% dc_shell
dc_shell>
In design compiler;
Source VHDL is read into DC by read command.
Optimization constraints is specified using include command prior to compile.
Compile is performed by Compile command which executes optimization. After the read command, on executing the compile command, a netlist for the source VHDL is generated.
Compile has a number of option, including low, medium, and high. The default option is medium.
After compile, write command writes out netlist of the design in specified format. Then timing report can be generated by using report_timing command and timing constraint violation report can be generated by report_constraints -all_violators -verbose command.
Example:
Read design by design compiler:
dc_shell> read -f vhdl design.vhd
Include the constraint file:
dc_shell> include constraints.con
Compile the design:
dc_shell> compile
Write out netlist in specified format:
dc_shell> write -f vhdl design -output design_netlist.vhd
Generate report:
dc_shell> report_timing dc_shell> report_constraints -all_violators -verbose
The above design compiler commands can be issued from dc_shell command line one after another or those can be put in a script file in the same order and run that script by the following commands:
Example: design.scr
------read -f vhdl design.vhd include constraints.con compile write -f vhdl design -output design_netlist.vhd report_timing report_constraints -all_violators -verbose ------
edasun1% dc_shell -f design.scr
It first invokes design compiler then executes all the commands in the script. The constraint file constraint.con must contain required synthesis constraints.
There are two type of synthesis constraints:
a. Optimization constraint b. Deign Rule constraint.
Optimization consraint are user specified the two optimization constraint and the related dc_shell commands are as follows:
Speed: set_input_delay set_out_put_delay max_delay create_clock
To provide greater flexibility, these commands has a point- to-point optimization capabilty i.e. designer can specify timing constraints from one specific port/pin in the design to another provided such a timing path exists betn. the two points.
Area: max_area
In addition to optimization constraints, the synthesis tool is required to meet another set of optimization constraint called Design Rule constraint (DRC). DRC are constraints imposed upon the design by requirements specified in the target ASIC vendor library. These constraints and related dc_shell commands are:
Max Fanout: set_max_fanout Max Transition: set_max_transition Max Capacitance: set_max_capacitance
Example: constraint.con
------max_delay 0 -from all_inputs() -to all_outputs() set_input_delay 5 -from all_inputs() -to all_outputs() set_output_delay 5 -from all_inputs() -to all_outputs() create_clock clk -period 5 set_max_transition 5 design
Typical Sequences of Activities in a Desiqn Cycle: The following steps show a typical sequences of activities you can use in CSUN EDA-ASIC Laboratory to run Synopsys tools to complete a design cycle:
Start: You are in front of the work station.
1. Enter your login number at:
login: xxxxxxxxx
2. Enter your password at:
password: xxxxxxxx
3. After you are logged in, type op or openwin at UNIX prompt to open X-Window ( or it may be opened automatically)
edasunx% op edasunx% openwin
4. You will create separate directories for the practice design. Create one now by entering following command and go to that directory:
edasunx% mkdir practice edasunx% cd practice
5. You need a work directory for the analyzed files. Create this directory with the following command
edasunx% mkdir work
6. Open (if already exists in the working directory) or create the VHDL source code of the design.
Open existing file:
edasunx% pico filename1.vhd
Create new file: Invoke "pico" text editor by the following command in UNIX prompt:
edasunx% pico
Type the VHDL code of the design file. c. When finished, press ctrl+x to exit pico Select `Y' (yes) to save buffer Write filename with extension .vhd and press enter. 7. Analyze the source file with VHDL analyzer:
edasunx% vhdlan filename.vhd edasunx% gvan filename.vhd
If there is any error, fix it and analyze the file again. Do this until your design file code is error free.
8. Simulate the design with VHDL Simulator (vhdlsim) or VHDL Debugger (vhdldbx).
Invoke VHDL Simulator by entering following command:
edasunx% vhdlsim filename
Invoke VHDL Debugger by entering following commands:
edasunx% vhdldbx&
9. Display simulation result with interactive waveform viewer (waves).
Invoke wave form viewer by entering following commands:
edasunx% waves or from VHDL debugger by selecting `trace' for any signal.
10. Use Design Analyzer to Synthesize, Optimize, get reports, plot schematic and save the design.
Invoke Design Analyzer by entering following commands:
edasunx% design_analyzer
These are some menu-selections and buttons in Design Analyzer window you need to use in this step:
Read the design:
File -> Read
Traverse the design hierarchy:
Select Hierarchy View, Symbol View, Schematic View :buttons
Optimize the design:
Tools -> Design Optimization Generate Report:
Analysis -> Report
Plot the schematic of the design:
File -> Plot
Save the design:
File -> Save
13. Quit all open windows
14. Exit from X-window.
15. Log-off from SUN workstation by typing exit and press enter.
If you want to use design compiler, you can use that after step 9.
Finding Information:
The following sources of information are available to help you use Synopsys System:
- Set of manuals - On-line man page - On-line Manual - Simulator help command - Error messages help.
Set of Manuals: These are the hard copy of manuals available in the lab.
On-line man page: The on line man pages describe VSS family programs and command syntax. To view a man page make sure that the operating systems set up and the type
edasunx% man subject
On-line manual: Using the dialog box from Synopsys on line manual, you can find information on a any subject. Invoke Synopsys on line manual by entering following command:
edasunX% iview
Enter the subject in find box and click find. Click the appropriate topic in the list and click open.
Using help command: You can get help subject by typing following command
eadasunx% help subject
You can see a list of help subject by:
edasunx% help -l
Necessary UNIX commands:
1. ps :report status of active process 2. pstat :report system status 3. pwd :display current working directory. 4. rm filenames :remove(delete) files 5. rmdir directory :remove empty directory.-r option deletes files and sub-directories also. 6. telnet computername :access remote system. 7. tty :report name of terminal 8. uname :display name of current system. 9. pico :open pica text editor. 10. who :report active users. 11. cancel requestlD :cancel a print job. 12. cat filename.ext :display file on screen. 13. cd [directory] :change current directory to indicated directory 14. clear :clear terminal screen. 15. cp file1.ext file2.exe :copy files 16. du :report disk usage. 17. find directories :find matching files starting from 18. specified directory and 19. perform specific actions. 20. grep text files.ext :find lines in one or more files that 21. contain a particular word 22. lc :list directory contents in columns. 23. logname :get login name 24. lp, lpr file.ext :print a file 25. lpstat :list the status of all available printer 26. ls :list the files a directory 27. mkdir :create a new directory 28. more :display a file in one page on the 29. screen at the time. 30. mv file1.ext file2.ext :rename a file 31. mv file.ext directory :move file from one directory to another
32. diff file1.ext file2.ext :compare two files and the print lines 33. the files differ. 34. exit :log out 35. history 9 :list the last 9 commands you typed. 36. id :displays numeric user and group ID. 37. jobs :lists the jobs that are running. 38. kill -9 PID :kill specified job. 39. sort filename :sort the lines in a text file 40. tail filename :display last few lines of a file 41. shutdown :stop UNIX and prepare workstation to 42. turn off. 43. !! :repeat the last command 44. !find :repeats last command begin with find. 45. :repeats command #3 from history list 46. ^et^ir :repeat previous command replacing fixing et with ir
Use of wildcards ( ? and * ): In a command, you can use two wild cards, ? and * with the names.
? means any single letter * means anything at all.
References:
1. Synopsys Manuals 2. Synopsys on line documents. 3. Logic Synthesis using synopsys: Taher Abbasi