@head: Max’s Chips and Dips: A bumper issue of iDESIGN @deck: More articles and viewpoints than we can handle, and more hot news than you can swing a stick at!

@text: Good Grief Charlie Brown! Things are happening so thick-and-fast that I barely have time to draw breath these days. As you’ll see, this is a bumper issue of iDESIGN, with twice the regular number of articles and twice the regular number of viewpoints. Our problem at the moment is that we currently have so much interesting material racing in through the door that we can barely publish it fast enough!

And of course there’s more news happening than you can swing a stick at. For example, the folks at Forte Design Systems (www.forteds.com) recently announced that they have upgraded their industry-leading Cynthesizer behavioral synthesis solution to provide a more extensive production ESL design flow. Available immediately, the latest incarnation of this little rapscallion supports power estimation, formal verification, modular interface IP, FPGA prototyping, and a comprehensive design reporting subsystem.

But wait, there’s more! I’ve said it before and I’ll say it again: one of the coolest things I saw at DAC 2005 this summer was the sequential equivalency checker from Calypto Design Systems (www.calypto.com). Conventional equivalence checkers find it difficult (if not impossible) to handle logic being moved around between registers (such as in retiming), and they completely fall over on their backs of you present two versions of a design with different numbers of pipelining stages. Well, in addition to handling this type of thing, Calypto’s technology also allows you to compare designs at different levels of abstraction, such as a SystemC representation with an RTL implementation. So it comes as no real surprise to hear that Calypto and Forte have just announced plans to integrate Forte’s behavioral synthesis technology with Calypto’s equivalence checking technology.

Meanwhile, Freddy Santamaria (“The Smooth Operator”) who is the man with his finger on the pulse of EDA in Europe just informed me that the Italian company YOGITECH (www.yogitech.com) have launched a highly integrated and automated mixed-signal verification component kit that goes way beyond the limits of traditional solutions. This kit extends the most advanced functional dynamic verification techniques to analog circuits and mixed-signal designs, including concepts such as pseudo-random stimulus and coverage analysis, thereby dramatically reducing verification time and increasing verification quality.

Are you interested in using high-speed serial data communications in your FPGA designs? If so, those clever little rapscallions at Altera are hosting a free one-hour webcast at TechOnline on Tuesday October 11th at 11:00am Pacific time (http://seminar2.techonline.com/s/altera_oct1105). During this seminar, they are going to show us how external PHYs and FPGAs can provide cost- effective solutions for high-speed serial designs, and also how PMC-Sierra and Altera devices can be used to develop high-performance backplane and line interface solutions.

But, as usual, we digress … I very much hope you enjoy this issue of iDESIGN. Please email me with your thoughts and comments on the material in this issue, and also let me know if you have any ideas for technical articles or viewpoints for future issues of iDESIGN (you can drop me a line at [email protected]). Until next time, have a good one!

+++++++++++++++

By Clive (Max) Maxfield. Author of "Bebop to the Boolean Boogie (An Unconventional Guide to Electronics)" and "The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows)", Max is also the co-author of How Computers Do Math (ISBN: 0471732788) featuring the pedagogical and phantasmagorical virtual DIY Calculator. In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.