Head: High-End Chip Designs Require Sophisticated Thermal Analysis

@head: High-End Chip Designs Require Sophisticated Thermal Analysis @deck: Understanding the thermal signature of a chip, including the package-chip interaction, allows both the chip and the package-chip interface to be analyzed for potential problems.

@text: The temperature signature of a chip is greatly impacted by its package characteristics and the ambient conditions around that package. In order to correctly analyze the temperature gradients, the interaction between the chip and its external environment must be included. This means that the types of materials in the package and their thermal conductivity must be incorporated along with the physical dimensions and physical connection between the package and the chip. Once the thermal signature of the chip is known based on its package and the external environment, analysis of the physical interaction of the chip and the package can be performed. Understanding the package-chip thermal interaction requires a thorough analysis that accounts for the ambient conditions, the package characteristics, and the performance characteristics of the chip resulting in a true thermal signature of the chip.

Any physical connections to the chip – such as bond wires or bumps – can have a significant impact on the resulting thermal signature. For example, Figure 1 shows the thermal signature of a wire bond chip. Observe the dips along the outer edge of the design showing the impact of the bond wires on the thermal signature of the design. The temperature gradients created by the physical connection can cause problems, especially in designs containing sensitive circuitry near the periphery.

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The temperature signature of a chip will also be impacted by the power sources on the chip and their locations. The thermal signature in Figure 1 shows how the power source being located nearer the corner has caused the heat to be trapped at the right front corner of the chip. The heat is trapped due to the characteristics of the package including its thermal conductivity and the size of the cavity. Temperature gradients created by the position of multiple power sources on the chip are difficult to predict as illustrated in Figure 2. The position of power sources and their interaction can create hot spots on the chip and corresponding temperature gradients that require thorough analysis to predict.

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As packages become more sophisticated, the thermal conductivity of the package becomes directional such as when there are exposed pads on the package or copper plates in the package. Flip chip packages have a similar impact since they conduct heat through their bumps creating heat dissipation over more of the top of the chip. The sources of directional thermal conductivity must be properly modeled to understand the detailed thermal signature of the chip. These physical connections will help to dissipate heat from the chip, but the heat in the wires in the middle layers of metal may be trapped due to the significant difference in thermal conductivity between the dielectric and the substrate or bumps. Since heat is generated in these wires, especially supply nets, due to Joule heating, a detailed analysis is required to understand their temperature. Failure to understand the temperature of these high current wires may lead to premature failures due to electro-migration.

The detailed thermal signature of the chip can be used to understand the peak temperature and the difference in temperature between different areas on the chip. This information can be helpful in understanding the mechanical interaction between the chip and the package. The analysis of the temperature differences and changes will help in determining the potential for stress related failures.

By understanding the thermal signature of a chip taking into account the package-chip interaction, both the chip and the package-chip interface can be analyzed for potential problems. The detailed thermal signature of the chip should be used to determine potential for the impact of thermal gradients on the chip performance and reliability and also the mechanical interaction between the chip and the package. author: Kevin Moynihan, Gradient Design Automation Inc

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Captions:

Figure 1. Thermal signature of a wire bond chip

Figure 2. Thermal signature of a chip with multiple high power sources