Chapter 4 Finite State Machines

4-1 Theory of Computation

Chapter 4 Finite State Machines This section also includes Finite State Acceptors.

This section and the next on Turing Machines are concerned with deciding what a computer "can do". We have seen how to prove that a program meets a specification - we now consider whether there are some specifications which can not be met by any program.

Definitions Chapter 4 A process is a sequence of steps which if performed will result in a task being carried out. Chapter 4 An effective process (or algorithm) is a process which may be executed by a machine - i.e. a computable process.

To define the term computable there are three main approaches: Chapter 4 Abstract Machine Approach (Turing) Chapter 4 Functional Approach (Church, Kleene) Chapter 4 Symbol Manipulation (Post)

We shall look at the first two of these during this module.

The Abstract Machine Approach We have said that an alogorithm is a process which can be executed by a machine - we need a 'yardstick' machine which is Chapter 4 as simple as possible Chapter 4 sufficiently powerful to execute all algorithms which can be executed on any machine (ignoring e.g. speed contraints).

Finite State Machines (FSM) Chapter 4 At any moment, a FSM is in one of a finite number of states. Events, which are one of Chapter 4 receive an input stimulus Chapter 4 emit an output response Chapter 4 enter a new state Chapter 4 happen instantaneously at discrete time intervals. Chapter 4 Input stimuli arrive at regular time intervals from the 'environment'.

Finite State Machine M may be described by Chapter 4 M=[S,I,O,fs,fo] where Chapter 4 S is the set of States{s0,s1,s2,.., sn} Chapter 4 I is the input alphabet {0, 1, 2,..,m} Chapter 4 O is the output alphabet {0, 1, 2,..,k} Chapter 4 fs is a mapping from SxI onto S

4-1 4-2 Theory of Computation

(state transition mapping) Chapter 4 fo is a mapping from S onto O (output mapping)

The functions fs,fo may be defined in one of two ways either Chapter 4 State table or Chapter 4 State graph (state transition diagram) The action of a Finite State machine may be traced in a Chapter 4 State-Time Table

Chapter 4 Example the following FSM has

Chapter 4 S is the set of States{s0,s1,s2} Chapter 4 I is the input alphabet {} Chapter 4 O is the output alphabet {}

1 Present Next State Output 1 State Present Input 0 S /0 S /1 0 1 0 1

s0 s1 s0 0 1 s1 s2 s1 1 0

s2 s2 s0 1 S2 /1

Chapter 4 trace for input 00011010

Time t0 t1 t2 t3 t4 t5 t6 t7 t8 Input 0 0 0 1 1 0 1 0

State s0 s1

Output 0

State Graph / State Transition Diagram Chapter 4 A state transition diagrams links old states with new states, indicating any corresponding input and output. Chapter 4 A typical element is: 1 sa/1 sb/2

Note: Chapter 4 Different inputs can produce different events Chapter 4 sb could be the same as sa Chapter 4 fo(sa)= 1 and fo(sb)= 2 Chapter 4 fs(sa, 1)= sb Chapter 4 There is always an input. Chapter 4 There might be no output. State Table Present Next State Output State Present Input

 0   m

s 0 f s (s 0 ,  0 ) … f s (s 0 ,  m) f o (s 0 )

: : : :

s n f s (s n ,  0 ) … f s ( s n ,  m) f o ( s n )

Example - Parity Machine Chapter 4 This machine records whether the number of 1s received as input is even or odd. Chapter 4 Need two states Chapter 4 one records even number of 1s so far Chapter 4 the other records odd number of 1s so far Chapter 4 S is {s0 ,s1} Chapter 4 I is {0,1} Chapter 4 O is {0,1} 0 for even number of 1s 1 for odd number of 1s

Chapter 4 The initial state is s0 (as always). So Chapter 4 s0 is the even state Chapter 4 s1 is the odd state Chapter 4 Need to alter state when a 1 is read Chapter 4 Need to stay in same state when 0 is read

One Moment Delay Machine A machine which copied input to output as soon as possible would have a given input character appearing as output 1 time interval later. Chapter 4 This machine "holds on" to an input for 1 time interval, so that it becomes the output 2 time intervals later. Chapter 4 Initial 0s used to 'pad out' the output. Extra 0 used to ‘pad out’ the input. Chapter 4 These 'delay' machines may be regarded as memory machines. Chapter 4 1 time delay Chapter 4 remembers 1 binary signal - 2 states Chapter 4 2 time delay Chapter 4 remembers 2 binary signals - 4 states

To remember N binary signals requires 2N states. N binary signals are equivalent to numbers in the range 0.. 2N -1, so 2N states can store numbers 0.. 2N -1, or M states can store numbers 0..M-1.

Chapter 4 FSMs have a finite memory capability.

Example - Serial Binary Adder

This machine adds two binary numbers from right to left. Each input symbol consists of one bit from each of the two input numbers, so there are four possible inputs, 00, 01, 10 and 11.

So I = {00,01,10,11}

The output from the machine will be a sequence of binary digits.

So O = {0,1}

Trace for adding 6 and 7 Chapter 4 6 = 0110 Chapter 4 7 = 0111 Chapter 4 our input 01 11 11 00

The serial binary adder can add two arbitrary numbers. We might say

"computable - computable by a FSM" But….

FSM Minimisation Chapter 4 Two machines M aand M’ are equivalent if for they are given identical input they always produce identical output sequences. Chapter 4 A FSM is said to be minimal if all machines that are equivalent to it have the same number or more states than it. Chapter 4 A state is said to be unreachable if it cannot be reached from the starting state S0 under any circumstances.

It is easy to see that a minimal machine will not have any unreachable states. First stage in minimistaion is to remove all unreachable states.

Two states are said to be equivalent if for any input they produce identical output sequences. If we can discover all the equivalent states then we may merge these in order to produce a minimal machine. A minimal machine will have no equivalent states.

1 1 0 0

Two states are k-equivalent if for any input of length k. So we should be able to find the Chapter 4 0-equivalent states Chapter 4 1-equivalent states Chapter 4 : Chapter 4 n-equivalent states

Whenever the n-equivalent states are identical to the n+1-equivalent states we may deduce that we have found all the equivalent states.

Present State Next State Output Present Input 0 1 s0 s2 s3 0 s1 s3 s2 1 s2 s0 s4 0 s3 s1 s5 1 s4 s6 s5 1 s5 s2 s0 0 s6 s4 s0 1

Chapter 4 Consider the 0-equivalent states Chapter 4 {s0,s2,s5} {s1,s3,s4,s6}

Chapter 4 Then the 1-equivalent states Chapter 4 {s0,s2} {s5} {s1,s3,s4,s6}

Chapter 4 Then the 2-equivalent states Chapter 4 {s0,s2}{s5} {s1,s6}{s3,s4}

Chapter 4 Then the 3-equivalent states Chapter 4 {s0,s2}{s5} {s1,s6}{s3,s4}

As the 3-quivalent and 2-equivalent states are the same we have found all the equivalent states.