Tips on DRC and LVS (Micro Magic)

Tips on DRC and LVS ( Micro － Magic )

1. Continuous Design-Rule Checking

When you are editing a layout with Magic, the system automatically checks design rules on your behalf. Every time you paint or erase, and every time you move a cell or change an array structure, Magic rechecks the area you changed to be sure you haven't violated any of the layout rules. If you do violate rules, Magic will display little white dots in the vicinity of the violation. This error paint will stay around until you fix the problem; when the violation is corrected, the error paint will go away automatically. Error paint is written to disk with your cells and will re-appear the next time the cell is read in. There is no way to get rid of it except to fix the violation.

Continuous design-rule checking means that you always have an up-to-date picture of design-rule errors in your layout. There is never any need to run a massive check over the whole design unless you change your design rules. When you make small changes to an existing layout, you will find out immediately if you've introduced errors, without having to completely recheck the entire layout （Cadence user has to run DRC manually）.

2. Getting Information about Errors

Pull down Misc Menu on the tool bar, you can select the DRC command to check why there is an error and what error is that. Or you can use Hotkey as shown below to figure out what DRC tells you.

Explain DRC under Box

Hotkey: Y Draw a box over a DRC error in MAX (white dots). Then select "Explain DRC under Box" and the DRC information will be printed in the Command Window (page 2-15). If multiple DRC errors are under the box, all of the DRC violations will be listed.

Find Next Error

Hotkey: n Step through each of the DRC errors in MAX. As each DRC error is highlighted, MAX also zooms in on the error. The DRC error explanation is printed in the Command Window (page 2-15).

Find Next Kind of Error

Hotkey: None Step to next type of error. For example, if you are looking at Metal1 min. spacing errors, this command would skip to the next type of error (i.e. Metal2 min. spacing).

After DRC, your layout cell should be clean without white dots as shown below (NAND cell). LVS

1. Make sure your layout design is DRC clean 2. Save all cellviews. 3. If you don't have SUE running at this time, start it, and load the MyNAND cell. If you are continuing from before, click on the MyNAND cell in the Schematic List box. Your screen should look like below. Click on Sim/”Change Simulation Mode” on the menu and change the mode to type sim. Now create a sim Netlist by either clicking Sim/”sim netlist” or pressing “Shift-N”. This will create FA.sim in your directory.

Next, you should toggle back to the Max window. Click on “tool/ Sue LVS” on the tool bar. LVS useing Gemini (a netlist compare program from the University of Washington) is run to compare the schematic and layout netlists and determine node equivalents. You will see the following text in your command window:

Running LVS: extracting...

Edit cell is now MyNAND (Topmost cell in the window) done. running ext2sim... running gemini on MyNAND_lay.sim vs. ./MyNAND.sim ... Format line not on first line of SIM file Format line not on first line of SIM file Format line not on first line of SIM file Gemini 2.7.2 1994/3/15

Graph "MyNAND_lay.sim": unit scale = 1, format = UCB Number of devices: 4 Number of nets: 6

Graph "./MyNAND.sim": unit scale = 1, format = MIT format = NULL (assume MIT) Reading alias file "./MyNAND.al" Number of devices: 4 Number of nets: 6 6 entries written to the dictionary file. 6 (54%) matches were found by local matching All nodes were matched in 6 passes 0 devices and 0 nets displayed in lvs_err19818.err.mag

LVS is CLEAN! done.