The Quality of Mercyis Not Strained

ECE 491 Laboratory 1 – Introducing FPGA Design with Verilog Revised August 29, 2006 Goals 1. To introduce the use of the Verilog Hardware Description Language for combinational logic design in FPGAs. 2. To become familiar with the Xilinx ISE software for FPGA design. 3. To become familiar with the Spartan-3 FPGA and the “Spartan 3 Starter Kit” FPGA Board. Background During the semester we will use the “Spartan 3 Starter Kit” FPGA Board extensively. This board includes a XC3S200 FPGA and a number of useful inputs and outputs, including pushbuttons, slide switches, a 4-digit 7-segment display, 8 LEDs, 2 RS-232 interfaces, a PS/2 port, and a VGA output. Information about how to use the FPGA and the board inputs and outputs will be provided as needed. For further information, see the "Spartan 3 Starter Kit Board User Guide" and the "Spartan FPGA Datasheet", which are available in a binder in the lab and also as links on the "Labs" page of the ECE 491 website. Preparation 1. Get a Laboratory Notebook (one per group). During the course of the semester, you will use this notebook to record design ideas and describe the steps that you take in each experiment. In each experiment, you will include observations and discuss problems encountered. Notebook entries should contain enough detail to establish how a design was created and to allow others to duplicate the results that you obtained in each experiment. Each entry should be signed and dated. 2. Study the Verilog examples discussed in class. 3. Read this document carefully before coming to Lab. 4. Study the attached listings of the Verilog seven-segment decoder and the top-level module for the Spartan-3 Starter Kit Board. Sketch block diagrams of the "s3board" and "seven_seg" modules in your Lab Notebook, showing all input and output ports. In the Lab 1. Start the ISE Project Navigator from the Start Menu: Start->Programs->ISE 7.1i->Project Navigator 2. Create a new project: File->New Project… 3.. When the new project wizard appears, specify a project name (Lab 1) and directory (C:\Lab1). Specify “HDL” for the “Top-Level Module Type” and click “Next”.

1 4. For the next wizard menu, specify Device Family “Spartan 3”, Device “xc3s200”, Package “ft256”, etc. as shown below:

5. Skip the next two menus (“Create a New Source” and “Add Existing Sources”) by clicking the “Next” button twice, and then click the “Finish” Button.

2 6. Open a web browser in a separate window and go to the ECE 491 Labs web page at http://foghorn.cadlab.lafayette.edu/ece491/labs.html. Download the files “s3board.v”, “s3board.ucf”, and “seven_seg.v” into the project directory that you created in step 3. 7. Use the command “Project->Add Source…” to add the verilog files “s3board.v” and “seven_seg.v” to the project. Make sure to specify that these are “Verilog Source Files”, not “Verilog Test Fixture File”. 8. Use the command “Project->Add Source…” to add the constraints file “s3board.ucf”. When prompted, indicate that these constraints apply to file “s3board”. 9. Use the editor to examine the source code for files “s3board.v” and “seven_seg.v”. Add code to “s3board.v” to create an instance of the seven-segment decoder and a 4- bit adder that sums together the upper four and lower four bits of the slide switches, respectively. The output of this adder should feed to the input of the seven-segment decoder. The output of the seven-segment decoder should feed to the segment outputs for the seven-segment display. Add also Verilog code that sets the output port digit_enable_out to the binary value "1110". (this enables the least significant digit of the seven-segment display. Also, use an assign statement to connect the carry output of the addition to the “decimal point” of the seven-segment display. Update the header comment of this file to include your names and a summary of your changes.

3 seg_out_a .. seg_out_f 10. The constraints file that you read in has all the input and output ports commented out since ISE gives an error for unused ports. Edit the constraints file by selecting the file “s3board.ucf” in the upper left hand panel of the Project Navigator; then double click “Edit Constraints (Text)” in the lower left-hand panel of the Project Navigator. Remove the comment (“#”) symbol from all “NET” statements that correspond to ports that your design uses. For example, #NET "sw_in<0>" LOC = "F12"; should become NET "sw_in<0>" LOC = "F12"; 11. Modify the seven-segment decoder to display hexadecimal digits as well as the decimal (0-9) digits. Be sure to modify the header comment to add your names and a description of your modifications. 12. Compile your design. First, make sure that your top-level file (“s3board.v”) is selected in the upper left panel of the Project Navigator. Next, double-click on “Synthesize – XST” in the lower left panel of the Project Navigator. Wait for synthesis to complete, and examine the output in the bottom panel of the Project Navigator for errors and warnings. Errors must be fixed, but warnings should also be considered carefully since they often indicate problems with your design. Warnings referring to ports you are not currently using can be ignored. Repeat this process until all errors are removed and you are sure that any remaining warnings are not important. 13. Implement your design. Double-click on “Implement Design” in the lower left panel of the Project Navigator. As before, check for error and warning messages. 14. Set up the software to use JTAG programming by right clicking on “Generate Programming File” in the lower left panel of Project Navigator and selecting “Properties”. When the “Process Properties” menu pops up, select the “Startup Options” tab and change the first entry “FPGA Start-Up Clock” to “JTAG Clock” and click “OK”.

4 15. Generate the FPGA bitstream file by double-clicking “Generate Programming File” in the lower left panel of the Project Navigator. 16. Download the bitstream design to the FPGA board. First, make sure that the FPGA board is connected to the parallel port of the PC and powered up. Next, double clock “Configure Device (iMPACT)” in the lower left panel of the Project Navigator. When the “Configure Devices” menu pops up, select “Boundary-Scan Mode” (should already be selected) and Click “Next”. When the next menu appears, select “Automatically connect to cable and identify Boundary-scan chain” (should already be selected) and Click “Finish”.

5 17. The iMPACT program will now prompt for bitstream files for the FPGA and EEPROM on the S3 board. For the FPGA, select the file “s3board.bit”. For the EEPROM, click “Cancel” since we are not programming the EEPROM in this lab. 18. Program the FPGA from iMPACT by selecting the “xc3s200” icon, right-clicking over this icon, and selecting the “Program…” menu item. Now test the operation of the FPGA board and check for errors. If errors are found, correct your design and repeat the previous steps to re-program. Note that you must exit and re-start the iMPACT program to load a recompiled FPGA.

6 19. Demonstrate the proper operation of your circuit to the Instructor. 20. Describe any problems you encountered in this lab in you Laboratory Notebook. 21. Make backup copies of your Verilog files and constraint file by copying them to a network drive or a "keychain" disk. 22. Hand in your Lab Notebook and listings of your modified Verilog files.