Standards Update p.5 CompactPCI Serial ascends to Revision 2, AdvancedTCA primed for Ethernet and IPv6 enhancement Advancing Networks p.6 Proprietary implementations of open source in DSN

@PICMG_Tech Advertiser Index

PAGE ADVERTISER PICMG Systems & Technology Editorial/Production Staff 1 Annapolis Micro Systems, Inc. – Joe Pavlat, Editorial Director Steph Sweet, Creative Director WILDSTAR 6/AMC [email protected] [email protected] Brandon Lewis, Assistant Managing Editor Konrad Witte, Senior Web Developer 3 Excalibur Systems, Inc. – [email protected] [email protected] mil-1553.com Jessica Isquith, Industry Editor John McHale, Group Editorial Director [email protected] [email protected] 6 VEROTEC Electronics Packaging – System building Sales Group components Tom Varcie, Sales Manager Regional Sales Managers [email protected] Barbara Quinlan, Southwest 7 Computex – See you (586) 415-6500 [email protected] June 2-6, 2015 Rebecca Barker (480) 236-8818 Strategic Account Manager Denis Seger, Southern California 9 MEN Micro Elektronik GmbH – [email protected] [email protected] Breaking the chains! (281) 724-8021 (760) 518-5222 Eric Henry Sydele Starr, Northern California 12 Elma Electronic – Strategic Account Manager [email protected] Intelligent embedded [email protected] (775) 299-4148 computing – MicroTCA.4 (541) 760-5361 Europe Sales system platforms Kathleen Wackowski, Strategic Account Manager James Rhoades-Brown [email protected] [email protected] (978) 888-7367 13 Interface Concept – Asia-Pacific Sales Reprints and PDFs Build your own VPX system! Elvi Lee, Account Manager [email protected] [email protected] 15 N.A.T. GmbH – The smart way of composing – board level OpenSystems Media Editorial/Creative Staff products and system solutions by N.A.T. John McHale, Group Editorial Director Lisa Daigle, Assistant Managing Editor 16 ASIS – Beyond the Military Embedded Systems Military Embedded Systems standard – ATCA 3.0-3.7, PC/104 and Small Form Factors PC/104 and Small Form Factors mTCA, VPX, & custom PICMG Systems & Technology [email protected] platforms VITA Technologies Mariana Iriarte, Assistant Editor Rich Nass Military Embedded Systems 17 LCR Embedded Systems – Embedded Computing Brand Director [email protected] Rugged systems engineered for Embedded Computing Design Sally Cole, Senior Editor [email protected] Military Embedded Systems your application Jerry Gipper, Editorial Director [email protected] VITA Technologies 18 VadaTech Inc. – Rory Dear, Technical Contributor [email protected] Embedded Computing Design Introducing the UTC004 Curt Schwaderer, Editorial Director [email protected] 3rd generation MCH Embedded Computing Design Konrad Witte, Senior Web Developer [email protected] Steph Sweet, Creative Director 40 Vector Electronics & Monique DeVoe, Managing Editor Dave Diomede, Creative Services Director Embedded Computing Design Technology, Inc. – VectorPak Joann Toth, Senior Designer [email protected] systems packaging Chris Rassiccia, Graphic Designer Joy Gilmore, E-cast Manager [email protected] Corporate www.opensystemsmedia.com Patrick Hopper, Publisher Emily Verhoeks, Financial Assistant [email protected] Headquarters – ARIZONA: EVENTS Rosemary Kristoff, President 16626 E. Avenue of the Fountains, Ste. 201 [email protected] Fountain Hills, AZ 85268 ESC Boston John McHale, Executive Vice President Tel: (480) 967-5581 May 6-7, 2015 [email protected] MICHIGAN: Boston, MA Rich Nass, Executive Vice President 30233 Jefferson www.embeddedconf.com/boston/conference [email protected] St. Clair Shores, MI 48082 Wayne Kristoff, CTO Tel: (586) 415-6500 COMPUTEX TAIPEI Subscriptions www.opensystemsmedia.com/subscriptions June 2-6, 2015 Print ISSN 2333-5947, Online ISSN 1550-0381 PICMG Systems & Technology (USPS 019-288) is published three times a year (Spring, Fall and Winter) by OpenSystems Media, Taipei, Taiwan 16626 E. Ave of the Fountains, Ste 201, Fountain Hills, AZ 85258. PICMG Systems & Technology is free to qualified engineers or management dealing with or www.computextaipei.com.tw considering open system technologies. For others, paid subscription rates inside the US and Canada are $63/year. For first class delivery outside the US and Canada, subscriptions are $90/year (advance payment in US funds required). Periodicals postage paid at Scottsdale, AZ, and at additional mailing offices. Canada: Publication agreement #40048627. Return undeliverable Canadian addresses to: WDS, Station A, PO Box 54, Windsor, ON N9A 615. POSTMASTER: Send address changes to PICMG Systems & Technology 16626 E. Ave of the Fountains, Ste 201, Fountain Hills, AZ 85258.

2 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com

SPRING 2015 | VOLUME 19 NUMBER 1

picmg-systems.com @PICMG_Tech Standards-based technology platforms for open innovation On the cover

As the IEEE looks to advance Ethernet speeds from 40G to 400G for backplane-based systems such as AdvancedTCA, the PICMG Systems & Technology 2015 Resource Guide tracks the evolution of networking technologies in articles that range from 40 GbE MicroTCA and AMCs to 100G backplane design. The Resource Guide also includes myriad products for the designer of next-generation network infrastructure solutions, with products such as the Annapolis Micro Systems WILDSTAR 6/AMC featured beginning on page 19.

Identifying challenges in 100G backplane design Standards Update | Joe Pavlat By Sergej Dizel, Pentair Technical Products GmbH 5 CompactPCI Serial ascends to Revision 2, AdvancedTCA primed for Ethernet and IPv6 enhancement Technology Focus 8

Advancing Networks | Brandon Lewis 6 Proprietary implementations of open source in SDN

Technology Focus 8 Identifying challenges in 100G backplane design By Sergej Dizel, Pentair Technical Products GmbH

Application Feature Upgrading MicroTCA.0 and AMC.2 to 40 GbE speed levels 11 Upgrading MicroTCA.0 and AMC.2 to 40 GbE speed levels By Justin Moll,VadaTech, Inc. By Justin Moll,VadaTech, Inc. Application Feature 11 Industry Outlook 14 Ethernet – 40G to 400G Interview with John D’Ambrosia, Chairman, Ethernet Alliance; Chair, IEEE P802.3bs 400 GbE Task Force; and Chief Ethernet Evangelist, Dell

PICMG Resource Guide 19 Resource Guide Profiles AdvancedMC ...... 19 AdvancedTCA ...... 19 COM Express ...... 25 Ethernet – 40G to 400G Interview with John D’Ambrosia CompactPCI ...... 27 Industry Outlook 14 DSP-FPGA Boards ...... 32 Front Panel Hardware ...... 31 Mezzanines ...... 38 ® 2015 OpenSystems Media ® Comp actPCI, PICMG, PICMG, ATCA, AdvancedTCA, MicroTCA, AdvancedMC, MicroTCA ...... 39 GEN4, and their logos are registered trademarks of PICMG. TM xTCA is a trademark of PICMG. © 2015 PICMG Systems & Technology All registered brands and trademarks in AdvancedTCA & CompactPCI Systems are property of their respective owners. Member since 1998

4 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com Standards Update CompactPCI Serial ascends to Revision 2, AdvancedTCA primed for Ethernet and IPv6 enhancements

By Joe Pavlat [email protected]

Open standards for embedded com- to grow, and now includes MEN Mikro puting offer the customer a wide range Elektronik GmbH, Elma Electronic, of products, vendor independence, and Kontron, EKF Elektronik GmbH, ADLINK a fairly predictable upgrade path to Technology, Hartmann Electronic, Schroff incorporate new semiconductor, stor- GmbH, Teledyne Lecroy, ADDI-DATA, age, and software technologies. The and others. standards themselves are generally developed and maintained by open A new revision of the standard in now organizations or consortia that work to being released, Revision 2. It adds incre- be inclusive and not beholden to one or mental features and capabilities, which Figure 1 | CompactPCI Serial a few companies. There are many suc- is typical of revisions to well-established › supports both 3U and 6U configurations. cessful open standards organizations in standards. CompactPCI Serial Revision 2 Shown here is an example 9-slot, 3U CompactPCI Serial system (Figure operation, and the IEEE, PICMG, and now supports placement of the system courtesy MEN Mikro Elektronik GmbH). VITA are among the best known. slot on either the left or right side of the backplane. More importantly, Revision 2 One of PICMG’s early successful stan- supports additional rear I/O on the P6 dards is CompactPCI, which incorpo- connector and increased capability rates the wealth of PCI silicon developed on rear transition modules (RTMs). for the desktop PC world into a modular Graphics, USB, SATA, and other system and rugged standard for embedded slot connections can now be routed computing. First released in 1995, it out the rear, important for conduction continues to be the solution of choice cooling applications where the front for a very wide range of applications, module is fully encased. PCI Express Figure 2 | Depicted here is an example including the Mars rover, Curiosity (I just can also be routed out the rear, making › CompactPCI Serial backplane with the never get tired of saying that). it possible to easily interconnect mul- P6 connector configured for multiple rear Ethernet connections (Figure courtesy of tiple homogeneous or heterogeneous MEN Mikro Elektronik GmbH). Over the last ten years or so, the parallel PCI Express systems. PCI bus has given way to a serial ver- the beginning, and it was originally sion, PCI Express. Serial buses are faster AdvancedTCA 100G Ethernet specified to use 32-bit IP addresses and the chips cheaper, because they Driven by the need for higher bandwidth according to the IPv4 protocol. trade pin count (which is expensive) for in mobility, video, and security, this effort However, IPv4 supports 4 billion distinct a larger number of transistors (which are will provide capacity improvement to the IP addresses, and in the emerging world essentially free). Other buses, including AdvancedTCA (ATCA) specification by of Internet of Everything and billions USB and Serial ATA (SATA) have fol- incorporating 100 Gb backplane Ethernet of interconnected devices, this is not lowed suit. The granddaddy of all serial while maintaining backward compatibility. enough. IPv6 uses 128-bit addresses, communications interfaces, Ethernet, is Formally designated PICMG 3.1 R3.0, so more than 3.4 x 1038 devices can be still with us and just keeps getting faster. the 100G ATCA standard will update directly addressed. This new feature will AdvancedMC ...... 19 the PICMG 3.1 specification to incorpo- be released as an Engineering Change AdvancedTCA ...... 19 CompactPCI Serial – Revision 2 rate 100GBASE-KR4 (NRZ) Ethernet sig- Notice to the current revision of ATCA, A few years ago, PICMG released a naling. This effort began in early 2015, Revision 3.0, helping get this much COM Express ...... 25 new version of CompactPCI known as and work is expected to be completed by needed capability to the market quickly. CompactPCI ...... 27 CompactPCI Serial. It provides a tenfold the end of the year. It is being headed by The IPv6 feature is completely optional DSP-FPGA Boards ...... 32 or so increase in performance, more Doug Sandy, CTO of PICMG and Artesyn and does not affect backwards compat- Front Panel Hardware ...... 31 interconnectivity using fewer pins, and Embedded Technologies, who also lead ibility in any way, so all existing ATCA- Mezzanines ...... 38 cost-effective features such as the inclu- the successful 40G ATCA effort a couple compliant systems will remain so. sion of multi-channel Ethernet without years back. MicroTCA ...... 39 the need for a switch. It is already pop- 40G for MicroTCA and AMC ular in Europe where it was developed, IPv6 for AdvancedTCA The 40G MicroTCA and AMC effort and its popularity is now moving around Hardware platform management (HPM) is well underway. The next issue will the globe. The vendor base continues has been an integral part of ATCA since explore this in more detail.

www.picmg-systems.com PICMG Systems & Technology Resource Guide | Spring 2015 | 5 Advancing Networks Proprietary implementations of open source in SDN

[email protected] By Brandon Lewis

Earlier this year I had the opportunity to speak with Jeff Reed, by the Linux Foundation and had more than 250 contributors in VP of the Enterprise Infrastructure and Solutions Group at 2014, the vast majority of the now more than 1 million lines of Cisco on the company’s software-defined networking (SDN) code are courtesy networking giants such as Juniper, Brocade, strategy and trends in SDN in general[1]. I went in armed with Microsoft, Intel, and, of course, Cisco[2]. So while OpenDaylight some questions about OpenFlow, expected to hear about the flies under the flag of open source, is it really? company’s involvement in the OpenDaylight initiative, and was primarily interested in the company’s take on how SDN archi- Let me direct your attention back to OpFlex. OpFlex is a tectures are impacting vendors of hardware platforms such as Cisco-envisioned protocol that orchestrates policy between AdvancedTCA (ATCA). But when I asked about Cisco’s SDN the controller and network switch in ACI implementations (as strategy, Reed was quick to point me to their Application Centric mentioned, ACI is Cisco’s answer to SDN). Ironically, OpFlex is Infrastructure (ACI); when I said OpenFlow he responded with basically the equivalent of what the OpenFlow controller does OpFlex. Do you see where I’m going with this? for SDNs in OpenDaylight configurations, only faster and with more fine-grained control. Currently OpFlex is an open pro- Proprietary implementations of open source tocol, and Cisco has committed to licensing it under Apache In early 2013, Cisco teamed with IBM on the beginnings of 2.0 in addition to proposing it as a standard to the IETF[3]. OpenDaylight, an open-source project aimed at accelerating the development of SDN and network functions virtualization While an open-source variant of OpFlex would make the pro- (NFV). Of course, the term “open source” is used loosely at tocol widely accessible to the vendor community at large, it’s best these days, and although OpenDaylight is now managed also undoubtedly an endorsement of Cisco’s ACI. In addition to an application policy infrastructure controller (APIC), the ACI model relies on hardware such as Cisco’s Nexus 9000 and Nexus 9300 switches. Meanwhile, Reed also pointed out during VEROTEC INTEGRATED PACKAGING our conversation that Cisco has been working on a line of net- work ASICs over the past couple years that include a flexible System building components parser and flexible data pipeline so that the ICs “can support IEEE1101.1 and 1101.10 commercial and rugged systems protocols that didn’t even exist when we shipped it.” 19” standard, screened and Eurocard rack cases “That’s such a terrific toolset to have with SDN and ACI because if a customer deploys one of those boxes and a great new pro- tocol comes along a year from now, they can support it without having to go buy a new piece of hardware,” Reed said. “So there’s a lot of opportunity for ACI to continue to drive the rele- vance of capabilities on the network infrastructure itself. Almost Shielded and unshielded front panels and modules every new product or development activity we’re working on ties into ACI and how we enable it via the controllers. That’s part and parcel to how you’ll see Cisco build its products over the next few years.”

In all, these ASICs will provide a migration path from SDN/ Card cages 3U to 9U OpenFlow to Cisco’s ACI/OpFlex architecture, or other future SDN infrastructure combinations. If you’re interested in keeping abreast of the evolution of SDN, I’d suggest you pay attention to contributions in open-source projects such as OpenDaylight; if for no other reason than to make sure there are no surprises.

References: Continuing 50 years of excellence in functional and elegant enclosures for 1. “Software-defined networking – A view from the top.” cPCI, VME, VME64x, VPX, other major bus structures and general electronics http:// opsy.st/CiscoSDN 2. “A survey of open networking standards, part 1: OpenDaylight.” ELECTRONICS PACKAGING http://opsy.st/QualiSystemsOpenDaylight Ph: 603.821.9921 • [email protected] • www.verotec.us 3. “OpFlex: Another example of Cisco being Cisco.” http://opsy.st/CiscoBeingCisco.

6 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com See you JUNE 2 - 6, 2015

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Tel: +886-2-2725-5200 Ext. 2634 Organizers: E-mail: [email protected] Fax: +886-2-2725-3501 Technology Focus Identifying challenges in 100G backplane design

By Sergej Dizel, Pentair Technical Products GmbH

Since the introduction of AdvancedTCA (ATCA) in 2002, the race for more data transfer speed on the backplane has been on. The telecom and datacom markets have a hunger for processing power that is never satisfied. Today’s processor technologies such as multicore, GPGPUs, and powerful co-processors can satisfy the demands of full HD video on demand, increasing the number of data-hungry services available for smartphones and other applications. In addition to providing the processing power for these applications, infrastructure must be able to support the huge amount of data traffic they generate.

From packet switching backplanes with 1 Gbps of data transfer in the beginning of the millennium, today’s ATCA backplanes support 40 Gbps data transfer. This is achieved by four ports, each with two differential pairs transferring 10 Gbps each, which together are capable of transferring 40 Gbps. Even this is not sufficient to feed today’s most demanding processor blades.

Today, dual-dual star backplanes are often used where two switches work in parallel to increase the data traffic between transmitter and receiver to 80 Gbps, though this is certainly not the end point of demand for data speed. The IEEE specification for 100 Gigabit Ethernet (GbE) over copper was released at the end of 2014, and a PICMG working group is defining 100G Ethernet for ATCA based on the IEEE spec.

100 Gbps data rates create many new connectors, the bare board, and the transition between board and back- challenges for backplane design. Figure 1A copper trace structures have to be plane. One way of possibly achieving and 1B show the thresholds for insertion de­signed for those higher frequencies. this is to decrease the size of the through and return loss of the IEEE802.3ap spec- holes in the backplane. This method cre- ification (which defined 40G Ethernet), The current ZD+ connector as defined ates another advantage for backplane and the new standard IEEE802.3bj that in the ATCA specification is not rated for routing as the smaller hole sizes create defines 100G. At 100G, the IEEE defined those high frequencies. At the moment, a larger routing channel in between the two coding methods, 100GBASE-KR4 no such ATCA connector is defined or connector pins. This leads to a more and 100GBASE-KP4. As shown in the freely available on the market, although homogeneous impedance of the traces figures, the thresholds for both new connector vendors are working on a and a lower cross talk. The down side methods of 100G are defined for much solution. The main challenge for the of smaller hole sizes is that the press-fit higher frequencies. For the backplane new ATCA connector is to achieve a connector pins must be smaller and less this means that all components, such as much more homogeneous impedance robust and may have lower cohesion.

8 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com Figure 1A

Breaking the Figure 1B Chains!

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n Communication via Figures 1A and 1B | These graphs compare the thresholds for insertion loss (1A) and return real-time Ethernet loss (1B) at 40G and both methods of 100G. › n Connection to any railway fieldbus type like CANopen, Figure 2 shows the simulation of insertion loss (Sdd21) of a 30 mm-long differential MVB, PROFINET, etc. pair in an ATCA backplane without the connectors assembled. The difference between n Comes with complete the current configuration with a 0.6 mm through hole and a reduced through hole certification package including size of 0.36 mm is obvious. A reduction of the distance of the press-fit pins within hardware, safe operation system the differential pair from 1.5 mm to 1 mm is able to further reduce the losses of the and software transmission line. n Compliant with EN 50155

The near future will show what the new ATCA connector design for 100G will be, including the footprint for mounting to the backplane. At the same time the PICMG 100G ATCA working group is striving to define the new connector in a way that allows several connector manufacturers to create the 100G ATCA backplane and board connector.

Tackling cross talk The next important part of the backplane that must be addressed in 100G ATCA designs is the trace structures, especially their dimensioning with regards to losses and cross talk. Not every differential pair has similar properties. For example, when com- paring two differential stripline pairs each with a 100 Ohm impedance but different www.menmicro.com/markets/railways.html trace widths (and thus a different layer stackup), they will have different behavior with www.picmg-systems.com PICMG Systems & Technology Resource Guide | Spring 2015 | 9 Technology Focus

zHG 0 zHG 5 zHG 01 zHG 51 zHG 02 zHG 52 zHG 0 dB

-2 dB

-4 dB

-6 dB

-8 dB

-10 dB

-12 dB Insertion loss with 6mm vias, 30mm trace length Insertion loss with 3,6mm vias, 30mm trace length › Figure 2 | Comparison of insertion loss of a 30 mm differential pair with 6 mm and 3.6 mm vias. regards to transmission line losses and cross talk (emission and immission). At 40G backplane data transfer this issue is solved, but there are new challenges with 100G that became visible when conducting the first simulations for 100G data transfer, as the impedance discon- tinuities between the connector and the differential pair need to be evaluated very carefully. This part of the transmis- sion line already plays a significant role in a 40G backplane, but at 100G it will be much more critical. The impedance discontinuities between the connector › Figure 3 | An example of vias and traces in a backplane. and the backplane have a significant influence on the properties of the whole allow a 100G data transfer. This means it is essential to very carefully choose a PCB transmission channel (losses and cross manufacturing partner who understands these needs and has their processes carefully talk). If the discontinuities are too large, controlled. A close partnership is needed to qualify those suppliers and qualify the the signal fed into the transmission line production technology and processes. is more sensitive to cross talk from adja- cent differential signal traces. When the As the PICMG 100G ATCA specification is not yet complete, only prework on qualifying losses and/or influence from cross talk a 100G ATCA backplane design can be done at the moment. Verification of a 100G are to great, the receiver cannot cor- backplane is not possible until the PICMG specification is defined because the param- rectly read the signal; with that, the bit eter limits for the backplane have not been selected yet. error rate gets increased. The IEEE802.3bj 100G specification defines the parameter for the whole Ethernet To achieve the desired trace structure channel, which is located between both transceiver chips. The transmission line of in a bare board, new requirements for an ATCA backplane is just a part of the whole transmission channel; as ATCA boards the quality of the bare board are needed are located before and after the backplane within the transmission channel. For that (Figure 3). Bare board material, prepreg reason the IEEE802.3bj parameter can’t be used one-to-one for backplane validation. and core types, backdrilling, drilling The IEEE802.3bj parameter limits must be separated between these three parts of the offset, etching, and many other factors channel for both ATCA boards and the backplane. The PICMG 100G working group will play an enormous role in 100G back- is currently addressing these issues, and companies like Pentair are playing an active plane design. role defining this new important standard.

Spec’ing and certifying ATCA at 100G Sergej Dizel is an electrical and backplane design engineer at Pentair Technical In addition to correctly defining those Products GmbH. parameters, the quality and the toler- ances of the bare board manufacturing process is essential to guarantee repro- Pentair Technical Products GmbH ducible 100G data transfer results. Even www.pentairprotect.com the smallest process deviation during [email protected] manufacturing will influence the signal 1.800.525.468 properties, and, in the worst case, not

10 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com Application Focus

Upgrading MicroTCA.0 and AMC.2 to 40 GbE speed levels

By Justin Moll,VadaTech, Inc.

The Higher Speed Ethernet Fabrics for MicroTCA.0 and AMC.2 committee is working to bring 40 GbE to these specifications. The specification currently runs at up to 10 GbE levels per 10GBASE-KX and 10GBASE-KR. There are several pieces involved in this effort, and careful attention has been made to its effect on related specifications.

The largest aspect of the 40G over MicroTCA (mTCA) activity is ensuring the archi- ›› Simplicity – Keep the testing tecture will perform well at these speeds. In doing so, the committee will provide as simple as possible and limit an eye mask and design parameters for third-party users to adhere to when they the amount of expensive test develop their own boards. The goal is to provide enough guidelines and rules so that equipment required the mTCA vendor’s 40G products are fully interoperable at 40 GbE speeds, and third- party developments will also have enough guidance from the specification to work One of the key steps the committee took effectively at the increased rates. was to leverage core parts of the eco- system to create a model for the full inter- 40G over MicroTCA will be leveraging practices used in the sister specification for connect path. Using multiple vendors’ PICMG 3.1 (40GbE over AdvancedTCA). Listed below are a few of the guidelines: AMCs, MCHs, and backplanes/chassis, the Higher Speed Ethernet Fabrics ›› Ecosystem Interoperability – Components will be tested from active mTCA for MicroTCA.0 and AMC.2 working developers to ensure the various connectors, backplanes, AMCs, and MicroTCA group looked at several parameters for Carrier Hubs (MCHs) work together 10GBASE-KR compliance testing. This ›› Confidence Level – Establish that any party testing to the guidelines provided has included the differential insertion loss, a reasonably high level of confidence that their solution will perform to the metrics skew, differential return loss, crosstalk ›› Independent Development – Allow that backplanes, modules, and AMCs can ratio to insertion loss, and jitter tolerance. be developed separately Overall, the results were very good and ›› Minimize Cost Impact – Design options will be kept open to allow cost provided a solid baseline for 40G signal optimization innovation by vendors/suppliers integrity efforts. www.picmg-systems.com PICMG Systems & Technology Resource Guide | Spring 2015 | 11 Application Feature

As visible in Figure 1, all of the results for the insertion loss of a short channel path fell well above the fail line. As the S-parameters were based in FR4 PCB material, there is “THE 40G OVER mTCA confidence that plenty of margin exists for higher speeds; in the worst case, materials GROUP HAS PROVIDED with a low dielectric constant could be used. RECOMMENDED As shown in Figure 2, the differential return loss passes as well, but comes a bit close RESOLUTIONS FOR THE OPEN in the low frequencies. It is not expected for there to be a problem at 40G levels, but all of the areas will have to be watched closely. Again, as base FR4 materials CRS IN MICROTCA.0 ...” were the basis of analysis, there is room for recommending other materials in the specification if needed. during the simulation studies. The goal is The 40 GbE over mTCA efforts are continuing. Once simulation models are fully to have all simulations complete in Q1 of instituted, characterization of 40 GbE modules and backplanes with specially made 2015, with characterization commencing paddle/test cards will begin. This will provide confirmation of the parameters we set in Q2 or Q3.

Other activities Another part of the Higher Speed Ether­- net over MicroTCA.0 and AMC.2 speci- fication the committee is addressing are Correction Requests (CRs). These most often occur when a related specification addresses an issue and a request is made to have the adjustments incorporated in all corresponding specifications. When changes are made special care is given to not materially harm or affect the compatibility and function of related specs, but sometimes small adjustments and clarifications are required for consis- tency and accuracy.

MicroTCA and its related specifications have been very active in recent years, including the ratification of MicroTCA.2 and several notes/changes to MicroTCA.1. Intelligent Embedded Computing The task of aligning all of these specs can MicroTCA.4 System Platforms be time-consuming, but it is important to ensuring an effective family of speci- • Beam forming and test fications. Furthermore, there has been a wealth of activity in MicroTCA.4 led by • Scientific Data Acquisition & Diagnostics the high-energy physics (HEP) commu- • Energy Research Equipment nity, and the original authors’ allowance • Control Systems for Particle Accelerators & Colliders for the use of rear transition modules (RTMs) in the MicroTCA.0 has become a The mTCA architecture is well suited for use in applications key attribute of MicroTCA.4. Addressing CRs in this instance made life easier when such as particle accelerator labs, smart grid, trying to keep the specifications aligned wireless infrastructure and gateway systems. and up to date. Elma has the expertise and resources to help you design and build your system. The 40G over MTCA group has provided recommended resolutions for the open CRs in MicroTCA.0, and they will be sub- mitted to PICMG membership for a vote.

Join the committees MicroTCA is gaining traction in physics, mil/aero, and many other applications. Texas Instruments has based some of

12 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com OSM_PICMG_ad_mTCA_Fall.indd 1 2/27/2015 12:52:35 PM Build your own VPX system ! INTERFACE CONCEPT product range of Sin- gle Board Computers, FPGA boards, ADC/ DAC FMC and Graphic boards are ideal to devise a complete VPX system for compute intensive and image processing applica- tions (radar, electronic warfare, electro optical and IR, visualization systems)

Figure 1 | Insertion loss testing of 10GBASE-KR4 Ethernet for use in 40G MicroTCA.0 and › AMC.2 systems has yielded encouraging results. Intel® CoreTM i7 SBC

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Graphic Boards Figure 2 | Differential return loss testing of 10GBASE-KR4 Ethernet in 40G MicroTCA.0 and › AMC.2 systems was also successful, however the smaller margin for error may at some point necessitate a base material other than FR4. their new evaluation modules on the AMC form factor, and it is also common to find a new specialty AMC board vendor crop up in unexpected places. If you are an active • One AMD RadeonTM E8860 user or developer of AMC/MicroTCA systems and are interested in joining the group, • One KintexTM-7 325T FPGA • Support for DP, HDMI, VGA, Stanag3350, contact [email protected] or [email protected] for details. Arinc8181... • One PMC/XMC site Justin Moll is Director of Marketing for VadaTech, Inc. Justin is active in the embedded industry and is currently the Chair of the 40 GbE over MicroTCA committee within PICMG.

VadaTech, Inc. www.vadatech.com www.interfaceconcept.com [email protected] +33 (0)2 98 57 30 30 www.picmg-systems.com PICMG Systems & Technology Resource Guide | Spring 2015 | 13

IC-Jan15-exe.indd 1 16/01/2015 16:37 Industry Outlook

Ethernet – 40G to 400G

Interview with John D’Ambrosia, Chairman, Ethernet Alliance; Chair, IEEE P802.3bs 400 GbE Task Force; and Chief Ethernet Evangelist, Dell

With Ethernet speeds advancing past 40G to 100G and higher, designers of systems such as AdvancedTCA (ATCA) meticulously follow activities in the IEEE 802.3 Ethernet subcommittee for any indicators on the future of backplane-based systems. In this interview with John D’Ambrosia, IEEE P802.3bs Chair, Chairman of the Ethernet Alliance, and Dell’s Chief Ethernet Evangelist, he discusses the development and deployment of the recently released 100GBASE-KR4 and -KP4 specifications, as well as the beginnings of IEEE work on 400G Ethernet and beyond.

Give a little background on 10 GbE across the backplane. So as the group was winding down on 100G develop- the 100GBASE-KR4 spec, it’s ment, which was really an optics focus, we realized that we needed to start introducing development, and finalization. the next members of the 100G family. And following those discussions we had around developing the optics, we started looking at developing 4 x 25 Gbps Ethernet. That’s D’AMBROSIA: The 100GBASE-KR4 why it was called “Backplane and Copper Cable.” spec was developed as part of what was referred to as the IEEE 802.3 100 GbE As that project emerged, it became 100GBASE-KR4 (which is a backplane solution Backplane and Copper Cable project. based on NRZ signaling), there’s 100GBASE-KP4 (which is based on PAM4 sig- That project was being considered naling), and then there’s 100GBASE-CR4 (which is across a twinaxial cable for 5 m as the development of 40 GbE and based on four differential pairs of 25 Gbps Ethernet in each direction). The actual 100 GbE was coming to a close. In that project started with a call for interest (CFI) that happened in November of 2010, case, the 40 GbE and 100 GbE project and that spec was ratified in the middle of last year. That’s been finalized, so that hadn’t developed any new electrical sig- spec is out there now. naling on a per lane basis, meaning that all of the electrical interfaces developed What were some of the challenges with 100G spec development, and how do as part of that project were based on the KR4 and KP4 specs differ? 10 GbE signaling. D’AMBROSIA: In hindsight, some of the FEC encoding became more involved, and 100 GbE optics actually was developed the bigger point in terms of AdvancedTCA (ATCA) is you had new channel specs. This with a 4-lambda approach based on is where -KR4 and -KP4 came from. 25 GbE per lambda. When you look at the optical specs you see 100GBASE-LR4 As a kind of rule of thumb, you’re probably looking at a 25 dB to 35 dB solution and 100GBASE-ER4; that was really the at the Nyquist rate. So, if I’m running at 10 Gbps, Nyquist is roughly half of that – initial 100 GbE project. So right off the 5 Gbps – for NRZ signaling. That’s kind of constant, so when we jumped to 25 Gbps bat there was this understanding that we the channel was in the 25 dB to 35 dB range, but now at 12.5 Gbps. So as you were going to go to 25 GbE technology move to higher speeds, the channel itself becomes an issue. That’s always one of just because we had looked at it from an the challenges you’ll face, and you can see the same kind of thing with the 10 GbE optics perspective, which really became and 40 GbE specs. a systems perspective. NRZ signaling stands for non-return-to-zero, and it’s a form of pulse-amplitude modu- As I said, the electrical interfaces that lation (PAM). So it’s your classic zeros and ones. In the case of PAM4, the way that were developed for the 100 GbE project, I like to describe it is if you sit in a room and you ask people to raise their hands, those which did not include a backplane solu- are ones; if they don’t put their hands up, those are zeros. So it’s usually very easy tion by the way, were based on 10 lanes to tell the difference between zeros and ones. Normally it doesn’t really matter how of 10 GbE. As an old backplane designer quickly they put their hands up, but as you start moving faster and faster, you start to I can tell you that there’s no way in hell run into some issues. One of those is the challenges of the channel, and one of those I want to have to deal with 10 lanes of challenges is cost.

14 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com If you were to look at PAM4, going back that rule of thumb about 25 dB to 35 dB at Nyquist, but in the case of PAM4 it’s not on my analogy, there would be more really 25 dB to 35 dB at 12.5 Gbps, it’s really 25 dB to 35 dB 6.25 Gbps to 7 Gbps places for people to raise their hands. because of some overspeed. That becomes a way to deal with channels that may So zero would be their hands down, involve lower cost materials. That’s really the benefit here – being able to send more the next level might be at their waist, information over a lower cost channel is essentially the benefit of PAM4 over NRZ. the next level would be at their head, and the last level would be above their head. Pulse amplitude modulation at “YOU SEE MORE PRODUCTS BEING INTRODUCED four levels, or PAM4. Inherently, that reduces your signal-to-noise ratio right SUPPORTING 100GBASE-KR4 THAN 100GBASE-KP4 TODAY. off the bat. YOU HAVE TO REALIZE THAT THERE’S AN ECOSYSTEM

In the case of NRZ, you send a symbol OUT THERE THAT SUPPORTS NRZ SIGNALING. IT GOES that represents a 0 or a 1. In the case FROM THE TEST EQUIPMENT TO JUST THE BASIC of PAM4, you send a symbol (the baud rate), but in this case it is enabled by ENGINEERING UNDERSTANDING.” two bits. So when you’re at level 0 it represents something, when you’re at level 1 it represents two 2 bits, when What kind of adoption are you seeing for each specification, and what type you’re at level 2 it represents two bits, of interoperability challenges, if any, do the two types of signaling pose for when you’re at the highest level it rep- backplane designers? resents two bits – also, depending on the different transitions, you get into D’AMBROSIA: One of the things that we are seeing is a lot more work being devoted representing what those two bits are. to 100GBASE-KR4, the NRZ specification. You see more products being introduced So you’re sending more information in supporting 100GBASE-KR4 than 100GBASE-KP4 today. You have to realize that a single symbol than you do with NRZ, there’s an ecosystem out there that supports NRZ signaling. It goes from the test so your baud rate is half now. I gave you equipment to just the basic engineering understanding.

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But the debate between NRZ and PAM4 50 GbE PAM4. There are some people who are pointing to that saying it’s a good has been going on for a long time, and thing because we could support backwards compatibility, and as we look at having there are more and more people inter- to go backwards it would be to our benefit to consider doing 50 GbE PAM4 because ested in PAM4. Going back 13 years, of the popularity of 25 GbE NRZ, as opposed to having to go to newer processes to I helped form a group called the High support 50 GbE NRZ. Those arguments are already happening now as we look at sup- Speed Backplane Initiative, and we were porting 50 Gbps electrical signaling as part of the 400 GbE project. looking at using PAM4 for backplanes back then. At that time there were a few The IEEE hasn’t announced any intentions of taking copper backplanes parties interested in it, but ultimately the further than 100 GbE. From your perspective, what are the most viable options industry decided to not specify PAM4 moving forward? and specify NRZ for 10 GbE signaling. When it came time to do 4 x 25 GbE D’AMBROSIA: We’re developing 400G now. The 802.3bs Ethernet Task Force has signaling, more companies stepped decided that it will develop electrical interfaces for chip-to-chip (by chip-to-chip I up saying that they think we should mean on a card, not across cards) and chip-to-module. We will develop 25 GbE and do PAM4. Now as we look to going to 50 GbE electrical interfaces – 25 GbE will leverage NRZ signaling, 50 Gbps is still a 400 GbE and trying to go faster, more topic of debate over whether it will be NRZ or whether it will be PAM4. and more people are looking at using PAM4 signaling to support 50 Gbps The interesting thing here is that, when I said from a backplane designer’s perspec- electrical, especially over the longer tive that doing 10 x 10 GbE interfaces across a backplane didn’t sound appealing, for channels just because of the inherent 400G it would be 16 x 25 GbE and 8 x 50 GbE. Even at 50 GbE that sounds really ugly channel challenges. to me, but it is pretty much recognized that 50 Gbps signaling is going to be the next development point. It’s an interesting question as we go for- ward because a lot of the 25 GbE NRZ The introduction of 50 Gbps though, if you look at what’s going on inside the IEEE that has been developed and is now out right now, could raise some interesting questions. When you look at what’s happening in the market provides similar circuitry with how we’re developing 25 Gbps signaling technology as part of 4 x 25 GbE for to what would be needed to support 100G, and then you look at 40G, which is leveraging 4 x 10 GbE today, what you see

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16 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com Figure 1 | The 2015 Ethernet Roadmap outlines the ongoing development of Ethernet through 2020, and and includes projections for electrical/ › optical speeds possibly as high as 10 Tbps.

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www.picmg-systems.com PICMG Systems & Technology Resource Guide | Spring 2015 | 17 Industry Outlook is that you can’t get the same port density into an ASIC at 40G as you can at 25G because the basic building blocks don’t line up. In the case of 25 GbE, they do – 25 GbE I/O on the chip to 25 GbE I/O on the boxes. So you can get to the maximum “... WILL WE SEE 50 GBE density this way and the maximum throughput on the chips, which helps to optimize AND 200 GBE EMERGE? ... your switches, which helps to optimize and reduce cabling costs, power costs, and so on. So there is this inherent niceness to 1x or 4x architectures. I DON’T HAVE AN ANSWER

Now we’re getting to the question, and this is still a question, “Will we see 50 GbE FOR YOU TODAY, and 200 GbE emerge as speeds for backplanes?” BUT I GET THE LOGIC.” There’s been a lot of discussion and debate, and the logic of this is very relevant. But we’re still in the early stages of developing 50 GbE electrical signaling. I can tell you as Task Force Chair that this comes up and I have to keep people within the scope of there haven’t been any votes yet taken our project par. It’s not a foregone conclusion yet by any means in IEEE 802 because on any of these discussions. These are really industry debates around 50 GbE and 200 GbE.

So, will we see 50 GbE and 200 GbE “The Game-Changer” emerge? That is the question. I don’t have the answer for you today, but I get “A 40GbE MCH is here!” the logic. The role of the IEEE 802 specs is to produce high-quality, market-rele- vant standards. The IEEE 802 does not “ decree, “Thou shalt develop.” That’s not On-board GPS the way the process works. By market- receiver” relevant standards, what we’re saying is that the market decides what it wants to develop a standard for next. So the market market comes forward and says, “We want to do this.”

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18 | Spring 2015 | PICMG Systems & Technology Resource Guide www.picmg-systems.com PICMG Systems & Technology AdvancedMC

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Advantech’s ATCA solutions are more than just hardware designs as we go much further than an ordinary ODM. We ensure that our systems not only have outstanding stability secured by a world-class design quality assurance process, but are enhanced by building in features which improve availability, serviceability and usability. Features which have a moderate impact on cost as they have been carefully designed by Advantech’s in-house engineering teams and are kept consistent across the product line. Blades PICMG Systems & Technology The cornerstones of our ATCA product line are the blades designed in our own labs and manufactured on our own production lines. We manage the entire lifecycle and control all our costs to give customers the best service at the FEATURES right price. Our x86, NPU, DSP and switch blades are designed in unison with the leading silicon suppliers to give you early access to the very latest tech- ĄĄ Netarium-14 nology to accelerate your next generation product design and give you first- • 14-Slot, 14U fully integrated AdvancedTCA system ® ® mover advantage. • 12 Dual Intel Xeon blades + 2 hub blades (dual star) or 10 Dual Intel® Xeon® blades + 4 hub blades (dual-dual star) Systems • 40GbE/100GbE Switches ™ Advantech’s Netarium series of ATCA systems are specifically targeted to • AC or DC power; 300W+ per slot help network equipment providers reach superior levels of performance over • Advanced Shelf Management with Intel® Atom™ C2000 traditional rackmount servers or appliances and extend their product range at • OVS with DPDK offload; QuickAssist ready the high end. The series represents a new generation of systems which offer ĄĄ MIC-5342 Telecom Blade superior performance, scalability and flexibility with the latest 40/100GbE • Two Intel® Xeon® E5-2600 v3 Processors and Intel® DH8955 switches and application blades. We optimize the systems to achieve the • Up to 256GB ECC Memory highest possible density at the rack level, with a maximum number of payload • Up to 4x 40GBaseKR4 on FI (dual-dual star); 2x 1000BASE-T ports on BI blades, network ports and switching capacity. ĄĄ MIC-5345 Server Blade eATCA – For More High-End Real-Estate • Optimized for virtualized environments The new Extended ATCA (eATCA) system architecture from Advantech • Two Intel® Xeon® E5-2600 v3 Processors with Intel® C610 responds to next generation networking needs for more high performance I/O • Up to 256GB ECC memory connectivity and increased flexibility to add application-specific optimization • Up to 2x 40GBaseKR4 ports on FI ( dual star); 2x 1000BASE-T ports on BI hardware in high-end systems. • Single CPU version adds two 2.5" SSDs and two MO-297 SSDs (or two 2.5" SSDs and two CFast Cards) eATCA is a system architecture based on ATCA that delivers increased I/O and packet processing performance for networking platforms facilitating border- ĄĄ DSP-8901 DSP Blade less enterprise, secure datacenter, and cloud computing applications. eATCA • 20 Texas Instruments C6678 DSPs systems integrate standard ATCA blades with extended Rear Transition Mod- • 512MB/1GB DDR3 memory per DSP • BCM56321 10GbE switch for both FI and BI ules (eRTMs), providing almost four times more real estate for PCIe-based I/O ™ connectivity and enabling new capacity for acceleration and offload. • Freescale QorIQ P2020 for Local Management Processor (LMP) • IDT Tsi577 Serial RapidIO switches eATCA & ATCA Platform Management ... Appliance Style ĄĄ ATCA-7310 Network Processor Blade The SMM-5060, at the core of our ATCA platform management approach • Dual Cavium Octeon II CN6880 1.0 GHz makes ATCA look like a big appliance and is able to support a consistent • Up to 64GB DDR3 1066 MHz DIMMs; 32GB per NPU management view across our customers’ full product line. This means OEMs • 40 GbE (KR4) & 4x 10 GbE (KR) FI with Dual Star support utilizing appliances for their entry and mid-range networking gear will find • 8x 10GbE SFP+ and 4x 1GbE SFP to Rear I/O it surprisingly easy to add an ATCA based system as an extension of their ĄĄ product line at the high end. ATCA-9223 100GbE Hub Blade • 100GbE switch blade provides switching between two 100GbE uplinks, ® ™ Advantech’s SMM-5060 ATCA Shelf Manager features an Intel Atom pro- up to eighteen 10GbE uplinks and twelve 40GbE node slots cessor C2000 which brings added value system control and service process- • Fabric interface bandwidth up to 960Gpbs ing to ATCA and eATCA systems, and can be used as a centralized service • Broadcom BCM56150 base fabric switch with 70Gbps switching capacity access point or blade boot server. The SoC’s features enable encryption and • Intel® Atom Processor C2000 for flexible control plane processing decryption of external management traffic in business and mission critical • Two Virtex 7-690 systems. The SMM-5060 has been designed to maximize management flex- • FPGAs connect 2x 100G and 8x 10G for inline processing ibility in multi-blade systems. • Switch management

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