Metamaterial-Inspired CMOS Tunable Microwave Integrated Circuits for Steerable Antenna Arrays

Metamaterial-Inspired CMOS Tunable Microwave Integrated Circuits For Steerable Antenna Arrays

Mohamed A.Y. Abdalla

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto

°c Copyright by Mohamed Abdalla 2009

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Metamaterial-Inspired CMOS Tunable Microwave Integrated Circuits For Steerable Antenna Arrays Mohamed A.Y. Abdalla

Doctor of Philosophy, 2009

Graduate Department of Electrical and Computer Engineering

University of Toronto

Abstract

This thesis presents the design of radio-frequency (RF) tunable active inductors (TAIs) with independent inductance (L) and quality factor (Q) tuning capability, and their application in the design of RF tunable phase shifters and directional couplers for wireless transceivers.

The independent L and Q tuning is achieved using a modiﬁed gyrator-C architecture with an additional feedback element. A general framework is developed for this Q- enhancement technique making it applicable to any gyrator-C based TAI. The design of a 1.5V, grounded, 0.13µm CMOS TAI is presented. The proposed circuit achieves a

0.8nH-11.7nH tuning range at 2GHz, with a peak-Q in excess of 100.

Furthermore, printed and integrated versions of tunable positive/negative refractive

index (PRI /NRI) phase shifters, are presented in this thesis. The printed phase shifters are comprised of a microstrip transmission-line (TL) loaded with varactors and TAIs,

which, when tuned together, extends the phase tuning range and produces a low return loss. In contrast, the integrated phase shifters utilize lumped L-C sections in place of

ii the TLs, which allows for a single MMIC implementation. Detailed experimental results are presented in the thesis. As an example, the printed design achieves a phase of -40o to +34o at 2.5GHz.

As another application for the TAI, a reconﬁgurable CMOS directional coupler is presented in this thesis. The proposed coupler allows electronic control over the coupling coeﬃcient, and the operating frequency while insuring a low return loss and high isolation. Moreover, it allows switching between forward and backward operation. These features, combined together, would allow using the coupler as a duplexer to connect a transmitter and a receiver to a single antenna.

Finally, a planar electronically steerable patch array is presented. The 4-element array uses the tunable PRI/NRI phase shifters to center its radiation about the broadside direction. This also minimizes the main beam squinting across the operating bandwidth. The feed network of the array uses impedance transformers, which allow identical interstage phase shifters. The proposed antenna array is capable of continuously steering its main beam from -27o to +22o oﬀ the broadside direction with a gain of 8.4dBi at 2.4GHz.

iii Acknowledgments

I would like to gratefully acknowledge the enthusiastic supervision of my advisors Pro- fessor Khoman Phang, and Professor George Eleftheriades for their continuous guid- ance, and inspiration. Throughout the course of my Ph.D. I have learned alot from them, and I will always remain indebted to them. I would like to thank Professor Khoman Phang for consistently being there for me, week after week to meet and dis- cuss all the diﬀerent aspects of this work. As for Professor George Eleftheriades, I would like to deeply thank him for his invaluable advice and feedback, without which this work would not have been accomplished. I would also like to extend my thanks the former and current graduate students in my research group as well as in the electro-magnetics group for their invaluable technical assistance and friendship from which I have learned alot. From the electronics group, I would like to thank Dr. Anas Hamoui, Dr. Ahmed Gharbiya, Dr. Mohammad Ha- jirostam, Joseph Aziz, Pradip Thachile, Masum Hossain, Farsheed Mahmoudi, Stephen Liu, Euhan Chong, Kentaro Yamamoto, Dr. Faisal Musa, Robert Wang, Dr. Afshin Haftbaradaran, Imran Ahmed, Navid Yaghini, Oleksiy Tyshchenko, Kevin Banovic, Tony Kao, David Allred, Akram Nafee, Trevor Caldwell, Samir Parikh, and Nasim Nikkhoo. From the Electro-magnetics group, I would like to thank Marco Antoniades for all the long hours we spent in technical discussions, and also Rubaiyat Islam, Dr. Omar

iv Acknowledgements

Siddiqui, Ashwin Iyer, Joshua Wong, and Peter Wang. Also, I would like to thank Tse Chan and Gerald Dubois for their continuous technical support. I would also like to extend my thanks the Canadian Microelectronics Corporation (CMC) for providing the fabrication facilities, and for NORTEL Networks, and the Natural Sciences and Engineering Research Council (NSERC) of Canada for ﬁnancially supporting this work. Lastly, I would like to thank my beloved wife Aliaa, my parents, and my sister for their continuous support, and encouragement throughout the course of my Ph.D., and last but not least, I would like to thank my daughter Jana, whom without knowing has been a motivation for my accomplishments. The least I can do is to dedicate this work to them.

v List of Related Publications

The material presented in this thesis has been presented in part in the following journal and conference publications.

Journal Publications

1. M. Abdalla, K. Phang, and G. V. Eleftheriades, “A 0.13µm CMOS phase shifter using tunable positive/negative refractive index transmission line,” IEEE Microw. Wireless Components Lett., Vol. 16, no. 12, pp. 705-707, Dec. 2006. 2. M. Abdalla, K. Phang, and G. V. Eleftheriades, “Printed and integrated CMOS positive/negative refractive-index phase shifters using tunable active inductors,” IEEE Trans. Microw. Theory and Tech., Vol. 55, no. 8, pp. 1611-1623, August 2007. 3. M. Abdalla, K. Phang, and G. V. Eleftheriades, “A compact highly- reconﬁg- urable CMOS MMIC directional coupler,” IEEE Trans. Microw. Theory and Tech., Vol. 56, no. 2, pp. 305-3019, Feb. 2008. 4. M. Abdalla, K. Phang, and G. V. Eleftheriades, “A Planar Electronically Steer- able Patch Array Using Tunable PRI/NRI Phase Shifters,” IEEE Trans. Microw. Theory and Tech., accepted for publication Dec. 2008.

vi Conference Publications

1. M. Abdalla, and K. Phang , “A 0.13µm CMOS active inductor based on a modi- ﬁed gyrator-C architecture,” Micronet Annual Workshop, Ottawa, Canada, May 2005. 2. M. Abdalla, G. V. Eleftheriades, and K. Phang, “A diﬀerential 0.13µm CMOS active inductor for high frequency phase shifters,” Proc. IEEE Circuits and Sys- tems ISCAS 06, Kos, Greece, pp. 3341-3344, May 2006. 3. M. A. Y. Abdalla, K. Phang, and G. V. Eleftheriades, “a tunable metamaterial phase-shifter structure based on a 0.13µm CMOS active inductor,” Proc. 36th European Microwave Conf., Manchester, Great Britain, pp. 325-328, Sept. 2006. 4. M. A. Y. Abdalla, K. Phang, and G. V. Eleftheriades, “A bi-directional electronically tunable CMOS phase shifter using the high-pass topology,” 2007 IEEE MTT-S Int. Microwave Symp. Dig., Honolulu, Hawaii, pp. 2173-2176, June 2007. 5. M. A. Y. Abdalla, K. Phang, and G. V. Eleftheriades, “A steerable series-fed phased array architecture using tunable PRI/NRI phase shifters,” Invited paper, Int. Workshop on Antenna Tech. iWAT 08, Chiba, Japan, March 2008.

vii Contents

List of Figures xii

List of Tables xviii

List of Acronyms xx

List of Symbols xxii

1 Introduction 1 1.1 Overview ...... 1 1.2 Phased Antenna Array Front-Ends ...... 1 1.3 Thesis Scope and Outline ...... 5

2 Background 8 2.1 Metamaterials ...... 8 2.1.1 History ...... 8 2.1.2 Metamaterial Applications ...... 10 2.2 Tunable Inductors ...... 11 2.2.1 MEMS Tunable Inductors ...... 11 2.2.2 Varactor-Based Tunable Inductors ...... 12 2.2.3 Transmission-Line Tunable Inductors ...... 13 2.2.4 Gyrator-C Tunable Inductors ...... 13 2.3 Phase Shifters ...... 22 2.3.1 Switched-Line Phase Shifters ...... 23

viii Contents

2.3.2 Reﬂection-Type Phase Shifters ...... 24 2.3.3 Transmission-Type Phase Shifters ...... 25 2.3.4 Lumped-Element L-C Phase Shifters ...... 26 2.3.5 PRI/NRI Metamaterial Phase Shifters ...... 30 2.4 Directional Couplers ...... 32 2.4.1 Branch-Line Directional Couplers ...... 34 2.4.2 Coupled-Line Directional Couplers ...... 35 2.4.3 Lumped-Element L-C Directional Couplers ...... 36 2.4.4 PRI/NRI Metamaterial Directional Couplers ...... 38 2.5 Phased Antenna Arrays ...... 39 2.5.1 Antenna Arrays Basics ...... 39 2.5.2 Microstrip Patch Antenna ...... 43 2.5.3 Phased Array Feed Network Topologies ...... 45 2.5.4 Metamaterial Phased Antenna Arrays ...... 51

3 CMOS Tunable Active Inductors 53 3.1 Introduction ...... 53 3.2 Traditional Gyrator-C Architecture ...... 54 3.2.1 Quality Factor Analysis ...... 55 3.2.2 Q-Enhancement Technique For Gyrator-C TAIs ...... 57 3.3 The Modiﬁed Gyrator-C Architecture ...... 58 3.4 A Grounded 0.13µm CMOS TAI ...... 61 3.4.1 Circuit Design ...... 61 3.4.2 TAI Small-Signal Analysis ...... 64 3.4.3 TAI Noise Analysis ...... 66 3.4.4 Physical Realization and Experimental Characterization . . . . 68

4 Wide Tuning Range CMOS Phase Shifters 83 4.1 Introduction ...... 83 4.2 High-pass Phase Shifter ...... 87 4.2.1 Analysis ...... 87 4.2.2 Design and Physical Implementation ...... 90 4.2.3 Experimental Characterization ...... 91 4.3 TL PRI/NRI Phase Shifter ...... 96 4.3.1 Analysis ...... 97 4.3.2 Design and Physical Implementation ...... 99 4.3.3 Experimental Results ...... 100 4.4 MMIC PRI/NRI Phase Shifter ...... 103 4.4.1 Analysis ...... 105 4.4.2 Design and Physical Implementation ...... 108

ix Contents

4.4.3 Experimental Results ...... 110 4.5 Passive MMIC PRI/NRI Phase Shifter ...... 115 4.5.1 Analysis ...... 115 4.5.2 Design and Physical Implementation ...... 120 4.5.3 Experimental Results ...... 121 4.6 Discussion and Comparison ...... 124 4.6.1 Group Delay of PRI/NRI Phase Shifters ...... 128

5 A Highly-Reconfigurable Directional Coupler 131 5.1 Introduction ...... 132 5.1.1 Tunable Coupling Coefficient Directional Couplers ...... 133 5.1.2 Tunable Operating Frequency Directional Couplers ...... 133 5.2 Theoretical Analysis ...... 134 5.2.1 Analysis of the MMIC Directional Coupler ...... 134 5.2.2 MMIC Directional Coupler Modes of Operation ...... 138 5.3 Circuit Implementation ...... 144 5.3.1 MMIC Directional Coupler Design ...... 144 5.4 Physical Implementation and Experimental Results ...... 146 5.4.1 Physical Implementation ...... 146 5.4.2 Experimental Characterization of the MMIC Directional Coupler 148 5.5 Effect Of The TAI On The Coupler Noise Performance ...... 162

6 Electronically Steerable Series-Fed Patch Array 166 6.1 Introduction ...... 166 6.2 Theory ...... 168 6.2.1 Antenna Array Architecture ...... 168 6.2.2 Feed Network Design ...... 171 6.2.3 Interstage Phase Shifters ...... 176 6.3 Antenna Array Design ...... 178 6.4 Physical Implementation and Experimental Results ...... 182 6.4.1 Interstage Phase Shifter ...... 182 6.4.2 Steerable Antenna Array ...... 186 6.5 Antenna Array Linearity ...... 194 6.6 Discussion and Comparison ...... 197

7 Conclusion 202 7.1 Summary ...... 202 7.2 Contributions ...... 204 7.3 Future Work ...... 205

x Contents

Appendix A: Beam Squinting Analysis 208

Appendix B: Simulation Procedure 210

References 212

xi List of Figures

1.1 Wireless network established between wireless device and access point in the presence of interferers...... 2 1.2 A transceiver front-end employing a phased antenna array...... 3 1.3 Prototype of a 2-D interface between a region with positive permittivity and permeability (left-side) and a NRI region (right-side)...... 4 1.4 Single-stage, two-stage, four-stage, and eight-stage metamaterial phase shifters compared to a conventional TL phase shifter...... 4

2.1 Photograph of the lefthanded metamaterial (LHM) sample, reproduced from [1]...... 9 2.2 Tunable TL inductor designed by terminating λ/4 TL with a tunable capacitor...... 13 2.3 Circuit symbol of the gyrator, showing the polarities and directions of the port voltages and currents, respectively...... 14 2.4 (a) Block diagram implementation of the gyrator using transconductors. (b) Tunable active inductor designed by terminating the second port of the gyrator with a capacitor...... 15 2.5 (a) CS-CD TAI using an NMOS-NMOS realization. (b) CS-CD TAI using an NMOS-PMOS realization...... 17 2.6 (a) CG-CS TAI using an NMOS-NMOS realization. (b) CG-CS TAI using an NMOS-PMOS realization...... 18 2.7 (a) CS-CD TAI using a cascoded CS stage. (b) CS-CD TAI using a gain-boosted cascoded CS stage...... 19 2.8 Cascoded CS-CD TAI with a feedback resistance Rf ...... 21 2.9 A single stage of a switched-line phase shifter...... 23

xii List of Figures

2.10 Reﬂection-type phase shifter utilizing a 3dB coupler loaded with varactors. 24 2.11 Single stage of a transmission-type phase shifter...... 25 2.12 Diﬀerent high-pass and low-pass topologies for constant-impedance second- order L-C phase shifters...... 27 2.13 All-pass constant-impedance second-order L-C phase shifter...... 29 2.14 PRI/NRI metamaterial phase shifter unit-cell...... 30 2.15 Block diagram of a 4-port directional coupler...... 32 2.16 Diagram of a microstrip branch-line directional coupler...... 33 2.17 Diagram of a microstrip coupled-line directional coupler...... 35 2.18 lumped-element L-C low-pass and high-pass Π realizations of a branch- line coupler...... 36 2.19 L-C lumped-element high-pass Tee realization of a branch-line coupler. 37 2.20 L-C lumped-element realization of a coupled-line coupler...... 37 2.21 N-element uniform linear antenna array with equal amplitude excitation and a progressive phase constant φ...... 40

2.22 Array factor of a 4-element antenna array fed in-phase and with dE = λ/2. 41 2.23 Array factor of a λo/2 4-element antenna array fed with a progressive phase shift of ±90o...... 42 2.24 Rectangular microstrip patch antenna fed with a microstrip TL . . . . . 43 2.25 Inset-fed rectangular microstrip patch antenna...... 44 2.26 Elevation plane gain plot for a 2.4GHz rectangular microstrip patch antenna: (a) in the y-z plane, (b) in the x-z plane...... 45 2.27 A 4-element parallel-fed antenna array...... 47 2.28 A 4-element corporate-fed antenna array...... 47 2.29 A basic 4-element series-fed antenna array...... 48 2.30 A 4-element series-fed traveling wave in-line antenna array using a termination load...... 49 2.31 A 4-element series-fed traveling wave out-of-line antenna array without a termination load...... 49

3.1 Gyrator-C architecture and its equivalent circuit...... 54

3.2 Function f(RS) versus the negative series resistance RS...... 57 3.3 Modified gyrator-C loop and its equivalent circuit...... 58 3.4 The modified differential gyrator-C architecture...... 61 3.5 Proposed TAI circuit with the tunable feedback resistance...... 62

3.6 Digital/analog feedback resistance Rf ...... 64 3.7 Grounded active inductor equivalent circuit...... 65 3.8 Simpliﬁed TAI schematic with the main current and voltage noise sources, and equivalent lumped noise current model...... 67 3.9 Tunable active inductor die micrograph...... 68

xiii List of Figures

3.10 Measured TAI characteristics versus frequency when VC1=0V and VC2 changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor...... 70 3.11 Measured TAI characteristics versus frequency when VC1=0.1V and VC2 changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor...... 71 3.12 Measured TAI characteristics versus frequency when VC1=0.2V and VC2 changes from 0.3V to 0.4V: (a) Inductance, (b) Quality factor...... 71 3.13 Measured TAI characteristics versus frequency when VC1 changes from 0V to 0.4V and VC2=0.3V: (a) Inductance, (b) Quality factor...... 72 3.14 Theoretical and measured self-resonance frequency, fr, versus the inductance, L, for the different bias conditions...... 73 3.15 Theoretical and measured peak quality factor frequency, fQ, versus the self-resonance frequency, fr...... 73 3.16 Measured Q versus frequency for different feedback voltages Vf . . . . . 75 3.17 Measured S11 of the TAI for different feedback voltages Vf ...... 75 3.18 Measured and simulated results versus frequency when VC1=0V and VC2 is set to 0.6V and 0.4V: (a) inductance (b) series resistance...... 77 3.19 Circuit setup used for the simulation of the TAI circuit...... 77 3.20 Experimental test setup used for characterizing the TAI circuit linearity. 78 3.21 Amplitude of the power reflected back by the TAI versus the input power when applying a single RF signal source...... 79 3.22 Amplitude of the power reflected back by the TAI at f1 and 2f1 − f2 versus the input power when combining two RF signal sources...... 80

4.1 Different series-fed phased array designs and their radiation patterns. . 84 4.2 High-pass phase shifter unit-cell...... 87 4.3 Phase tuning range versus the capacitor tuning ratio rC ...... 89 4.4 Proposed high-pass phase shifter circuit implementation...... 90 4.5 High-pass phase shifter die micrograph ...... 91 4.6 Measured phase vs. freq., for different bias conditions ...... 92 4.7 Measured S11 and S21 vs. freq., for different bias conditions ...... 93 4.8 Measured phase and S21 at 4GHz vs. VB ...... 93 4.9 Measured S21 at 4GHz versus the feedback voltage Vf ...... 94 4.10 Amplitude of the output power versus the input power when applying a single 4GHz RF signal source ...... 95 4.11 Amplitude of the output power at f1 and 2f1 −f2 versus the input power when combining two RF signal sources ...... 95 4.12 TL PRI/NRI metamaterial phase shifter unit-cell...... 97 4.13 TL PRI/NRI metamaterial phase shifter unit-cell...... 99 4.14 Photograph of the tunable PRI/NRI phase shifter unit-cell...... 100 4.15 The measured and theoretical phase responses vs. freq. for different bias conditions. The phase expression of Eq.(4.10) is used for the comparison. 101

xiv List of Figures

4.16 Measured S11 vs. freq. for different bias conditions...... 102 4.17 Measured S21 vs. freq. for different bias conditions...... 102 4.18 Proposed IC PRI/NRI metamaterial phase shifter unit-cell...... 104 4.19 Dispersion diagram of the periodic structure composed of the proposed MMIC PRI/NRI phase shifter unit-cells...... 106 4.20 Proposed IC PRI/NRI metamaterial phase shifter unit-cell...... 109 4.21 MMIC PRI/NRI metamaterial phase shifter die micrograph...... 110 4.22 The measured and theoretical phase responses vs. freq. for different bias conditions. The phase expression of Eq.(4.19) is used for the comparison. 111 4.23 Measured S11 vs. freq. for different bias conditions...... 112 4.24 Measured S21 vs. freq. for different bias conditions...... 112 4.25 Measured S21 and phase shift φ at 2.6GHz versus the TAI feedback voltage Vf ...... 113 4.26 Unit cell of the proposed MMIC PRI/NRI tunable phase shifter. . . . . 115 4.27 Dispersion diagram of the periodic structure composed of the proposed passive PRI/NRI MMIC unit-cells...... 117 4.28 Proposed passive MMIC PRI/NRI phase shifter circuit implementation. 119 4.29 Phase MMIC PRI/NRI shifter die micrograph ...... 121 4.30 Measured phase vs. freq., for different bias conditions ...... 122 4.31 Measured S11 and S21 vs. freq., for different bias conditions ...... 122 4.32 Measured phase and S21 at 2.6GHz vs. the varactor reverse bias voltage VB1 ...... 123 4.33 The measured group delays of the metamaterial phase shifter and the simulated group delay of two cascaded 2nd-order all-pass filters . . . . . 129

5.1 Block diagram of a 4-port directional coupler configured in: (a) the forward mode of operation, and (b) the backward mode of operation. . 132 5.2 The high-pass topology used by the proposed MMIC directional coupler. 135 5.3 The equivalent circuit with even-mode excitation...... 135 5.4 The equivalent circuit with odd-mode excitation...... 136 5.5 Series capacitance C2 and the shunt inductance L required to satisfy the conditions of Eq.(5.9) and Eq.(5.10) versus the series capacitance C1. . 139 5.6 Coupling coefficients achieved by the MMIC coupler circuit ...... 139 5.7 Operating frequency of the MMIC coupler and the series capacitance C1 versus the shunt inductance L...... 142 5.8 Proposed lumped-element MMIC directional coupler circuit implementation...... 145 5.9 MMIC directional coupler die micrograph...... 147 5.10 Measured and theoretical coupling coefficients C vs. freq. for different bias conditions...... 149 5.11 Measured isolation S41 vs. freq. for the same bias conditions as Fig. 5.10.149

xv List of Figures

5.12 Measured reﬂection coeﬃcient S11 vs. freq. for the same bias conditions as Fig. 5.10...... 150

5.13 Measured and theoretical S41 vs. freq., for different bias conditions . . 153 5.14 Measured S11 vs. freq., for different bias conditions ...... 154 5.15 Measured S21 and S31 to the left and S41 to the right vs. the coupler operating frequency...... 155 5.16 Measured MMIC coupler S-parameters vs. frequency. Case 1: forward operation, the input power is equally divided between ports 3 and 2 while port 4 is isolated...... 158 5.17 Measured MMIC coupler S-parameters vs. frequency. Case 2: backward operation, the input power is equally divided between ports 3 and 4 while port 2 is isolated...... 158 5.18 Differential phase response of the MMIC coupler vs. frequency for the forward and the backward modes of operation...... 159 5.19 Duplexer operation (a) Receive mode is achieved by configuring the coupler in the forward mode. (b) Transmit mode is achieved by configuring the coupler in the backward mode...... 160

5.20 Measured S21 and S31 at 2.6GHz on the left and S41 at 2.6GHz on the right vs. the input power level...... 161 5.21 Block diagram of a 3dB coupler with the noise current sources representing the eﬀect of the active circuits within the TAIs...... 163

6.1 Basic 4-element series-fed antenna array...... 169 6.2 4-element series-fed antenna array with λ/4 impedance transformers. . 169 6.3 Alternating patch array diagram indicating the required ideal power splitting ratios and all the λ/4 transformer impedances...... 171 6.4 Power mismatch between the ﬁrst and fourth antennas versus the interstage phase shifter insertion loss...... 175

6.5 Normalized array factors for a 4-element λo/2 antenna array...... 175 6.6 Transmission-line tunable PRI/NRI metamaterial phase shifter unit-cell. 177 6.7 Photograph of the fabricated tunable TL PRI/NRI interstage phase shifter.183

6.8 The measured insertion phase φPS vs. freq. for diﬀerent bias conditions. 184 6.9 Measured S21 and S11 at 2.4GHz versus the insertion phase of the interstage phase shifter...... 185 6.10 Photograph of the fabricated electronically steerable series-fed patch array utilizing the tunable TL PRI/NRI interstage phase shifters. . . . . 186 6.11 Measured co- and cross-polarization and simulated co-polarization gain patterns in the azimuth plane (x-z plane) for diﬀerent bias conditions. . 189 6.12 Measured peak gain of the antenna array and the half-power beamwidth versus the scan angle...... 191

xvi List of Figures

6.13 Measured co- and cross-polarization and simulated gain patterns in the y-z plane...... 191 6.14 Input return loss, S11, of the antenna array versus frequency for all the diﬀerent bias conditions given by Fig. 6.11...... 192 6.15 Beam squinting characteristics: antenna array main-lobe angle, θp, and the peak gain, Gp, versus frequency...... 193 6.16 Experimental setup used to characterize the linearity of the steerable antenna array...... 195 6.17 Measured output power, Pout, of the horn antenna at 2.4GHz versus the antenna array input power Pin...... 195 6.18 Measured horn output power at the fundamental frequency f1 and at third-order intermodulation frequency 2f1 − f2 versus the antenna array input power...... 196

B-1 Flow chart showing the procedure used to simulate the TL PRI/NRI metamaterial phase shifters...... 211 B-2 Flow chart showing the procedure used to simulate the steerable antenna array...... 211

xvii List of Tables

2.1 Comparison Between Diﬀerent Directional Coupler Topologies...... 39 2.2 Comparison Between Diﬀerent Antenna Array Feed Network Topologies And The Requirements On The Interstage Phase Shifters...... 51

3.1 Transistor Sizes of the TAI Circuit ...... 63

3.2 Transistor Sizes of the Digital/Analog Tunable Feedback Resistance Rf 63 3.3 Measured Inductances for the TAI at 2GHz for Diﬀerent Values of the Bias Voltages VC1 and VC2...... 70 3.4 Comparison Between Diﬀerent Tunable Active Inductor Implementations 81

4.1 Summary of The High-Pass Phase Shifter Performance...... 96 4.2 Summary of the TL PRI/NRI Phase Shifter Performance...... 103 4.3 Summary of the TAI-Based MMIC PRI/NRI Phase Shifter Performance. 114 4.4 Summary of the Passive MMIC PRI/NRI Phase Shifter Performance. . 124 4.5 Comparison Between Diﬀerent Phase Shifter Designs Presented In This Chapter...... 125 4.6 Comparison Between Diﬀerent PRI/NRI Phase Shifter Implementations 127

5.1 Comparison Between the Proposed MMIC Directional Coupler and Other Variable Coupling Coeﬃcient Couplers ...... 152 5.2 Comparison Between the Proposed MMIC Coupler and Other Couplers with Variable Operating Frequency ...... 156 5.3 Linearity Comparison Between Diﬀerent TAI based Couplers ...... 161

xviii List of Tables

6.1 Series Feed Network Eﬃciency For Diﬀerent Interstage Phase Shifter Loss Values ...... 174 6.2 Comparison Between The Proposed Steerable Patch Array And Other Published Series-Fed Steerable Antenna Arrays...... 198 6.3 Comparison Between The Measured Beam Squinting Of The Proposed Array And Other Published Antenna Arrays...... 200

xix List of Acronyms

1-D One-Dimensional

2-D Two-Dimensional

BiCMOS Bipolar Complementary Metal Oxide Semiconductor

BW Bandwidth

CD Common-Drain

CG Common-Gate

CMOS Complementary Metal Oxide Semiconductor

CPW Co-Planar Waveguide

CS Common-Source

DAC digital-to-analog converter

FOM Figure-of-merit

GaAs Gallium Arsenide

GSG Ground-Signal-Ground

GSGSG Ground-Signal-Ground-Signal-Ground

HPBW Half Power Beamwidth

xx List of Acronyms

IC Integrated Circuit ISM Industrial, Scientific and Medical LHM Left-Handed Medium LNA Low-Noise Amplifier MEMS Micro-electromechanical systems MESFET Metal-Semiconductor Field Effect Transistor MIM Metal-Insulator-Metal MMIC Monolithic Microwave Integrated Circuit NF Noise Figure NMOS N-channel Metal Oxide Semiconductor NRI Negative Refractive Index PCB Printed Circuit Board PIFA Planar Inverted F Antenna PMOS P-channel Metal Oxide Semiconductor PRI Positive Refractive Index QFN Quad Flat-Pack No Lead TAI Tunable Active Inductor TL Transmission-Line TX Transmitter RF Radio Frequency RHM Right-Handed Medium RX Receiver SiGe Silicon Germanium WSN Wireless Sensor Network

xxi List of Symbols

AF Antenna array factor β Propagation constant c Speed of light C Directional coupler coupling coefficient C Capacitance dE Inter-element distance dPS Phase shifter length D Directional coupler directivity ²r Relative dielectric constant ²eff Effective relative dielectric constant E Electric field EF Antenna element factor f Frequency ft Transistor unity-gain frequency φ Phase shift gm Transconductance G Interstage phase shifter absolute power gain γ Transistor noise coefficient Γe,o Reflection coefficient for even- and odd-mode circuits h Substrate height H Magnetic field i2 mean-square value of the drain current thermal noise for transistor M nMx x I Current k Boltzmann constant L Inductance

xxii List of Symbols

λ Wavelength nf Number of transistor fingers ηfeed Feed network efficiency N Number of antenna array elements P power Q Tunable active inductor quality factor QP Peak-Q rC Capacitance tuning ratio rL Inductance tuning ratio ro Transistor small-signal output resistance R Resistance RS Tunable active inductor series resistance s Complex frequency variable S11 Input reflection coefficient Sxy Transmission coefficient from port x to port y T Temperature Te,o Transmission coefficient for even- and odd-mode circuits Tgd Phase shifter group delay θ Angle of antenna array main beam v2 mean-square value of the thermal noise voltage for resistor R nRx x V Voltage VDS,sat Transistor saturation drain-source voltage VEF Transistor overdrive voltage VGS Transistor gate-source voltage VTH Transistor threshold voltage W Patch antenna width Wf Transistor finger width ω Angular frequency ωo Zero phase frequency ωp Tunable active inductor peak-Q frequency ωr Tunable active inductor resonance frequency X Susceptance Z Impedance ZA Antenna impedance Zo Characteristic impedance ZPS Phase shifter impedance ZT λ/4 transformer impedance

xxiii CHAPTER 1

Introduction

1.1 Overview W ireless communications is one of the major foundations of the current revolution in information technology. Due to its unlicensed nature, the 2.4-2.5GHz industrial, scientific and medical (ISM) band has become a popular choice for a variety of wireless applications. Unfortunately, this popularity is causing congestion, resulting in more interference and eventually degrading the performance of wireless links. Further- more, the increasing level of interference from the neighboring wireless devices imposes tough constraints on the transceiver design, starting with the specified level for the transmitted power and ending with the specified receiver noise figure. To meet the required performance from a wireless link, and at the same time relax the transceiver design constraints, one can utilize the principle of phased antenna arrays.

1.2 Phased Antenna Array Front-Ends

Phased antenna arrays are capable of producing narrow, high-gain beams compared to omni-directional antennas. In a phased array wireless link, the transmitted power

1 1.2. PHASED ANTENNA ARRAY FRONT-ENDS 2

Wireless access TX Interference point RX Interference TX RX

(a) (b)

Figure 1.1: Wireless network established between wireless device and access point in the presence of interferers. (a) In this case, all devices use omni-directional antennas, (b) In this case, the wireless device under consideration uses a phased antenna array, resulting in a narrow and steerable beam. is focused towards the intended wireless device, and at the same time, the receiving device is focused in the direction of the transmitting device. This is illustrated in Fig. 1.1-a and Fig. 1.1-b, which show qualitatively how the effect of interference from the neighboring devices and the effect of noise from the surrounding environment can be reduced by deploying phased antenna arrays. This will result in higher signal to noise ratios, leading to lower bit-error rates. It is also worth mentioning that, using phased antenna arrays reduces the effects of issues such as multi-path fading. A simplified block diagram of a transceiver front-end utilizing a phased antenna array is shown in Fig. 1.2. The electronic beam steering network is required to feed the different antennas with the appropriate signal amplitudes and phases by utilizing electronically tunable phase shifters. Currently, the use of phased arrays is largely limited to high-precision military radar systems and satellite communications due to the lack of compact, broadband, electronically tunable phase shifters that are cost-effective and can easily be integrated onto the same printed circuit board (PCB) with printed antennas. Furthermore, the large area occupied by the beam steering network of parallel-fed arrays, which are, to date, the dominant choice for high data-rate applications, has also been a deterring factor for deploying phased arrays in wireless consumer applications. 1.2. PHASED ANTENNA ARRAY FRONT-ENDS 3

Electronic Beam Steering

RX TX

Duplexer Low Noise Power Power monitoring Amplifier Amplifier RSSI

Transceiver

Figure 1.2: A transceiver front-end employing a phased antenna array.

The beam steering network of series-fed arrays, on the other hand, is very compact, but suffers from large beam squinting1 with frequency. However, with the recent developments in the field of metamaterials, there is the potential to design compact, broadband phase shifters suitable for series-fed antenna arrays, allowing their deployment in high data-rate wireless consumer applications. Metamaterials are artificial dielectrics that display electromagnetic properties that do not exist in naturally occurring materials: for example, simultaneous negative permittivity and permeability. Consequently, they can possess a negative index of refraction (NRI). For radio frequency (RF) applications, the interest in metamaterials was sparked by their compact planar implementation proposed in 2002 [3, 4], which allows for its integration with various RF and microwave electronic systems. Fig. 1.3 shows a photograph reproduced from [2] of a 2-D metamaterial. The unit-cell of this 2-D NRI metamaterial is comprised of two microstrip TLs loaded with series capacitors and a shunt inductor. Metamaterials concepts have been used to develop compact, broadband phase shifters with small and relatively flat group delays [5]. These phase shifters are designed by cascading multiple 1-D unit-cells of a NRI metamaterial. The compact implementation of these metamaterial phase shifters, which is illustrated in Fig. 1.4,

1Beam squinting is deﬁned here as the variation in the angle of the main beam of the antenna array with frequency. 1.2. PHASED ANTENNA ARRAY FRONT-ENDS 4

Figure 1.3: Prototype of a 2-D interface between a region with positive permittivity and permeability (left-side) and a NRI region (right-side). Picture reproduced from [2]. The inset magniﬁes a single unit cell of the NRI region, consisting of a microstrip grid loaded with surface-mounted capacitors and an inductor embedded into the substrate at the central node.

Metamaterial phase shifters

Conventional 360o TL phase shifter

Figure 1.4: Single-stage, two-stage, four-stage, and eight-stage metamaterial phase shifters compared to a conventional TL phase shifter. Picture reproduced from [5]. 1.3. THESIS SCOPE AND OUTLINE 5 is necessary for the beam steering networks of series-fed antenna arrays. Furthermore, the low group delay of metamaterial phase shifters will result in smaller variations in the direction of the array’s main beam across the operating bandwidth [6], which makes them suitable for high date-rate applications. However, until now, metamaterial phase shifters have utilized discrete, or printed capacitors and inductors having fixed values, and as such, are not tunable. By utilizing the capabilities offered by CMOS monolithic microwave integrated circuits (MMICs) to replace the fixed capacitors and inductors with tunable ones, the phase response of these metamaterial phase shifters would potentially be electronically tuned. Besides tunability, utilizing CMOS MMIC technology would result in a more compact implementation compared to current, TL-based implementations. These compact, electronically tunable metamaterial phase shifters could then be integrated within the feed network of series-fed antenna arrays. This would allow implementing the antenna array with the beam steering network on a single planar PCB, making it more appealing for high data-rate wireless consumer applications. The benefits of tunability could also extend to the duplexer. The duplexer in the phased array front-end of Fig. 1.2 operates as a switch, and is a necessary component in the transceiver front-end to allow sharing the same antenna array between the transmitter and the receiver. However, duplexers are usually designed using discrete, or printed components. Hence, duplexers are bulky and are not tunable. If the duplexers could be made tunable, transceivers could be made to support multi-standard operation. This can also be achieved by using CMOS MMICs to design highly-reconfigurable compact duplexers, which in the future will allow their integrating the duplexer with the transceiver front-end on a single CMOS integrated circuit (IC). Moreover, the transmitted and received power could be monitored by replacing the 3-port duplexer with a 4-port highly-reconfigurable directional coupler. This would allow for precise control over the level of the TX power and the gain of the low-noise amplifier.

1.3 Thesis Scope and Outline

This thesis investigates the design of RF tunable active inductors (TAIs), and their application in the design of tunable phase shifters, directional couplers, and steerable antenna arrays. An electronically tunable version of the compact, broadband, TL metamaterial phase shifter is presented. Furthermore, two novel fully-integrated, tunable, 1.3. THESIS SCOPE AND OUTLINE 6

versions of the metamaterial phase shifter are presented in this thesis. Tunability is achieved by combining the use of varactors and TAIs. The thesis also presents the design of a compact, CMOS MMIC, highly-reconfigurable, directional coupler to replace the duplexer in wireless transceiver front-ends, and at the same time allow for multi-standard operation as well as power monitoring. Similar to the tunable phase shifters, the proposed MMIC directional coupler combines the use of varactors and TAIs. Since the TAI plays a major role in the design of both the phase shifters and the directional coupler, this thesis also presents a design methodology for TAIs that allows independently tuning its inductance (L) and quality factor (Q). Tuning L and Q independently is a key feature to overcome the degradation of the insertion loss and return loss of the TAI-based circuits while electronically tuning their response. In addition, the tunable metamaterial phase shifters presented in this thesis are used to design the beam steering network of a series-fed patch array, and electronic beam steering is demonstrated using a prototype antenna array. Chapter 2 of this thesis starts by briefly summarizing the recent developments in the field of metamaterials and its applications. Following that, it gives the necessary background information about TAIs, phase shifters, directional couplers, and phased antenna arrays. Chapter 3 presents a design methodology for RF TAIs that allows independent tuning of their L and Q, by using a modified gyrator-C architecture with an additional feedback element. The proposed Q-enhancement technique is generalized for the gyrator-C architecture, which makes it applicable to any gyrator-C based TAI. To verify the proposed architecture, a novel grounded TAI design is presented along with the simulation and experimental results. In chapter 4, TL-based and fully-integrated versions of electronically tunable metamaterial phase shifters are presented. The TL-based phase shifters presented in this thesis have evolved from the metamaterial phase shifter topology presented in [5] by replacing the fixed, discrete components with IC, tunable, active elements (i.e. varactors and the TAIs presented in chapter 3). Combining the use of varactors and TAIs results in a wide phase tuning range, and allows the phase shifters to achieve a very low return loss across their entire tuning range. To the author’s knowledge, the CMOS MMIC designs presented in this chapter are considered the first attempts to design fully-integrated, tunable, metamaterial phase shifters in a standard CMOS process. 1.3. THESIS SCOPE AND OUTLINE 7

Following that, a novel CMOS MMIC, highly-reconfigurable directional coupler is presented in chapter 5. The directional coupler uses varactors and the TAIs presented in chapter 3 to allow extensive electronic control over the coupling coefficient. At the same time, this allows the coupler to be re-configured for operation over a wide range of frequencies. To the author’s knowledge, this is the first coupler that combines those two features; i.e. simultaneously providing a tunable coupling coefficient and a tunable operating frequency. Moreover, the symmetric configuration of the coupler allows it to switch from forward to backward operation by simply exchanging the bias voltages applied to the varactors. This makes the proposed directional coupler ideal to replace the bulky passive duplexers in transceiver front-ends, enabling multi-standard operation as well as power monitoring. Chapter 6 presents a planar electronically steerable series-fed patch array for 2.4GHz ISM band applications. The proposed steerable array uses the tunable TL metamaterial phase shifters, presented in chapter 4, to center its radiation about the broadside direction and allow scanning in both directions off the broadside. Also, using the metamaterial phase shifters reduces the squinting of the main beam across the operating bandwidth. The feed network of the proposed array uses λ/4 impedance transformers. This allows using identical interstage phase shifters, which share the same control voltages to tune all stages. Furthermore, using the impedance transformers in combination with the CMOS-based, constant-impedance metamaterial phase shifters guarantees a low return loss for the antenna array across its entire scan angle range. To the author’s knowledge, the proposed antenna array is the first resonant antenna-element structure that demonstrates electronic beam steering utilizing tunable metamaterial phase shifters. Finally, Chapter 7 concludes the thesis and suggests directions for future research. CHAPTER 2

Background

This chapter reviews the basic concepts in topics related to the work presented in this thesis. This chapter does not present new material and readers can skip it and proceed to chapter 3 for the main contributions of the thesis.

2.1 Metamaterials

metamaterial is a broad word referring to any artiﬁcial material having properties A that are not found in nature. It stems from the Greek word meta meaning beyond. Throughout this thesis, the term metamaterial will refer to mediums possessing a negative permeability simultaneously with a negative permittivity.

2.1.1 History

In 1968, Veselago proposed that materials with simultaneously negative permeability and permittivity will provide a negative index of refraction [7]. Furthermore, in such a medium, the electric ﬁeld, E, the magnetic ﬁeld, H, and the propagation vector, k, will form a left-handed triplet instead of a right-handed one, thus it can also be termed

8 2.1. METAMATERIALS 9

Figure 2.1: Photograph of the lefthanded metamaterial (LHM) sample, reproduced from [1]. The LHM sample consists of square copper split ring resonators and copper wire strips on ﬁber glass circuit board material. The rings and wires are on opposite sides of the boards.

a left-handed medium. However, their realization was not possible before 1999 when Pendry et al. showed how to realize a negative permeability from a split ring resonator structure [8]. Following that, Smith et al. showed a composite 3-dimensional (3-D) material that exhibits simultaneously negative permittivity and permeability [1, 9]. These structures use strip wires to realize the negative permittivity and use split ring resonators to synthesize the negative permeability [8]. The dimensions of the split ring resonators and strip wires determine their resonance frequencies and hence the overlapping regions with negative permittivity and permeability [1,9]. Figure 2.1 shows a photograph reproduced from [1] of a 3-D NRI medium based on an array of split ring resonators and strip wires. The dependence on the resonance of the split ring resonators to synthesize a negative permeability makes the NRI medium inherently narrow-band, the design presented in [1] shows a negative index of refraction over a range of frequencies from 10.2GHz to 10.8GHz. Furthermore, the implementation of the 3-D NRI medium is quite bulky. In his paper, Veselago pointed out many interesting phenomena related to wave propagation in NRI metamaterials, such as: reversed refraction, or, in different terms, inverted Snell’s law, and reversed Doppler effect. Hence, metamaterials moved from a theoretical concept to a practically realizable medium, and their reverse refraction characteristic made them suitable for focusing electromagnetic waves at a PRI1/NRI boundary with sub-wavelength resolving properties. This idea was proposed in 2000 2.1. METAMATERIALS 10 when a 3-D NRI metamaterial lens was presented in [10]. However, metamaterials still remained bulky 3-D structures, which hindered their application within various RF and microwave electronic systems. In 2002, Eleftheriades et al. proposed a new approach to build a 2-dimensional (2-D) NRI metamaterial by periodically loading TLs with series capacitors and shunt inductors [11], thus replacing the bulky 3-D wire strips and split ring resonators by a 2- D planar design. The same method was also proposed by another group at UCLA [12]. A photograph of a 2-D metamaterial designed using microstrip lines as the host TLs is shown in chapter 1 in Fig. 1.3. The unit-cell of this NRI metamaterial is comprised of microstrip TLs loaded with series capacitors and a shunt inductor. These developments allowed the first experimental demonstration of focusing from a planar 2-D PRI/NRI interface [3]. Following this, interest in NRI metamaterials was sparked in the RF and microwave community.

2.1.2 Metamaterial Applications

Novel RF and microwave circuits were designed utilizing the additional degree of freedom offered by NRI media, such as building compact broadband TL PRI/NRI zero- degree phase shifters with small and relatively flat group delays [5]. These phase shifters are designed by cascading the 1-D version of the unit-cell shown in Fig. 1.3 to create a 1-D metamaterial line. One application that would benefit from these PRI/NRI phase shifters is series-fed antenna arrays, as will be described in more detail throughout this thesis. Furthermore, broadband PRI/NRI series power dividers have been proposed in [13] to feed loads in phase that are not electrically close to each other. Directional couplers can also benefit from the advances in planar NRI metamaterials; a dual-frequency branch-line coupler was presented in [14] and two high directivity coupled-line couplers were presented in [15] and [16]. Moreover, it was demonstrated in [17] that one of the dimensions of a coupler can be significantly reduced by coupling the electromagnetic power between a NRI line and a PRI TL as opposed to a conventional coupler design in which power is coupled between two PRI TLs. The compact planar metamaterial implementation also enabled other applications, such as the leaky

1PRI stands for a positive-refractive-index media, which corresponds to having a positive permittivity and permeability. 2.2. TUNABLE INDUCTORS 11 backward-wave antennas presented in [18]. Also, electrically-small, metamaterial-based antennas have recently been presented in [19, 20]. Hence, the field of metamaterials appears to have much potential for both RF and microwave applications. Electronically tuning the characteristics of metamaterials, by replacing the fixed series capacitors and shunt inductors with electronically tunable capacitors and inductors, can provide re-configurability to all the different metamaterial applications. Further- more, this may open-up a whole new range of applications, such as designing planar RF lenses which posses a tunable focal length. Since tunable capacitors can easily be obtained by using varactors, the next section will focus instead on techniques used to design tunable inductors.

2.2 Tunable Inductors

The most widely used method to design printed inductors on PCBs or integrated inductors in current IC technologies is by means of planar spirals. However, the inductance of spiral inductors is a function of their geometry. Hence, spiral inductors provide only ﬁxed inductances.

2.2.1 MEMS Tunable Inductors

Micro-electromechanical systems (MEMS) have demonstrated the capability of synthesizing RF tunable inductors. For instance, a MEMS tunable RF inductor is presented in [21], which consists of two loops self-assembled with a specific angle between them. By controlling the ambient temperature of the inductor, this angle and hence the effective distance between the two loops can be varied, which in turn changes the mutual inductance component. This, however, results in a limited inductance tuning range; 0.83-0.65nH at 4GHz for varying the temperature from 25oC to 200oC, respectively, and a low Q of 6, where Q is a measure of the efficiency of an inductor, and is given by Im(Zin)/Re(Zin). In another more recently published paper [22], an electronically tunable MEMS inductor was presented. This inductor is composed of an aluminum layer micro-machined on top of an amorphus silicon layer. The tunability of the inductor is based on the bimorph effect, which can be explained as follows. When a voltage is applied across 2.2. TUNABLE INDUCTORS 12

the inductor, its structure deforms in a controllable manner, which occurs due to difference in the thermal expansion coeﬃcients of the two layers. The inductor achieves a 6.5-9.8nH tuning range at 3GHz, and achieves quality factors ranging from 5 to 15 respectively. However, the inductor dissipates 220mW to actuate the necessary de- formation in its structure. This power is required to raise the temperature of the structure. Although MEMS tunable inductors, in general, can provide high self-resonance frequencies and high-speed operation, most of them use thermal eﬀects to tune the inductance. This dramatically reduces the speed of switching, which is the time required to change the inductance from one value to another. Furthermore, most of the MEMS inductors rely on vertical movements to tune their inductance. Consequently, the resulting 3-D moving structures make it challenging to package and to integrate MEMS inductors with electronic circuits fabricated in a standard CMOS process.

2.2.2 Varactor-Based Tunable Inductors

Another common method to tune the inductance of IC spirals is to use varactors. By connecting a varactor in series, or in shunt, with a fixed spiral inductor, one can tune the effective inductance by varying the bias voltage applied across the varactor. On such example is demonstrated in [23], where a series varactor is used to tune the inductance of a 2-port, i.e. series, spiral inductor to design a tunable phase shifter. However, this technique is only valid over a very narrow-band of frequencies (with fractional bandwidths of 10%-20% as reported in [23]), since the effective inductance can only be assumed constant over a narrow-band of frequencies. This is a result of the direct relation between the effective inductance and the frequency, which for a shunt connection is given by: 1 L = L − , (2.1) eff ω2C where L and C are the fixed spiral inductance and the tunable varactor capacitance respectively. Furthermore, this technique results in low quality factors, since the effective Q is limited by the low-Q of the IC spiral inductors. 2.2. TUNABLE INDUCTORS 13

CL in /4

Figure 2.2: Tunable TL inductor designed by terminating λ/4 TL with a tunable capacitor.

2.2.3 Transmission-Line Tunable Inductors

Another very simple approach to build tunable inductors can be derived from the basic

TL model. Terminating a λ/4 TL with an arbitrary impedance ZL, where λ = c/f is the wave-length, c is the speed of light, and f is the design frequency, results in an input impedance of: 2 Zo Zin = , (2.2) ZL where Zo is the characteristic impedance of the TL [24]. As Eq.(2.2) indicates, a λ/4 TL acts as an impedance inverter. Hence, loading this TL with a capacitor results in an inductive input impedance, with an inductance of:

2 L = Zo CL, (2.3)

where CL is the load capacitance. Furthermore, the inductance can be tuned by replacing the ﬁxed capacitor with a varactor as shown in Fig. 2.2. Although this technique might seem unsuitable for IC designs due to the need for TLs, when operating at high frequencies the TL size becomes practical for IC implementations. However, this technique results in very narrow band inductors; since Eq.(2.2) is only valid at the design frequency f, which limits its applicability.

2.2.4 Gyrator-C Tunable Inductors

The most popular technique used to build tunable synthetic inductors is by terminating a gyrator with a capacitive load. This technique has greatly beneﬁted from the advances in modern CMOS technologies, which are now capable of providing transistors with very

high unity-gain frequencies (ft), allowing the design of RF TAIs. The use of RF TAIs have been demonstrated in numerous applications. For instance, they were used by 2.2. TUNABLE INDUCTORS 14

I1 I2 + + I1 + + I2

V1 V2 V1 V2 CL - - - -

(a) (b) Figure 2.3: Circuit symbol of the gyrator, showing the polarities and directions of the port voltages and currents, respectively.

Mukhopadhyay et al. in [25] to design wide-tuning range voltage-controlled oscillators (VCOs), they were also used by Wu et al. in [26] to design RF tunable ﬁlters, and in [27] and [28] to design RF phase shifters and power dividers respectively.

History

The gyrator, of which circuit symbol is shown in Fig. 2.3-a was originally introduced as a new circuit element in 1948 by Tellegen [29]. Using the standard 2-port network representation, the impedance matrix of a gyrator can be deﬁned as: " # " #" # V 0 −r I 1 = 1 1 , (2.4) V2 r2 0 I2

where V1,2 and I1,2 are the voltage and current at ports 1 and 2 of the gyrator, respec-

tively, as indicated in Fig. 2.3-a, and r1 and r2 are the gyration resistances. Terminat-

ing a gyrator with a load impedance ZL, as shown in Fig. 2.3-b, results in an input

impedance Zin, which is expressed as:

r1r2 Zin = . (2.5) ZL

Hence, terminating the circuit with a capacitive load CL results in an inductive input impedance with an inductance L expressed as:

L = r1r2CL. (2.6)

According to Eq.(2.6), the inductance of the circuit can simply be tuned by varying

either the load capacitance or the gyration resistances r1 or r2. Hence, the gyrator-C 2.2. TUNABLE INDUCTORS 15

io1=gm1vin1

io1 vin1 gm1 gm1

V1 V2

I1 I2 CL Zin

-gm2 -gm2 vin2 io2

io2=-gm2vin2 (a) (b)

Figure 2.4: (a) Block diagram implementation of the gyrator using transconductors. (b) Tunable active inductor designed by terminating the second port of the gyrator with a capacitor.

architecture is capable of synthesizing a tunable inductance. The gyrator-C inductors are termed active, since gyrators are implemented using active devices (transistors). Furthermore, unlike Eq.(2.1), Eq.(2.5) is valid for all frequencies as long as the gyrator characteristics can still be described by the impedance matrix of Eq.(2.4). To the author’s knowledge, the first circuit implementation of a gyrator was presented by Morse et al. in 1964, and was based on operational amplifiers [30]. The proposed circuit implementation used four operational amplifiers. Following that, other designs were presented in the literature trying to minimize the number of operational amplifiers required to implement the gyrators. For instance, the design in [31] was published in 1971, and requires only two operational amplifiers. An alternative circuit implementation for a gyrator is to use two transconductors connected back-to-back (gm1 and gm2) as shown in Fig. 2.4-a. This approach was originally proposed by Sharpe in 1957 [32], and the first circuit implementation of a such a circuit was presented along with its experimental characterization in 1965 [33]. Using operational amplifiers initially seemed more attractive to build gyrators, due to their standard designs. However, most of the RF TAIs presented in the literature use transconductors, since this approach is more suitable for high-speed applications [25, 26, 34–43]. Hence, our focus here is directed towards this latter approach to build TAIs, and throughout this 2.2. TUNABLE INDUCTORS 16

thesis, the term gyrator-C TAI will refer to the transconductor-based design. It is worth mentioning that, the gyrator-C active inductor in Fig. 2.4-b is single-ended, or, in other words, it represents a grounded inductor. Although the generalized gyrator-C circuit in Fig. 2.3-b can produce 2-port, or ﬂoating, inductors, the diﬃculty of its implementations prohibits the design of 2-port active inductors. This will be one of the main factors in the selection of the appropriate architectures for the TAI-based phase shifters and the TAI-based coupler in chapters 4 and 5, respectively.

First-Order Analysis of Gyrator-C TAIs

Assuming ideal transconductors, one can show that the impedance matrix of the circuit in Fig. 2.4-a is given by:   " # 1 " # V 0 − I 1  gm1  1 =  1  . (2.7) V2 0 I2 gm2

By comparing Eq.(2.7) with Eq.(2.4), it becomes evident that the circuit is equivalent

to a gyrator. Furthermore, terminating the circuit with a capacitive load CL, as shown in Fig. 2.4-b, results in an inductive input impedance, and the inductance L can be expressed as: C L = L . (2.8) gm1gm2 According to Eq.(2.8), the inductance of the circuit can simply be tuned by varying the load capacitance CL, gm1, or gm2. This analysis assumes ideal transconductors with infinite input and output impedances as well as zero input and output capacitances. This results in an ideal inductor with an infinite Q, which is defined as:

Im(Z ) Q = in , (2.9) Re(Zin)

where Zin is the input impedance of the gyrator-C circuit. A more detailed analysis of the gyrator-C architecture will be presented in chapter 3 which takes into account the second-order eﬀects. 2.2. TUNABLE INDUCTORS 17

Vdd Vdd

Vdd Vdd I2 I1 I1 M2

M1 M1 I2 Zin Zin (a) (b)

Figure 2.5: (a) CS-CD TAI using an NMOS-NMOS realization. (b) CS-CD TAI using an NMOS-PMOS realization.

Overview of Transistor-Based Gyrator-C TAIs

The simplest implementation of a high-Q TAI can be obtained by replacing each transconductor in Fig. 2.4 with a single-transistor transconductor2. Only two different combinations of transistor topologies are possible to maintain the negative feedback; a common-source, common-drain topology (CS-CD), and a common-gate, common- source topology (CG-CS). Using different combinations of NMOS and PMOS transistors results in eight different TAI circuit implementations. These eight different TAI realizations are summarized in [34]. Figure 2.5-a shows the CS-CD topology using an NMOS-NMOS realization, whereas Fig. 2.5-b shows the CS-CD topology using an

NMOS-PMOS realization. In either case, the capacitor CL, used to terminate the gyrator in Fig. 2.4, is removed and the circuit relies on the input capacitance of the second transconductor instead, i.e. the capacitance at the gate of M2. Eliminating CL and re- lying on the parasitic capacitance makes the TAI circuit capable of operating at higher speeds. The circuit in Fig. 2.5-a was originally proposed in [45], and requires a minimum supply voltage of 2VGS +VDS,sat. The circuit in Fig. 2.5-b was originally proposed in [46], and requires only VGS +2VDS,sat making it more appealing for low-voltage oper-

2Active inductors can also be designed using a single transistor. For example, in the presence of a gate resistance the impedance looking into the source terminal of a common-drain ampliﬁer, has an inductive component [44]. However, this techniques are not suited for high-Q wide-tuning range active inductors. 2.2. TUNABLE INDUCTORS 18

Vdd Vdd Vdd I2 I1,2

M2 M2 VB VB

M1 Zin I1+I2 Zin

(a) (b)

Figure 2.6: (a) CG-CS TAI using an NMOS-NMOS realization. (b) CG-CS TAI using an NMOS-PMOS realization.

ation. However, one can show that for both transistors to be ON and operating in the

saturation region the value of the overdrive voltage of transistor M2, which is given by

VEFF 2 = VSG2 −|VTHP |, has to satisfy the following equation: VEFF 2 < VTHN −|VTHP |,

where VTHN and VTHP are the threshold voltages of the NMOS and PMOS transis-

tors respectively. In modern CMOS processes, where the values of VTHN and VTHP are close, this results in a small ft for transistor M2 making the circuit of Fig. 2.5-b incapable of high-speed operation. The two other CS-CD TAI circuit realizations can be derived from Fig. 2.5 by using a PMOS-PMOS and a PMOS-NMOS conﬁguration for M1 and M2 respectively.

Figure 2.6-a shows the CG-CS topology using an NMOS-NMOS realization. This circuit was originally proposed in [47], and requires a minimum supply voltage of

VGS + VDS,sat. This makes it suitable for low-voltage applications. Furthermore, both transistors use the same bias current making this TAI topology suitable for low-power applications. The NMOS-PMOS realization of the CS-CG topology is shown in Fig. 2.6- b. It requires a minimum supply voltage of VGS +2VDS,sat, which is slightly higher than that of the NMOS-NMOS realization. Also, the ability to control the bias current of both transistors results in a wider inductance tuning range at the expense of higher power consumption. 2.2. TUNABLE INDUCTORS 19

Vdd Vdd Vdd Vdd I1 I1

M2 M2 VB VB + M3 A M - 3

M1 M1

I2 I2 Zin Zin

(a) (b)

Figure 2.7: (a) CS-CD TAI using a cascoded CS stage. (b) CS-CD TAI using a gain- boosted cascoded CS stage.

Quality Factor Enhancement Techniques For Gyrator-C TAIs

Replacing each transistor with its small-signal equivalent model and neglecting all the

capacitances except for Cgs2, one can show that the input impedance of the CS-CD TAI circuit of Fig. 2.5-a can be approximated as:

1 sCgs2 Zin ≈ + . (2.10) gm2 × (ro1gm1) gm1gm2

Equation (2.10) indicates that the TAI can be modeled by an inductor in series with a resistor. The series resistor represents the loss associated with the TAI circuit. To minimize the losses and achieve a high-Q, it is desired to minimize the value of this series resistance. In other words, it is desired to move the zero of the input impedance transfer

function, i.e. the zero of the numerator of Eq.(2.10) ωz = 1/ro1Cgs2, to lower frequencies. On the other hand, more elaborate analysis reveals that the input impedance

of the TAI circuit has a pole frequency at ωp = gm2/Cgs2, which is responsible for degrading the inductor Q at high frequencies. Hence, it is desired to move the pole to higher frequencies. It is worth mentioning that, adding an extra capacitor CL at the gate of M2 to terminate the gyrator results in the following expression for the input 2.2. TUNABLE INDUCTORS 20

impedance: 1 + s(Cgs2 + CL) ro1 Zin ≈ . (2.11) (gm1 + sCL)(gm2 + sCgs2)

Hence, besides affecting the value of the TAI inductance, the capacitor CL also adds a pole frequency which further limits the operating frequency of the TAI circuit. There- fore, in most high-speed TAIs the load capacitor CL is not used and the circuit relies on the parasitic capacitances of the transistors. By investigating Eq.(2.10) closely, one can show that the series resistance is equal to the resistance looking into the source of M2 divided by the CS stage gain, i.e. gm1ro1. To reduce the series resistance of the TAI, a cascode device can be added to the circuit as shown in Fig. 2.7-a. Adding the cascode device, increases the output impedance of the CS amplifier and consequently increases its gain by a factor of gm3ro3, this decreases the series resistance by approximately the same factor. This technique was proposed in [42], furthermore, the authors of [42] proposed a gain-boosted cascode implementation, which is shown in Fig. 2.7-b. This reduces the series resistance by a factor A×gm3ro3 compared to the circuit of Fig. 2.5-a, where A is the gain of the feedback amplifier. This Q-enhancement technique can be applied to any of the various CS-CD or CG-CS TAI topologies. Another approach that is used to enhance the Q of TAIs is by using cross-coupled differential pairs to generate a negative resistance to cancel the resistive losses. This technique was used in [47] to enhance the Q of a differential CG-CS TAI, and in [43] to enhance the Q of a differential-pair-based TAI. However, this technique is more suited for two port inductors excited by differential signals. Using more elaborate transconductors, such as differential pairs in [43] and [40], to implement the TAIs enhances the inductor characteristics by giving the designer more freedom in shaping its frequency response, namely in the locations of the zeros and poles of the input impedance transfer function. This comes at the expense of power dissipation. Whether a TAI circuit uses a two-transistor topology or a differential-pair-based topology, the inductance is electronically tuned by changing the bias currents of the two transconductors, or it

can also be tuned by changing the value of the load capacitor CL, when one is used to terminate the gyrator. Another Q enhancement technique that has recently been proposed for TAIs involves adding a feedback resistance in the gyrator loop. This was ﬁrst proposed in [41], where 2.2. TUNABLE INDUCTORS 21

Vdd

I1 Vdd

Rf M2

VB M3

I2 Zin

Figure 2.8: Cascoded CS-CD TAI with a feedback resistance Rf .

a differential-pair-based TAI used a tunable MOS-based resistance inserted between the output of the first differential-pair and the input of the second differential pair. However, no analysis was presented that explained the effect of adding the feedback resistance in the gyrator loop. Following that, another TAI circuit employing a feedback resistance within a cascoded CS-CD topology was presented in [39]. This TAI circuit is shown in Fig. 2.8, where the feedback resistance is inserted between the output of the cascoded CS stage and the input of the CD transistor. In [39], the analysis of the cascoded CS-CD TAI circuit with the additional feedback resistance was presented, and experimental results were provided to validate the idea. The same circuit, i.e. the CMOS cascoded CS-CD TAI, was also presented in [25] together with a BiCMOS implementation using a common-emitter, common-collector topology. Both circuits in [25] use the feedback resistance to enhance the Q. However, the analysis presented in [39] and [25] is limited to the specific circuits presented by each paper. Consequently, an intuitive understanding of the effect of adding this feedback resistance is missing. This will be explained later on in chapter 3, as it is one of the contributions of this thesis to generalize this Q-enhancement technique (i.e. adding a feedback resistance to the gyrator-C architecture), and to explain its effect with the aid of very simple and intuitive equations. 2.3. PHASE SHIFTERS 22

TAIs with Tunable Inductance and Quality Factor

Most of the previously published TAI implementations suffer from one major drawback, which is their inability to independently control both the TAI inductance and Q. Tun- ing the inductance without affecting the Q is a key feature to overcome the degradation of the insertion loss and return loss in any TAI-based application, due to the decrease of the TAI’s Q when its inductance is being tuned. Moreover, it is important to have control over the TAI’s Q without affecting its inductance, since this allows controlling the level of the losses in a TAI-based application without significantly affecting the desired response. Very few published TAI circuits have demonstrated independent L and Q tuning capability [25,38,48]. The designs presented in [48] and [38] utilize GaAs MESFETs. The first CMOS TAI with L and Q tuning capability was presented in [25]. The CMOS design in [25] employs a tunable feedback resistance in the gyrator loop. Besides enhancing the Q of the TAI, the additional tunable feedback resistance allows tuning both the L and the Q. Again, the methods used to achieve the independent tuning in [25,38,48] are specific to each individual presented circuit. Hence, a generalized method that can be directly applied to the gyrator-C architecture is missing and would prove to be very useful. This will be discussed in more detail in chapter 3, as it is one of the contributions of this thesis to provide a general method applicable to any gyrator-C TAI to achieve the independent L and Q tuning capability.

2.3 Phase Shifters

Electronically tunable phase shifters are essential building blocks for many RF and microwave applications. In steerable antenna arrays, the direction of the antenna array’s main beam is controlled by the inter-element phase shift. An excellent review for the different classifications of phase shifters can be found in [49] and [24]. This section will very briefly summarize the main types of electronically tunable phase shifters. Electronically tunable phase shifters can be classified into many categories depending on different criteria. For example, phase shifters can be analog in nature or digital, which refers to having a continuous phase tuning range or discrete phase values respectively. At the same time, phase shifters can be classified according to their design into five main categories: 2.3. PHASE SHIFTERS 23

Figure 2.9: A single stage of a switched-line phase shifter.

• Switched-line or switched-network phase shifters • Reﬂection-type phase shifters • Transmission-type or loaded-line phase shifters • Lumped-element L-C phase shifters • PRI/NRI metamaterial phase shifters

2.3.1 Switched-Line Phase Shifters

Switched-line phase shifters rely on using single pole, double throw switches to select between one of two TLs having different lengths as shown in Fig. 2.9. The differential phase shift, i.e. the phase difference between the two paths, is given by:

|∆φ| = β |L1 − L2| , (2.12)

where β is the propagation constant of the two TLs, and L1 and L2 are their lengths. To obtain a large differential phase shift, the difference between the length of the TL should be increased. Also, more than one stage can be cascaded to obtain larger phase shifts. Usually, each stage of a cascaded switched-line phase shifter is designed to achieve binary weighted phases. For example, a 3-bit phase shifter would employ 180o, 90o, and 45o stages, which results in a maximum phase shift of 315o and a minimum phase shift (resolution) of 45o. Hence, the resolution of the discrete phase shifter depends on the number of digital control bits. For an n-bit phase shifter employing 180o, 90o, 45o, etc. stages, the resolution of the phase shifter becomes 360o/2n. The same concept can be used to design a lumped-element phase shifter by switching between different networks, for example, switching between a low-pass network and a high-pass 2.3. PHASE SHIFTERS 24

Input port (1) -90o (2)

o -180 CL Output port 180 o (4) - (3) -90o CL

Figure 2.10: Reﬂection-type phase shifter utilizing a 3dB coupler loaded with varactors.

network [50]. The insertion loss of the switched-line phase shifters becomes an issue as more stages are cascaded to increase its resolution. This is a result of the increasing number of switches that the signal has to propagate through. This problem becomes more obvious for IC implementations, which use transistor-based switches. To overcome the losses of the switches, ampliﬁers can be employed. This, however, makes the phase shifters uni- directional. Furthermore, switched-network phase shifters occupy a large area, since they require at least two networks for each control bit.

2.3.2 Reﬂection-Type Phase Shifters

Reflection-type phase shifters, rely on terminating a 3dB coupler with a reactive load. Either varactors or TAIs can been used to terminate a 3dB coupler, however varactors are more commonly used. Fig. 2.10 shows a simplified diagram of a reflection-type phase shifter terminated with varactors. Assuming that the coupler is ideal, i.e. the coupler has no losses, equally divides the input power from port 1 among ports 2 and 3, and provides -90o and -180o phase shifts at the two ports respectively, one can show that the power reflected back from ports 2 and 3 adds up in-phase at port 4 and out-of- phase at port 1. Furthermore, the phase of the output signal at port 4 is proportional to the phase of the reflection coefficient at ports 2 and 3, Γ, which is given by:

Z − Zo 1 − jωC Zo Γ = L = L , (2.13) ZL + Zo 1 + jωCLZo 2.3. PHASE SHIFTERS 25

S21

S11 CL

Figure 2.11: Single stage of a transmission-type phase shifter.

where ZL is the varactor impedance, CL is its capacitance. Using Eq.(2.13), one can show that the output phase at port 4 can be expressed as:

−1 φ = −2 tan (ωCLZo) . (2.14)

If the varactor capacitance is varied from CLmax to CLmin, the phase tuning range is given by: −1 −1 |∆φ| = 2 tan (ωCLmaxZo) − 2 tan (ωCLminZo) . (2.15)

The return loss, i.e. S11, of reflection-type phase shifters remains very low as long as the two varactors are perfectly matched. Reflection-type phase shifters tend to have a small bandwidth on the order of 15% [49], with the main limiting factor being the bandwidth of the 3dB coupler. Furthermore, reflection-type phase shifters tend to occupy a large area, since their size is mainly governed by the size of the 3dB coupler. Hence, the focus of research into reflection-type phase shifters has been directed towards designing lumped-element couplers to reduce area [51,52].

2.3.3 Transmission-Type Phase Shifters

Transmission-type (or loaded-line) phase shifters are one of the popular methods to implement phase shifters due to their simplicity. A transmission-type phase shifter consists of a TL loaded with a shunt reactive impedance, which in most cases is a varactor. A simpliﬁed diagram of such a phase shifter is shown in Fig. 2.11. One can show that if a TL with a characteristic impedance Zo is loaded with a varactor with a capacitance CL, the return loss and the transmission coeﬃcient, as indicated on 2.3. PHASE SHIFTERS 26

Fig. 2.11, are expressed as:

−jωCLZo S11 = , and (2.16) 2 + jωCLZo

2 S21 = (2.17) 2 + jωCLZo respectively. Hence, the excess phase shift due to loading the TL with the varactor is given by: µ ¶ ωC Z φ = − tan−1 L o . (2.18) 2

If the varactor capacitance is varied from CLmax to CLmin, the phase tuning range is expressed as: µ ¶ µ ¶ ωC Z ωC Z |∆φ| = tan−1 Lmax o − tan−1 Lmin o . (2.19) 2 2

By comparing Eq.(2.19) with Eq.(2.15), one can conclude that for the same capacitance tuning range, transmission-type phase shifters result in a smaller phase tuning range compared to reflection-type phase shifters. However, they do not require a 3dB coupler which makes them more compact. Furthermore, transmission-type phase shifters are more wide-band compared to reflection-type phase shifters. Examining Eq.(2.16) reveals that, unlike reflection-type phase shifters, transmission-

type phase shifters always suﬀer from ﬁnite return losses. In other words, S11 does not

approach zero except for CL = 0, which limits the phase tuning range of such phase shifters. To overcome this, the TL can be loaded with two identical varactors separated by λ/4, where λ is the wavelength of the propagating signal. This causes the reﬂected signals from the two varactors to cancel-out and reduces the return loss of the phase shifter [24].

2.3.4 Lumped-Element L-C Phase Shifters

The ﬁrst three phase shifter topologies presented in this chapter mainly rely on using either TLs or coupled TLs. For IC applications operating in the low GHz frequency range, the length of these TLs becomes excessively long, which makes these techniques unsuitable for such applications. Hence, most IC designs operating in the low GHz fre- 2.3. PHASE SHIFTERS 27

CC L

L C C

(a) (b) C L L

C L L

Figure 2.12: Diﬀerent high-pass and low-pass topologies for constant-impedance second-order L-C phase shifters [53].

quency range use standard lumped-element filters (low-pass, high-pass, etc.) to implement phase shifters. Although R-C filters have been extensively used by IC designers to implement on-chip phase shifters (for example, for the generation of quadrature-phase signals in RF transceivers), R-C filters are not suitable for beam steering applications.

This stems from the fact that they cannot provide matching to a real impedance (Zo). Although matching is usually not an issue for on-chip applications, the focus of this thesis is directed towards phase shifters for beam steering applications, and so matching is one of the main criteria. This leads us to L-C phase shifters, which can provide both the matching as well as the required phase shift. Second-order bi-directional L-C phase shifters can take one of the four implementations shown in Fig. 2.12 [53]. The high-pass T architecture of Fig. 2.12-a and the low-pass Π (Pi) architecture of Fig. 2.12-b use the minimum number of inductors and hence occupy a smaller area. This makes the high-pass T and the low-pass Π architectures more suitable for compact IC implementations.

The phase shift, φHP , of the high-pass Tee phase shifter of Fig. 2.12-a can be ex- 3 pressed as : √ 2 φHP ≈ √ . (2.20) ω LC 2.3. PHASE SHIFTERS 28

Equation (2.20) indicates that the phase can be tuned by changing the capacitance and the inductance, which can be achieved by using varactors and TAIs. Simultaneously

changing the capacitance from Cmax to Cmin and the inductance from Lmax to Lmin results in the following phase tuning range: √ √ 2 2 |∆φHP | = √ − √ . (2.21) ω LminCmin ω LmaxCmax

If the capacitance and inductance tuning ratios are deﬁned as rC = Cmax/Cmin and

rL = Lmax/Lmin, Eq.(2.21) can be re-written as: µ ¶ 1 |∆φHP | = φHPmin 1 − √ . (2.22) rC × rL

Similarly, the phase response of the low-pass phase shifter of Fig. 2.12-b can tuned by changing the capacitance and the inductance. However, since the low-pass Π architecture uses a ﬂoating (or 2-port) inductor, it becomes diﬃcult to replace the inductor with a TAI. For this reason, the phase response of L-C low-pass phase shifters is usually tuned using varactors [54, 55], whereas for high-pass designs, both varactors and TAIs can be employed to extend the tuning range. In spite of this, most high-pass L- C phase shifter designs published in the literature use a single tuning element to tune their phase response; varactors in [56,57], and TAIs in [27]. Although it is evident from Eq.(2.22) that combining the use of varactors and TAIs will extend the phase tuning range, to the author’s knowledge, until now, a phase shifter that combines the use of varactors and TAIs has not been published. A detailed discussion about combining the use of varactors and TAIs is presented later in chapter 4.

L-C phase shifters can also be designed using all-pass networks. For example, Fig. 2.13 shows a second-order all-pass phase shifter, which has a constant resistive

input and output impedance Zo for all frequencies [53]. The transmission-coeﬃcient of

3This phase expression is derived under the assumption that the phase shifter is matched, the detailed derivation of this expression is presented later on in chapter 4. 2.3. PHASE SHIFTERS 29

C1 C1

Figure 2.13: All-pass constant-impedance second-order L-C phase shifter.

the all-pass phase shifter can be expressed as:

2 ωr 2 s − s + ωr Qp S21 = , (2.23) 2 ωr 2 s + s + ωr Qp where ωr and Qp are the frequency and the quality factor of the complex conjugate poles. Using Eq.(2.23), the phase shift can be expressed as: µ ¶ −1 ωωr/Qp φ = −2 tan 2 2 . (2.24) ωr − ω

Equation (2.24) indicates that the phase can be tuned by varying the value of ωr. However, since the values of the circuit components (the capacitors and inductors) are related to the all-pass filter parameters by the following equations: L1 = 2Zo/ωrQp, 2 C1 = Qp/ωrZo, L2 = QpZo/2ωr, and C2 = 2Qp/ωr(Qp−1)Zo, this necessitates changing the values of all the circuit elements. Tuning four different elements simultaneously complicates the tuning process. Furthermore, as discussed in section 2.2.4, the floating inductor is difficult to synthesize using TAIs. However, this approach using all-pass filters results in a relatively flat magnitude response compared to the low- and high-pass approaches. All-pass phase shifters have also been designed using active circuits. For example a recently published design in [58] uses two transistors in feedback, where a series resonator consisting of a fixed inductor and a varactor form the feedback path. The 2.3. PHASE SHIFTERS 30

C TL TL C

d/2 L d/2

Figure 2.14: PRI/NRI metamaterial phase shifter unit-cell.

phase is tuned via a single varactor voltage, and the phase shifter achieves 100o tuning range at 1GHz. Another active phase shifter that was published in [23], combines a gain stage together with two different classes of phase shifters. The design in [23] uses a switched-network phase shifter, but instead of cascading multiple stages to cover the entire phase tuning range, only one stage is used to realize a coarse tuning of 180o, while the rest of the phase tuning range is covered by varactor-tuned L-C low-pass phase shifters. In spite of the numerous advantages offered by amplifier-based active phase shifters, using amplifiers to design all-, low-, or high-pass phase shifters results in uni-directional designs which makes them unsuitable for operating in both the transmit and receive modes when incorporated within the beam steering network of a wireless transceiver.

2.3.5 PRI/NRI Metamaterial Phase Shifters

The recent developments in the ﬁeld of metamaterials have generated strong interest in building phase shifters by cascading NRI metamaterial lines with PRI TLs [5]. Figure 2.14 shows the unit-cell of a TL PRI/NRI phase shifter [5]. It is composed of a regular microstrip line (PRI section) loaded with two series capacitors, C, and a shunt inductor, L (NRI section). Cascading the PRI TL, which has a low-pass response, with the NRI section, which has a high-pass response, compensates the phase shift incurred by the propagating signal. One can show that, the phase shift of the PRI/NRI phase shifter in Fig. 2.14 can be approximated as: √ 2 φ ≈ √ − 2θT L, (2.25) ω LC 2.3. PHASE SHIFTERS 31

where θT L is the phase shift of a single microstrip TL. Equation (2.25) was originally derived in [5]. According to Eq.(2.25), the PRI/NRI phase shifter can be designed to produce a zero-degree phase at the design frequency. This is achieved through the phase compensation process as opposed to accumulating a -360o or a +360o, which would be necessary to achieve the zero-degree phase in a traditional low-pass or high- pass topology respectively. Although, both approaches seem identical in terms of the phase value at the design frequency, the latter approach (using low- or high-pass structures) results in a signiﬁcantly larger group delay and consequently a much smaller bandwidth. Hence, using the PRI/NRI approach allows building compact broadband phase shifters with a linear frequency response, this was demonstrated in [5] and will be also demonstrated in chapter 4 of this thesis. Centering the phase shift at 0o is desirable, for example, for scanning about the broadside direction in series-fed steerable antenna arrays. This will be explained in more detail in section 2.5.1, as well as in chapter 6. It is obvious from the phase expression of Eq.(2.25), that the phase of the PRI/NRI phase shifter can be tuned using the capacitance C and the inductance L. Simultane- ously changing the capacitance from Cmin to rC × Cmin and the inductance from Lmin to rL × Lmin results in the following phase tuning range: √ µ ¶ 2 1 |∆φ| = √ 1 − √ . (2.26) ω LminCmin rLrC

Equation (2.26) reveals that, tuning both the capacitance and inductance results in increasing the phase tuning range compared to only varying the capacitance. A tunable composite PRI/NRI TL phase shifter was presented in [59] using two tunable loading elements: series and shunt ferroelectric varactors. However, this implementation requires high control voltages (15V ). Furthermore, the design in [59] uses a fixed shunt inductor which makes it impossible to achieve a low return loss across the entire phase tuning range. This will be explained in more detail in chapter 4. Also, the ferroelectric varactors result in a modest phase tuning range of 12.5o/unit-stage. The above discussion summarizes the different types of phase shifters and the state- of- the-art in phase shifters’ design. This section also described the recent advances in metamaterial-based phase shifters, and highlighted the main differences and similarities between them and traditional phase shifters. 2.4. DIRECTIONAL COUPLERS 32

Input port Through port (1) (2)

Isolated port S41 S31 Coupled port (4) (3)

Figure 2.15: Block diagram of a 4-port directional coupler.

2.4 Directional Couplers

Since chapter 5 of this thesis describes a novel MMIC directional coupler, it is instructive to present here a brief section describing directional couplers. Directional couplers are one of the most commonly used building blocks in microwave and RF systems. Some applications of directional couplers are: signal monitoring and automatic level control, in-phase/quadrature-phase modulators, signal splitting, combining, and phase shifting. The block diagram of a 4-port directional coupler is shown in Fig. 2.15. The input signal is applied to port 1 and is divided among the through and coupled ports, ports 2 and 3 respectively, according to the value of the coupling coefficient C. A directional coupler is characterized by the coupling coefficient C, and the isolation I, which are defined as: µ ¶ P1 C = 10 log = −20 log |S31|, and (2.27) P3 µ ¶ P1 I = 10 log = −20 log |S41|, (2.28) P4

where P1 is the input power at port 1, and P3 and P4 are the output powers from the coupled and isolated ports respectively. If a directional coupler is designed to achieve equal output powers at the coupled and through ports, P2 = P3 (in other words, a 3dB coupling coeﬃcient), it is usually termed as a hybrid coupler. The isolation of a coupler indicates how well the coupler prevents the input signal from leaking to port 4 (isolated port). Another popular parameter used in the literature to characterize couplers is the directivity D, which is deﬁned as: µ ¶ ¯ ¯ ¯ ¯ P3 ¯S31 ¯ D = 10 log = 20 log ¯ ¯ . (2.29) P4 S41 2.4. DIRECTIONAL COUPLERS 33

Input port Through port (1) (2) /4

Isolated port Coupled port (4) (3)

Figure 2.16: Diagram of a microstrip branch-line directional coupler.

However, the directivity can be inferred from the coupling coeﬃcient and the isolation using the following equation: D = I − C (dB). (2.30)

Using printed microstrip TLs to design directional couplers is one of the most common methods to implement planar couplers suitable for low form factor RF and microwave systems. An instructive review of printed TL directional couplers is available in [24]. Printed TL implementations of directional couplers impose limitations on the area occupied by the couplers especially for systems operating in the low GHz frequency range. This has hindered the integration of couplers into MMICs and has motivated the development of various lumped-element coupler topologies [60]. Directional couplers can be classiﬁed into four main categories according to their structure:

• Branch-line directional couplers • Coupled-line directional couplers • Lumped-element L-C directional couplers • NRI/PRI metamaterial directional couplers

The following sections summarize the main topologies of printed and integrated directional couplers and highlights the recent advances in the design of directional couplers using NRI metamaterials. 2.4. DIRECTIONAL COUPLERS 34

2.4.1 Branch-Line Directional Couplers

A branch-line coupler consists of four λ/4 TLs with a characteristic impedance of √ Z1 = Zo, and Z2 = Zo/ 2 connected as shown in Fig. 2.16, where λ is the wavelength. Following the analysis outlined in [24], one can show that if the coupler is excited

at port 1 while the rest of the ports are terminated with Zo, then the input port is

perfectly matched at the design frequency, i.e. S11(ω = ωo) = 0. Furthermore, the transmission coeﬃcients of the through, coupled, and isolated ports can be expressed as: j S21(ω = ωo) = −√ , (2.31) 2 1 S31(ω = ωo) = −√ , and (2.32) 2

S41(ω = ωo) = 0 (2.33)

respectively. Equation (2.31) and Eq.(2.32) indicate that the input signal power is equally divided among the through and coupled ports. Furthermore, the two signals at the through and coupled ports have a 90o phase difference. On the other hand, Eq.(2.33) indicates that port 4 is completely isolated from the input signal. However, since the operation of the branch-line coupler relies on having λ/4 TLs, its bandwidth is usually limited to about 15% [24]. Branch-line couplers can be designed for different coupling coefficients, by changing the characteristic impedances of the microstrip TLs

Z1 and Z2. In fact, one can show that, in the general case [61], the amplitude of the through and coupled signals can be expressed as:

Z1 S21(ω = ωo) = −j , and (2.34) Zo

Z1 S31(ω = ωo) = − . (2.35) Z2

Hence, the ratio Z1/Z2 can be used to determine the coupling coeﬃcient of a branch-line coupler. However, for a lossless design, power conservation dictates that the following equation should be satisﬁed: µ ¶ µ ¶ Z 2 Z 2 1 + 1 = 1. (2.36) Zo Z2 2.4. DIRECTIONAL COUPLERS 35

Input port Through port (1) (2) /4

Coupled port Isolated port (3) (4)

Figure 2.17: Diagram of a microstrip coupled-line directional coupler.

2 2 This can be obtained from the more intuitive expression |S21| + |S21| = 1, and using

Eq.(2.34) and Eq.(2.35) to substitute for S21 and S31, respectively.

2.4.2 Coupled-Line Directional Couplers

A printed coupled-line coupler consists of two closely spaced microstrip TLs, as shown in Fig. 2.17. The amount of coupling, and hence the coupling coeﬃcient, C, between the two microstrip TLs is a function of their width and spacing, as well as the substrate thickness and dielectric constant [24]. But, the amount of power coupled to port 3, is not only a function of the coupling coeﬃcient, C, but is also a function of the length of the coupler. To maximize the coupled power an electrical length of π/2 is usually picked for the design of coupled-line couplers, which corresponds to a λ/4 length.

Given a speciﬁc coupling coeﬃcient C, and a characteristic impedance Zo, then the required even- and odd-mode characteristic impedances of the coupled TLs should be calculated using the following equations: r r 1 + C 1 − C Z = Z , and Z = Z . (2.37) oE o 1 − C oO o 1 + C

The even- and odd-mode characteristics impedances, ZoE and ZoO, are used to characterize any two coupled TLs when excited by a common-mode and a diﬀerential signal

respectively [24]. Based on the values of ZoE and ZoO, obtained from Eq.(2.37), one can determine the coupled TLs parameters such as their width, separation, and the required substrate height and dielectric constant using standard charts, such as the one found on page 388 of [24]. In practice coupled-line couplers are usually used to achieve small power coupling levels. In contrast, higher power coupling levels close to 3dB 2.4. DIRECTIONAL COUPLERS 36

Figure 2.18: lumped-element L-C low-pass and high-pass Π realizations of a branch-line coupler.

are only achievable using branch-line couplers. However, coupled-line couplers usually have much larger bandwidths compared to branch-line couplers.

2.4.3 Lumped-Element L-C Directional Couplers

Printed branch- and coupled-line couplers occupy a large area, since they rely on λ/4 TLs, which tend to be a few centimeters for applications operating in the low GHz frequency range. This prevents their integration with other RF and digital circuits on the same chip for a fully-integrated system, and has motivated the development of various lumped-element topologies for implementing integrated couplers [60]. Most of the lumped-element realizations of couplers are inspired from the TL branch- line or the TL coupled-line topologies. For example, replacing each λ/4 TL of the branch-line coupler in Fig. 2.16 with a -90o low-pass, Π, L-C phase shifter results in the L-C coupler realization of Fig. 2.18-a. On the other hand, using +90o high-pass, Π, L-C phase shifter results in the L-C coupler realization of Fig. 2.18-b. In both designs of Fig. 2.18, the values of the inductors and capacitors are chosen to achieve the desired ±90o phase shift, and, at the same time, set the required line impedances. Both the L-C couplers of Fig. 2.18 use four inductors, and four capacitors. It is interesting to note that the high-pass, Π, L-C coupler topology of Fig. 2.18-b constitutes the core of a 2-D unit-cell of a NRI metamaterial medium. This points out the strong relation between the ﬁeld of NRI metamaterials and directional couplers. In fact, couplers have 2.4. DIRECTIONAL COUPLERS 37

L C1 C1 (1) (2)

C2 C2 L L

C2 C2

(4) (3)

C1 C1 L

Figure 2.19: L-C lumped-element high-pass Tee realization of a branch-line coupler.

C1 C1 L1 (1) (2)

C2 C2

(4) (3) L1 C1 C1

Figure 2.20: L-C lumped-element realization of a coupled-line coupler.

beneﬁted from the recent developments in the ﬁeld of metamaterials [4,17,62–65], and this point will be discussed in more detail in section 2.4.4. Other L-C coupler realizations can be obtained by using -90o low-pass, Tee, L-C phase shifters or by using +90o high-pass, Tee, L-C phase shifters. The former requires the use of eight inductors, which makes the size of the coupler excessively large compared to the architectures of Fig. 2.18. On the other hand, using +90o high-pass Tee L-C phase shifters, as shown in Fig. 2.19, results in the same number of inductors, however it requires eight capacitors. IC capacitors usually occupy a much smaller area compared to IC inductors, so this does not result in a larger area. However, having two capacitors in the signal path of each phase shifter will result in more losses especially for a tunable coupler design where these capacitors are to be replaced with on-chip varactors. 2.4. DIRECTIONAL COUPLERS 38

Lumped-element L-C couplers can also be designed based on TL coupled-line couplers o by replacing the two λ/4 TLs with two -90 , Π, L-C sections (L1 and C1), as shown in Fig. 2.20, and adding two coupling capacitors, C2, to model the coupling occurring between the two TLs. This implementation requires only two spiral inductors, which makes it very attractive for designing compact on-chip couplers. Furthermore, for IC implementations the two inductors can be replaced with two coupled spiral inductors. This further reduces the area occupied by the L-C coupler [66]. Although lumped- element couplers, in general, oﬀer numerous advantages over their printed counterparts, such as small area and ease of integration with RF and digital circuits, lumped-element couplers have smaller bandwidths compared to printed couplers. One technique that is used to extend the bandwidth of L-C couplers is to use a cascade of multiple L-C sections [67].

2.4.4 PRI/NRI Metamaterial Directional Couplers

PRI/NRI metamaterial coupler designs [4, 17, 62–65] are relatively new and have all emerged following the planar L-C realization of metamaterials. The interesting properties of NRI metamaterial lines have motivated designers to investigate the beneﬁts of using NRI lines to build branch-line and coupled-line couplers. In [17], it was shown that combining the use of PRI and NRI lines to design printed branch-line couplers results in a much more compact size without any bandwidth degradation. Two branch- line couplers designs were presented in [17]. In the ﬁrst design, the low impedance √ lines (50/ 2Ω) were implemented using regular PRI microstrip TLs, whereas the high impedance lines (50Ω) were implemented using NRI lines. This resulted in an area of λ/4 × λ/12 (i.e. length by width) for the coupler, which corresponds to an area savings of 66% compared to a traditional branch-line coupler. The second design presented √ in [17] uses NRI lines to implement the low impedance lines (50/ 2Ω), and regular PRI microstrip TLs to implement the high impedance lines (50Ω). In this case, the area of the coupler is λ/4 × λ/14, which corresponds to an area savings of 77% compared to a traditional branch-line coupler. Furthermore, NRI metamaterial lines have been used to design dual-band branch- line couplers [4]. Dual-band operation is enabled by replacing the PRI microstrip TLs of a branch-line coupler with NRI metamaterial TLs. As demonstrated in [4], NRI lines 2.5. PHASED ANTENNA ARRAYS 39

Table 2.1: Comparison Between Diﬀerent Directional Coupler Topologies. Parameter Branch-line Coupled-line Lumped-element Printed PRI/NRI √ Integration X X X Coupling coeﬀ. >3dB <3dB Arbitrary Arbitrary Bandwidth Average Large Small Average Size Large Medium Very small Medium

allow full control over the values of the two frequencies f1 and f2 at which the NRI lines achieve a +90o and a +270o (which is equivalent to -90o) phase shift respectively. This guarantees identical operation of the branch-line coupler at the two frequencies f1 and f2, allowing for dual-band operation. On the other hand, in a traditional branch-line coupler using only PRI TLs, the PRI TLs would achieve the -90o and a -270o (which is o equivalent to -90 ) phase shifts only at fo and 3×fo respectively, where fo is the design frequency. Hence, using traditional PRI TLs does not give control over the choice of the two frequencies, since f2 has to be three times f1, which is usually not suitable for most dual-band applications. Coupled-line couplers have also beneﬁted from the advances in metamaterials. NRI /PRI metamaterial couplers have been designed by coupling a PRI TL with a NRI metamaterial line in [4,62,64,65] and by coupling two NRI metamaterial lines together in [63,65]. The main beneﬁt from using NRI lines to design such couplers is the ability to achieve high power coupling levels, as opposed to traditional coupled-line designs, using only PRI TLs, which limit the coupling level to small values. By using NRI metamaterial lines, coupling levels of -3dB were demonstrated in [62,63], and near 0dB coupling levels were demonstrated in [4,63]. Table 2.1 qualitatively compares between the achievable performance from the different directional coupler topologies presented in this section.

2.5 Phased Antenna Arrays

2.5.1 Antenna Arrays Basics

A phased antenna array, as deﬁned by the glossary of telecommunication terms [68], is a group of antennas in which the relative phases of the signals feeding the antennas are set in such a way that the eﬀective radiation pattern of the array is reinforced in 2.5. PHASED ANTENNA ARRAYS 40

A Ae+j Ae+j2 Ae+j(N-1)

dE dE

Figure 2.21: N-element uniform linear antenna array with equal amplitude excitation and a progressive phase constant φ.

a desired direction and suppressed in undesired directions. Generally, phased arrays are either planar (2-D) or linear (1-D). This thesis focuses on linear arrays, as they are considered the basic building block for planar arrays. In general, the radiation pattern of an antenna array can be decomposed into the product of two terms: an array factor AF (θ), which depends on the geometry of the array, the number of elements, and the relative amplitudes and phases of the signals fed to each antenna, and an element factor EF (θ), which represents the radiation pattern of a single antenna [69]. Fig. 2.21 shows a uniform, linear antenna array, i.e. the array has equally spaced elements which are excited with equal amplitudes A and a progressive phase shift φ. The array factor of this array can be expressed as: µ ¶ N sin (kd sin θ + φ) 1 2 E AF (θ) = µ ¶ , (2.38) N 1 sin (kd sin θ + φ) 2 E

In Eq.(2.38), dE is the inter-element spacing, θ is the angle measured from the normal to the array axis, and k is the wave-number, which is related to the operating frequency by k = ω/c, where c is the speed of light. The zeros of the array factor will result in nulls in the antenna array’s radiation pattern. Also, if the individual antenna elements are omni-directional, then the locations of the maxima in the array’s radiation pattern are mainly determined by the maxima of the array factor. Using Eq.(2.38), one can 2.5. PHASED ANTENNA ARRAYS 41

Major lobe 0° −30° 30° HPBW Side lobes

−60° 60°

0 −10 −20 −90° −30 90°

Figure 2.22: Array factor of a 4-element antenna array fed in-phase and with dE = λ/2.

show that the maxima of the array factor occur at: µ ¶ −1 λo θm = sin (−φ ± 2mπ) , m = 0, 1, 2,..., (2.39) 2πdE where λo is the free-space wavelength, given by λo = c/f. In many applications, it is desired to center the main beam of the array about the broadside direction, i.e. at θ = 0o. The necessary condition for broadside radiation o can be obtained from Eq.(2.39) by setting θ0 = 0 to obtain the ﬁrst maximum of the radiation pattern at broadside. This results in the following condition for broadside radiation: φ = 0 (2.40) indicating that a uniform array should be fed in-phase in order to center its main beam at broadside. This is demonstrated in Fig. 2.22, which plots the theoretical expression of the array factor, Eq.(2.38), of a 4-element array when the elements are fed in-phase and the inter-element spacing, dE, is set to λo/2. The array factor plot of Fig. 2.22 shows one major lobe and two side lobes. Side lobes represent radiation in undesired directions, which should be minimized. According to Fig. 2.22, a 4-element array with omni-directional antenna elements would achieve a side lobe level of -11dB. Furthermore, its half-power beamwidth (HPBW) would be 26o as shown by Fig. 2.22. 2.5. PHASED ANTENNA ARRAYS 42

φ=+90o o 0° φ=−90 −30° 30°

−60° 60°

0 −10 −20 −90° −30 90°

Figure 2.23: Array factor of a λo/2 4-element antenna array fed with a progressive phase shift of ±90o.

In general, when the antenna elements are fed with a progressive phase shift of φ, the direction of the main beam (i.e. the scan angle) can be written as: µ ¶ −1 λo θ0 = − sin φ . (2.41) 2πdE

Equation (2.41) indicates that, using phase shifters capable of generating negative progressive phase shifts results in positive scan angles θ0, and vice versa. Hence, to scan the main beam about the broadside direction, the progressive inter-element phase shift should acquire both positive and negative values. This conclusion plays an important role in the selection of the topology of the inter-element phase shifters, especially in series-fed arrays as will be described later. For a progressive inter-element phase shift of ±90o the main beam of the array factor can be scanned all the way from −30o to +30o about the broadside direction as illustrated in Fig. 2.23. Also, as the main beam is scanned oﬀ the broadside direction another minor lobe appears in the radiation pattern. However, its level remains below -11dB.

In most applications, it is also important to avoid the creation of grating lobes in the radiation pattern (i.e. other global maxima for the array factor). Using Eq.(2.39), it can be shown that, to avoid creating grating lobes in the radiation pattern while 2.5. PHASED ANTENNA ARRAYS 43

Z W

r h X

Figure 2.24: Rectangular microstrip patch antenna fed with a microstrip TL .

operating the array at broadside, the following condition should be satisﬁed:

λ d ≤ o . (2.42) E 2

Equation (2.42) is a fundamental equation, since it sets the maximum separation distance between two consecutive antenna elements. Hence, tight limitations are set on the phase shifter dimensions to ﬁt in-between the antenna elements of a series-fed design, if it is desired to integrate the phase shifters with the antennas on a single PCB. However, if the array uses a parallel feed network, such tight constraints are not imposed on the phase shifter dimensions.

2.5.2 Microstrip Patch Antenna

Phased antenna arrays can use a variety of antenna elements. However, for wireless consumer applications where size, weight, form factor, and cost are constrained, microstrip patch antennas become a popular choice. A patch antenna consists of either a rectangular or circular shaped conductor on top of a ground plane. Figure (2.24) shows a rectangular patch antenna fed with a microstrip TL. The geometry of a patch antenna is a function of the desired resonance frequency, i.e. the frequency of opera-

tion, and the substrate properties [69]. Given the desired resonance frequency fr of a

rectangular patch and the substrate dielectric constant ²r and height h, its width can 2.5. PHASED ANTENNA ARRAYS 44

Figure 2.25: Inset-fed rectangular microstrip patch antenna.

be calculated using: r 1 2 W = √ . (2.43) 2fr µo²o 1 + ²r To a ﬁrst order of approximation, the length of the patch is equal to the resonance √ length, L ≈ λo/2 ²r, where λo is the free space wavelength. However, due to the existence of fringing ﬁelds the patch antenna seems electrically longer than its physical length. Hence, a more accurate estimate of the patch length can be obtained using the following expression [69]: λo L = √ − 2∆L, (2.44) 2 ²eff where ²r + 1 ²r − 1 ²eff = + p , and (2.45) 2 2 1 + 12h/W (² + 0.3)(W/h + 0.27) ∆L = 0.4h eff . (2.46) (²eff − 0.26)(W/h + 0.8)

At resonance, the input impedance of a patch antenna is real and usually takes very large values. For example, the patch resistance can take values close to 300Ω. This, however, depends on the patch and substrate properties. To bring the patch resistance down to reasonably low values (i.e. to values close to the characteristic impedance of the microstrip feed line), the microstrip TL feeding the patch is recessed inwards as shown in Fig. 2.25 [69]. The value of the inset feed point yo determines the value of 2.5. PHASED ANTENNA ARRAYS 45

0° 0° −30° 30° −30° 30°

−60° 60° −60° 60°

10 10 0 0 −10 −10 −20 −20 −90° −30 90° −90° −30 90° (a) (b)

Figure 2.26: Elevation plane gain plot for a 2.4GHz rectangular microstrip patch antenna: (a) in the y-z plane, (b) in the x-z plane. the patch resistance at resonance. Figure 2.26-a and Fig. 2.26-b show the gain of a microstrip patch antenna in the x-y plane (as shown in Fig. 2.24). The patch is designed to operate at 2.4GHz with a dielectric constant, ²r, of 4.5 and a substrate thickness h of 3.175mm (125mil). The gain plot of Fig. 2.26-a is for the y-z plane, whereas that of Fig. 2.26-b is for the x- z plane. Both plots show that the patch antenna has a large HPBW. Hence, when patches are used it is necessary to employ arrays to produce more directive, high-gain beams.

2.5.3 Phased Array Feed Network Topologies

The popular approach to building a phased array transceiver for low GHz applications is by using a single transceiver combined with a beam steering network to feed the different antennas with the appropriate signal amplitudes and phases. As will be described in this section, the beam steering network of this type of phased arrays can either take a parallel or a series configuration. Aside from utilizing electronically tunable phase shifters, in the RF domain, to generate the appropriate signal phases, the beam steering network has to take care of the power splitting and combining. The reason for the popularity of this approach for low GHz applications, is the large size of the antennas and the large distance between them, which scale with the wavelength. Consequently, the transmission-lines (TLs) connecting the printed antennas to 2.5. PHASED ANTENNA ARRAYS 46 the transceiver can readily be used for power splitting, combining, and phase shifting, without significantly increasing the area occupied by the phased array. Furthermore, the TLs provide an adequate means for designing low-loss power splitters and combin- ers, which are very challenging to design and integrate on-chip at these frequencies. It is also worth mentioning that, this type of phased array transceivers require only one low-noise amplifier, mixer, and power amplifier. On the other hand, for millimeter-wave applications, performing the phase shifting in the RF domain becomes a challenge. This necessitates performing the phase shifting at lower frequencies, which requires each antenna in the phased array to have a separate transceiver. Consequently, the majority of millimeter-wave phased array transceivers utilize a parallel architecture, which requires a separate transmit/receive path for each antenna in the array [70, 71]. An N-element phased array transceiver of this type would require roughly N times the area and the power consumption of a single transceiver, which is why this approach is not attractive at the low GHz frequency range. This approach has been used in many recent publications to design millimeter- wave phased array transceivers, as it conveniently allows integrating the entire phased array transceiver onto a single chip. Furthermore, at these high frequencies the antenna dimensions shrink, allowing their integration with the transceivers on a single chip. This, however, is still being investigated, as there are many challenges facing the design of efficient on-chip antennas in silicon [72–74]. The objective of this thesis is to demonstrate beam steering for 2.4GHz ISM band applications. Consequently, the first approach, is adopted to design the steerable phased array. Feed networks for microstrip patch arrays can take a series or a parallel configuration. A good review of the different feeding configuration of patch arrays can be found in [75].

Parallel-Fed Arrays

In parallel-fed arrays, the individual antennas are fed in parallel using a TL power division network as illustrated in Fig. 2.27. Parallel-fed arrays are the popular choice for electronic beam steering, since they easily allow inserting phase shifters to control the phase excitation of each patch. However, the simpliﬁed parallel architecture of Fig. 2.27 uses unequal TLs to feed the individual patches, which results in unequal 2.5. PHASED ANTENNA ARRAYS 47

dE<

Figure 2.27: A 4-element parallel-fed antenna array.

dE<

Figure 2.28: A 4-element corporate-fed antenna array. 2.5. PHASED ANTENNA ARRAYS 48

dE<

Figure 2.29: A basic 4-element series-fed antenna array.

phase variations across the signal bandwidth. Figure 2.28 shows another version of the parallel-fed architecture, which uses equal length TLs to feed the patches, termed the corporate-fed architecture. Using equal length TLs makes the phase excitations, and hence the radiation pattern of the array, less sensitive to frequency variations, i.e. results in less beam squinting. This makes corporate-fed arrays relatively wide- band, making them a popular choice for beam steering in high data-rate applications. This, however, comes at the expense of the large area occupied by the feed network. Occupying a large area also increases the insertion losses associated with the feed network lowering the array’s eﬃciency. Furthermore, another disadvantage of parallel- and corporate-fed architectures is that they require phase shifters having a very wide tuning range; an N-element parallel- or corporate-fed array requires a maximum phase shift of (N − 1)φ to produce a progressive phase shift of φ.

Series-Fed Arrays

In a series-fed array, the individual patch antennas are excited in series as illustrated in Fig. 2.29. Here, the power is delivered to the patch antennas one after the other. The feed network of this type has the advantage of being less complex, and much more compact in terms of area compared to the parallel or corporate types. Its compact size also minimizes the insertion losses, and the undesired radiation caused by the feed network. This makes series-feed arrays more eﬃcient than their parallel- or corporate- fed counterparts. Furthermore, an N-element series-fed array requires a maximum phase shift of only φ to produce a progressive phase shift of φ, since in the series conﬁguration each phase shifter is reused by more than one patch. 2.5. PHASED ANTENNA ARRAYS 49

d < E LPS

Figure 2.30: A 4-element series-fed traveling wave in-line antenna array using a termination load.

dE<

LPS

Figure 2.31: A 4-element series-fed traveling wave out-of-line antenna array without a termination load. 2.5. PHASED ANTENNA ARRAYS 50

Series-fed arrays can use in-line feeding or out-of-line feeding. In-line fed arrays utilizes a single TL which directly feeds all the patch antennas as shown in Fig. 2.30. On the other hand, out-of-line fed arrays utilize short TLs to connect the patches to the main feed line as shown in Fig. 2.31. Series-fed arrays using the in-line feeding technique occupy a very small area [76,77], and hence have the smallest insertion losses associated with the feed network. However, the in-line feeding technique makes the series-fed array very narrow band as it makes the inter-element phase shift a function of the patch’s narrow-band impedance and the interconnecting TLs. On the other hand, the out-of-line feeding technique alleviates the dependence of the inter-element phase shift in series-fed arrays on the patch characteristics [78]. Furthermore, as illustrated in Fig. 2.31, moving the patches off the centerline of the array gives more room for the inclusion of the inter-element phase shifters required for beam steering. Series-fed antenna arrays can also be classified into resonant [76–78] or traveling wave arrays [77]. Resonant series-fed arrays can be designed using the in-line or the out-of-line architectures. In either case, the array is terminated with either a short circuit or an open circuit. Hence, the reflected wave creates a standing wave. Placing the microstrip patches m × λ apart, where m could take any integer value, excites all the patches with the same amplitude and with the same phase, i.e. φ = 0o. This makes resonant series-fed arrays a very popular technique to build broadside arrays. However, resonant arrays are not usually used for electronic beam steering. Furthermore, they are very narrow-band, as any frequency variation changes the way the incident and reflected waves add up at the patches, resulting in mismatches at the array input. On the other hand, the feed-line of a traveling wave array is designed to be well matched, and ideally free of any reflections. Similar to series-fed resonant arrays, traveling wave arrays can be designed using the in-line or the out-of-line architectures. However, the spacing between the elements does not have to be multiple integers of the λ, which allows series-fed traveling wave arrays to produce off-broadside beams, as well as broadside beams, if their spacing is a multiple of λ. For electronic beam steering, this is achieved using electronically tunable inter-element phase shifters. The signal amplitude on the main feed-line of a traveling wave array tapers due to the power radiated by the patches and due to the insertion loss of the phase shifters. This results in an imbalance in the signal power feeding each patch antenna. However, by using proper design techniques, this amplitude imbalance can be eliminated. This will 2.5. PHASED ANTENNA ARRAYS 51

Table 2.2: Comparison Between Different Antenna Array Feed Network Topologies And The Requirements On The Interstage Phase Shifters. Parameter Parallel-Fed Series-Fed Corporate In-line Out-of-line Feed network size Large Very small Small Scan angle rangea Small Large Large Bandwidth Large Small Small Beam Squinting Low High High Req. phase tuning range (N-1)φ φ φ Req. phase shifter losses Relaxed Small Small Req. phase shifter size Relaxed Very small Small aScan angle range is estimated for the same phase tuning range. be described later on in chapter 6. At the end of a series-fed traveling wave array, the remaining power is usually absorbed by a termination impedance, usually a 50Ω load, as illustrated in Fig. 2.30 for an in-line architecture. This implies that a small percentage of the input power in the TX mode (or the received power in the RX mode) is dissipated in the termination, which reduces the overall efficiency of the array. To increase the efficiency of a traveling wave series-fed array, the conductance of the individual antennas can be increased to couple into them more power from the main feed-line. However, this loads the main feed-line resulting in higher mismatches. Alternatively, higher array efficiencies are achieved by increasing the number of elements [79]. Another approach used is to design the array in such a way that the last patch absorbs this remaining power, as illustrated in Fig. 2.31 for the out-of-line architecture. Table 2.2 qualitatively compares the achievable performance from the different feed network topologies presented in this section as well as the requirements set on the interstage phase shifters.

2.5.4 Metamaterial Phased Antenna Arrays

With the recent advances in metamaterial phase shifters, it is natural that antenna arrays would also beneﬁt from these advances. As described in section 2.3.5, metamaterial phase shifters are capable of achieving zero-degree phase shifts using the concept of phase compensation, and it was demonstrated in [5] that these metamaterial-based phase shifters achieve much lower group delays as opposed to a traditional -360o TL 2.5. PHASED ANTENNA ARRAYS 52

segment. A low group delay is necessary to minimize the beam squinting with frequency variations in series-fed antenna arrays. In order to demonstrate this, one can

obtain the derivative of the main beam angle θo using Eq.(2.41). This results in the following expression: µ ¶ dθo λo φ ≈ + Tgd , (2.47) dω 2πdE ω where Tgd = −dφ/dω is the group delay of the inter-element phase shifters. Equation (2.47) clearly indicates that a low group delay would result in less beam squinting with frequency variations. This was veriﬁed experimentally in [6] where a series-fed dipole array using PRI/NRI metamaterial phase shifters was presented. In [6], the performance of a zero-degree metamaterial-based dipole array was compared to two of the traditional approaches which achieve a -360o phase at the design frequency; the ﬁrst uses long meandered TLs, and the second uses a capacitively loaded TL. It was demonstrated that the metamaterial-based dipole array results in less beam squinting and occupies a more compact area compared to the traditional designs. It is the aim of chapter 6 of this thesis to demonstrate the use of the electronically tunable PRI/NRI metamaterial phase shifters, presented in chapter 4, towards the design of series-fed antenna arrays in order to achieve electronic beam steering as well as low beam squinting. CHAPTER 3

CMOS Tunable Active Inductors

3.1 Introduction T he most popular technique used to build tunable active inductors (TAIs) is by using gyrators. This technique has greatly benefited from the advances in modern CMOS technologies, which are now capable of providing transistors with very high unity-gain frequencies (fts), thereby allowing the design of RF TAIs. However, most of the published TAI designs suffer from one major drawback, which is their inability to independently control both the TAI inductance and quality factor. Moreover, the few published TAI designs which demonstrated the independent L and Q tuning capability [25,38,48] use techniques which are specific to each individual circuit implementation. Hence, a generalized technique that can be directly applied to the gyrator-C architecture is missing and would prove to be very useful. In this chapter, the addition of a feedback element to enhance the Q of TAIs is generalized to the block diagram level of the gyrator-C architecture, thus making this Q-enhancement technique applicable to any TAI based on the gyrator-C architecture as opposed to previously published work [25, 38, 48], which do not provide this general framework. The effect of adding the feedback resistance is analyzed and design

53 3.2. TRADITIONAL GYRATOR-C ARCHITECTURE 54

gm1

Z Co1 ro1 in L

r C +C R Zin o2 in1 o2 s -gm2 C +C in1 o2 ro2 Cin2

Figure 3.1: Gyrator-C architecture and its equivalent circuit.

equations are presented. It will be shown that the modiﬁed gyrator-C architecture allows independent control over L and Q. The proposed architecture is used to design a 0.13µm CMOS grounded TAI operating from a 1.5V supply. Experimental results from a test chip are used to verify some of the design equations, and to demonstrate that the L and Q can be independently tuned. The principles of enhancing the Q of the traditional gyrator-C architecture are described in section 3.2. Following that, the modiﬁed gyrator-C architecture is presented in section 3.3. Finally, the design of the grounded TAI is presented in section 3.4.

3.2 Traditional Gyrator-C Architecture

The gyrator-C architecture consists of two transconductors (gm1 and gm2) connected back-to-back, as shown in Fig. 3.1. If the output resistance and capacitance of the

transconductor gmi (where i = 1, 2) are modeled by roi and Coi, respectively, and its

input capacitance is modeled by Cini, then the input impedance, Zin, of the gyrator-C circuit is expressed as:

1 + s(Co1 + Cin2) ro1 Zin = µ ¶ . 2 Co1 + Cin2 Cin1 + Co2 1 s (Co1 + Cin2) (Cin1 + Co2) + s + + + gm1gm2 ro2 ro1 ro1ro2 (3.1) This can be represented by the equivalent circuit shown in Fig. 3.1, where the series

and parallel resistors (RS and ro2) model the losses, and the capacitor is incorporated 3.2. TRADITIONAL GYRATOR-C ARCHITECTURE 55

to model the self-resonance of the TAI circuit. Furthermore, the inductance, L, and

the series resistance, RS, of the equivalent circuit are given by:

C + C L = o1 in2 , and (3.2) gm1gm2

1 RS = . (3.3) gm1gm2ro1 According to Eq.(3.2), the inductance of the TAI circuit can simply be tuned by varying

the transconductances gm1 and gm2. This is usually done by varying the bias currents of the two transconductors. However, this will also aﬀect the value of the series resistance

RS.

3.2.1 Quality Factor Analysis

To understand the eﬀect of tuning the inductance, L, on the TAI’s Q, one has to derive

the expression for Q using its basic deﬁnition Q = Im(Zin)/Re(Zin), which results in the following expression:

2 2 Lro2 (1 − ω (Cin1 + Co2) L) − ro2(Cin1 + Co2)RS Q = ω × 2 2 2 . (3.4) RS + ro2RS + ω L

It is instructive to obtain the expression of the circuit’s self-resonance frequency, ωr, since it helps in pointing out the dominant terms in Eq.(3.4). The self-resonance frequency is deﬁned as the frequency at which the imaginary part of the input impedance becomes zero, which for a gyrator-C TAI is expressed as: s 2 L − (Cin1 + Co2)RS ωr = 2 . (3.5) (Cin1 + Co2)L

Equation (3.5) indicates that for a high-Q TAI to have a high self-resonance frequency,

which is necessary for high-speed operation, L should be much greater than (Cin1 + 2 Co2)RS, resulting in the following simpliﬁcation for the self-resonance frequency: s 1 ωr ≈ . (3.6) (Cin1 + Co2)L 3.2. TRADITIONAL GYRATOR-C ARCHITECTURE 56

Furthermore, the quality factor expression of Eq.(3.4) can be simpliﬁed to:

Lr (1 − ω2(C + C )L) Q ≈ ω × o2 in1 o2 , (3.7) f(RS) where the function 2 2 2 f(RS) = RS + ro2RS + ω L . (3.8) As Eq.(3.7) indicates, Q is a function of frequency, starting at a low value and increases with frequency until it peaks, then it starts to drop again due to the resonance with

the parasitic capacitance. The frequency at which Q reaches its peak value, ωp, can be found by diﬀerentiating Eq.(3.7) and equating the derivative to zero. This results in

the following expression for ωp: Ã s ! 2 2 2 2 2RS + ωr L 8RSωr L (ro2 + RS) ωp = 2 × 1 + 1 − 2 2 2 , (3.9) 4L (2RS + ωr L ) which can be approximated as: s 1 R r ω S o2 √r ωp ≈ ωr × − 2 2 ≈ . (3.10) 2 ωr L 2

It is interesting to note that, the ratio between peak-Q frequency, ω , of a gyrator-C p √ TAI and its self-resonance frequency, ωr, is approximately ﬁxed and equal to 1/ 2. To arrive at the result of Eq.(3.10), the frequency dependence of the equivalent series

resistance RS was neglected. This simpliﬁcation results in a very small error between

the values of ωp predicted by Eq.(3.10) and the values obtained from the experiential characterization of a gyrator-C based TAI, which will be demonstrated later in section

3.4.4. Substituting with ωp in Eq.(3.7) results in a peak-Q, Qp, of: s ro2 L Qp ≈ × . (3.11) 2f(RS) 2(Cin1 + Co2)

In order for the gyrator-C TAI to have a high peak-Q, the value of the function f(RS)

should be minimized. According to Eq.(3.3), which only allows positive values for RS,

this implies that RS should be very small in order to minimize f(RS). Consequently, 3.2. TRADITIONAL GYRATOR-C ARCHITECTURE 57

Negative RS

Figure 3.2: Function f(RS) versus the negative series resistance RS. one can neglect the ﬁrst two terms of Eq.(3.8). Combining this with Eq.(3.10) and Eq.(3.6), one can simplify Eq.(3.11) to: r (C + C ) Q ≈ r × in1 o2 . (3.12) p o2 2L

Equation (3.12) shows the direct relationship between the inductance and the peak-Q

for a gyrator-C TAI, indicating that as L is tuned, via gm1 and gm2, the peak-Q also changes, which is not desirable in most applications. Instead, having independent control over L and Q is necessary to provide the capability of optimizing the performance.

3.2.2 Q-Enhancement Technique For Gyrator-C TAIs

To overcome this interdependence between the L and Q of a gyrator-C TAI, we further

exploit the dependence of the peak-Q on f(RS), and hence RS. Figure 3.2 shows a

sketch for the quadratic function f(RS) versus RS, the function f(RS) has two negative real roots given by: r 1q R = − o2 ± r2 − 4ω2L2. (3.13) S1,2 2 2 o2 p

Values of RS between the two roots (RS1 and RS2) will produce a negative Q possibly resulting in an unstable TAI, therefore this region is avoided in general. Otherwise, if 3.3. THE MODIFIED GYRATOR-C ARCHITECTURE 58

gm1

Co1 ro1 Zin L Rf

ro2 Cin1+Co2 Rs Zin Z -gm2 C +C in1 o2 ro2 Cin2

Figure 3.3: Modiﬁed gyrator-C loop and its equivalent circuit.

RS < RS2 or RS > RS1, the Q is positive and the circuit is stable. To obtain a high

value for the peak-Q, RS should be picked close to either of the two roots but outside the unstable region. Consequently, the TAI circuit has two possible operating points

on Fig. 3.2; P1 and P2 in regions 1 and 2 respectively. From Eq.(3.5), operating at P1 with a smaller |RS|, will result in a higher self-resonance frequency than operating at

P2, but will make the Q more sensitive to any parasitic resistance that might add to

RS. Also, the effect of RS on the Q differs according to the operating point chosen; increasing RS while operating at P1 lowers the Q. On the other hand, increasing RS while operating at P2 increases the Q. In the next section, a modified structure for the gyrator-C architecture, which uses an additional feedback resistance, is proposed.

Adding a feedback resistance allows the series resistance RS to achieve negative values.

Furthermore, it allows RS to be tuned without aﬀecting the inductance. Consequently, this modiﬁed gyrator-C architecture will achieve independent L and Q tuning.

3.3 The Modiﬁed Gyrator-C Architecture

This section analyzes the eﬀect of adding a feedback resistance to the traditional gyrator-C architecture. It will be shown that adding a feedback resistance to the gyrator-C architecture generates the negative resistance RS necessary to enhance the TAI’s Q. The modiﬁed gyrator-C block diagram and its equivalent circuit are shown in

Fig. 3.3, where the resistance Rf is the additional feedback resistance. One can show 3.3. THE MODIFIED GYRATOR-C ARCHITECTURE 59

that the expression for the input impedance of the modiﬁed gyrator-C architecture is: µ µ ¶¶ 1 R + s C + C 1 + f + s2C C R r o1 in2 r o1 in2 f Z = o1 o1 , (3.14) in D(s) where

D(s) = s3R C C (C + C ) µf in2 o1 o2 in1 µ ¶ ¶ R R + s2 C C f + (C C + C C ) 1 + f + C C + C C o1 in2 r in1 in2 o1 o2 r in1 o1 o2 o1 µ o2 µ ¶¶ o1 C + C C C R + s in1 o2 + o1 + in2 1 + f ro1 ro2 ro2 ro1 1 1 + + . (3.15) ro1ro2 gm1gm2

Although Eq.(3.14) appears to be very cumbersome, comparing it to Eq.(3.1) shows

that adding the feedback resistance Rf to the gyrator-C loop adds a zero and a pole to the input impedance transfer function, which allows more control over the frequency response of the TAI. To be speciﬁc, the additional zero in the input impedance transfer function generates a negative, frequency dependent term that can be used to enhance the TAI Q. To understand more how the Q-enhancement takes place, the same approach of section 3.2 is followed here and the circuit is modeled by the L-C circuit shown in Fig. 3.3. It can be shown that the impedance of the inductive branch (Z), given by the series combination of the equivalent inductance L and equivalent series resistance

RS, is expressed as: µ µ µ ¶ ¶ ¶ 1 2 Rf 1 Z = × s Rf Co1Cin2 + s Cin2 1 + + Co1 + . (3.16) gm1gm2 ro1 ro1

Hence, the equivalent inductance L and the equivalent series resistance are expressed as: µ µ ¶ ¶ 1 Rf L = × Cin2 1 + + Co1 , and (3.17) gm1gm2 ro1 µ ¶ 1 1 2 RS = × − ω Cin2Co1Rf . (3.18) gm1gm2 ro1 3.3. THE MODIFIED GYRATOR-C ARCHITECTURE 60

Equation (3.17) indicates that the inductance is independent of the feedback resistance

Rf as long as the feedback resistance is much smaller than the output resistance ro1

of the ﬁrst transconductor. On the other hand, Eq.(3.18) indicates that, RS can take

negative values, and its value can be controlled via the feedback resistance Rf . By comparing the L-C models of Fig. 3.1 and Fig. 3.3, one can conclude that the addition of the feedback resistance to the gyrator-C loop generates the negative tunable resis-

tance RS necessary for the Q-enhancement technique described in section 3.2. Thus, a variable feedback resistance will allow us to control the TAI operating point on Fig. 3.2, which will guarantee stable operation with a tunable high-Q. Furthermore, controlling

RS via Rf does not aﬀect L (assuming ro1 >> Rf ), which consequently allows us to

independently tune L and Q. An intuitive way to explain how adding Rf enhances the

gyrator-C Q, is to consider the phase shift the output of the ﬁrst transconductor gm1

undergoes before it feeds the second transconductor gm2. Tuning Rf allows us to set this phase shift in order to push the loop towards positive feedback. As previously explained in section 3.2.2, the circuit has two possible operating points

for high-Q operation, which are represented by points P1 and P2 in Fig. 3.2. If the

TAI operates at point P1, a smaller feedback resistance Rf is required. This will make Q very sensitive to any interconnect resistance in the feedback path. Furthermore, if the feedback resistance is slightly nonlinear, this will cause Q to be sensitive to the signal level in the feedback path, which may lead to distortion and instability. This nonlinearity might arise due to the implementation of the variable feedback resistance,

Rf , since, in most cases, Rf will vary with the signal level as will become evident in section 3.4. On the other hand, the TAI will have a lower self-resonance frequency at

point P2. However, operating at point P2 requires a larger feedback resistance, which alleviates the sensitivity, distortion, and instability issues. It is worth mentioning that this Q-enhancement technique is applicable to any TAI based on the gyrator-C architecture. Consequently, the previous analysis provides a general framework for the design of TAIs with independent L and Q, unlike previously published work [25, 39, 48]. Moreover, the 1-port, modified gyrator-C architecture of Fig. 3.3 can be easily extended to build differential or 2-port TAIs simply by replacing the single-ended transconductors gm1 and gm2 with differential transconductors as shown in Fig. 3.4. Following the same theoretical procedure of the grounded architecture presented in section 3.3, one can show that adding two tunable feedback resistors 3.4. A GROUNDED 0.13µm CMOS TAI 61

+ + Zin,diff gm1 ro1 ro1 - - L Co1 Co1

ro2 Cin1+Co2 Rs

Rf Rf Zin,diff ro2 ro2

ro2 Cin1+Co2 Rs + + Cin2 Cin2 L -gm2 Cin1+Co2 Cin1+Co2 - -

Figure 3.4: The modified differential gyrator-C architecture. to the differential gyrator-C architecture produces a differential inductor with independently tunable L and Q. This differential topology was presented in more detail by the author in [80]. However, an in-depth analysis of this differential topology was not included as part of this thesis since all the circuits presented in chapters 4, 5, and 6 rely on the single-ended, 1-port, architecture.

3.4 A Grounded 0.13µm CMOS TAI

This section presents the design of a grounded 0.13µm CMOS TAI circuit capable of independently tuning the L and Q by using the modiﬁed gyrator-C architecture presented in section 3.3.

3.4.1 Circuit Design

Figure 3.5 shows the proposed TAI circuit, the ﬁrst transconductor gm1 of the modi-

ﬁed gyrator-C architecture is replaced by a diﬀerential pair (M1 − M2), and the second

transconductor gm2 is replaced by a common-source ampliﬁer (M4). A tunable feedback

resistance Rf is inserted between the output of the ﬁrst transconductor gm1 and the

input of the second transconductor gm2. Although the transconductors were replaced in this design with a diﬀerential pair and common-source stages, as previously mentioned, this Q-enhancement technique is applicable to any gyrator-C TAI. As another exam- 3.4. A GROUNDED 0.13µm CMOS TAI 62

Vdd Vdd

Vdd Vdd M6 M5 Vc2

IC M12 M11

Vc1 Vdd gm1

VCM M1 M2 M8 M10

Zin -g m2 IB

M4 M3 M7 M9

Figure 3.5: Proposed TAI circuit with the tunable feedback resistance.

ple, a differential, 2-port TAI circuit was presented by the author in [80], where two differential-pair transconductors were used with the tunable feedback resistors. This differential TAI, however, is not presented as part of this thesis, since it is not relevant to the subsequent circuits presented in chapters 4, 5, and 6.

In the grounded TAI circuit of Fig. 3.5, transistors M3 and M5 mirror a ratio of the

reference current in (M7 − M8) and M6, respectively, to bias the circuit. Moreover,

M12 mirrors half of the current in M11 to generate the necessary current to bias M2.

To ensure that M3 and M9 mirror the desired current from the reference transistor

M7, a low-voltage cascode current mirror is used. Sizing cascode transistors M8 and

M10 appropriately will guarantee that the drains of M3, M7, and M9 have the same potential, this is achieved by setting:

W W W W /L 8 = 10 = 2 2 × 7 7 . (3.19) L8 L10 L2 W3/L3

The transistor sizes of the proposed grounded TAI circuit are given in Table 3.1, where 3.4. A GROUNDED 0.13µm CMOS TAI 63

Table 3.1: Transistor Sizes of the TAI Circuit Transistor Size nf × Wf × L Transistor Size nf × Wf × L M1, M2 40 × 2.85µm × 0.12µm M8, M10 4 × 2.85µm × 0.12µm M3 60 × 3.3µm × 0.2µm M7, M9 3 × 3.3µm × 0.2µm M5 36 × 4µm × 0.2µm M6 3 × 4µm × 0.2µm M11 2 × 4µm × 0.2µm M12 20 × 4µm × 0.2µm M4 40 × 4.5µm × 0.12µm

Table 3.2: Transistor Sizes of the Digital/Analog Tunable Feedback Resistance Rf

Transistor Size nf × Wf × L Transistor Size nf × Wf × L Mf1 1 × 0.5µm × 2µm Mf2 1 × 0.5µm × 1µm Mf3 1 × 1µm × 1µm Mf4 1 × 2µm × 1µm Mf5 1 × 4µm × 1µm Rf0 500Ω MN 4 × 5µm × 0.12µm MP 12 × 5µm × 0.12µm

nf is the number of ﬁngers used to implement each transistor and Wf is the ﬁnger width.

The choice of the transistor sizes, especially M1,M2, and M4 dictates the achievable range of inductances by the TAI circuit. In general, to achieve large inductances, smaller sizes should be picked. However, using small sizes for the transistors makes the TAI circuit incapable of supporting a large signal swing at its input port with an acceptable level of distortion. On the other hand, to achieve smaller inductances, either the sizes of the transistors should be large, which will add more parasitic capacitance to the TAI circuit, or their bias current should be increased, which increases the power dissipation. Hence, there exists many trade-oﬀs between the desired inductance range, power dissipation, speed, signal swing, and area. Consequently, careful simulations were required to determine the appropriate transistor sizes.

Tunable Feedback Resistance

To implement the tunable feedback resistance Rf , binary weighted NMOS transistors operating in the triode region are connected in parallel as shown in Fig. 3.6. The NMOS transistors are also connected in parallel to a ﬁxed resistance, Rf0, to improve linearity by making the overall feedback resistance and hence Q less sensitive to the variations in the overdrive voltage of the transistors. This will make Q less sensitive to the input signal swing and will improve the circuit stability. The NMOS transistors are switched 3.4. A GROUNDED 0.13µm CMOS TAI 64

Rf0

Vf Mf1

Mf5 Digital word

Figure 3.6: Digital/analog feedback resistance Rf .

ON and OFF using a 5-bit digital word, this allows coarse tuning of the Q. To enable ﬁne tuning, the digital word is applied to the gates of the NMOS transistors through

ﬁve CMOS inverters having a variable supply voltage, Vf , as shown in Fig. 3.6. The

voltage Vf is used to set the level of the gate voltage for the ON NMOS transistors [81]. Combining digital and analog control to tune the resistor value allows a wider tuning range for the feedback resistance, and hence for the Q. This also makes the circuit more robust to process and temperature variations. To reduce the number of pads required by the TAI circuit and hence reduce the circuit area, the 5-bit digital word is serially shifted into an on-chip shift-register. The sizes of the transistors used to implement

the digital/analog tunable feedback resistance Rf are given in Table 3.2.

3.4.2 TAI Small-Signal Analysis

An approximate expression for the TAI equivalent L and RS can be directly obtained

from Eq.(3.17) and Eq.(3.18) by replacing gm1 and gm2 with gm1,2 /2 and gm4, respectively. This results in the following expressions for the inductance and series resistance 3.4. A GROUNDED 0.13µm CMOS TAI 65

Cgs1/2+Cgd1+ R Zin ro4||ro5 s Cdb4+Cgd5+Cdb5 Z

Figure 3.7: Grounded active inductor equivalent circuit. of the equivalent L-C circuit of Fig. 3.3: µ µ ¶ ¶ 2 Rf L ≈ × Cgs4 1 + + Co , and (3.20) gm1,2gm4 ro µ ¶ 2 1 2 RS ≈ × − ω CoCgs4Rf , (3.21) gm1,2gm4 ro where ro and Co are the output resistance and capacitance of the differential pair transconductor. Equation (3.20) shows that, provided that Rf is much smaller than ro, L is independent of the feedback resistance and hence is independent of Q. Also, by closely investigating Eq.(3.20), one will realize that the value of the inductance has some dependence on process, supply, and temperature variations. Since the focus of this work has been on the initial development and validation of the TAI, a detailed sensitivity analysis of the performance of the TAI to process, supply and temperature variations lies outside the scope of this thesis. However, when using this circuit in a practical application, one can ensure that it achieves a process, supply, and temperature independent inductance by using a constant-gm bias circuit [82] to bias transistors M1,M2, and M4. Alternatively, since the circuit provides a tunable inductance, one can simply ensure that the circuit’s tuning range is wide enough to calibrate for process, supply, and temperature variations. Similarly, since Q is a function of the feedback resistance which is implemented using MOS transistors it exhibits process, supply, and temperature dependence. However, a high Q can be achieved by means of the independent L and Q tuning capability of the circuit. More elaborate circuit analysis replaces each transistor by its small-signal equivalent model (gm, ro,Cgs,Cgd), but results in a fairly complicated expression for the input impedance. To obtain a simplified expression, which is necessary to gain insight in the circuit operation, the effect of the output resistance of the NMOS transistors is 3.4. A GROUNDED 0.13µm CMOS TAI 66

neglected. The input impedance Zin obtained from the analysis can be represented by the equivalent circuit shown in Fig. 3.7. The impedance of the inductive branch, Z,

which consists of the series combination of L and RS, can be expressed as: µ µ ¶¶ R 1 s2R C C + s C + C 1 + f + f o gs4 o gs4 r r Z ≈ 2 × o o . (3.22) gm1,2gm4

This results in the same inductance and series resistance expressions given by Eq.(3.20) and Eq.(3.21), respectively, which is consistent with our generalized gyrator-C block diagram analysis presented in section 3.3.

3.4.3 TAI Noise Analysis

This section analyzes the noise generated by the TAI circuit due to the various tran-

sistors as well as the feedback resistor Rf . Our goal is to ﬁnd an equivalent noise

current source (inL), which can be connected in parallel to the TAI circuit to model the effect of the various noise sources. The results of this analysis will be used later on in chapter 5 to quantify the noise performance of the TAI-based directional coupler. In this analysis, the effect of the flicker noise generated by the transistors is neglected, since for RF applications the design frequency is well above the 1/f corner frequency. Therefore, only the thermal noise components are considered.

A simpliﬁed schematic of the TAI circuit with the diﬀerent noise sources is shown in Fig. 3.8, where i2 is the mean-square value of the drain current thermal noise nMx generated by transistor M , and v2 is the mean-square value of the thermal noise x nRf voltage generated by the feedback resistance Rf . For simplicity, the gate noise is neglected throughout this analysis as well as the output resistances ro1,2, and the gate-

source capacitances Cgs1,2 of transistors M1 and M2. Assuming all the various noise sources are uncorrelated, one can use superposition to show that, the mean-square

value of the input referred noise current (inL) at the inductor input port is expressed 3.4. A GROUNDED 0.13µm CMOS TAI 67

Vdd

in5 Vdd M5 in12

M12 Vdd

in1

in2 M1 M2 L i Inductor Inductor nL input port input port

in4 in3 M4 M3

vnRf Rf + -

Figure 3.8: Simpliﬁed TAI schematic with the main current and voltage noise sources, and equivalent lumped noise current model.

as:

2 2 2 v2 (1 + ω2C2r2) in1 + in2 + in3 2 nRf o o + in12 + 2 2 2 2 2 4 ro inL(ω) = in4 +in5 +gm4 × µ ¶2 µ µ ¶¶2 , (3.23) 1 2 2 Rf − ω Rf CoCgs4 + ω Co + Cgs4 1 + ro ro where ro and Co are the output resistance and capacitance of the diﬀerential pair respectively. If the TAI circuit is conﬁgured for high-Q operation, one should set the

feedback resistance Rf to cancel the resistive part of the circuit’s input impedance. According to the approximate expression of Eq.(3.21), this results in the following value for the feedback resistance:

1 Rf ≈ 2 , (3.24) ωo roCoCgs4

where ωo is the design frequency. Hence, for high-Q operation, the mean-square value 3.4. A GROUNDED 0.13µm CMOS TAI 68

1mm

Open G S G S G Active ct. pad inductor 0.5mm circuit

Digital Digital DC/bias circuitry control inputs inputs circuit Short G S G ct. pad

Figure 3.9: Tunable active inductor die micrograph.

of the input referred noise current becomes:

2 2 2 v2 (1 + ω2C2r2) in1 + in2 + in3 2 nRf o o o + in12 + 2 2 2 2 2 4 ro inL(ωo) ≈ in4 + in5 + gm4 × µ µ ¶¶2 . (3.25) 2 Rf ωo Co + Cgs4 1 + ro

The transistor drain thermal noise current i2 is given by 4kT γg , whereas the nMx mx resistor thermal noise voltage v2 is given by 4kT R , where k = 1.38×10−23 J/K is the nRf f Boltzmann constant, and T is the absolute temperature in degrees Kelvin. The value of the coeﬃcient γ typically ranges from 2 to 3 for short-channel transistors [44, 83]. This results in the following expression for the TAI equivalent noise current:   2 2 2 2gm1,2 + gm3 Rf (1 + ωo Co ro)  + gm12 + 2  2  2 4 γro  i (ωo) = 4kT γ gm4 + gm5 + g × µ µ ¶¶  . nL  m4 2  2 Rf ωo Co + Cgs4 1 + ro (3.26)

3.4.4 Physical Realization and Experimental Characterization

Figure 3.9 shows the die micrograph of the fabricated grounded TAI circuit, the chip was fabricated in a 1.5V , 0.13µm CMOS process. The TAI circuit occupies 150µm × 3.4. A GROUNDED 0.13µm CMOS TAI 69

170µm. A 150µm-pitch GSG (ground-signal-ground) probe was used to probe the TAI, while two 80µm-pitch multi-contact wedges with DC needles were used to provide the bias and control voltages. A CS-5 calibration substrate was used to perform a 1-port calibration to de-embed the frequency response of the RF probe, connectors, and cable.

The TAI was characterized by measuring the reflection coefficient, S11, that was in turn used to extract the L and Q. As indicated by Fig. 3.9, open- and short-circuited pads were included on the fabricated chip to estimate the input’s pad parasitic capacitance and inductance. The pad capacitance and series inductance were obtained from the measured input reflection coefficients of the open- and short-circuited pads respectively. For a 65µm×65µm square pad, the measurements show that, the capacitance is 30fF, and the inductance is 70pH. Consequently, they will not have a large effect on the TAI performance, and all the measurements presented herein will include the effects of the pad parasitics, i.e. the pad parasitics were not de-embedded. The tuning characteristics of the TAI circuit are demonstrated through tuning modes I and II described below.

Tuning Mode I: Variable L and Fixed Peak-Q

In this mode, the inductance is tuned while maintaining a ﬁxed peak-Q. The TAI L

is tuned via gm1,2 and gm4 according to Eq.(3.20), where the two transconductances

are set by the two bias voltages VC2 and VC1, respectively (see Fig. 3.5). However, this will also change the value of the peak-Q according to Eq.(3.11). To compensate

for this change, the feedback resistance Rf is tuned to bring the peak-Q back to its

desired value. According to Eq.(3.20), changing Rf does not have a significant effect on L. As indicated by Eq.(3.6), changing the bias point to tune L will also affect the

TAI self-resonance frequency, fr, since the change in L necessitates a change in the frequency at which L resonates with the TAI parasitic capacitance.

To fully characterize the TAI circuit performance, the two bias voltages VC1 and VC2 are swept using two DC voltage sources and the measured L and Q are reported herein.

The measured L and Q are plotted in Fig. 3.10 when VC1 is ﬁxed at 0V and VC2 is swept

from 0.3V to 0.6V. As indicated by Fig. 3.10-a, increasing VC2 results in a larger value

for the bias current IB, and consequently gm1,2 increases. This causes L to decrease. Across this inductance tuning range, the peak-Q is maintained in excess of 100 as shown by Fig. 3.10-b. This high Q is achieved by adjusting the value of the feedback 3.4. A GROUNDED 0.13µm CMOS TAI 70

* V =0.3V, + V =0.35V * V =0.3V, + V =0.35V C2 C2 250 C2 C2 ∆ V =0.4V, x V =0.5V ∆ V =0.4V, x V =0.5V 4 C2 C2 C2 C2 (nH) O V =0.6V O V =0.6V C2 C2 200 3 150 2

100 1

50 0 Measured TAI quality factor Measured TAI inductance 0 1 2 3 4 5 1 2 3 4 Frequency (GHz) Frequency (GHz) (a) (b)

Figure 3.10: Measured TAI characteristics versus frequency when VC1=0V and VC2 changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor.

Table 3.3: Measured Inductances for the TAI at 2GHz for Diﬀerent Values of the Bias Voltages VC1 and VC2. Voltage VC2 0.3V 0.35V 0.4V 0.5V 0.6V 0V 4.4nH 2.1nH 1.3nH 0.9nH 0.8nH 0.1V 5nH 1.9nH 1.5nH 1.1nH 0.9nH VC1 0.2V 6.5nH 2.4nH 1.8nH 0.35V 9.5nH 0.4V 11.7nH

voltage Vf , which controls the value of the series resistance, RS. However, increasing the inductance shifts the self-resonance frequency of the TAI to lower frequencies. This, in turn, moves the the location of the peak-Q to lower frequencies as expected from Eq.(3.10).

Figures (3.11) and (3.12) show the measured L and Q when VC1 is ﬁxed at 0.1V and

0.2V, respectively, and VC2 is swept. In Fig. 3.11, VC2 is swept from 0.3V to 0.6V, while in Fig. 3.12, VC2 is swept from 0.3V to 0.4V. On the other hand, Fig. 3.13 shows the measured L and Q of the TAI circuit when VC1 is swept from 0.4V to 0V and VC2 is ﬁxed at 0.3V. Decreasing VC1 results in a larger transconductance gm4, resulting in a lower inductance. 3.4. A GROUNDED 0.13µm CMOS TAI 71

* V =0.3V, + V =0.35V 5 C2 C2 ∆ V =0.4V, x V =0.5V C2 C2 (nH) 150 O V =0.6V 4 C2

3 100 2

1 50 * V =0.3V, + V =0.35V 0 C2 C2 ∆ V =0.4V, x V =0.5V C2 C2

O V =0.6V Measured TAI quality factor C2

Measured TAI inductance −1 0 1 2 3 4 5 1 1.5 2 2.5 3 3.5 4 Frequency (GHz) Frequency (GHz) (a) (b)

Figure 3.11: Measured TAI characteristics versus frequency when VC1=0.1V and VC2 changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor.

∆ V =0.3V, O V =0.36V ∆ V =0.3V, O V =0.36V C2 C2 C2 C2 x V =0.4V 250 6 C2 x V =0.4V

(nH) C2 5 200 4 3 150 2 100 1 0 50

−1 Measured TAI quality factor Measured TAI inductance 0 1 2 3 4 1 1.5 2 2.5 3 Frequency (GHz) Frequency (GHz) (a) (b)

Figure 3.12: Measured TAI characteristics versus frequency when VC1=0.2V and VC2 changes from 0.3V to 0.4V: (a) Inductance, (b) Quality factor. 3.4. A GROUNDED 0.13µm CMOS TAI 72

O V =0.4V, x V =0.35V 300 O V =0.4V, x V =0.35V C1 C1 C1 C1 ∆ V =0.15V, + V =0V ∆ V =0.15V, + V =0V C1 C1 C1 C1 (nH) 10 250

200 5 150

100 0 50 Measured TAI quality factor Measured TAI inductance 0 0.5 1 1.5 2 2.5 3 0.4 0.6 0.8 1 1.2 1.4 1.6 Frequency (GHz) Frequency (GHz) (a) (b)

Figure 3.13: Measured TAI characteristics versus frequency when VC1 changes from 0V to 0.4V and VC2=0.3V: (a) Inductance, (b) Quality factor.

In summary, the results show that the proposed TAI circuit has a very wide inductance tuning range; the inductance can be tuned from 0.93nH to 2.7nH at the 2.4GHz ISM band, while maintaining a peak-Q greater that 100 across the entire inductance tuning range. However, the Q at 2.4GHz ranges from a maximum of 180, at the middle of the inductance tuning range, to a minimum of 15 at the extremes of the tuning range. The largest inductance tuning range is achieved by the circuit at 2GHz, where the circuit can provide inductances as low as 0.8nH and as high as 11.7nH while maintaining a peak-Q in excess of 100. Table 3.3 summarizes the measured inductance values at

2GHz for the diﬀerent values of the bias voltages VC1 and VC2. As illustrated by the various inductance plots, when the inductance increases the

TAI’s self-resonance frequency, fr, decreases. As previously explained, this behavior is expected from analyzing Eq.(3.6). The measured TAI self-resonance frequencies, fr, are plotted versus the measured TAI inductance, L, in Fig. 3.14 together with the theoretical values predicted from Eq.(3.6). The plot shows very good agreement between the theoretical prediction and the measured values although the expression of Eq.(3.6) is derived based on the gyrator-C block diagram and it neglects the second term of Eq.(3.5). This also shows that the simple passive L-C model of Fig. 3.1 yields accurate results. 3.4. A GROUNDED 0.13µm CMOS TAI 73

5.5 Measurements Theory 5

4.5 (GHz) r f 4

3.5

2.5 Resonance frequency, 2

1.5 1 2 3 4 5 6 Measured TAI inductance, L (nH)

Figure 3.14: Theoretical and measured self-resonance frequency, fr, versus the inductance, L, for the diﬀerent bias conditions.

3.5 (GHz)

p 3

2.5 Measured TAI

Q frequency, f frequency, Q 2 Theory CMOS TAI [25] CMOS TAI [39] Peak− 1.5 GaAs TAI [48]

1 2 3 4 5 6 Resonance frequency, f (GHz) r

Figure 3.15: Theoretical and measured peak quality factor frequency, fQ, versus the self-resonance frequency, fr. The measured data presented is from the proposed circuit and from [25], [39], and [48], while the theoretical expression used for the comparison is f = √fr , which is given by Eq.(3.10). Q 2 3.4. A GROUNDED 0.13µm CMOS TAI 74

As previously mentioned, increasing L causes the peak-Q frequency, fp, to shift to lower values. This is a result of using the gyrator-C architecture to implement the TAI, which results in a direct relationship between both its peak-Q and resonance frequencies as given by Eq.(3.10). The measured peak-Q frequencies of the proposed TAI circuit and the theoretical values predicted by Eq.(3.10) are plotted in Fig. 3.15 versus

the self-resonance frequency, fr. The ﬁgure shows good agreement between the measurements and the theoretical expression of Eq.(3.10), although it was derived using the generalized gyrator-C block diagram. To further demonstrate this, Fig. 3.15 also plots

fp versus fr for other gyrator-C based TAI circuits presented in the literature [25,39,48]. Despite being fabricated in diﬀerent technologies; GaAs, 0.18µm CMOS, and 0.13µm CMOS, in most of the cases, their peak-Q frequencies can be accurately estimated from the theoretical expression of Eq.(3.10). This is true even though the derivation of Eq.(3.10) neglects the frequency dependence of the equivalent series resistance RS.

The diﬀerence between the measured fp and the theoretical predication in Fig. 3.15 can be attributed to the negative term of Eq.(3.10) which was neglected. Also, Fig. 3.15 shows that the proposed TAI circuit has a very wide tuning range as it can operate with a peak-Q in excess of 100 over a very wide frequency range; 1.3-3.3GHz. The circuit inductance, for each of these cases, can be obtained by combining the results of Fig. 3.14 and Fig. 3.15.

Tuning Mode II: Variable Q and Fixed L

In this mode, L is ﬁxed and the peak-Q is tuned by changing the feedback resistance Rf .

Increasing Rf will decrease the series resistance RS according to Eq.(3.21). Assuming

the TAI is operating at point P2 on Fig. 3.2, f(RS) will increase causing the peak-Q to

decrease. On the other hand, decreasing Rf will result in a higher peak-Q. Tuning the

peak-Q via the feedback resistance Rf does not aﬀect the TAI bias point. Consequently,

the transconductances gm1,2 and gm4 are unaﬀected. Moreover, during the design phase

the feedback resistance Rf was chosen much smaller than the output resistance of

the diﬀerential pair transconductor, ro. According to Eq.(3.20), this ensures that the inductance will remain unchanged while the Q is set to its desired value, thus allowing us to achieve independent tuning. The measured Q of the TAI is plotted versus frequency in Fig. 3.16 for diﬀerent 3.4. A GROUNDED 0.13µm CMOS TAI 75

250 V =800mV f V =900mV f V =920mV 200 f V =950mV f

150 V increasing & f R decreasing f 100

Measured TAI quality factor 50

0 1 1.5 2 2.5 3 3.5 Frequency (GHz)

Figure 3.16: Measured Q versus frequency for diﬀerent feedback voltages Vf .

V =0.8V® 0.95V f

6.7% variation in L at the peak Q frequency, f =2.4GHz Qp

TAI resonates at f =3.1GHz r

Figure 3.17: Measured S11 of the TAI for diﬀerent feedback voltages Vf . 3.4. A GROUNDED 0.13µm CMOS TAI 76

values of the feedback voltage Vf . These measurements were obtained with the TAI conﬁgured for a nominal inductance of 1.7nH. The plot shows that the peak-Q can be tuned from 10 to 200 by sweeping Vf from 800mV to 950mV. Across this tuning range, the measured inductance variation at 2.4GHz is less than 6.7% of its nominal value.

As indicated by the measured Q plots, the peak-Q frequency, fp, remains relatively fixed at 2.4GHz, which is a direct result of the independent L and Q tuning capability, since the relatively unchanged L results in the same self-resonance as well as peak-Q frequencies as indicated by Eq.(3.6) and Eq.(3.10) respectively. The measured reflection coefficient of the TAI is plotted in Fig. 3.17 for the different values of the feedback voltage. The TAI circuit resonates at 3.1GHz regardless of the value of its peak-Q.

It is also worth mentioning that, tuning Q using the feedback resistance Rf does not require any additional power dissipation, as opposed to using traditional methods such as cross-coupling a diﬀerential pair to generate a negative resistance [43]. Although all the measured results that were presented in the previous sections were obtained from a single die, other dice were also tested to verify the consistency of the results. Furthermore, the consistency of the die-to-die performance will be practically demonstrated in chapter 6, through the use of multiple chips to design the steerable antenna array, which uses 6 packaged TAI chips within its beam steering network.

Measurements Versus Simulations

The proposed TAI circuit does not use a capacitor to terminate the the output of the diﬀerential-pair transconductor, instead it relies on the gate capacitance of transistor

M4. As previously explained in chapter 2, this makes the TAI circuit suitable for high-speed operation. However, it makes the TAI circuit very sensitive to any parasitic capacitance, requiring special care during the design, simulation, and layout phases in order to obtain the desired response. Figure 3.18 shows the simulated L and series resistance for a subset of the bias con-

ditions; (VC1=0V, VC2=0.6V) and (VC1=0V, VC2=0.6V), and compares the simulated results with the measurements. Good agreement is achieved between the measured and simulated inductances with a mismatch of approximately 15% at 2.4GHz. To achieve this fairly good agreement between the measured and simulated inductance, a ﬁxed 100pH inductor is added in series with the TAI, as shown in Fig. 3.19, to model the 3.4. A GROUNDED 0.13µm CMOS TAI 77

5 20 Measurements Measurements 4 Simulations Simulations ) 15 Ω 3 10 Vc2=0.4V Vc2=0.4V 2 5 1 Inductance (nH) Vc2=0.6V

Series Resistance ( 0 0 Vc2=0.6V

−1 −5 1 2 3 4 5 1 1.5 2 2.5 3 3.5 4 Frequency (GHz) Frequency (GHz) (a) (b)

Figure 3.18: Measured and simulated results versus frequency when VC1=0V and VC2 is set to 0.6V and 0.4V: (a) inductance (b) series resistance.

Vdd VC1 VC2

Lpad VCM M1 M2 100pH

Zin TAI circuit

Cp 100fF Vf

Figure 3.19: Circuit setup used for the simulation of the TAI circuit. 3.4. A GROUNDED 0.13µm CMOS TAI 78

RF signal combiner

f 1 + Circulator probe 1-port DUT

f2 Grounded tunable RF signal active inductor chip sources Spectrum Analyzer

Figure 3.20: Experimental test setup used for characterizing the TAI circuit linearity.

pad and input port interconnect inductance. Also, a ﬁxed 100fF capacitor was added

at the gate of M4 to model the parasitic capacitance associated with this critical node. The measured and simulated series resistance values, shown in Fig. 3.18-b, fairly match with each other. However, they are oﬀ by approximately 4Ω at 2.4GHz. To this end, the TAI was extensively characterized, and its measured S-parameters were used to design all the subsequent circuits presented in this thesis (the phase shifters, the directional coupler, and the antenna array). This approach will enable us to accurately predict the response of the diﬀerent TAI-based circuits, and achieve good matching between the measured and the desired response.

Linearity Measurements

Numerous measures are incorporated in the design of the TAI to achieve good linearity. The TAI circuit is designed to allow a large signal swing at its input port by setting the common-mode voltage, Vcm, to VDD/2. Also, the bias current of transistor M4, IC , is selected large enough to allow the TAI to supply and drain the input current without

considerably aﬀecting the bias point of M4. Despite being a 1-port device, the linearity of the grounded TAI circuit can be experimentally characterized by using an RF signal source to excite it through a circulator as shown in Fig. 3.20. The circulator directs the reﬂected wave from the TAI circuit to its third port and the various inter-modulation components are analyzed using a 3.4. A GROUNDED 0.13µm CMOS TAI 79

−5

−10

−15

−20

−25

−30 Output power (dBm) −35

−40

−45 −30 −25 −20 −15 −10 −5 0 5 10 Input power (dBm) Figure 3.21: Amplitude of the power reflected back by the TAI versus the input power when applying a single RF signal source. spectrum analyzer. This experimental setup was presented in [84] to characterize the linearity of a grounded GaAs TAI. The 1-dB compression point of the TAI circuit is characterized by using only one RF signal source, and measuring the amplitude of the power reflected by the TAI. Figure 3.21 shows the amplitude of the reflected power at the same frequency of the RF signal source, f1, which was selected as 4GHz. The measured results show that the TAI achieves a +2.16dBm input compression point, which corresponds to approximately an 800mVpp voltage swing at the TAI input port while operating from a 1.5V supply. This is considered a very high 1-dB compression point for an active inductor. However, this comes at the expense of the power consumption, which is reported in the Table 3.4. The IIP3 (third-order input intercept point) of the

TAI is characterized by combining two input frequencies f1 and f2 and extrapolating the measured output powers at f1 and 2f1 − f2 until they intersect. The measured output power at f1 and 2f1 − f2 are plotted in Fig. 3.22, where f1 is chosen as 4GHz and the frequency separation between the two input signals was chosen as 10MHz. As indicated by Fig. 3.22, the TAI achieves an IIP3 of 12.5dBm. 3.4. A GROUNDED 0.13µm CMOS TAI 80

−20

−40

−60

−80

Output power (dBm) −100

Ouput power at f −120 1 Ouput power at 2f −f 1 2 −140 −30 −20 −10 0 10 Input power (dBm)

Figure 3.22: Amplitude of the power reflected back by the TAI at f1 and 2f1 −f2 versus the input power when combining two RF signal sources. 3.4. A GROUNDED 0.13µm CMOS TAI 81 m ⇒ 200 µ ⇒ 11.7 This work Q :10 > 100 m 0.13 µ m 0.18 50 88 × 90 150 × 170 µ × 50 70,51 ⇒ 8.5 5.7,8 0.83 ⇒ 0.5 1.55,2.2 3.5 ⇒ 0.75 > m 0.18 µ × 50 100 ⇒ 5.6 1 . – – – +2.16dBm 100 Q or d m 0.18 S and the input power level. µ R S R [25] [25] [25] [39] -7dBm –––– @5GHz @2.1GHz @2GHz7 ⇒ 2 – 1.65– @2GHz 1.8V 3 – 1.8V– 1.8V – 2V – – 1.5V – 6.7%@2.4GHz – +12.5dBm > 50> 9.5 – – 4.1 ⇒ 2.5 2.5,2.8 5.35 ⇒ 2.4 0.18 40 × 50 and L b :-5.6 ⇒ 20.8 m ⇒ 110 1 ⇒ 8 2.1 S – – – – 1 6V 240 ⇒ 90 1.8– 7.2 7.2 8 52.5 ⇒ 22.5 900 × 700 R – b c ⇒ 15 :-10 m 1 µ S µ [37] [38] 65 ⇒ 90 65 GaAs– GaAs– – 1.1 BiCMOS CMOS4% CMOS– – CMOS CMOS -0.9dBm – 1 R 1200 × 1700 -order harmonic in the inductor current becomes equal to the fundamental component. nd b 700 :-20 ⇒ 44 ⇒ 56 m S [48] 1 µ GaAs 9.6 @1.7GHz 3400 1.7 2.2 R 2%@1.7GHz 9V 369 900 × – – ) a DD of TAI Performance ) (GHz) DD Table 3.4: Comparison Between Different Tunable Active Inductor Implementations V Q f (GHz) × µm r f p µm tuning range freq. S feature size QQ Q R ecification or uning mode II can be characterized by measuring the tuning range for either tuning range (nH) variation Size includes bias andInput on-wafer power measurement at pads which strong dependence was observed between both Simulated input power at which the 2 T Peak Res. freq. Supply voltage Power diss. (mW@ V L Technology measured at 1dB comp. point IIP3 L Peak Q TAI size ( Sp Min. c a b d Comparison 3.4. A GROUNDED 0.13µm CMOS TAI 82

Table 3.4 presents a detailed comparison between the proposed TAI and diﬀerent TAIs presented in the literature [25,37–39,48]. Among these recently published TAIs, this work provides the largest inductance tuning range and the highest resonance frequencies (with the exception of the BiCMOS design) in spite of the low-voltage CMOS process. Furthermore, the proposed design provides a mechanism to control the Q with very small variations in the inductance. Compared to the other CMOS and BiCMOS implementations, the proposed TAI dissipates more DC power in order to achieve better linearity. Unfortunately, linearity was not reported in most of the previous publications to allow for an adequate comparison. CHAPTER 4

Wide Tuning Range CMOS Phase Shifters

P hase shifters are essential building blocks for many RF and microwave applications. One of the most important applications of phase shifters is electronically steerable antenna arrays. The direction of the antenna array’s main beam can be controlled by appropriately setting the relative phases of the signals feeding each antenna element in the array. To achieve a wide scan-angle range, it is necessary to design phase shifters with a wide tuning range. Furthermore, to avoid power losses due to reﬂections at the input and output ports of a phase shifter, it is required to have a constant input and output impedance across its entire tuning range. These two constraints (i.e., wide tuning range, and matching) limit our choice of the phase shifter’s architecture.

4.1 Introduction

As described in chapter 2, to achieve a wide tuning range from an L-C phase shifter, two tunable elements are necessary. This requires the use of both varactors and TAIs to extend the phase tuning range. To facilitate using TAIs to design phase shifters, one should use L-C phase shifter architectures requiring grounded inductors as opposed to ﬂoating or 2-port inductors. Among the diﬀerent L-C architectures in Fig. 2.12,

83 4.1. INTRODUCTION 84

-ve

TAI Electronic Beam Steering Network (a) MMIC High-pass TAI-based PS

-ve +ve C C

TAI

(b) Printed TAI-based PRI/NRI PS C C Lo Lo TAI Co Co Co Co

Electronic Beam Steering Network (c) MMIC Lumped-Element TAI-based PRI/NRI PS

C C Lo Lo

L Co Co Cv Co Co

(d) MMIC Lumped-Element Passive PRI/NRI PS

Figure 4.1: Diﬀerent series-fed phased array designs and their radiation patterns: (a) shows the high-pass phase shifters used by the top design, (b) to (d) show the PRI/NRI phase shifters used by the lower design. 4.1. INTRODUCTION 85

this limits us to the high-pass Tee architecture redrawn here in Fig. 4.1-a, since it uses the minimum number of inductors as opposed to the high-pass Π architecture. Consequently, the first wide tuning range phase shifter presented in this chapter uses the high-pass Tee architecture. Although this is a standard phase shifter architecture, the design presented here combines the use of varactors and TAIs to insure the matching of the phase shifter across its entire phase tuning range besides extending its tuning range. The high-pass phase shifter is only capable of providing positive phase shifts, which according to Eq.(2.41) will only result in negative scan angles if used in the feed network of a series-fed phased array1. Figure 4.1 shows two series-fed phased arrays, the top one uses tunable high-pass phase shifters, which makes the array only capable of achieving negative scan angles. Whereas, the lower one uses phase shifters which enable the antenna array to center its main beam around the broadside direction. To achieve this, the phase shifters are required to generate both positive and negative phase shifts1. In other words, their phase response should be centered around 0o. As described in chapter 2, PRI/NRI metamaterial phase shifters are capable of achieving 0o phase shifts with much lower group delays compared to traditional −2π TL phase shifters. This makes them more suitable for broadband applications, in which it is required to minimize the beam squinting with frequency variations. To this end, this chapter presents three novel electronically tunable PRI/NRI metamaterial phase shifter designs, which are capable of achieving both positive and negative phase shifts. To the author’s knowledge, this represents the first published attempt to design tunable PRI/NRI metamaterial phase shifters that have a phase response centered around the 0o, and at the same time have a low return loss across their entire phase tuning range. The proposed PRI/NRI tunable phase shifters shown in Figs.(4.1-b), (4.1-c), and (4.1-d), can be used in series-fed phased arrays to steer the main beam about the broadside direction. The TL PRI/NRI tunable phase shifter of Fig. 4.1-b is presented in section 4.2. It uses the same architecture of the TL PRI/NRI phase shifter presented in [5]. However, electronic tunability and matching are simultaneously achieved by replacing the fixed

1This conclusion is reached assuming that the progressive inter-element phase shift is only generated by the phase shifters, which neglects the phase contribution of the feed network. The effect of the feed network phase response is discussed in more detail later in chapter 6 since it depends on the array architecture. 4.1. INTRODUCTION 86 series capacitors with varactors and the fixed shunt inductors with the grounded TAIs presented in chapter 3. Following this, a fully-integrated version of the PRI/NRI tunable phase shifter, shown in Fig. 4.1-c, is presented in section 4.3. This design replaces the TL sections with lumped L-C sections, which enables integrating the entire phase shifter on a single MMIC resulting in a much more compact implementation. The CMOS grounded TAI of chapter 3 is used to design the first three tunable phase shifters; the high-pass design of Fig. 4.1-a, the TL PRI/NRI design of Fig. 4.1-b, and the MMIC PRI/NRI design of Fig. 4.1-c. The capability to tune its inductance and quality factor independently is a key feature to overcome the degradation of the phase shifter’s insertion loss and return loss due to the variation of the TAI’s Q when the TAI inductance is tuned. Furthermore, having control over the TAI’s Q without affecting its inductance, allows controlling the phase shifter’s insertion loss. Moreover, the TAI is capable of generating a negative series resistance, which can be used to partially compensate the varactor losses while maintaining the bi-directionality of the phase shifters as opposed to using amplifiers. Another MMIC PRI/NRI tunable phase shifter design is presented in section 4.5. However, this design is passive and does not use TAIs to tune the shunt inductance. Alternatively, it uses a variable capacitor connected in parallel with a shunt spiral inductor as shown in Fig. 4.1-d. Compared to the TAI-based design of Fig. 4.1-c, this design does not consume any DC power and at the same time it eliminates the noise and non-linearity contributions of the TAI circuit. In summary, this chapter presents four different electronically tunable phase shifter designs:

• The high-pass TAI-based phase shifter of Fig. 4.1-a [Section 4.2] • The TL PRI/NRI TAI-based phase shifter of Fig. 4.1-b [Section 4.3] • The MMIC PRI/NRI TAI-based phase shifter of Fig. 4.1-c [Section 4.4] • The MMIC PRI/NRI passive phase shifter of Fig. 4.1-d [Section 4.5]

Throughout this chapter, we follow the same procedure for each phase shifter design, by presenting its design equations, implementation, and its experimental characterization. Following that, the advantages and disadvantages of the diﬀerent phase shifter designs are discussed and they are compared to previous designs published in the literature. 4.2. HIGH-PASS PHASE SHIFTER 87

C C

Figure 4.2: High-pass phase shifter unit-cell.

4.2 High-pass Phase Shifter

This section presents the design of the tunable high-pass phase shifter. The phase shifter achieves a wide phase tuning range and at the same time a low return loss across its entire tuning range by combining the use of two tunable elements; varactors and TAIs. Also, this section presents the experimental characterization of critical performance limits of the TAI-based phase shifter, such as linearity, which is rarely reported in other publications.

4.2.1 Analysis

Phase Response

If the high-pass phase shifter of Fig. 4.2 is terminated with a source and load impedance

of Zo, one can show that the forward transmission coeﬃcient, S21, can be expressed as:

s3 S = µ ¶ µ ¶. (4.1) 21 1 Z 1 s + s2 + s o + CZo 2L 2CL

Eq.(4.1) shows the high-pass nature of the phase shifter, and at the same time it reveals that the phase shifter has one real pole at ω = 1/CZ and a pair of complex poles √ p1 o at ωp2,3 = 1/ 2CL. The operating frequency of the phase shifter should be chosen greater than the pole frequencies in order to avoid attenuating the input signal. Using Eq.(4.1), one can show that the insertion phase, φ, is expressed as:

µ 2 ¶ 3π −1 2ωCZo(1 − ω LC) φ = − tan 2 2 . (4.2) 2 1 − ω C(2L + CZo ) 4.2. HIGH-PASS PHASE SHIFTER 88

At the same time, to match the impedance of the phase shifter to the source and load

impedances, Zo, one equates the input reﬂection coeﬃcient, S11, to zero:

1 + s2(2CL − Z2C2) S = µ ¶ µ o ¶ = 0. (4.3) 11 1 Z 1 s + s2 + s o + CZo 2L 2CL

This results in the following matching condition:

1 + ω2C2Z2 L = o . (4.4) 2ω2C

Since the phase shifter should be designed to operate at frequencies higher than its

pole frequency, 1/CZo, the matching condition of Eq.(4.4) can be approximated as: r CZ2 2L L ≈ o ⇒ Z = . (4.5) 2 o C

Using the result of Eq.(4.4), the phase shift expression can be simpliﬁed to: √ 2 φ ≈ √ . (4.6) ω LC

Equation (4.6) indicates that the phase shifter provides a phase advance, i.e. a positive phase shift. Furthermore, the insertion phase, φ, can be tuned by varying the values of both the series capacitors, C, and the shunt inductor, L. If L and C are varied from

their nominal value to rL×L and rC ×C, the phase tuning range can be expressed as: µ ¶ √ 1 2 |∆φ| = 1 − √ × √ . (4.7) rLrC ω LC

Figure 4.3 plots the phase tuning range given by Eq.(4.7). To generate this plot, a nominal value of 3nH is chosen for L, also the operating frequency is arbitrarily chosen as 2.4GHz, and the value of C is calculated using the matching condition of Eq.(4.5). The figure plots the tuning range for two cases; the first one assumes we use fixed

inductors and variable capacitors, i.e. rL=1, and the second one assumes we use both

variable capacitors and inductors with rL = rC . As indicted by Fig. 4.3, tuning both elements results in increasing the tuning range by 53%. Furthermore, tuning both 4.2. HIGH-PASS PHASE SHIFTER 89

50 ↓

30 ↑ 53% increase 20 in tuning range

→ Phase tuning range (deg) Tuning L and C r =r 10 L c Tuning only C → r =1 L

0 1 1.5 2 2.5 3 3.5 4 Capacitor tuning ratio r c

Figure 4.3: Phase tuning range versus the capacitor tuning ratio rC .

elements allows one to maintain the matching condition of Eq.(4.5) across the entire phase tuning range, by setting rL = rC . In contrast, designs using only one tunable element are not capable of satisfying the matching condition across the entire tuning range.

Loss Compensation

To investigate the effect of the series resistance, RS, associated with the shunt TAI, on the phase shifter loss, one can derive the expression for the forward transmission coefficient, S21 taking into account the effect of RS. Under the matching condition of

Eq.(4.5), S21 can be expressed as: µ ¶ R s2 s + S L S21 = µ ¶ µ ¶. (4.8) 1 2 Zo + 2RS 1 s + s + 2 s + 2 2 CZo CZo C Zo

As previously mentioned the phase shifter has a pair of complex conjugate poles. How- ever, Eq.(4.8) indicates that the quality factor associated with the complex conjugate 4.2. HIGH-PASS PHASE SHIFTER 90

C C

gm1 TAI Z in Rf

Gyrator-C -gm2 active inductor C

Figure 4.4: Proposed high-pass phase shifter circuit implementation.

poles, ωp2,3, is a function of RS, and is given by:

Zo Qp2,3 = . (4.9) Zo + 2RS

Hence, the value of RS determines the poles’ quality factor, i.e. it determines the damping factor associated with the two poles. By generating a negative resistance, RS, through the TAI circuit, higher values of Qp2,3 can be achieved. This will increase the peaking that occurs in the frequency response of S21, which can be used to partially compensate for the series capacitors’ losses. This will, in turn, minimize the phase shifter insertion loss.

4.2.2 Design and Physical Implementation

The circuit diagram of the proposed high-pass phase shifter is shown in Fig. 4.4. It is designed in the 1.5V, 0.13µm CMOS process. The variable capacitors are implemented using 10×0.8µm×10µm on-chip hyper-abrupt junction varactors2, whereas the tunable inductor is implemented using the same grounded TAI circuit described in chapter 3. The reverse bias voltage across the varactors sets their capacitance. The cathode voltages, VB, is set through the input and output ports of the phase shifter via two external bias-Tees. On the other hand, their anode voltages have a ﬁxed value which is set from within the TAI circuit and is approximately equal to VCM of the TAI circuit. The varactors’ capacitance can be tuned from 0.8pF to 0.3pF by changing the reverse

2Hyper-abrupt junction varactors have P-N junctions which are doped to optimize the range of capacitance versus the reverse bias voltage. 4.2. HIGH-PASS PHASE SHIFTER 91

DC/Bias inputs

Phase shifter 250 m

G G 550 m m S S 250

500 m

Figure 4.5: High-pass phase shifter die micrograph bias voltage across them from 0V to 3V. Although the supply voltage for this process is 1.5V, it oﬀers varactors which can have reverse bias voltages up to 3V.

4.2.3 Experimental Characterization

Figure 4.5 shows the die micrograph of the fabricated phase shifter. The circuit occupies 250µm×250µm, out of which the TAI occupies 150µm×170µm. Two 150µm-pitch GSG (ground-signal-ground) probes were used to characterize the phase shifter, while two 80µm-pitch multi-contact wedges with DC needles were used to provide the bias and control voltages.

S-parameter Measurements

Figure 4.6 shows the measured insertion phase, φ, for diﬀerent bias conditions. To tune the phase shift φ, the series capacitance and the shunt inductance are varied using the input and output port DC voltage, VB, and the TAI bias point (Vc1, Vc2, Vf ). VB is swept from 0V to 3.6V, and for each bias voltage the appropriate inductance is generated by the TAI circuit using Vc1 and Vc2 in order to satisfy the matching condition of Eq.(4.5). 4.2. HIGH-PASS PHASE SHIFTER 92

180

160 φ tuning range at o o 140 4GHz = 14 to 110.5

120 ↓ (deg)

φ 100

80 V = 0V → 3.6V B 60

40 Insertion phase 20 ↑ 0

−20 3 3.5 4 4.5 5 Frequency (GHz)

Figure 4.6: Measured phase vs. freq., for diﬀerent bias conditions

This will double the phase tuning range compared to tuning only the capacitance and at the same time will ensure a low return loss across the entire tuning range. The phase shift can be tuned from 14o to 110.5o at the design frequency, which for this design is 4GHz.

Figure 4.7 shows the measured input reﬂection coeﬃcient, S11, and the insertion loss, S21, for the same bias conditions used to generate the phase responses in Fig. 4.6.

Across the entire tuning range, the worst S11 at 4GHz is -18dB, and the phase shifter has a bandwidth of 250MHz over which S11 <-10dB. Although the frequency independent nature of the matching condition of Eq.(4.5) implies that the phase shifter will have a wide bandwidth, the measurements indicate that the phase shifter has a relatively narrow bandwidth. This is due to the self-resonance of the TAI, which according to the measurements presented in chapter 3 resonates in the vicinity of the phase shifter design frequency. For each of the bias points, used to generate the phase responses of Fig. 4.6, the feedback voltage, Vf , of the TAI is selected to achieve an appropriate negative resistance that partially compensates the varactor losses. As demonstrated by Fig. 4.7, across the entire phase tuning range S21 varies from -1.3dB to -2.7dB at

4GHz. The tuning characteristics are presented in Fig. 4.8, which shows φ and S21 at

4GHz versus the varactor voltage, VB. To demonstrate the eﬀect of the negative resistance generated by the TAI on the 4.2. HIGH-PASS PHASE SHIFTER 93

S at 4GHz varies 21 → ↓ from −1.3dB −2.7dB 0 0 ↑

−10 (dB)

(dB) BW = 250MHz 21

11 ← → −10 S S −20

−30 Return loss −20 Insertion loss

−40 Worst case S at 11 4GHz = −18dB −30 3.5 3.75 4 4.25 4.5 Frequency (GHz)

Figure 4.7: Measured S11 and S21 vs. freq., for diﬀerent bias conditions

100 −0.5 ← (dB) (deg) 21 φ

80 −1 S

−1.5 60

−2 40 → Insertion loss at 4GHz Insertion phase at 4GHz −2.5 20 −3 0 0.5 1 1.5 2 2.5 3 3.5 Varactor reverse bias voltage V (V) B

Figure 4.8: Measured phase and S21 at 4GHz vs. VB 4.2. HIGH-PASS PHASE SHIFTER 94

o dB 21 S

Vf V

Figure 4.9: Measured S21 at 4GHz versus the feedback voltage Vf

phase shifter loss, RS is varied by sweeping the feedback voltage, Vf , of the TAI, and the measured S21 is plotted in Fig. 4.9. This shows that the insertion loss can be enhanced by 2dB with less than 23o phase variation. This variation is due to the slight dependence between the TAI L and RS, as well as the additional terms that appear in

Eq.(4.8) due to RS. The eﬀect of Vf on S21 can be explained by the variation in the TAI series resistance, i.e. Re(Zin,T AI ). Using the results of chapter 3, one can show that the TAI series resistance Re(Zin,T AI ) = ωL/Q is directly proportional to the function f(RS), which was plotted in Fig. 3.2. Hence, as Vf increases, the feedback resistance

Rf decreases, resulting in an increase in the series resistance of the TAI equivalent circuit, RS. This will lead to a decrease in Re(Zin), until f(RS) reaches its minimum value. After that, Re(Zin) will start to increase. This is the reason behind the decrease of S21 in Fig. 4.9 after it reaches the maximum loss compensation point.

Linearity Measurements

To characterize the linearity of the high-pass phase shifter, the 1-dB compression point for an input signal at 4GHz is measured. As shown by Fig(4.10), the high-pass phase shifter achieves a 1-dB input compression point of -2.2dBm, which corresponds to an input signal swing of 0.55Vpp, while operating from a 1.5V supply. The inter-modulation 4.2. HIGH-PASS PHASE SHIFTER 95

−10

−20

Output power at 4GHz (dBm) −30

−40 −40 −30 −20 −10 0 10 20 Input power at 4GHz (dBm) Figure 4.10: Amplitude of the output power versus the input power when applying a single 4GHz RF signal source

−50

Output power (dBm) −100 Output power at f 1 Output power at 2f −f 1 2

−150 −40 −30 −20 −10 0 10 20 Input power (dBm)

Figure 4.11: Amplitude of the output power at f1 and 2f1 − f2 versus the input power when combining two RF signal sources 4.3. TL PRI/NRI PHASE SHIFTER 96

Table 4.1: Summary of The High-Pass Phase Shifter Performance. Parameter Value Design frequency 4GHz Technology 0.13µm CMOS Phase shift 14o ⇒110.5o=96.5o Insertion loss 1.3dB to 2.7dB FOMa 48.2o/dB Size 0.25mm×0.25mm No. of unit-cells 1 S11 -18dB Bandwidthb 0.25GHz Fractional BW 6.25% Max. bias volt. 3.6V 1-dB comp. -2.2dBm IIP3 +7.4dBn aFigure of merit [85]: FOM = | ∆φ |. min|S21|dB b Bandwidth measurement criterion: S11 < −10dB. distortion components are also evaluated to fully characterize the linearity of the phase shifter. Two signals the ﬁrst at f1=4GHz and the second at f2 = f1-10MHz are obtained from two RF signal generators and combined together using an RF signal combiner. This frequency spacing is chosen to guarantee that the two input signals are treated as in-band signals. The combined signal is then applied to the phase shifter, and the inter-modulation products are measured at the output using a spectrum analyzer.

Figure 4.11 shows the output power at f1 and 2f1 − f2 versus the input power. The phase shifter achieves an input third-order intercept point (IIP3) of +7.4dBm. To summarize, the measured performance of the TAI-based high-pass shifter is presented in Table 4.1. The high-pass design achieves a ﬁgure of merit, FOM, of 48.2o/dB, which is deﬁned as the phase tuning range per dB of insertion loss [85].

4.3 TL PRI/NRI Phase Shifter

This section presents an electronically tunable TL PRI/NRI metamaterial phase shifter, which is capable of achieving both positive and negative phase shifts. To the author’s knowledge, this is considered the ﬁrst published attempt to design an electronically tunable TL PRI/NRI metamaterial phase shifter that has a phase response centered 4.3. TL PRI/NRI PHASE SHIFTER 97

C TL TL C

d/2 L d/2

Figure 4.12: TL PRI/NRI metamaterial phase shifter unit-cell.

around the 0o, and at the same time has a low return loss across its entire phase tuning range. The proposed phase shifter uses the same architecture of the TL PRI/NRI phase shifter presented in [5]. However, electronic tunability and matching are simultaneously achieved by replacing the ﬁxed series capacitors with varactors and the ﬁxed shunt inductor with a TAI.

4.3.1 Analysis

Figure 4.12 shows the unit-cell of the TL PRI/NRI phase shifter [5]. It is composed of a p regular microstrip TL, with a characteristic impedance Zo = Lo/Co, where Lo and Co are the TL inductance and capacitance per unit-length, respectively. The microstrip TL is loaded with two series capacitors, C, and a shunt inductor, L. Cascading the PRI TL with the NRI section compensates the phase shift incurred by the propagating signal. The phase shifter unit-cell is analyzed herein using periodic analysis for terminated periodic structures. This technique can be applied to a finite number of unit-cells when terminated with the corresponding Bloch impedance [24]. Using this technique simplifies the analysis and offers good design insight. One can show that the insertion phase, φ, of the unit-cell is given by [3,5]: µ ¶ µ ¶ 1 1 Zo 1 cos φ = cos 2θTL 1 − 2 + sin 2θTL + − 2 , (4.10) 2ω CL ωCZo 2ωL 2ω CL

where θ is the phase lag due to one section of the PRI microstrip TL, given by TL √ θTL = βTLd/2 = ω LoCod/2. By equating the phase shift, φ, to zero, one can ﬁnd the zero-phase frequencies of the periodic structure. The full analysis of the TL PRI/NRI unit-cell can be found in [3, 5], therefore only the important results are pointed-out here. In summary, this analysis reveals that the underlying periodic structure exhibits 4.3. TL PRI/NRI PHASE SHIFTER 98

√ a stop-band centered around the zero-phase frequency, ωo = 1/ LCod, over which the input signal is attenuated. In order to close this stop-band, the following condition has to be satisﬁed: r r Lo 2L Zo = = . (4.11) Co C

Interestingly, satisfying the stop-band closure condition of Eq.(4.11) insures that

the TL phase shifter is perfectly matched at the zero-phase frequency, ω = ωo. This becomes evident by deriving the expression of the phase shifter reﬂection coeﬃcient,

S11. If a unit-cell of the TL phase shifter is terminated with an impedance Zo, one can show that, at the zero-phase frequency, the reﬂection coeﬃcient is expressed as:

2L L − o C C S (ω = ω ) = o√ . (4.12) 11 o 2L L LL − o + 2j √ o C Co Co d

When the condition of Eq.(4.11) is satisﬁed, the two terms in the numerator of S11 cancel-out, which results in perfect matching at the zero-phase frequency. However, when the component values (L and C) are varied to tune the phase shift, the location √ of the zero-phase frequency, ωo = 1/ LCod, changes. Hence the frequency at which the phase shifter is matched changes. Nevertheless, the TL phase shifter still achieves a low return loss across a wide range of frequencies as long as the stop-band closure condition of Eq.(4.11) is satisﬁed. This is mainly due to the nature of the PRI TL sections, which determines the characteristic impedance of the loaded TLs.

Under the stop-band closure condition, the phase shift can be approximated as: √ 2 φ ≈ √ − 2θT L. (4.13) ω LC

Equation (4.13), which was originally derived in [5], indicates that positive and negative phase shifts can be realized by a single unit-cell without having to go through a complete phase rotation as in a traditional high-pass or low-pass architecture. Furthermore, the phase can be tuned by simultaneously changing the values of both loading elements;

L and C. If L and C are varied from their nominal value to rL × L and rC × C, the 4.3. TL PRI/NRI PHASE SHIFTER 99

C C VAR TL TL VAR

d/2 d/2 TAI gm1 Z in Rf

-gm2 Gyrator-C C Packaged active inductor TAI chip

Figure 4.13: TL PRI/NRI metamaterial phase shifter unit-cell. phase tuning range can be expressed as: µ ¶ √ 1 2 |∆φ| = 1 − √ × √ . (4.14) rLrC ω LC

Similar to the high-pass phase shifter, varying both L and C results in increasing the

phase tuning range compared to varying C only. Furthermore, setting rL = rC will maintain the matching condition of Eq.(4.11) and will result in a low return loss across the entire phase tuning range.

4.3.2 Design and Physical Implementation

The TAI circuit described in chapter 3 is packaged using a 4mm×4mm high-speed QFN (Quad Flat-Package No Lead) package to minimize the parasitics associated with the package, and the packaged chip is used to implement the TL PRI/NRI phase shifter. Figure 4.13 shows the unit-cell of the proposed tunable TL phase shifter. The series capacitors, C, are replaced by discrete varactors, where the reverse voltage across the varactors controls their capacitance. The PRI TL sections are implemented using printed microstrip lines on a low-loss 10mil Rogers RT/duroid 5880 substrate. To design the TL PRI/NRI metamaterial phase shifter both circuit and electromagnetic simulations had to be carried out. This was necessary to choose the appropriate varactor capacitance tuning range and the properties of the printed TL structure. A detailed explanation of the method used to simulate and consequently design the TL PRI/NRI 4.3. TL PRI/NRI PHASE SHIFTER 100

10.8mm

Varactors

RFin RFout

10.4mm

DC bias/control lines Active inductor chip

Figure 4.14: Photograph of the tunable PRI/NRI phase shifter unit-cell. metamaterial phase shifter is presented in Fig. B-1 in Appendix B. A picture of the TL phase shifter is given in Fig. 4.14, the bias and control lines going to the TAI chip are supplied from the lower side of the board, whereas the right and left connectors are the input and output ports of the phase shifter, which also supply the bias voltages to the series varactors. A low substrate permittivity, ²r, of 2.2 was chosen to reduce the phase shift incurred by the signal, hence making the phase shifter more wide-band. The varactors used are 1.7mm×0.9mm plastic packaged silicon hyper-abrupt junction varactor diodes from Skyworks, Irvine, CA (SMV1232). The TL phase shifter unit-cell size is 10.8mm×10.4mm; the TL and series varactors occupy 10.8mm×1mm, while the chip and the bias lines roughly occupy 10.8mm×9.4mm. The unit-cell width is mainly set by the MMIC inductor package, which can be easily reduced by more than 22% by using a smaller package size (3mm×3mm). The smaller package was not used here, since the chip contained other test circuits that needed to be packaged.

4.3.3 Experimental Results

Figure 4.15 shows the measured and theoretical phase responses when both the TAI inductance and varactor capacitance are varied. The theoretical response is predicted using the exact phase expression of Eq.(4.10). The ﬁgure shows good agreement between the measurements and theory. Using the approximate expression of Eq.(4.13) 4.3. TL PRI/NRI PHASE SHIFTER 101

Measurements Theory 100 φ tuning range at 2.5GHz = −40o to +34o

(deg) 50 φ ↓ V = 0V → 4.2V var

Insertion phase −50 ↑

−100 1.5 2 2.5 3 3.5 Frequency (GHz) Figure 4.15: The measured and theoretical phase responses vs. freq. for different bias conditions. The phase expression of Eq.(4.10) is used for the comparison. results in an error of less than 6.5o, hence Eq.(4.13) can still serve as a good starting point for initial hand calculations, and at the same time, it gives good design insight. The good agreement between the theoretical and experimental results is achieved by extracting the values of the different circuit components using accurate simulations (electromagnetic/circuit simulations). The component values obtained are then used to predict the phase response based on the theoretical equations. At the design frequency of 2.5GHz, the phase can be varied from -40o to +34o passing through the zero-phase point. The phase shifter unit-cell is capable of achieving both positive and negative phase shifts at the design frequency without going through an entire 360o rotation, which requires an 88mm microstrip TL. This corresponds to a 73% area saving compared to meandering the microstrip TL. Furthermore, over the entire phase tuning range the matching condition is satisfied, and S11 is maintained below -19dB at the design frequency, as shown in Fig. 4.16. As the varactors’ reverse bias voltage, Vvar, increases, their capacitance decreases, and the TAI’s L has to decrease to satisfy Eq.(4.11). When Vvar approaches 4.2V, the matching condition is increasingly difficult to satisfy, since the package adds a fixed inductance to the TAI inductance, thereby setting a minimum achievable L. Nevertheless, the phase shifter achieves a bandwidth of 2.6GHz over which S11 is less than -10dB (see Fig. 4.16). The measured

S21 is presented in Fig. 4.17, the insertion loss is set by the varactor losses and the 4.3. TL PRI/NRI PHASE SHIFTER 102

−5 S < −10dB over a 11 (dB) bandwidth of 2.6GHz 11 −10 ← → S

−15

−20

−25 Worst case S at 11 −30 → 2.5GHz = −19dB V = 3.9V & 4.2V var

Input reflection coefficient −35

−40 1.5 2 2.5 3 3.5 4 4.5 5 Frequency (GHz)

Figure 4.16: Measured S11 vs. freq. for diﬀerent bias conditions.

0 ↓ ↑ −5 (dB)

21 S at 2.5GHz varies S −10 21 from −0.55dB → −1.1dB

−15

−20 Insertion loss

−25

−30 1 2 3 4 5 6 Frequency (GHz)

Figure 4.17: Measured S21 vs. freq. for diﬀerent bias conditions. 4.4. MMIC PRI/NRI PHASE SHIFTER 103

Table 4.2: Summary of the TL PRI/NRI Phase Shifter Performance. Parameter Value Design frequency 2.5GHz Technology 0.13µm CMOS/microstrip Phase shift -40o ⇒+34o=64o Insertion loss 0.5dB to 1.1dB FOM 128o/dB Size 10.8mm×10.4mm No. of unit-cells 1 S11 -19dB Bandwidth 2.6GHz Fractional BW > 100% Max. bias volt. 4.2V Av. power diss. [email protected] Av. Sim. NF 7.6dB

TAI Q. The insertion loss at 2.5GHz varies from 0.55dB to 1.1dB over the entire phase tuning range. Across the entire 2.6GHz bandwidth, the insertion loss varies from 0.25dB to 4.6dB. The TL phase shifter dissipates an average DC current of approximately 32.9mA from a 1.5V supply which corresponds to 49.4mW across the entire phase tuning range. This power is required to bias the TAI circuit in order to generate the required inductance. The average noise ﬁgure of the TL phase shifter is predicted from simulations to change from 6.1dB to 9.3dB at 2.5GHz across the phase tuning range with an average value of 7.6dB. From simulations, the main noise contributor to the phase shifter’s noise ﬁgure is the TAI circuit. The performance of the TL PRI/NRI phase shifter is summarized in Table 4.2.

4.4 MMIC PRI/NRI Phase Shifter

To reduce the size of the TL PRI/NRI phase shifter unit-cell, it is desirable to get rid of the TL sections. The TL sections are important to compensate the phase incurred by the signal due to the NRI loading elements. By replacing each TL with a lumped- element L-C section and carefully selecting the values of the series inductance and shunt capacitance, a similar phase response can be achieved while occupying a much smaller area. This implementation will eliminate the need for bulky microstrip TLs and will allow integrating the entire PRI/NRI phase shifter onto a single MMIC. To 4.4. MMIC PRI/NRI PHASE SHIFTER 104

C Lo Lo C

Co Co L Co Co

Figure 4.18: Proposed IC PRI/NRI metamaterial phase shifter unit-cell.

the author’s knowledge, this work is considered the ﬁrst published attempt to design a fully-integrated tunable PRI/NRI phase shifter. The proposed MMIC PRI/NRI phase shifter unit-cell is shown in Fig. 4.18. The

microstrip TL sections are replaced with a low-pass Π section Lo-Co. The resulting lumped-element phase shifter can admittedly be thought of as a band-pass filter, created by cascading low-pass and high-pass sections. However, here we are mainly interested in its phase response, as opposed to conventional band-pass filters which are mainly used for their magnitude response. Moreover, the corresponding structure should be thought of as being a periodic one and having the unit-cell of Fig. 4.18. This is also unlike bandpass filters which typically are non-periodic. The architecture of the proposed lumped- element PRI/NRI phase shifter is similar to that presented in [3] to model a TL, which was loaded with discrete series capacitors and shunt inductors for the sake of analyzing it. However, a complete Π section with two shunt capacitors and a series inductor is used here to synthesize the TL sections. This creates two zeros in the reflection

coefficient transfer function, S11, resulting in two frequencies at which the phase shifter is perfectly matched. This extends the MMIC phase shifter bandwidth as opposed to a lumped-element phase shifter based on the unit-cell presented in [3]. Furthermore, this topology makes the phase shifter more suitable for implementation in IC form, since the discrete components are replaced with on-chip components fabricated on a silicon substrate. More specifically, the explanation lies with the implementation of the series capacitors C, which will be replaced with MOS capacitors, as will be described later in section 4.4.2. The series MOS capacitors are associated with large parasitic gate and drain/source diffusion capacitance to the substrate. Therefore, these parasitic

capacitors can be naturally lumped with the shunt capacitor Co, and accounted for as a contributor to the phase of the PRI section. Similarly, the eﬀect of the parasitic 4.4. MMIC PRI/NRI PHASE SHIFTER 105

capacitance associated with the series inductors can also be lumped within the shunt capacitors Co. This makes the proposed unit-cell in Fig. 4.18 well suited for the MMIC phase shifter implementation.

4.4.1 Analysis

Using periodic analysis one can show that the phase shift of the MMIC PRI/NRI phase shifter unit-cell is expressed as: µ ¶ µ ¶ C 6C L L C cos φ = 2ω4L2C2 1 + o − ω2L C 4 + o + o + o o o o C o o C L LC µ ¶ 4C L 2L C 1 + 1 + o + o + o o − . (4.15) C L LC ω2LC

A simpler and more intuitive expression for the phase shift can be obtained by assuming that the signal incurs a small phase shift φ, hence cos φ ≈ 1 − φ2/2. This is used to simplify Eq.(4.15) resulting in the following expression: √ p p 2 2 2 4 2 φ ≈ √ (1 − ω Lo(C + Co)) × (1 − ω Co(Lo + 4L) + 2ω C LLo). (4.16) ω LC o

By equating the phase shift φ to zero, one can ﬁnd the zero-phase frequencies: s 1 ωo1 = , and Lo(C + Co) s p 2 2 Lo + 4L ± Lo + 16L ωo2,3 = . (4.17) 4CoLLo

Furthermore, Eq.(4.16) reveals that there is a range of frequencies over which the phase is imaginary. This indicates that the underlying periodic structure exhibits a stop-band, over which the input signal is attenuated. Figure 4.19 shows the dispersion diagram of the periodic structure, where the component values are picked in such a way to show the stop-band. In order to close the stop-band centered around the 0o mark, the two zero-phase frequencies, ωo1 and the lower frequency of ωo2,3 should coincide,

i.e. ωo1 = ωo2. This is similar to the method adopted in [3] for the TL-based structure. 4.4. MMIC PRI/NRI PHASE SHIFTER 106

5 L=3nH 4.5 C=2.4pF L =1.7nH o 4 C =0.18pF pass−band o ω 3.5 o2 (GHz) 3 periodic structure stop−band 2.5 Frequency ω 2 o1 pass−band 1.5

1 −150 −100 −50 0 50 100 150 Phase (deg) Figure 4.19: Dispersion diagram of the periodic structure composed of the proposed MMIC PRI/NRI phase shifter unit-cells.

This results in the following stop-band closure condition:

2L L (C + C ) 2L L = o o ⇒ ≈ o . (4.18) C Co(Co + 2C) C 2Co

This approximation is based on the assumption that the shunt capacitor Co is smaller than the series loading capacitor C, which will ensure that the cut-off frequency of the low-pass section is higher than the cut-off frequency of the high-pass section. This stop- band closure condition is similar to the condition obtained for the TL implementation (Eq.(4.11)), since a TL section with a characteristic impedance Z can be modeled by o p two shunt capacitors, Co, and a series inductor, Lo, given that Zo = Lo/2Co. If the stop-band closure condition of Eq.(4.18) is satisfied, then the phase shift per unit-cell can be re-written as: √ 2 2 φ ≈ √ × (1 − ω Lo(C + Co)) (4.19) ω LC √ 2 √ p ≈ √ − 2 2ω LoCo. (4.20) ω LC 4.4. MMIC PRI/NRI PHASE SHIFTER 107

Similar to Eq.(4.13), the phase expression of Eq.(4.20) has two terms. The ﬁrst term results in a phase lead and is caused by the NRI section (high-pass), whereas the second term results in a phase lag and is caused by the PRI section (low-pass). Hence, similar to the TL phase shifter, a zero-degree phase shift can be realized by a single unit-cell without having to go through a complete 360o phase rotation. Furthermore, positive and negative phase shifts can be realized depending on which of the two terms dominate. To center the phase shift around the zero-degree mark, the lumped-element values should be chosen such that the phase contributions of the PRI and NRI sections cancel out.

It is also important to investigate the return loss of the phase shifter unit-cell. When

a unit-cell of the MMIC phase shifter is terminated with an impedance Zo, one can

show that the reﬂection coeﬃcient, S11, at the zero-phase frequency is expressed as:

2L L (C + C ) − o o C Co(Co + 2C) S11(ω = ωo1) = 2 . (4.21) Lo(C + Co) 2L 2L(C + Co) − + j 2 Co(Co + 2C) C C Co(Co + 2C)ωo1Zo

Similar to Eq.(4.12), this indicates that by satisfying the stop-band closure condition of Eq.(4.18), the MMIC phase shifter becomes perfectly matched at the zero-phase

frequency, ω = ωo1. However, when the component values are varied to tune the phase response, the location of the zero-phase frequency changes according to Eq.(4.17). Hence the frequency at which the phase shifter is matched changes. Since it is desired to achieve a wide bandwidth, it is important to investigate the phase shifter matching at frequencies diﬀerent from the zero-phase frequency. One can derive the matching

condition by equating S11 to zero at frequencies diﬀerent from the zero-phase frequency

(ω 6= ωo1). This results in the following matching condition: r (C(2L + L ) + C (4L + L ))ω2 − 1 Z ≈ o o o . (4.22) o ω2C2

Equation (4.22) indicates that the proposed IC phase shifter has a second frequency at which it is perfectly matched. This is a result of an additional zero in the reﬂection coeﬃcient transfer function. Using Eq.(4.22), one can show that this second frequency 4.4. MMIC PRI/NRI PHASE SHIFTER 108

where S11 dips is expressed as:

1 ωm = p . (4.23) Lo(Co + 2C)

Having two frequencies at which S11 dips, ωo1 and ωm, helps extend the bandwidth of the MMIC phase shifter compared to a lumped element phase shifter based on the unit-cell of [3], where S11 dips only at the zero-phase frequency. Also, as indicated by Eq.(4.20), the MMIC implementation allows varying the phase contribution of both the PRI and NRI sections, as opposed to the TL implementation which only allows varying the phase of the NRI section. In the MMIC implementation, the phase of the

NRI section is tuned via L and C, while that of the PRI section is tuned via Co. To demonstrate this, L, C, and Co are varied from their nominal values to become rL × L, rC × C, and rCo × Co respectively. This results in the following phase tuning range: √ µ ¶ 2 1 √ p √ |∆φ| = √ × 1 − √ + 2 2ω LoCo × ( rCo − 1), (4.24) ω LC rLrC where the tuning ratios rL, rC , and rCo should be chosen in order to satisfy the stop- band closure condition of Eq.(4.18) as well as the matching condition of Eq.(4.22). By comparing Eq.(4.14) and Eq.(4.24), one can see that the MMIC phase shifter has an extra term which further extends its phase tuning range compared to the TL phase shifter while still satisfying the matching condition. Furthermore, integrating the phase shifter on a single MMIC eliminates the parasitics associated with the individual component packages, which in turn extends the tuning range even more.

4.4.2 Design and Physical Implementation

The schematic diagram of the MMIC PRI/NRI tunable phase shifter is shown in Fig. 4.20. A 0.13µm CMOS process was chosen to fabricate the phase shifter since the TAI has already been characterized in that process. The same TAI circuit described in chapter 3 is used to implement the phase shifter’s shunt inductor. The series capacitors, C, are implemented using on-chip MOS varactors; each MOS varactor consists of an array of 16 by 15 small MOS varactors with an aspect ratio of 1µm/0.5µm, and can be tuned from 0.38pF to 1.4pF via the gate to drain/source voltage. The gate 4.4. MMIC PRI/NRI PHASE SHIFTER 109

Figure 4.20: Proposed IC PRI/NRI metamaterial phase shifter unit-cell. voltage of the MOS varactors is set by the DC voltage applied at the input and output ports of the phase shifter, VDC . On the other hand, the drain/source voltage is generated by the TAI, and is approximately equal to VCM ≈ 0.6V. The Q of the series MOS varactors has a strong impact on the phase shifter insertion loss, given that its eﬀect can be modeled as a series resistance in the signal path. To achieve the large capacitance value required to make the design frequency 2.6GHz, a larger series capacitance is required. To this end, a ﬁxed 0.67pF on-chip high-Q MIM (Metal-Insulator-Metal) capacitor, CMIM , is connected in parallel with the MOS varactor to achieve the required capacitance without reducing S21. The shunt capacitors of the PRI sections,

Co, are implemented using on-chip hyper-abrupt junction varactors, which provide a wide tuning range. The varactors’ capacitance can be tuned from 90fF to 270fF by changing the varactor cathode voltage, VB, from 3.8V to -0.1V. The varactor anodes are biased by the voltage generated by the TAI. The series inductors of the PRI sections, Lo, are implemented using on-chip 1.7nH spiral inductors with 2.5 turns and an outer diameter of 200µm. The spiral inductors have a low-Q at the design frequency, which will contribute to the insertion loss of the phase shifter. The die micrograph of the MMIC phase shifter is shown in Fig. 4.21, it occupies an area of 550µm×1300µm, from which the core circuit without the pads occupies 380µm×960µm. To the author’s knowledge, this is the smallest tunable PRI/NRI metamaterial phase shifter reported in the literature, that operates in this frequency band. The TAI occupies 150µm×170µm from the overall area, and is located in the 4.4. MMIC PRI/NRI PHASE SHIFTER 110

Series spiral inductors (L ) 960 m o

G G m

S S 550 380

G TAI G m

G Series MIM capacitors DC/bias inputs (CMIM) 1300 m

Figure 4.21: MMIC PRI/NRI metamaterial phase shifter die micrograph. middle section of the layout. The spiral inductors to the left and right of the TAI are the series inductors of the PRI sections, Lo. They occupy a larger area than the TAI, and are surrounded by ground shields to minimize the coupling between them. The series MIM capacitors, CMIM , occupy a very small area, and can be seen in the die micrograph. On the other hand, the series MOS varactors and the shunt varactors are not visible in the die micrograph because they are covered by the metal ﬁll introduced by the foundry to achieve certain layer densities. The bias and control voltages are provided to the circuit from the bottom pads. Large on-chip de-coupling capacitors are used to stabilize the bias and control voltages by providing a low-impedance path to ground. The right and left pads correspond to the input and output ports of the phase shifter, which also provide the bias voltage to the series MOS varactors.

4.4.3 Experimental Results

The MMIC phase shifter is characterized by probing the dies and measuring the S- parameters. Two GSG probes are used for the RF ports while a multi-contact wedge with 8 DC needles is used to probe the DC pads. Figure 4.22 shows the measured and theoretical phase responses for diﬀerent bias conditions. The theoretical response is predicted here using the approximate phase expression of Eq.(4.19), which results in 4.4. MMIC PRI/NRI PHASE SHIFTER 111

Measurements Theory 150 V & V are swept DC B 100 from −0.3V→2.05V

(deg) → φ & 3.8V 0V, resp. ↓ 50

Insertion phase φ tuning range at ↑ −50 2.6GHz = −35o to +59o

1.5 2 2.5 3 3.5 Frequency (GHz) Figure 4.22: The measured and theoretical phase responses vs. freq. for diﬀerent bias conditions. The phase expression of Eq.(4.19) is used for the comparison.

good matching between the measurements and theory. Unlike the TL phase shifter, the exact phase expression of Eq.(4.15) and the approximate phase expression of Eq.(4.19) yield very accurate results. On the other hand, comparing the measured phase with the approximate phase expression of Eq.(4.20) results in a 12.2o phase error; this is mainly due to the approximations made in the derivation of Eq.(4.20) which utilizes the approximate matching condition of Eq.(4.18). Still Eq.(4.20) can serve as a good starting point for initial hand calculations, and at the same time, it gives good design insight.

To tune the phase shift φ, the series loading capacitance, CMOS, the shunt inductance,

as well as the shunt capacitance, CV AR are varied using VDC , the TAI bias point (Vc1,

Vc2, Vf ), and VB, respectively. The voltage VDC is swept from -0.3V to 2.05V and for each value the appropriate inductance is generated using Vc1 and Vc2 to satisfy the matching condition given by Eq.(4.18). In addition to that, VB is swept from 0.1V to 3.8V to extend the phase tuning range. The phase shift at 2.6GHz can be tuned from -35o to +59o passing through the zero-phase mark, without the need for an entire 360o rotation. This represents a 50% increase in the phase tuning range compared to the TL phase shifter presented in the previous section. As explained in section 4.4.1, this is due to the ability to control the shunt capacitance, CV AR. Furthermore, the MMIC phase shifter eliminates the parasitics associated with the TAI package, which limited 4.4. MMIC PRI/NRI PHASE SHIFTER 112

S < −10dB over a −5 11

(dB) bandwidth of 1.9GHz 11 ← → S −10

−15

−20

−25

Worst case S at −30 11 Input reflection coefficient 2.6GHz = −19dB

−35 1.5 2 2.5 3 3.5 4 4.5 Frequency (GHz)

Figure 4.23: Measured S11 vs. freq. for diﬀerent bias conditions.

0 S at 2.6GHz varies 21 → ↓ from −2.8dB −3.8dB

↑

(dB) −5 21 S

S (2.6GHz)=−3.8dB 21 for the case V =0V −10 B & V =2.05V Insertion loss DC

−15 1 1.5 2 2.5 3 3.5 4 4.5 Frequency (GHz)

Figure 4.24: Measured S21 vs. freq. for diﬀerent bias conditions. 4.4. MMIC PRI/NRI PHASE SHIFTER 113

Maximum loss −3.2 compensation |∆φ|≈7.4o 14 −3.3 12 −3.4 ← 10 −3.5 →

at 2.6GHz (dB) 2.6GHz at 8

21 −3.6 at 2.6GHz (deg) 2.6GHz at S φ −3.7 6

−3.8 4

2 Phase shift

Insertion loss −3.9 |∆φ|≈5.1o −4 0 1 1.1 1.2 1.3 1.4 1.5 Feedback voltage V (V) f

Figure 4.25: Measured S21 and phase shift φ at 2.6GHz versus the TAI feedback voltage Vf . the inductance tuning range in the TL phase shifter. Figure 4.23 shows the measured input reﬂection coeﬃcient S11, for the same bias conditions used to sweep the phase.

The worst case S11 at the design frequency is -19dB. The phase shifter has a bandwidth of 1.9GHz across which S11 is less than -10dB. The MMIC phase shifter has a smaller bandwidth compared to the TL phase shifter, which is expected, and is mainly due to the frequency dependent nature of the matching condition of Eq.(4.22).

Figure 4.24 shows the measured insertion loss S21 for the same bias points. As indicated by the figure, S21 varies from -2.8dB to -3.8dB at the design frequency. Across the entire phase shifter bandwidth, i.e. the 1.9GHz, the insertion loss varies from 2.8dB to a worst case of 7.2dB. The phase shifter insertion loss is mainly due to the losses associated with the spiral inductors and the series MOS varactors. It is also important to note that, as the shunt capacitance increases, the cut-off frequency of the PRI section decreases, which increases the phase shifter insertion loss. Hence, as indicated by Fig. 4.24, the worst case S21 results when VDC and VB are set to 2.05V and 0V respectively. To demonstrate the effect of the negative resistance generated by the TAI circuit on the phase shifter performance, the amount of negative resistance RS is varied by 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 114

Table 4.3: Summary of the TAI-Based MMIC PRI/NRI Phase Shifter Performance. Parameter Value Design frequency 2.6GHz Technology 0.13µm CMOS Phase shift -35o ⇒+59o=96o Insertion loss 2.8dB to 3.8dB FOM 34o/dB Size 0.38mm×0.96mm No. of unit-cells 1 S11 -19dB Bandwidth 1.9GHz Fractional BW 73% Max. bias volt. 3.3V Av. power diss. [email protected] Av. Sim. NF 10.3dB

sweeping the feedback voltage, Vf , of the TAI, and the measured S21 is plotted in Fig. 4.25. The plot shows that, at 2.6GHz, the phase shifter insertion loss can be enhanced by 0.8dB with less than 7.4o phase variation, which corresponds to a change of 7.8% of the phase tuning range.

The MMIC phase shifter dissipates an average DC current of 21mA from a 1.5V supply which corresponds to 31.5mW across the entire phase tuning range. This power is required to bias the TAI circuit in order to generate the required inductance. The MMIC PRI/NRI phase shifter has a lower average DC power consumption compared to the TL-based design, which consumes 49.4mW. The higher average power consumption of the TL-based design is mainly due to the parasitic package inductance, which adds a ﬁxed series inductance to the TAI. Hence, in order to satisfy the matching condition, lower inductance values are required by the TAI in the TL-based design, which in turn requires higher bias currents for the TAI circuit. The noise ﬁgure of the MMIC phase shifter is predicted from simulations to change from 8.4dB to 12.8dB at 2.6GHz across the phase tuning range, with an average value of 10.3dB. Similar to the TL phase shifter, the main noise contributor is the TAI circuit. The performance of the MMIC PRI/NRI phase shifter is summarized in Table 4.3. 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 115

C Lo Lo C

Co Co Cv L Co Co

Figure 4.26: Unit cell of the proposed MMIC PRI/NRI tunable phase shifter.

4.5 Passive MMIC PRI/NRI Phase Shifter

This section presents another compact tunable MMIC PRI/NRI phase shifter. The phase shifter is based on a similar L-C topology to that of the TAI-based MMIC PRI/NRI phase shifter presented in the previous section. However, this design is passive and does not use TAIs to tune the shunt inductance. Alternatively, it uses a variable capacitor connected in parallel with a shunt spiral inductor as shown in Fig. 4.26. The resulting topology still exhibits phase compensation properties which allows it to center its phase response around the zero-degree mark while having a small group delay. The series and shunt varactors are used to tune the phase and at the same time maintain the matching, which allows the phase shifter to achieve a low return loss across its entire phase tuning range. Compared to the TAI-based designs presented by the previous sections, this design does not consume any DC power and at the same time it eliminates the noise and non-linearity contributions of the TAI circuit.

4.5.1 Analysis

The passive MMIC PRI/NRI phase shifter consists of two lumped-element PRI sections that replace the TLs in order to generate the low-pass response, which is required to achieve the phase compensation. On the other hand, the high-pass response is achieved via the series loading capacitors, C, and the shunt loading inductor, L. To eliminate the active circuits used in the previous designs in order to tune the shunt inductance L, a variable capacitor, Cv, is added in parallel with a shunt spiral inductor to tune its eﬀective inductance. The eﬀect of adding this shunt capacitor on the phase response, the tuning range, and the matching are explained in this section. Similar to the previous designs, the passive MMIC PRI/NRI phase shifter unit-cell of Fig. 4.26 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 116

is analyzed using the periodic analysis [24]. One can show that the phase shift per unit-cell is expressed as: µ ¶ C C C cos φ = 2ω4L2C2 1 + o + v + v o o C 2C 2C µ o ¶ 6C L L C C 2C − ω2L C 4 + o + o + o o + v + v o o C L LC C C µ ¶ o o 4C L 2L C C 1 + 1 + o + o + o o + v − . (4.25) C L LC C ω2LC

A simpler and more intuitive expression for the phase shift can be obtained, by assuming that the signal incurs a small phase shift, φ, hence cos φ ≈ 1 − φ2/2. This is used to substitute in Eq.(4.25), resulting in the following expression: √ p 2 2 φ ≈ √ 1 − ω Lo(C + Co) (4.26) ω LC s µ ¶ C × 1 − ω2(C (L + 4L) + C L) + 2ω4C LL C + v . o o v o o o 2

By equating the phase shift, φ, to zero, one can ﬁnd the zero-phase frequencies:

1 ωo1 = p , and (4.27) Lo(C + Co) q p 2 2 LCv + 4LCo + LoCo ± (LCv − LoCo) + 8L Co(Cv + 2Co) ωo2,3 = p . (4.28) 2LLoCo(2Co + Cv)

Furthermore, Eq.(4.26) reveals that there is a range of frequencies over which the phase is imaginary. This indicates that the underlying periodic structure exhibits a stop-band, over which the input signal is attenuated. Figure 4.27 shows the dispersion diagram of the periodic structure, where the component values are picked in such a way to show the stop-band. In order to close the stop-band centered around the 0o mark, the two zero-phase frequencies, ωo1 and the lower frequency of ωo2,3 should coincide, 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 117

5 L=2.7nH C=1.5pF 4.5 L =1.5nH o C =0.17pF 4 o pass−band C =1.3pF v 3.5 ω o2 (GHz) 3 periodic structure 2.5 stop−band Frequency ω 2 o1 pass−band 1.5

1 −150 −100 −50 0 50 100 150 Phase (deg) Figure 4.27: Dispersion diagram of the periodic structure composed of the proposed passive PRI/NRI MMIC unit-cells.

i.e. ωo1 = ωo2. This results in the following stop-band closure condition:

2L L (C + C ) 2L L = o o ⇒ ≈ o . (4.29) C Co(Co + 2C) + CvC/2 C 2Co + Cv/2

This approximation is based on the assumption that the shunt capacitor Co is smaller than the series loading capacitor C, which will guarantee that the cut-oﬀ frequency of the PRI (low-pass) section is higher than the cut-oﬀ frequency of the NRI (high-pass) section. Based on the stop-band closure condition of Eq.(4.29), the phase shift per unit-cell can be re-written as: √ 2 √ p φ ≈ √ − 2ω Lo(4Co + Cv). (4.30) ω LC

The phase expression of Eq.(4.30) has two terms. The ﬁrst term results in a phase lead and is caused by the NRI section, while the second term results in a phase lag and is caused by the PRI section, and the additional shunt capacitor, Cv. Hence similar to the previous two designs, a 0o phase shift can be realized by a single unit-cell without having to go through a complete 360o phase rotation. Furthermore, positive and negative phase 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 118

shifts can be realized depending on which of the two terms dominate. Hence to center the phase shift around the 0o mark, the lumped component values should be chosen such that the two terms in Eq.(4.30) cancel out. It is also important to investigate the return loss of the phase shifter unit-cell. When a unit-cell of the proposed passive MMIC PRI/NRI phase shifter is terminated with

an impedance Zo, one can show that the reﬂection coeﬃcient, S11, at the zero-phase

frequency, ωo1, is expressed as:

2L L (C + C ) − o o C Co(Co + 2C) + CCv/2 S11(ω = ωo1) = 2 . Lo(C + Co) 2L 4L(C + Co) − + j 2 Co(Co + 2C) + CCv/2 C C (2Co(Co + 2C) + CCv)ωo1Zo (4.31)

This indicates that, by satisfying the stop-band closure condition of Eq.(4.29) the MMIC phase shifter becomes perfectly matched at the zero-phase frequency. But when the component values are varied to tune the phase shift, the location of the zero-phase frequency changes. Since it is desired to achieve a wide bandwidth, it is important to investigate the phase shifter matching at frequencies diﬀerent from the

zero-phase frequency. One can derive the matching condition by equating S11 to zero

at frequencies diﬀerent from the zero-phase frequency (ω 6= ωo1). This results in the following matching condition: r (C(2L + L ) + C (4L + L ) + LC )ω2 − 1 Z ≈ o o o v . (4.32) o ω2C2

Similar to the TAI-based design, Eq.(4.32) indicates that the passive MMIC phase shifter has a second frequency at which it is perfectly matched. This is a result of an additional zero in the reﬂection coeﬃcient transfer function. Using Eq.(4.32), one can

show that the second frequency where S11 dips is expressed as:

1 ωm = p . (4.33) Lo(Co + 2C)

Re-analyzing the PRI/NRI phase shifter unit-cell without the shunt capacitor, Co, in-

dicates that Co is the reason behind the additional zero that appears in the S11 transfer 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 119

CMIM CMIM

Lo Lo

C C MOS L MOS Co Co Cv Co Co

V B1 VB2

Figure 4.28: Proposed passive MMIC PRI/NRI phase shifter circuit implementation.

function. Having two frequencies at which S11 dips, ωo1 and ωm, helps extending the bandwidth of the MMIC phase shifter compared to a lumped-element phase shifter

based on the unit-cell of [3], where S11 dips only at the zero-phase frequency.

Similar to the TAI-based design, this phase shifter allows varying both terms of the

phase expression of Eq.(4.30). If C, Co, and Cv are varied from their nominal values

to become rC × C, rCo × Co, and rCv × Cv, respectively, this results in the following phase tuning range: √ µ ¶ 2 1 √ p ³p p ´ |∆φ| = √ × 1 − √ + 2 2ω Lo × 4CorCo + CvrCv − 4Co + Cv , ω LC rC (4.34) where the varactor tuning ratios rC , rCo, and rCv should be chosen in order to satisfy the stop-band closure condition of Eq.(4.29), and the matching condition of Eq.(4.32).

The eﬀect of varying Cv can be seen from the second term of Eq.(4.34), which helps extend the phase tuning range of the phase shifter although it does not use any active circuits to tune the shunt inductance. Furthermore, integrating the entire phase shifter on a single MMIC eliminates the parasitics associated with the individual component packages, which in turn increases its tuning range even more as opposed to TL-based design. 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 120

4.5.2 Design and Physical Implementation

The schematic diagram of the passive fully-integrated PRI/NRI tunable phase shifter is shown in Fig. 4.28. Since there is no need for any printed or oﬀ-chip components, the phase shifter was implemented using a single MMIC. The series capacitors, C, are implemented using on-chip MOS varactors, each MOS varactor consists of an array of 10 by 10 small MOS varactors with an aspect ratio of 2.3µm/0.5µm, and can be tuned

from 0.32pF to 1.26pF. The MOS capacitance, CMOS, is set via the gate voltage. The gate voltage of the MOS capacitors is set by the DC voltage applied at the input and

output ports of the phase shifter, VDC . The Q of the MOS varactors has a strong impact on the phase shifter insertion loss, given that its eﬀect can be modeled as a series resistance in the signal path. To achieve the large capacitance value required to make the design frequency, fo, 2.6GHz, a larger series capacitor is required. To this end, a ﬁxed 0.96pF on-chip high-Q MIM capacitor, CMIM , is connected in parallel

to achieve the required capacitance without reducing S21. The shunt capacitors of

the PRI sections, Co, are implemented using on-chip hyper-abrupt junction varactors, which provide a wide tuning range. The varactor capacitance can be tuned from 250fF

to 80fF by changing the varactor cathode voltage, VB1, from 0V to 3.3V. The series

inductors of the PRI sections, Lo, are implemented using on-chip 1.6nH spiral inductors with 3.25 turns and an outer diameter of 200µm. However, the spiral inductors have a low-Q at the design frequency, which will have a direct eﬀect on the phase shifter insertion loss. The shunt inductor, L, is implemented using a 1.1nH spiral inductor with

2.5 turns and an outer diameter of 240µm, while the shunt varactor, Cv, is implemented

using a hyper-abrupt junction varactor. The varactor capacitance Cv is controlled via

its cathode voltage, VB2, and can be tuned from 0.54pF to 1.6pF. The passive MMIC PRI/NRI phase shifter was fabricated in a standard 0.13µm CMOS process, and the die micrograph is shown in Fig. 4.29. The phase shifter occupies an area of 700µm × 1300µm. This is a very small area for a tunable PRI/NRI metamaterial phase shifter operating in this frequency band. The spiral inductor located in the middle section of the layout in Fig. 4.29 is the shunt inductor, L. Whereas,

the two spiral inductors to the left and right are the series inductors, Lo, of the PRI sections. Each inductor is surrounded by a ground shield to minimize the coupling. The bias and control voltages are provided to the circuit from the bottom pads. Whereas, 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 121

Shunt spiral Series spiral inductor (L) inductors (Lo) 1100 m

G G m

S S 700 380 m G G

G Series MIM capacitors DC/bias inputs (CMIM) 1300 m

Figure 4.29: Phase MMIC PRI/NRI shifter die micrograph

the right and left pads correspond to the input and output ports of the phase shifter, which also provide the bias voltage to the series MOS varactors.

4.5.3 Experimental Results

The passive MMIC PRI/NRI phase shifter was characterized by probing the dies and measuring the S-parameters. Figure 4.30 shows the measured insertion phase, φ, for diﬀerent bias conditions. To tune φ, the series capacitor C, the shunt capacitors Co,

and Cv are varied using the input/output port DC voltage, VDC , and the bias voltages

VB1 and VB2, respectively. VB1 and VB2 are swept from 0V to 3.3V, and for each bias condition the necessary series capacitance, CMOS is set through the bias voltage VDC in order to satisfy the matching condition of Eq.(4.32). This will guarantee a low return loss across the entire phase tuning range. The phase passes through the 0o mark at the design frequency, 2.6GHz, and is tunable from -25.5o to +27o, which corresponds to a o 51.5 per stage. Figure 4.31 shows both the measured input reﬂection coeﬃcient S11

and the measured insertion loss, S21, for the same bias conditions used to sweep the 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 122

120

100 φ tuning range at 80 2.6GHz = −25.5o to 27o 60

(deg) V & V are swept 40 DC B1,2 φ ↓ from −0.6V→1.5V 20 and 3.3V→0V 0

−20 ↑ −40 Insertion phase −60

−80

−100 1.5 2 2.5 3 3.5 Frequency (GHz)

Figure 4.30: Measured phase vs. freq., for diﬀerent bias conditions

S at 2.6GHz varies 0 21 from −4.9dB→ −5.1dB ↓ −5 (dB) ↑ BW=2GHz −10 ← →

−15

−20

−25

Insertion & Reflection loss Worst case S at −30 11 2.6GHz = −21dB

−35 1 1.5 2 2.5 3 3.5 4 4.5 5 Frequency (GHz)

Figure 4.31: Measured S11 and S21 vs. freq., for diﬀerent bias conditions 4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER 123

−4.6 20 (dB) (deg) 21 φ −4.8 10 S →

0 −5

−10 ← −5.2 Insertion loss at 2.6GHz Insertion phase at 2.6GHz −20 −5.4

−30 0 0.5 1 1.5 2 2.5 3 Varactor reverse bias voltage V (V) B1

Figure 4.32: Measured phase and S21 at 2.6GHz vs. the varactor reverse bias voltage VB1

phase. The worst case S11 at the design frequency is -21dB, and the phase shifter has a very wide bandwidth of 2GHz, across which S11 is less than -10dB. This corresponds to a fractional bandwidth of more than 76%. The wide bandwidth achieved is due to

the additional zero in the S11 transfer function, described in section 4.5.1. In practice,

the losses associated with the structure combines the two S11 dips into one wider dip,

resulting in a wide bandwidth. The insertion loss, S21, varies from -4.9dB to -5.1dB at the design frequency. The relatively large insertion loss is mainly due to the series MOS varactors’ low-Q, as well as the losses associated with the spiral inductors. It is worth mentioning that, using this topology to design phase shifters at higher frequencies will require smaller capacitors and inductors, which can be realized on-chip with higher Q values, hence resulting in lower insertion loss.

The tuning characteristics of the phase shifter are presented in Fig. 4.32, where the measured phase and insertion loss at 2.6GHz are plotted versus the shunt varactor

reverse bias voltage, VB1. The phase shifter has a very small insertion loss variation of 0.2dB across the entire tuning range. Table 4.4 summarizes the performance of the passive MMIC PRI/NRI phase shifter. 4.6. DISCUSSION AND COMPARISON 124

Table 4.4: Summary of the Passive MMIC PRI/NRI Phase Shifter Performance. Parameter Value Design frequency 2.6GHz Technology 0.13µm CMOS Phase shift -25.5o ⇒+27o=51.5o Insertion loss 4.9dB to 5.1dB FOM 10.5o/dB Size 0.7mm×1.3mm No. of unit-cells 1 S11 -21dB Bandwidth 2GHz Fractional BW 76% Max. bias volt. 3.3V Av. power diss. 0 Av. NFa 4.9dB to 5.1dB aThe noise ﬁgure is roughly estimated from the phase shifter insertion loss.

4.6 Discussion and Comparison

Using the PRI/NRI phase shifter topology of [5] to build electronically tunable phase shifters (i.e. the TL and the MMIC PRI/NRI phase shifters) has allowed building compact, low group delay phase shifters with phase responses centered around the zero-degree mark. As explained in section 2.5.1, compactness is an important feature for beam steering networks, especially for series-fed arrays, in order to avoid capturing grating lobes in the radiation pattern as the beam is scanned. Moreover, centering the phase response around the zero-degree mark is desirable for series-fed antenna arrays in order to allow scanning the main beam around the broadside direction. In addition, the proposed phase shifter design approach maintains their bi-directionality, thus allowing the same antenna array to operate as a transmitter and as a receiver. The low group delay property of PRI/NRI phase shifters is described in detail in section 4.6.1, and its importance for the design of series-fed antenna arrays will be demonstrated in chapter 6. Using TAIs to design the TL and the MMIC PRI/NRI phase shifters resulted in a wide phase tuning range and at the same time maintained the matching of the phase shifters as opposed to other implementations published in the literature which use a single tuning element [27, 56, 57], or use two tunable elements but in the form of 4.6. DISCUSSION AND COMPARISON 125

Table 4.5: Comparison Between Different Phase Shifter Designs Presented In This Chapter. Parameter High-pass TL PRI/NRI MMIC PRI/NRI Passive PRI/NRI Technology Integrated Printed Integrated Integrated Phase shift + √± √± √± Broadside rad. X Insertion loss Average Low Average High Size Very small Large Small Small Bandwidth Small Large Large Large Av. power diss. Average High Average 0 IIP3 Average Average Average High Noise figure High Average High Low series and shunt varactors only [59]. On the other hand, as mentioned in chapter 3, the TAI achieves a +2.16dBm 1-dB input compression point, which corresponds to approximately a 0.8Vpp voltage swing while operating from a 1.5V supply voltage, and a +12.5dBm IIP3. Consequently, using TAIs imposes limitations on the phase shifter’s linearity, especially since it operates from a low-voltage supply of 1.5V. This will be critical when an antenna array using these phase shifters operates in the transmit mode. As an example, the TAI-based high-pass phase shifter presented in section 4.2 achieves a -2.2dBm 1-dB input compression point, and a +7.4dBm IIP3. Although the proposed TAI-based phase shifters achieve a significantly higher 1-dB compression point compared to other TAI-based phase shifters in the literature [86], their limited power handling capability precludes their use in base stations. However, they can find applications in short-range wireless applications requiring low transmit power levels such as wireless sensor networks (WSN) and RF applications using ZigBee. Also, designing the PRI/NRI phase shifters utilizing TAIs results in higher noise figures compared to passive designs: 7.6dB and 10.3dB for the TL and MMIC phase shifters, respectively. Nevertheless, in a practical application, the noise figure of the phase shifter can be enhanced by preceding the phase shifter with a low noise amplifier when operating within a receiver [23]. The passive PRI/NRI phase shifter tries to address some of the drawbacks of the active designs by eliminating the TAI and using instead a shunt varactor. The resulting topology still exhibits phase compensation properties, which allows us to center its phase response around the zero-degree mark while having a small group delay. Fur- thermore, it is also capable of maintaining the phase shifter matching. The passive 4.6. DISCUSSION AND COMPARISON 126

PRI/NRI design does not consume any DC power and at the same time it eliminates the noise and non-linearity contributions of the TAI, which will potentially result in a lower noise figure and a higher IIP3, respectively. This, however, comes at the expense of a slightly lower phase tuning range, and a higher insertion loss. Table 4.5 qualitatively compares between the different phase shifter designs presented in this chapter. The phase shifters presented here are prototypes fabricated to prove the concept and to experimentally characterize them. When using these phase shifters within a practical system, a look-up table together with multiple DACs (Digital-to-Analog Converters) can be implemented to set the different bias voltages according to a single control input. All of the biasing circuitry can be easily integrated on the same die with the TAI for the case of the TL phase shifter or on the same die with the MMIC phase shifters. This is one of the main advantages of using a standard CMOS technology to implement the phase shifters as opposed to using other high ft technologies such as GaAs. Furthermore, this should not result in a significant increase in the die sizes, since removing the DC/bias pads would result in some area saving. Moreover, generating the bias voltages on-chip will reduce the number of pins required from the TAI IC package for the case of the TL phase shifter and from the IC package of the MMIC phase shifter, making it possible to move to a smaller package size for both designs. This will allow us to further shrink the dimensions of both designs. 4.6. DISCUSSION AND COMPARISON 127 /dB o o 9 20V 0 [87] 30 – 10GHz 2.2GHz 22% -12dB 28 5mm 2.6mm × 0.5mm × /dB o o & microstrip &0.25dB CPW to 0.5dB 0.8dB to 1dB 0 26V – [85] 60 6.5GHz 6.5 -9dB 1.9GHz 32 30% 0.96mm 20mm × o /dB o 17GHz 4 15V > 5GHz [59] 13 30% -12dB 12.5 o =96 o × 0.96mm 1.8mm m CMOS Ferroelectric varactors Varactors Ferroelectric varactors ⇒ +59 µ /dB o o 8.4dB ⇒ 12.8dB – 2.6GHz 1 -19dB 1.9GHz 3.3V [email protected] 0 34 73% 0.38mm -35 o =64 o CMOS 0.13 × 10.4mm to 1.1dB 2.8dB to 3.8dB 1dB to 1.3dB m ⇒ +34 /dB phase shifter IC phase shifter o o microstrip Fully-integrated & CPW TL 2.5GHz 0.13 µ & -40 0.5dB 128 10.8mm 1 -19dB 2.6GHz > 100% 4.2V [email protected] 6.1dB ⇒ 9.3dB able 4.6: Comparison Between Different PRI/NRI Phase Shifter Implementations T 1 1 3 loss shift, insertion loss, and size are reported per unit-cell. frequency 2 1 ecification 11 Phase Bandwidth Max. bias volt. S Av. power diss. Simulated NF Technology Size Fractional BW Phase shift FOM No. of unit-cells Sp Design Insertion 1 4.6. DISCUSSION AND COMPARISON 128

Table 4.6 presents a detailed comparison between the TAI-based TL and MMIC PRI/NRI phase shifters along with related PRI/NRI phase shifters reported in the literature. Note that, although the phase shifters presented in [59, 85, 87] utilize the PRI/NRI structure, they do not achieve a phase centered around the zero-degree mark at their design frequencies. Tuning the inductance in both the proposed TL and MMIC phase shifters results in a very wide phase tuning range compared to the other implementations. To this end, the TL phase shifter achieves the highest ﬁgure of merit (FOM=128o/dB). In contrast, the MMIC phase shifter has the largest phase tuning range, but it achieves a ﬁgure of merit of only 34o/dB. This is attributed to the higher losses of the MMIC phase shifter due to the low Q of the on-chip series spiral inductors and MOS varactors. In spite of this, the MMIC phase shifter implementation occupies a very small area compared to the other implementations, and has the potential of integration with RF and digital circuitry in a standard low-voltage and low-cost CMOS process. Furthermore, the fractional bandwidth of both the TL and MMIC phase shifters is much wider than those of other implementations reported in the literature. This is mainly due to the ability to tune the shunt inductance, which allows one to maintain the matching condition across the entire phase tuning range. Moreover, the designs in [59, 85, 87] require very high control voltages; 15V up to 26V, which makes them less suitable for hand-held applications.

4.6.1 Group Delay of PRI/NRI Phase Shifters

As previously described in chapter 2, a low group delay is necessary to minimize the beam squinting with frequency variations in series-fed antenna arrays. In [5], it was demonstrated that printed PRI/NRI phase shifters using ﬁxed discrete components achieve low group delays compared to traditional -360o TLs. In this section, we demonstrate the same, but for the electronically tunable PRI/NRI phase shifters. As an example, this is demonstrated here for the passive MMIC PRI/NRI phase shifter presented in section 4.5.

The group delay of the passive MMIC PRI/NRI phase shifter, Tgd, can be obtained using Eq.(4.30), which results in the following expression: √ dφ 2 √ p Tgd = − = √ + 2 Lo(4Co + Cv). (4.35) dω ω2 LC 4.6. DISCUSSION AND COMPARISON 129

1 0.35

0.8 (nsec) (nsec) 0.3 →

0.6 0.25 ← 0.4 0.2 Phase shifter group delay 0.2 All−pass filter group delay 0.15

0 1.5 2 2.5 3 3.5 4 Frequency (GHz) Figure 4.33: The measured group delays of the metamaterial phase shifter and the simulated group delay of two cascaded 2nd-order all-pass ﬁlters achieving a -360o at 2.6GHz

Note that, the individual phase contributions of the PRI and NRI sections in Eq.(4.30) do not need to be large to achieve the phase compensation. In fact, they can be small in magnitude, and to achieve the phase compensation they only need to be equal. Consequently, looking closely at Eq.(4.35), where the same two terms add up, one can see that this architecture results in smaller group delays compared to using other types of phase shifters which require a complete -360o or +360o phase rotation. Since, all-pass ﬁlters are well suited to design phase shifters, we will use the group delay of an all-pass ﬁlter as the reference for the comparison. Using the all-pass phase shifter described in chapter 2 to achieve a -360o phase shift requires us to cascade two of the 2nd-order constant-resistance stages. The resonance frequency of the all-pass

ﬁlter, ωr, is chosen as 2.6GHz, and the ﬁlter quality factor, Q, is chosen as 2 to result in equal inductances. This results in the following group delay expression:

2 2 2Qωr(ω + ωr ) Tgd = 2 2 2 2 2 2 . (4.36) Q (ω − ωr ) + ω ωr

The group delay of the all-pass filter obtained from Eq.(4.36) is plotted in Fig. 4.33 with the measured group delays of the passive MMIC PRI/NRI phase shifter for all the different bias conditions. As indicated by Fig. 4.33, the PRI/NRI phase shifter is 4.6. DISCUSSION AND COMPARISON 130 capable of achieving the 0o phase with a 76% reduction in the group delay compared to the reference all-pass phase shifter design. Furthermore, the PRI/NRI phase shifter’s group delay varies by 63% over the entire 2GHz bandwidth compared to a variation of 85% for the all-pass phase shifter design. It is also worth mentioning that, the group delays of the passive MMIC PRI/NRI phase shifter plotted in Fig. 4.33 remain relatively constant for the different bias conditions. This takes place because the phase is tuned by varying the contribution of the NRI and PRI sections of Eq.(4.30) in an opposite manner, which results in a very small variation in the group delay given by Eq.(4.35). These results are not only specific to the passive MMIC PRI/NRI phase shifter. In fact, it can be shown that the active TL and MMIC PRI/NRI phase shifters also achieve low and relatively fixed group delays. As explained in section 2.5.4, the low group delay property of PRI/NRI phase shifters is important to minimize the beam squinting in series-fed antenna arrays. This will be described in more detail in chapter 6. CHAPTER 5

A Highly-Reconﬁgurable Directional Coupler

uplexers are necessary building blocks for transceiver front-ends, since they allow D sharing the same antenna between the transmitter and the receiver, as shown in Fig. 1.2. Duplexers are usually designed using printed or discrete components. Consequently, they are bulky and do not provide any tunability. Also, for a transceiver to support multi-standard operation, it is necessary to employ an electronically tunable duplexer, capable of operating at different frequencies. In this chapter, the design of a highly-reconfigurable CMOS MMIC directional coupler is presented. The proposed directional coupler has the capability to operate with a tunable coupling coefficient, and at the same time to operate at a tunable center frequency. Also, the proposed coupler has the capability to switch the input power among its different ports. This makes it suitable for replacing the bulky passive duplexers in transceiver front-ends. Also, as explained in chapter 1, replacing the 3-port duplexer with 4-port highly-reconfigurable directional coupler enables one to monitor the transmitted and received power. Thus, allowing for precise control over the level of the TX power and the gain of the low-noise amplifier.

131 5.1. INTRODUCTION 132

Through port Isolated port (1) (2) (1) (2)

Isolated port Coupled port Through port Coupled port (4) (3) (4) (3)

(a) Forward (b) Backward

Figure 5.1: Block diagram of a 4-port directional coupler conﬁgured in: (a) the forward mode of operation, and (b) the backward mode of operation.

5.1 Introduction

The most popular method used to design directional couplers is using printed TL structures. However, the TL implementations impose limitations on the area occupied by the couplers, especially for systems operating within the low GHz frequency range. This has hindered the integration of the couplers to produce single MMIC solutions for such systems. Hence, various methods have been presented in the literature to design lumped-element directional couplers [60]. Furthermore, the recent demand for reconfigurable circuits capable of operating within multi-standard systems has created a need for couplers capable of operating within different frequency bands [86, 88–92], as well as capable of providing configurable coupling levels [93–95]. As a 4-port device, the directional coupler has the potential to simultaneously realize multiple functions: 1. Tuning the coupling coefficient 2. Tuning the operating frequency 3. Switching from forward to backward operation, as illustrated by the block diagram of Fig. 5.1, where the coupler is capable of switching the power between the through port (P2) and the isolated port (P4) while perfectly isolating the other. To date, existing reconfigurable couplers individually realize only one of the above features [86,88–95]. Furthermore, to the author’s knowledge, none of the MMIC directional couplers reported in the literature has demonstrated the capability of electronically switching between backward and forward operation. This feature could prove to be very useful for diversity systems, in which it is desired to electronically switch between different sub-systems (for example: antenna diversity systems). Also, it can be 5.1. INTRODUCTION 133 used within transceivers to connect the TX and RX ports to the antenna (duplexing). This will be explored in more detail later on in this chapter.

5.1.1 Tunable Coupling Coeﬃcient Directional Couplers

Directional couplers with electronically tunable coupling coefficients are presented in [93–95]. In [93] and [94], varactors are used to control the coupling between two printed TLs. The design in [93] achieves a large tuning range of 4.1dB to 19dB for the coupling coefficient, from the input port to the coupled port, over a wide bandwidth. Also, the design in [94] achieves a 6dB to 10dB coupling coefficient tuning range. However, in both designs the discrete varactors require a large reverse bias voltage; 25V for the former and 10V for the latter. The design in [95] proposes to use switches to control the coupling coefficient between two coupled TLs, resulting in coupling coefficients of 8dB to 16dB. Nevertheless, the switches are not actually implemented and they are replaced by hardwired connections (ideal short/open). Furthermore, both designs utilize printed TL structures, hence they occupy a large area compared to a lumped-element approach. To the author’s knowledge, lumped-element couplers with tunable coupling coefficients have never been published yet in the literature.

5.1.2 Tunable Operating Frequency Directional Couplers

Directional couplers with electronically tunable operating frequencies have also been presented in the literature [86,88–92]. In one of the most recently published papers [88], varactors are used to terminate the open-circuited TL stubs of a dual-band TL coupler, which was originally presented in [96]. Hence, the reverse bias voltage across the varactors controls the operating frequency, within a limited range, around each of the coupler bands by changing the effective electrical length of the stubs. Although the reverse bias voltage across the discrete varactors goes up to 30V, this technique results in a limited frequency tuning range of 0.62GHz to 0.9GHz and 1.63GHz to 1.8GHz for the lower and upper frequency bands respectively. Furthermore, the coupler isolation level is limited to 20dB and the design occupies a large area of approximately 6cm×6cm. Other printed TL coupler designs have also been published in the literature [89–91] that utilize varactors in different ways to tune the coupler operating frequency. But all of them occupy a large area compared to lumped-element couplers and they require 5.2. THEORETICAL ANALYSIS 134 large reverse bias voltages for the discrete varactors. Furthermore, they do not achieve a wide frequency tuning range: 1.3GHz to 1.7GHz and 1.7GHz to 2.17GHz for the designs in [89,90] and [91] respectively. Very few electronically tunable lumped-element directional coupler designs have been published. The coupler published in [92] utilizes discrete varactors with chip inductors to reduce the footprint of the coupler by 80% compared to the printed coupler of [91]. Nevertheless, using only tunable capacitors results in a limited frequency tuning range (1.7GHz to 2.17GHz). To the author’s knowledge, the coupler published in [86] is the first fully-integrated MMIC coupler achieving a tunable center frequency. The MMIC coupler in [86] is based on the high-pass Tee L-C coupler topology of Fig. 2.19, and uses TAIs with fixed on-chip Metal-Insulator-Metal (MIM) capacitors to achieve a tunable operating frequency. However, it can only operate with a fixed coupling coefficient and still does not offer the switching capability described in Fig. 5.1. In this chapter, a highly-reconfigurable compact CMOS MMIC directional coupler is presented. The MMIC directional coupler utilizes lumped-element varactors and TAIs to allow electronic tuning of both the coupling coefficient as well as the coupler’s operating frequency. To the author’s knowledge, this is the first coupler that combines both functions. Furthermore, combining the use of varactors and TAIs results in a very wide frequency tuning range while maintaining good isolation. Moreover, the MMIC directional coupler can be electronically reconfigured to operate as a forward or as a backward coupler, i.e. it is capable of switching the power from the through port to the isolated port, see Fig. 5.1. The design equations of the MMIC directional coupler are presented in section 5.2. Section 5.3 describes the MMIC directional coupler circuit implementation. The experimental results are presented in section 5.4. Finally, the noise performance of the MMIC coupler is evaluated in section 5.5.

5.2 Theoretical Analysis

5.2.1 Analysis of the MMIC Directional Coupler

The proposed MMIC lumped-element directional coupler uses the high-pass architecture shown in Fig. 5.2. Each branch of the coupler consists of a lumped element L-C section that provides the necessary 90o phase shift at the design frequency. The high- 5.2. THEORETICAL ANALYSIS 135

L L C1 (1) (2)

C2 C2

C1 (4) (3)

L L

Figure 5.2: The high-pass topology used by the proposed MMIC directional coupler.

L L +1/2 C1 Te

e Zo

Te +1/2 C1

e L L Zo

Figure 5.3: The equivalent circuit with even-mode excitation.

pass L-C topology requires grounded inductors as opposed to a traditional low-pass topology which requires ﬂoating inductors [92]. This allows the use of the TAIs in place of the spiral inductors. Furthermore, the high-pass Π topology is chosen to minimize the number of inductors, and hence the area occupied by the MMIC coupler. At the same time, this topology reduces the number of series capacitors in the signal path, which in turn, reduces the MMIC coupler insertion loss. To analyze the operation of the proposed MMIC directional coupler, the lumped- element L-C high-pass coupler is analyzed using the even-odd mode technique, originally presented in [97]. The eﬀect of an input signal applied at any of the ports (port

1 in this case) while terminating the rest of the ports with an impedance Zo, is eval- 5.2. THEORETICAL ANALYSIS 136

L L +1/2 C1 To

o Z 2C2 2C2 o V1 V2 2-port I1 Network I2 2C2 2C2 -1/2 C1 To Odd mode circuit o L L Zo

Figure 5.4: The equivalent circuit with odd-mode excitation.

uated by decomposing the original coupler of Fig. 5.2 into two circuits: an even-mode

circuit shown in Fig. 5.3, and an odd-mode circuit shown in Fig. 5.4, where Te,o and

Γe,o are the transmission and reflection coefficients of the even- and odd-mode circuits, respectively. The transmission coefficients S21,S31,S41 and the reflection coefficient S11 of the MMIC coupler can be obtained by properly superimposing the responses of the even- and odd-mode circuits [97].

In standard 2-port network theory, the ABCD matrix is deﬁned as: " # " #" # V AB V 1 = 2 , (5.1) I1 CD I2

where V1,2 and I1,2 are the voltage and current, respectively, at ports 1 and 2 of the odd-mode circuit shown in Fig. 5.4. Performing circuit analysis, one can show that the ABCD matrix of the odd-mode circuit is expressed as:   1 2β −  2 X 1   1 + L     β1µ ¶ jβ1   1 2  , (5.2)  µ ¶ 1   2β2 − 2β2 −  1 XL XL 2j 2β2 − − 1 + XL jβ1 β1 5.2. THEORETICAL ANALYSIS 137

where β1, β2, and XL are the susceptances of the series capacitors C1, C2 and the reac- tance of the shunt inductors L respectively. Using the standard relationship between the scattering parameters and the ABCD matrix of a 2-port network [24], one can evaluate the transmission and reﬂection coeﬃcients of the odd-mode circuit, To and

Γo, which are expressed as:

2 To =  µ ¶ , (5.3) 1 2 µ ¶  2β2 −  2 1 1  2 XL  2 + 2β2 − + + jZo 4β2 − −  β1 XL jβ1Zo  XL β1  and  µ ¶  1 2  2β2 −  1  2 XL  − jZo 4β2 − −  jβ1Zo  XL β1 

Γo =  µ ¶ . (5.4) 1 2 µ ¶  2β2 −  2 1 1  2 XL  2 + 2β2 − + + jZo 4β2 − −  β1 XL jβ1Zo  XL β1 

Similarly by analyzing the even-mode circuit, one can show that the transmission and

reﬂection coeﬃcients of the even-mode circuit, Te and Γe, are expressed as:

2 T = µ ¶ µ ¶, (5.5) e 1 j 2 1 2 1 − − − jZo − 2 XLβ1 β1Zo XL β1XL and µ ¶ j 2 1 − + jZ − β Z o X β X2 Γ = µ 1 ¶o L µ1 L ¶. (5.6) e 1 j 2 1 2 1 − − − jZo − 2 XLβ1 β1Zo XL β1XL To fully characterize the lumped-element directional coupler, the S-parameters are

evaluated by superimposing Te,o and Γe,o, in Eq.(5.3) through Eq.(5.6), according to 5.2. THEORETICAL ANALYSIS 138

[24]. To guarantee a low reflection coefficient, S11, the following equation has to be satisfied: Γ Γ S = o + e = 0. (5.7) 11 2 2 Furthermore, to guarantee high isolation, the following equation has to be satisfied:

Γ Γ S = e − o = 0. (5.8) 41 2 2

Solving Eq.(5.7) and Eq.(5.8) results in the following two conditions:

2 1 2 2 2 1 2 2 β1 = 2 + β2 ⇒ ωo C1 = 2 + ωo C2 , and (5.9) Zo Zo

1 1 XL = ⇒ ωoL = , (5.10) β1 + β2 ωoC1 + ωoC2 where ωo is the design frequency. Moreover, at the design frequency the transmission

coeﬃcients of the through and coupled ports, S21 and S31 respectively, are given by: s s 2 2 β2 C2 S21(ω = ωo) = j 1 − 2 = j 1 − 2 , and (5.11) β1 C1

−β2 −C2 S31(ω = ωo) = = . (5.12) β1 C1 Hence, the output signals at the coupled and the through ports, P3 and P2 respectively, have a 90o phase diﬀerence at the design frequency. At the same time, the magnitude of the signals delivered to both ports is determined by the ratio of the series capacitors

C1 and C2.

5.2.2 MMIC Directional Coupler Modes of Operation

Tunable Coupling Coeﬃcient

As indicated by Eq.(5.12), the coupling coeﬃcient C of the MMIC directional coupler can be tuned, and at the design frequency, is expressed as:

C2 C(ω = ωo) = −20 log |S31| = −20 log . (5.13) C1 5.2. THEORETICAL ANALYSIS 139

1.8 2

1.6 ← 1.8 1.4 (pF) 2 1.6 1.2 1.4 1 Inductance L (nH) Capacitance C 1.2 0.8 → 0.6 1

1.3 1.5 1.7 1.9 2.1 2.3 Capacitance C (pF) 1

Figure 5.5: Series capacitance C2 and the shunt inductance L required to satisfy the conditions of Eq.(5.9) and Eq.(5.10) versus the series capacitance C1.

7 C (dB) C 6

3 Coupling coefficient

1 1.4 1.6 1.8 2 2.2 Capacitance C (pF) 1 Figure 5.6: Coupling coeﬃcients achieved by the MMIC coupler circuit when the lumped-element components are chosen to satisfy both the matching and the isolation conditions. 5.2. THEORETICAL ANALYSIS 140

For example, in order to implement a 3dB coupler, the capacitance C has to be chosen √ 1 equal to 2 × C2. Furthermore, if the series capacitors are replaced by varactors, the coupling coefficient can be electronically tuned by changing the bias voltages applied across the varactors. In order to achieve a low return loss and a very high isolation while tuning the coupling coefficient, both conditions expressed by Eq.(5.9) and Eq.(5.10) must be satisfied across the entire coupling coefficient tuning range. Equation (5.9) reveals that, if C1 is increased to tune the coupling coefficient, the value of C2 must also increase for the MMIC directional coupler to operate at the same frequency. At the same time, the value of the shunt inductor L has to decrease according to the condition of Eq.(5.10). Figure 5.5 shows the values of C2 and L resulting from the theoretical expressions of Eq.(5.9) and Eq.(5.10) respectively when C1 is swept to tune the coupling coefficient. This plot is generated assuming a nominal design frequency of 2.6GHz and a 50Ω termination impedance (Zo). Although the coupling coefficient depends on the ratio of the two series capacitances, the nonlinear relationship between

C1 and C2 in Eq.(5.9) is enough to result in an 8.5dB tuning range for the coupling coefficient. This is demonstrated by Fig. 5.6 which plots the theoretical expression of the coupling coefficient given by Eq.(5.13) versus the value of C1. For each point the value of C2, calculated from Eq.(5.9), is used to calculate the coupling coefficient.

We have so far shown that, the coupling coeﬃcient of the MMIC directional coupler can be electronically controlled while maintaining a low return loss and a very high isolation across the entire tuning range. However, to achieve full electronic tunability for the coupling coeﬃcient, electronically tunable inductors are required. Thus, the lumped-element approach used to implement the coupler proves to be a valid choice, since this enables the integration of the coupler with the active circuits necessary to synthesize the TAIs on the same chip.

Further circuit analysis can be performed on the lumped-element coupler to show that the power delivered to the coupled port (P3), and hence the coupling coeﬃcient are, in general, a function of frequency. Moreover, the power delivered to the coupled 5.2. THEORETICAL ANALYSIS 141

port is expressed as:

S (ω) = 31 µ µ ¶ ¶ ω2 4C C Z2L3ω5 Z − 1 − jωL 1 2 o o ω2 µ µ o ¶ ¶ 2ω2 (ωL − jZo) Zo 2 − 1 − jωL ωo 1 × 2 2 (5.14) (Zo (2C1Lω − 1) − jωL)(Zo (2C2Lω − 1) − jωL)

Equation (5.14) indicates the high-pass nature of the lumped element coupler. Fur-

thermore, evaluating S31 at the design frequency ωo results in the simple expression of Eq.(5.13) as long as the two conditions of Eq.(5.9) and Eq.(5.10) are satisﬁed.

Tunable Frequency of Operation

The frequency of operation of the lumped-element coupler is deﬁned as the frequency at which high isolation and low return loss are achieved, while realizing the desired coupling coeﬃcient. This can simply be obtained by re-writing Eq.(5.10), which results in the following expression for the coupler operating frequency:

1 ωo = p . (5.15) L(C1 + C2)

The coupler operating frequency, ωo, given by Eq.(5.15) is a function of the shunt

inductance L and the series capacitances C1 and C2. However, to achieve low return loss and high isolation the condition of Eq.(5.9) must also be satisﬁed, which can re- written as: L C1 = 2 + C2. (5.16) Zo

As conﬁrmation, further circuit analysis showed the frequency dependent nature of 5.2. THEORETICAL ANALYSIS 142

3.6 3

3.2 →

(GHz) ← 2.6 o f (pF) 2.8 1

2.2 2.4

1.8 Capacitance C 2 Operating frequency

1.6 1.4

0.8 1.2 1.6 2 2.4 Inductance L (nH)

Figure 5.7: Operating frequency of the MMIC coupler and the series capacitance C1 versus the shunt inductance L. The series capacitance C1 is chosen to satisfy both the matching and the isolation conditions, while C2 is chosen to achieve an arbitrary coupling coeﬃcient of 3dB.

the isolation of the lumped element coupler, which could be expressed as:

S41(ω) = 3 2 2 2 2 2 jLZoω (ω − ωo )(ωo L − Zo ) 2 2 2 2 2 2 2 2 2 2 (ω ωo L + Zo (ω − ωo ) − jωo ZoLω)(ωωo L + jZo (2ω − ωo ))

(ωωoL + jZo (ω − ωo)) (ωωoL − jZo (ω + ωo)) × 2 2 2 2 2 2 2 (5.17) (ω ωo L − Zo (ω − ωo ) + jωo ZoLω)(ωL − jZo)

This result is derived under the assumption that the conditions of Eq.(5.9) and Eq.(5.10) are satisﬁed. Equation (5.17) conﬁrms the existence of a zero in the transfer function of S41 at ω = ωo, which results in perfect isolation at the operating frequency.

To tune the operating frequency ωo of the coupler, the shunt inductance L is varied and for each inductance value, the series capacitance C1 is calculated from Eq.(5.16). This is necessary in order to guarantee a low return loss as well as high isolation across the entire frequency tuning range. The resulting operating frequencies based on the theoretical expression of Eq.(5.15) are plotted in Fig. 5.7 together with the values of 5.2. THEORETICAL ANALYSIS 143

the shunt capacitance C1 versus the value of the shunt inductance L. To generate this

plot the value of the shunt capacitance C2 is chosen according to Eq.(5.13) in order to achieve an arbitrary coupling coeﬃcient of 3dB. Also, the termination impedance is set to 50Ω. Figure 5.7 indicates that changing the operating frequency from 3.6GHz to 1.6GHz (a 77% tuning range) requires tuning the inductance by a factor of 2.2, and at

the same time it requires tuning the capacitance C1, and consequently C2, by a factor of 2.2.

It is also possible to achieve a tunable frequency of operation for this MMIC coupler

by using a ﬁxed shunt inductance and varying both series capacitances C1 and C2. This will eliminate the need for TAIs if the coupler is only intended to have a tunable operating frequency and not a tunable coupling coeﬃcient as described earlier. How- ever, this will drastically reduce the frequency tuning range. To demonstrate this, one can show that the frequency tuning range achieved by tuning the shunt inductance L

as well as the series capacitance C1 while ﬁxing C2 is expressed as: ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯∆ωo ¯ 2C1 ¯∆L¯ ¯ ¯ = × ¯ ¯ . (5.18) ωo C1 + C2 L

On the other hand, if the shunt inductance is ﬁxed and both series capacitors C1 and C2 are varied to tune the operating frequency, and at the same time, satisfy the condition of Eq.(5.16), the frequency tuning range decreases to: ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯∆ωo ¯ C1 ¯∆C1 ¯ ¯ ¯ = × ¯ ¯ . (5.19) ωo C1 + C2 C1

Hence, for the same component tuning range, combining the use of varactors and TAIs extends the frequency tuning range by 50% compared to a design that uses series varactors and ﬁxed shunt inductors. The wider tuning range makes the proposed lumped-element directional coupler utilizing varactors and TAIs attractive for multi- standard applications where the coupler would be required to operate over a wide range of frequencies. 5.3. CIRCUIT IMPLEMENTATION 144

Power switching

Another interesting feature of this lumped-element MMIC coupler is its ability to be electronically reconﬁgured to operate as either a forward or a backward coupler, as described in the introduction. One can argue by symmetry that interchanging the two series capacitors C1 and C2 would result in interchanging the isolated and through ports of the MMIC directional coupler. Thus, implementing the series capacitors C1 and C2 using varactors allows switching from forward to backward operation by simply switching the bias voltage applied across the varactors. This section has summarized the three diﬀerent modes of operation of the proposed MMIC directional coupler. The next sections describe the design details of the MMIC directional coupler circuit as well as its experimental characterization.

5.3 Circuit Implementation

5.3.1 MMIC Directional Coupler Design

The schematic diagram of the proposed highly-reconfigurable CMOS directional coupler is shown in Fig. 5.8. Since there is no need for any printed or off-chip components, the entire directional coupler has been implemented on a single MMIC. The series capacitors C1 and C2 are implemented using on-chip MOS varactors, each MOS varactor consists of an array of 5 by 18 small MOS varactors with an aspect ratio of 2µm/0.5µm, and can be tuned from 0.25pF to 1pF. The Q of the varactors has a strong impact on the coupler’s insertion loss, given that its effect can be modeled as a series resistance in the signal path. To achieve the large capacitance value required to make the design frequency, fo, 2.6GHz, a larger series capacitance is required. To this end, a

ﬁxed 0.95pF on-chip high-Q MIM capacitor, CMIM2, is connected in parallel. This will slightly reduce the series capacitance tuning range, but it is necessary in order to achieve a low insertion loss for the coupler. The series MOS capacitance, CMOS, is set via the gate to drain/source voltage. The gate voltage of the series MOS capacitors in the top and bottom branches of the coupler are set by the DC voltage Vr1 through a 10kΩ bias resistor R as shown in Fig. 5.8. Furthermore, the capacitance of the right and left branches is set through the bias voltage Vr2. The drain/source voltage of all the series MOS capacitors is set by the TAI circuit. To isolate the gate voltage of the 5.3. CIRCUIT IMPLEMENTATION 145

Vr1

CMIM2 R TAI TAI CMIM1 (1) (2)

CMOS C CMIM2 CMOS CMOS MIM2 Vr2 R R

CMOS CMIM1 CMIM1 (4) (3)

CMIM1 TAI TAI g R m1

CMIM2 Zin Vr1 Tunable Active Inductor -gm2 C

Figure 5.8: Proposed lumped-element MMIC directional coupler circuit implementation. 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 146

series MOS capacitors from the DC voltage generated by the TAI circuit, an additional

DC-blocking MIM capacitor CMIM1 is added in series. Since CMIM1 has a fixed value and is connected in series with the effective tunable capacitor (the parallel combination of CMOS and CMIM2), it reduces the tuning range of the overall series branch capacitance. To avoid the reduction in the tuning range, CMIM1 should be significantly larger than CMOS + CMIM2. However, CMIM1 can not take an arbitrarily large value since its parasitic capacitance to the substrate increases as well. This decreases its self- resonance frequency and losses, which potentially increases the coupler losses. Since

CMOS + CMIM2 can vary from 1.2pF to 1.95pF, 10pF was found to be a good design choice for CMIM1, which was also veriﬁed using simulations.

5.4 Physical Implementation and Experimental Results

5.4.1 Physical Implementation

The MMIC directional coupler was fabricated in a standard 0.13µm CMOS process. The die micrograph is shown in Fig. 5.9, the dimensions of the fabricated chip are 1540µm×900µm, which includes the MMIC coupler as well as some test structures and the biasing/RF pads. The MMIC directional coupler occupies 730µm×600µm without the bias/RF pads. Arguably this is a very small area for a highly-reconﬁgurable directional coupler operating in this frequency band. Some test structures are fabricated beside the MMIC coupler circuit to help in characterizing the TAI as well as the varactors. It is worth mentioning that, adding these test structures together with their RF probing pads has resulted in some asymmetry in the MMIC directional coupler layout, making the interconnecting wires from the RF pads to two ports of the MMIC coupler (P3 and P4) longer than those of the two other ports (P1 and P2) as shown in Fig. 5.9. The eﬀect of this asymmetry on the MMIC coupler performance will be discussed in the following section. As indicated by Fig. 5.9, the majority of the area of the MMIC coupler is occupied by the TAI circuits, which occupy 150µm×170µm, followed by the series MIM capacitors

CMIM1. On the other hand, the series varactors CMOS and the MIM capacitors CMIM2 occupy a very small area. The MOS varactors are not visible in the layout because of the metal ﬁll required by the foundry to maintain certain layer densities. The bias 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 147

1540 m DC/bias inputs Test TAI Directional coupler circuit

G G G

P4 P1 S S 900

G G m P3 P2 S S

G G G

Test varactor DC/bias inputs V DD 730 m

Shunt TAI

P4 P1

Series

capacitors 600 CMIM2 &

CMOS m

P3 P2

Series MIM capacitor CMIM1 VDD

Figure 5.9: MMIC directional coupler die micrograph. The top ﬁgure shows the entire fabricated chip and the bottom ﬁgure shows a close-up on the MMIC directional coupler circuit. 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 148

and control voltages are provided to the circuit from the top and bottom pads. The rightmost and leftmost pads correspond to the four ports of the MMIC directional coupler as indicated by Fig. 5.9. To distribute the bias and control voltages to the

diﬀerent TAI circuits (VDD,Vcm,Vc1,Vc2) as well as the varactors reverse bias voltages

(Vr1,Vr2), the directional coupler circuit is surrounded by several bias distribution rings. Each bias voltage is tapped oﬀ its ring whenever a connection is required to one of the circuit components. This helps reduce the voltage drop across the bias lines, which reduces mismatches between the responses of the diﬀerent TAI circuits. Furthermore, this facilitates the layout and routing process.

5.4.2 Experimental Characterization of the MMIC Directional Coupler

The MMIC directional coupler was characterized by probing the dies and measuring the corresponding 4-port S-parameters using a 4-port network analyzer. A pair of 150µm- pitch differential GSGSG probes were used to probe the 4-ports of the MMIC coupler. Two multi-contact wedges, each with 8 probe needles at 150µm-pitch, were used to supply the bias and control voltages to the circuits. A CS-2 differential calibration substrate from GGB Inc. is used to perform a 4-port calibration to de-embed the frequency response of the RF probes, connectors, and cables. The different operating modes of the MMIC directional coupler, which were described in section 5.2.2, have been experimentally characterized and are summarized here.

Tunable coupling coeﬃcient

The MMIC directional coupler was conﬁgured to operate at the nominal design fre-

quency of 2.6GHz, and the value of the series MOS capacitor C1 was varied using the bias voltage Vr1 to tune the coupling coefficient of the MMIC coupler. To keep the return losses low and the isolation of the coupler very high, the second series MOS capacitor C2 is tuned via Vr2 and the shunt inductance is tuned via Vc1 and Vc2 according to the conditions of Eq.(5.9) and Eq.(5.10) respectively. The resulting coupling coefficient C and the isolation of the MMIC coupler for different biasing conditions are plotted versus frequency in Fig. 5.10 and Fig. 5.11 respectively. Figure 5.10 also com- 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 149

10 Measured C tunable from 1.42dB Theory to 7.14dB at 2.6GHz 8 ↓ C (dB) 6

Coupling coefficient 2 C /C ↑ 2 1 decreasing 0 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 Frequency (GHz) Figure 5.10: Measured and theoretical coupling coeﬃcients C vs. freq. for diﬀerent bias conditions.

−10dB bandwidth = 0.45GHz −10 ← →

(dB) −20 41 S Worst case isolation −30 at 2.6GHz is 41dB Isolation

−40

−50 2.2 2.4 2.6 2.8 3 Frequency (GHz)

Figure 5.11: Measured isolation S41 vs. freq. for the same bias conditions as Fig. 5.10. 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 150

−5

−10 (dB) 11

S −15

−20

Return loss −25

−30

−35 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 Frequency (GHz)

Figure 5.12: Measured reflection coefficient S11 vs. freq. for the same bias conditions as Fig. 5.10. pares the measured and theoretical coupling coefficients, which are predicted using the expression of Eq.(5.14). The figure shows good agreement between the measurements and theory. Using the exact expression of Eq.(5.14) is necessary for the comparison in order to predict the frequency response of the coupling coefficient since the simple expression of Eq.(5.13) is only valid at the design frequency. The measurements in Fig. 5.10 and Fig. 5.11 show that the coupling coefficient of the MMIC coupler can be electronically tuned from 1.4dB to 7.1dB at 2.6GHz, while maintaining the isolation of the MMIC coupler higher than 41dB across the entire coupling coefficient tuning range. This coupling coefficient tuning range corresponds to directing 72% to 19% of the input power at port 1 to the coupled port (P3), respectively. Furthermore, across this tuning range, the return loss is maintained below -16.5dB, as indicated by Fig. 5.12. There is an exception to this, which takes place when the MMIC coupler is configured to operate with a coupling coefficient of -1.42dB which results in a S11 of -12.6dB. The MMIC directional coupler draws an average DC current of approximately 139mA from a 1.5V supply which corresponds to dissipating 208mW across the entire coupling coefficient tuning range. This power is required to bias the TAI circuits in order to 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 151 generate the required inductance. A more detailed discussion about power consumption is presented towards the end of section 5.4.2. 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 152 ⇒ -32dB µ m × 600 ⇒ -51dB ⇒ 3.1GHz 1.4 ⇒ 7.1dB This work 0.13 µ m CMOS -41 Continuous [email protected] -12.6 2V Tunable a b × 50mm 730 ⇒ 16dB 8 45mm -15dB Fixed – [95] – at 5.2GHz 2.1 2.2mm ⇒ -35.4dB -15dB ⇒ 10dB 14.8mm × 6 Fixed 0 -17dB -16 [94] 10V of 2.2. r ² c λ/ 4 for an ted/Varactors Printed/Varactors Printed/Switches tinuous Continuous Discrete × ⇒ -19dB ⇒ -45dB 4.5GHz at 2GHz λ/ 4 [93] Prin Fixed at 4.1 ⇒ 19dB Con -14 -22 25V 0 12mm × ) C ) 11 ) S 41 S Coefficient Couplers hes are not implemented, they are replaced by fixed short/open connections. ecification echnology Different coupling coefficients areSize obtained estimation from is different based prototypes. on Switc able 5.1: Comparison Between the Proposed MMIC Directional Coupler and Other Variable Coupling Tuning Power dissipation Center frequency Coupling coeff. ( Max bias voltage Return loss ( Isolation ( Size Sp T c a b T 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 153

0 Measured −5 Theory

−10

−15

(dB) −20 41 S −25

−30

Isolation −35

−40

−45

−50 2 2.2 2.4 2.6 2.8 3 3.2 Frequency (GHz)

Figure 5.13: Measured and theoretical S41 vs. freq., for diﬀerent bias conditions

Table 5.1 summarizes the performance of the proposed MMIC directional coupler with other tunable coupling coeﬃcient couplers presented in the literature [93–95]. The proposed coupler provides a smaller coupling coeﬃcient tuning range compared to [93]. Also, using the lumped-element approach to design the proposed coupler results in a smaller bandwidth compared to the printed designs in [93] and [94]. Nevertheless, using the lumped-element approach to design the coupler results in a very compact implementation. This enables fabricating the coupler in a standard CMOS process allowing its integration with other RF/digital circuits on the same chip. Furthermore, the integrated MOS varactors used in this design, require a much lower bias voltage compared to the discrete varactors used in [93] and [94]. Moreover, the proposed MMIC coupler achieves very high isolation levels compared to other designs.

Tunable Frequency of Operation

As explained in section 5.2.2, the proposed directional coupler is capable of operating at diﬀerent center frequencies. This is achieved by changing the value of the shunt inductance via Vc1 and Vc2 and simultaneously changing the series MOS capacitance

C1 via Vr1 in order to satisfy the condition of Eq.(5.16). This will guarantee a low 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 154

−5

−10

−15 (dB) 11

S −20

−25

−30 Return loss −35

−40

−45 1.5 2 2.5 3 3.5 Frequency (GHz)

Figure 5.14: Measured S11 vs. freq., for different bias conditions return loss and a very high isolation for the MMIC coupler across its entire frequency tuning range. Figure 5.13 shows the measured coupler isolation for the different biasing conditions, and compares it with the theoretical isolation, which is predicted using the expression of Eq.(5.17). The figure shows good agreement between the measurements and theory. As indicated by Fig. 5.13, the MMIC coupler can be electronically tuned to operate over a very wide band of frequencies; namely 2.15GHz to 3.1GHz. Across this wide frequency range, the isolation level between the input port (P1) and the isolated port (P4) remains higher than 40dB. An exception to this happens when the coupler is configured to operate at 3.1GHz, where the isolation drops to 34dB. At the same time, the return loss of the MMIC coupler at each operating frequency is maintained below -18.6dB over the entire frequency range, except for the case when the coupler is configured to operate at 2.15GHz where the return loss goes slightly up to -15dB as shown by Fig. 5.14.

As previously explained in section 5.2.2, varying L and C1 in order to tune the operating frequency while fixing the value of C2 will affect the value of the coupling coefficient. During measurements, in order to ensure that the coupler satisfies the matching and isolation conditions, and achieves equal power splitting between the through and coupled ports (S21 = S31), the value of C2 is linearly scaled with C1 using 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 155

−3 0

−10 −4 ← −20 (dB) o (dB) o at f at at f −5 −30 41 31 S & S 21

S −40 Isolation −6 → −50

−7 −60 2 2.2 2.4 2.6 2.8 3 3.2 Coupler center frequency f (GHz) o

Figure 5.15: Measured S21 and S31 to the left and S41 to the right vs. the coupler operating frequency. Electronically tuning the capacitances C1 and C2 provides precisely equal power splitting between the through and isolated ports, i.e. S21 = S31.

Vr2. The measured MMIC coupler power levels at the coupled (P3) and through ports (P2), as well as the coupler isolation levels are plotted versus the coupler operating frequency in Fig. 5.15. The measured results show that across this entire range of operating frequencies, S21 and S31 are equal and both of them vary from -3.35dB to -4.44dB. This corresponds to a best case insertion loss of 0.35dB and a worst case of 1.44dB. In this mode of operation, the MMIC directional coupler draws an average DC current of approximately 132mA from a 1.5V supply, which corresponds to dissipating 197mW across the entire frequency tuning range. According to Fig. 5.7, higher operating frequencies require smaller inductance values, which require larger bias currents, and vice versa. Hence, configuring the coupler to operate at 3.1GHz results in dissipating the maximum power which is 216mW. On the other hand, configuring the coupler to operate at the 2.15GHz results in dissipating the minimum power which is 132mW. A more detailed discussion about power consumption is presented towards the end of section 5.4.2. 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 156 m m CMOS m × 600 µ µ 2V 1.4 ⇒ 7.1dB This work 36% Tunable m 730 µ 200 µ m CMOS 0.13 m × µ ⇒ [email protected] 132 ⇒ [email protected] µ ⇒ -21dB -43 ⇒ -15.8dB ⇒ 0.4dB 0.3 ⇒ 1.4dB [86] -18 ⇒ -14dB -50 ⇒ -34dB 1.8V 17.6 3dB 26% Fixed ⇒ -14dB -28 [92] – 8V 0 3dB 24% Fixed ⇒ -21.1dB -25 ⇒ 0.8dB 1.3 ⇒ 1.4dB 0.2 0 3dB 18mm × 8mm × 400 – Fixed ⇒ -32dB, -27.4 ⇒ 1.9GHz 1.5 ⇒ 1.93GHz, 1.7 ⇒ 2.17GHz 1.7 ⇒ 2.17GHz 3.2 ⇒ 4.7GHz 2.1 ⇒ 3.1GHz [89], [90] [91] 20dB – , 0.15dB 0.3 – -36 – 1.3 Fixed 16V, 11.2V0 8V < -43dB, < 50dB 60mm . o 10% 25%, 35% 24% ted/Varac. Printed/Varac. Printed/Varac. Lumped/Varac. 0.18 ⇒ 0.9GHz, ⇒ 1.8GHz [4] Prin 0.62 1.63 33%, Fixed 3dB -24 ⇒ -10dB, -40 ⇒ -27dB -25 ⇒ -20dB, -20dB 0.5dB 30V 0 60mm × ) a C ) 11 ) 41 quency loss ecification ractional freq. range = ∆ f/f echnology F able 5.2: Comparison Between the Proposed MMIC Coupler and Other Couplers with Variable Operating Fre- Freq. tuning range Coupling coeff. ( Max bias voltage Power diss. (mW) Size Isolation ( S Return loss ( S Frac. freq. range Sp T Insertion a T 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 157

Table 5.2 summarizes the performance of the proposed MMIC coupler with other couplers presented in the literature [86, 88–92]. The proposed MMIC coupler has the widest frequency tuning range (∆f/fo), and at the same time, offers very high isolation levels compared to the other designs. The design in [90] offers both a comparable frequency tuning range and high isolation levels, but requires a high bias voltage of 11.2V for the discrete varactors. Besides, its printed implementation would require a large area. Moreover, the compact CMOS implementation of the proposed MMIC coupler allows integrating it with other RF/digital circuits, as opposed to the printed designs of [88–91]. Similar to our proposed design, the coupler published in [86] also utilizes TAIs in a high-pass topology. However, it does not employ varactors together with the TAIs. As such, the coupler presented in [86] can only operate with a fixed coupling coefficient and can not switch between forward and backward operation, as in the proposed design. Furthermore, using TAIs only to tune the operating frequency does not allow satisfying both the matching condition and the isolation condition simultaneously (see Eq.(5.15) and Eq.(5.16)). This results in modest isolation and a lower relative frequency tuning range, ∆f/fo. The design in [86] operates at slightly higher frequencies and consumes less power, but this comes at the expense of the linearity of the coupler, and hence its power handling capability, as will be discussed later.

Power switching

As described in section 5.2.2, one can electronically conﬁgure the MMIC coupler to operate as either a forward coupler or as a backward coupler, i.e. switching the power between the through port (P2) and the isolated port (P4). This is simply achieved by interchanging the values of the bias voltages Vr1 and Vr2 applied at the gates of the series MOS varactors C1 and C2 respectively. Figure 5.16 shows the measured S-parameters of the MMIC coupler when it is conﬁgured to operate in the forward mode at the nominal design frequency of 2.6GHz. By interchanging the values of the bias voltages applied at the gates of the series MOS varactors, Vr1 and Vr2, the MMIC coupler switches to the backward mode of operation as indicated by Fig. 5.17. For both modes of operation, the MMIC coupler has an isolation level higher than 42dB and a return loss that is less than -20dB. Furthermore, in both modes of operation 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 158

0 S 21 −5 S 31 −10 S 41 −15 (dB) −20

−25

−30 S−parameters −35

−40

−45 1.5 2 2.5 3 Frequency (GHz) Figure 5.16: Measured MMIC coupler S-parameters vs. frequency. Case 1: forward operation, the input power is equally divided between ports 3 and 2 while port 4 is isolated.

0 S 21 −5 S 31 −10 S 41 −15 (dB) −20

−25

−30 S−parameters −35

−40

−45 1.5 2 2.5 3 Frequency (GHz) Figure 5.17: Measured MMIC coupler S-parameters vs. frequency. Case 2: backward operation, the input power is equally divided between ports 3 and 4 while port 2 is isolated. 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 159

140 Forward Backward 130

120 (deg) 110

100

90 ← → 94±2o over

Differential phase 80 a bandwidth of 0.3GHz 70

60 2 2.2 2.4 2.6 2.8 3 3.2 Frequency (GHz) Figure 5.18: Diﬀerential phase response of the MMIC coupler vs. frequency for the forward and the backward modes of operation.

the output power is divided equally between the two output ports; P3 and P2 in the forward case, and P3 and P4 in the backward case. In the backward mode of operation, the MMIC coupler achieves a differential phase (between P3 and P4) of 94±2o across a 0.3GHz bandwidth centered around the design frequency. However, when the MMIC coupler is configured to operate in the forward mode of operation, the asymmetry in the layout of the MMIC coupler, described in section 5.4.1, results in some offset in the differential phase between the output ports (P3 and P4), which becomes 98.6o. This is shown in Fig. 5.18, which plots the differential output phase for both cases. This differential phase offset can be eliminated by positioning the MMIC coupler circuit in the center of the fabricated chip to make the interconnecting lines from the MMIC coupler circuit to the RF pads symmetrical. However, in this fabricated prototype the test structures were positioned in between the MMIC coupler circuit and the left-side RF pads due to area constraints. One potential application for this mode of operation is to connect the TX and RX ports of a transceiver to its antenna (duplexing) while providing very high isolation. This is shown in Fig. 5.19, where in Fig. 5.19-a, the coupler is configured to operate 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 160

Monitoring Monitoring Antenna device Antenna device (1) (2) (1) (2)

TX: Isolated RX TX RX: Isolated (4) (3) (4) (3)

(a) (b) Forward operation: Receive mode, Figure 5.19: Duplexer operation (a) Receive mode is achieved by conﬁguring the coupler in the forward mode. (b) Transmit mode is achieved by conﬁguring the coupler in the backward mode.

in the forward mode. Hence, if the coupling coefficient, C, is configured to a very low value (1.4dB), then most of the received power is directed to the receiver and only a small portion goes to the through port, which could be connected to a monitoring device to control the gain of the programmable LNAs in the receiver. Furthermore, the TX port is isolated from the received signal. On the other hand, when transmitting, the reconfigurable coupler is switched to the backward mode of operation. As shown in Fig. 5.19-b, the input port of the coupler becomes port 4, which is connected to the TX port. However, since the coupler is operating in the backward mode, the transmitted signal is now isolated from the RX port and is divided among the antenna and the monitoring device. In this case, the coupling coefficient can be configured to have a very high value (7.1dB). Hence, most of the transmitted signal power is directed towards the antenna. Finally, with measured operating frequencies ranging from 2.15GHz to 3.1GHz, the proposed design would be a suitable duplexer for multi-band applications.

The power dissipation of the proposed coupler, as it stands, is too high to be used in portable transceivers, which tend to have low-power requirements. One possible method to reduce the power consumption is to switch between more than one TAI circuit in order to cover the required inductance tuning range. Hence, instead of in-

creasing the bias currents of transistors M1, M2, and M4 in Fig. 3.5, the TAI circuit responsible for small inductances can use a larger gate width for transistors M1 and

M2 and a smaller width for M4. This follows from Eq.(3.20), which can be re-written 5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 161

−3 0

−4 −10 ← −5 −20

−6 → −30 at 2.6GHz (dB) 2.6GHz at at 2.6GHz (dB) 2.6GHz at 41

31 −7 S

& S −40

21 −8 S Isolation −50 −9

−10 −60 −25 −20 −15 −10 −5 0 Input power level (dBm)

Figure 5.20: Measured S21 and S31 at 2.6GHz on the left and S41 at 2.6GHz on the right vs. the input power level.

Table 5.3: Linearity Comparison Between Diﬀerent TAI based Couplers Speciﬁcation [86] This work 1dB compression point (P1dB) -16dBm -4.16dBm Isolation (S41) at P1dB – -28.3dB

as: s C W L ∝ gs4 ∝ 4 , (5.20) gm1,2gm4 IM1,2W1,2 × IM4 where Wi and IMi are the width and bias current, respectively, of transistor Mi in Fig. 3.5. Another method is to use a single TAI circuit, but replace each of the transistors M1, M2, and M4 with more than one parallel-connected transistors. Hence, instead of increasing the bias current, the TAI inductance can be decreased by appropriately switching in and out transistors.

Linearity measurements

To characterize the linearity of the MMIC directional coupler, the circuit is biased to operate at the nominal frequency of 2.6GHz. The input power of a 2.6GHz signal is 5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE 162 swept from -20dBm to 0dBm and the resulting S-parameters are plotted in Fig. 5.20. The MMIC coupler achieves a 1-dB compression point of -4.16dBm, which corresponds to a peak-to-peak voltage swing of 391mV at the MMIC coupler input port while operating from a 1.5V supply. Also, as indicated by Fig. 5.20, as the input power increases the isolation of the MMIC coupler drops and reaches a value of 28.3dB at the 1-dB compression point. For input powers below -17dBm the isolation appears to remain unchanged at approximately 55dB, which is due to the limited dynamic range of the measurement setup. Table 5.3 summarizes the linearity performance of the proposed MMIC coupler and compares it with the TAI-based coupler presented in [86]. Although the proposed coupler achieves a signiﬁcantly higher 1-dB compression point compared to the TAI-based coupler in [86], its limited power handling capability precludes its use in base stations. However, it can ﬁnd applications in short-range wireless applications requiring low transmit power levels such as wireless sensor networks (WSN) and RF applications using ZigBee.

5.5 Eﬀect Of The TAI On The Coupler Noise Performance

Combining the use of varactors and TAIs to implement this MMIC directional coupler have made it a versatile highly-reconfigurable coupler capable of operating with different coupling coefficients as well as operating at different frequencies while ensuring both a low return loss and very high isolation. Furthermore, the coupler can electronically switch between forward and backward operation. However, using active circuits and varactors to synthesize the tunable inductors and capacitors, respectively, affects the noise performance of the MMIC coupler, with the main noise contributors being the TAI circuits. Hence, this section will demonstrate the effect of the noise contribution of the TAI circuits on the MMIC coupler noise performance. Figure 5.21 shows the block diagram of the MMIC coupler when it is configured to operate in the forward mode as a 3dB coupler, which is used here to derive an expression for the output referred noise of the MMIC coupler at its through and coupled ports. The results will then be generalized for any arbitrary coupling level. The noise contribution of each of the grounded (1-port) TAI circuits is modeled by a shunt noise current source inLx where x is the port number. The relationship between these noise current sources and the noise contribution of the various TAI 5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE 163

i i Input port nL1 nL2 Through port (1) (2)

Zo inL4 inL3 Isolated port (4) (3) Coupled port

Noiseless 3dB Z Z o coupler o

Figure 5.21: Block diagram of a 3dB coupler with the noise current sources representing the eﬀect of the active circuits within the TAIs.

circuit elements (the transistors and the feedback resistor Rf ) was presented in section 3.4.3. It is interesting to note that each of the noise sources of Fig. 5.21 sees the same impedance, which is the parallel combination of the source impedance (Zs = Zo)

and the input impedance of the coupler Zin. This fact facilitates the calculation of the output referred noise voltages of the MMIC coupler. Assuming that the noise generated by the TAI circuits is uncorrelated, one can use superposition to show that, the mean-square value of the output referred noise voltage at the through port P2 is expressed as:

(Z ||Z (ω))2 ³ ´ v2 (ω) = o in × i2 (ω) + 2i2 (ω) + i2 (ω) . (5.21) n2 2 nL1 nL2 nL4

If the average noise power generated by the four TAI circuits is the same (i2 = i2 = nL1 nL2 i2 = i2 ), this results in the following: nL3 nL4

2 2 2 vn2(ω) = 2 (Zo||Zin(ω)) × inL(ω). (5.22)

At the design frequency, the coupler input impedance is equal to Zo in order to achieve good power matching. Hence the output referred noise voltage can be re-written as:

Z2 v2 (ω ) = o × i2 (ω ). (5.23) n2 o 2 nL o 5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE 164

To obtain an expression for the total output noise, the noise contribution of the source/termination impedances should be accounted for. Assuming that the noise sources associated with each port are uncorrelated, the expression of the output referred noise voltage becomes:

Z2 Z2 ³ ´ v2 (ω ) = o × i2 (ω ) + o × i2 + i2 , (5.24) n2 o 2 nL o 8 ns1 ns4

2 where insx = 4kT/Zo is the thermal noise current generated by the source/termination impedance at port x. Since the noise power generated by all the source/termination impedances are equal, the total output referred noise voltage at the through port P2 can be re-written as: Z2 Z2 v2 (ω ) = o × i2 (ω ) + o × i2 . (5.25) n2 o 2 nL o 4 ns From the symmetry of the coupler circuit, one can show that the output referred noise voltage at the coupled port P3 is identical to that of the through port P2 given by Eq.(5.25). Equation (5.25) also indicates that minimizing the noise current of the TAI circuits is essential for optimizing the MMIC noise performance.

If the coupler is re-conﬁgured to operate with any arbitrary coupling level C, the output referred noise voltage at the through port P2 becomes:

2 2 2 2 i (ωo)Z ¡ ¢ i (ωo)Z v2 (ω ) = nL1 o × 1 − A2 + nL2 o + (5.26) n2 o 4 4 2 2 2 2 2 2 i (ωo)Z Z i ¡ ¢ Z i nL4 o × A2 + o ns1 × 1 − A2 + o ns4 × A2, 4 4 4

where the factor A is given by A = 10−C/20. Again, assuming that the average noise power generated by the four TAI circuits is the same, one obtains the same expression of Eq.(5.25) for the output referred noise voltage at the through port. Hence, the noise at the through and coupled ports remains the same for any arbitrary coupling level C achieved by the MMIC coupler.

Substituting with the expression of the TAI’s noise current, given by Eq.(3.26), which 5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE 165

was derived in chapter 3, the output referred noise voltage becomes:

2 2 vn(ωo) ≈ kTZo + 2kT Zo γ (gm4 + gm5)

2 2 2 2gm1,2 + gm3 Rf (1 + ωo Co Ro) + gm12 + 2 2 2 4 γRo +2kT Zo γgm4 × µ µ ¶¶2 , (5.27) 2 Rf ωo Co + Cgs4 1 + Ro where k = 1.38 × 10−23 J/K is the Boltzmann constant, and T is the absolute temperature in degrees Kelvin. The value of the coefficient γ typically ranges from 2 to 3 for short-channel transistors [83]. To verify the expression of Eq.(5.27), noise simulations were carried out for the MMIC coupler while configured to operate as a 3dB coupler. The simulated MMIC √ coupler output noise voltage, v , and the TAI noise current, i , were 5.25nV/ Hz √ n nL and 0.17pA/ Hz respectively at the design frequency. On the other hand, the corresponding noise voltage and current obtained from using the theoretical expression √ √ of Eq.(5.27) and Eq.(3.26) are 6.2nV/ Hz and 0.2pA/ Hz respectively. This shows that Eq.(5.27) provides a fairly accurate representation of the MMIC directional coupler noise. To minimize the noise of the MMIC coupler, one should design the TAI circuit using small values for the transistor transconductances, as well as design the differential pair

to achieve a large output resistance Ro. On the other hand, large transconductances are required to achieve the low inductance values which are necessary for configuring the coupler to operate at high frequencies. Hence, a tradeoff exists between the maximum frequency of operation and the noise generated by the MMIC coupler. In a telecommunication system, the effect of the noise generated by the MMIC coupler on the overall noise figure can be reduced by preceding it with a low noise amplifier [23]. CHAPTER 6

Electronically Steerable Series-Fed Patch Array

6.1 Introduction T he majority of consumer wireless applications use omni-directional antennas, and, in some cases, antenna arrays are employed, producing narrow beams and providing better wireless coverage for speciﬁc, ﬁxed areas. However, the lack of compact electronically tunable phase shifters that can easily be integrated with printed antennas has hindered the use of electronically steerable phased arrays in most wireless consumer applications, and limited the use of electronic beam steering to high-precision, military radar systems and satellite communications. As explained in chapter 2, the compact feed network of a series-fed array is one of the main advantages which make it more attractive as opposed to its parallel- or corporate- fed counterparts. Besides compactness, the small size of series-fed arrays results in less insertion loss and less radiation by the feed network. Also, the cumulative nature of the phase shift in series arrays relaxes the design constraints on the phase tuning range of the interstage phase shifters. For example, an N-element series-fed design can achieve

166 6.1. INTRODUCTION 167

the same scan angle range as a parallel-fed design with (N-1) times less phase tuning range. However, this cumulative nature also results in increased beam squintinga with frequency variations, which is one of the main limitations in series-fed designs. Another design challenge for series-fed designs is the tight limitations set on the size occupied by the interstage phase shifters, as well as on the variation in its input impedance across its phase tuning range. Furthermore, in most applications it is desired to center the main beam about the broadside direction, which is achieved by feeding the individual antennas, of a uniform array, in-phase. This implies that an inter-element phase shift of zero-degrees is required. Moreover, to scan the angle of the main beam about the broadside direction, the interstage phase shifters have to be capable of generating both positive and negative phase shifts. Traditionally, phase shifters have employed either a low-pass or a high-pass topology. Hence, the in-phase feeding of the antennas was achieved by feeding them with an inter- element phase shift of -360o or +360o, respectively. This, however, requires cascading multiple stages, or using meandered delay lines to achieve such large phase shifts, potentially increasing the size and insertion loss of the phase shifters. This also increases the group delay of the phase shifters, which in turn results in more beam squinting. With the recent developments in the ﬁeld of metamaterials [3, 4], it is now possible to design compact PRI/NRI phase shifters having phase shifts centered around the zero-degree mark and at the same time having small group delays [5]. The work in [5] was combined with CMOS microelectronic circuit techniques in chapter 4 of this thesis to build printed as well as fully-integrated compact tunable PRI/NRI phase shifters by using both varactors and TAIs. These tunable PRI/NRI phase shifters also feature constant input impedance and are capable of producing both positive and negative phase shifts. The compact size of these PRI/NRI phase shifters allows them to be integrated with series-fed antenna arrays onto a single PCB. The resulting planar structure is more appealing for low-cost wireless consumer applications, as opposed to traditional designs in which the phase shifters and the antennas are implemented on separate PCBs [98]. Furthermore, using the PRI/NRI phase shifters allows centering the main beam of the array at the broadside direction and electronically scanning it in both directions. In contrast, in the majority of the previously published designs this

aBeam squinting is deﬁned here as the variation in the angle of the main beam of the antenna array with frequency. 6.2. THEORY 168

is achieved by physically terminating the input port and exciting the array from the opposite port [98–100]. PRI/NRI phase shifters have been employed in [101] to design a high-gain leaky-wave antenna array. This array is capable of electronically scanning its main beam about the broadside direction, achieving both positive and negative scan angles. However, using only varactors as the tunable elements results in a poor return loss for the antenna array across its entire scan angle range, with a best case of -12.5dB and a worst case of -6dB. Furthermore, the leaky-wave design results in a very large gain degradation of 55% when the beam is merely scanned beyond ±6o off the broadside direction. In this chapter, an electronically steerable, series-fed patch array for 2.4GHz ISM band applications is presented. The entire antenna array (i.e. the antennas, phase shifters, and the feed network) is integrated onto a single PCB. The proposed steerable array uses zero-degree tunable PRI/NRI phase shifters to center its radiation about the broadside direction and allow scanning in both directions off the broadside. Also, using these PRI/NRI phase shifters minimizes the squinting of the main beam across the operating bandwidth. Furthermore, the feed network of the proposed array utilizes λ/4 impedance transformers, which allows using identical interstage phase shifters, and the sharing of the same control voltages to tune all stages. To the author’s knowledge, the proposed antenna array is the first resonant antenna-element structure that demonstrates electronic beam steering utilizing tunable PRI/NRI phase shifters. The proposed steerable array uses the TAI-based, TL zero-degree PRI/NRI phase shifters presented in chapter 4 in order to extend the scan angle range and at the same time maintain a low return loss. Furthermore, the proposed array is capable of steering its beam with small variations in its gain and its HPBW.

6.2 Theory

6.2.1 Antenna Array Architecture

The electronically steerable antenna array presented in this chapter consists of four series-fed antennas and three interstage phase shifters as depicted by the basic architecture in Fig. 6.1. The array has a travelling-wave nature, however, it is not terminated with a 50Ω load impedance as in traditional travelling-wave designs. Instead, the real 6.2. THEORY 169

dE< T

PS PS PS

ZPS1 ZPS2 ZPS3

Figure 6.1: Basic 4-element series-fed antenna array.

dE< T

PS PS PS

ZPS ZPS ZPS

Figure 6.2: 4-element series-fed antenna array with λ/4 impedance transformers. part of the antenna impedances are used as the termination for the array. Eliminat- ing the load impedance improves the overall efficiency of the array, since it suppresses the power dissipated in the termination, which could be on the order of 12.5% of the input power as in the 5-element series-fed patch array in [99, 100]. For such an array configuration, the standard and simplest design approach used in previously published work (for example [98]) to feed the antennas is to progressively change the characteristic impedance of the main feed line in order to maintain good matching for the array. This, however, requires all the interstage phase shifters to have different impedance levels, which complicates the array design by requiring different interstage phase shifter designs. Furthermore, it complicates the process of electronic scanning by requiring a separate set of control voltages to be applied to each interstage phase shifter. An alternative approach is proposed in this chapter to allow using identical interstage phase shifters, and to permit using a single set of control voltages to tune all the stages. In this architecture, two λ/4 transformers are inserted before and after each interstage phase shifter, which helps set the impedance level of the feed line to the value required by the phase shifters (ZPS). Hence, the impedance of the λ/4 transformers is 6.2. THEORY 170 adjusted to achieve the desired matching, while keeping all the interstage phase shifters identical. This allows using a single set of control voltages for tuning all the stages simultaneously, thereby simplifying the steering of the antenna beam. Furthermore, if constant input impedance phase shifters are utilized, the return loss of the series-fed array can be minimized across the entire phase tuning range, or in other words, across the entire scan-angle range. Moreover, these λ/4 transformers allow one to control the power splitting ratios at each junction in Fig. 6.2, which helps ensure equal amplitude excitation for the individual antennas. This will be described in more detail later in section 6.2.2.

In the array architecture of Fig. 6.2, each λ/4 transformer contributes a -90o phase shift. Hence, the total cumulative phase shift from one antenna to the next, φT , is given by: π φ = −2 × + φ . (6.1) T 2 P S To achieve the desired broadside radiation, the antennas need to be fed in-phase, i.e.

φT = 0, which according to Eq.(6.1) requires the phase response of the interstage o phase shifters φPS to be centered around +180 . But as described above, such large phase shifts result in large group delays, which, in turn, will result in increased beam squinting.

To address this problem, the array architecture in Fig. 6.2 is modiﬁed by alternating the antennas with respect to the feed line as shown in Fig. 6.3. Alternating the antennas is a known technique for the design of series-fed arrays. However, this is the ﬁrst time it has been used with tunable metamaterial PRI/NRI phase shifters to realize an electronically steerable phased array. To achieve broadside radiation using the proposed o alternating architecture, the total cumulative phase shift φT should be set to 180 , which is already realized by the intrinsic phase shift of the two λ/4 transformers. Hence, according to Eq.(6.1) the interstage phase shift φPS should be centered around the zero- degree mark. This means that the alternating series-fed array architecture of Fig. 6.3 can take advantage of the recent developments in small group delay metamaterial PRI/NRI phase shifters to scan the main beam about the broadside direction, and at the same time, minimize beam squinting. 6.2. THEORY 171

(1:3) PA ¾ PA

¼ PA dE< Z in1 Z ABCZPS ZPS PS PS PS PS Z ZT2 ZT1 ZT7 ZT6 ZT5 ZT4 T3

(1:1) P ̃ B PC ½ PC

P P B ̄ B ½ PC (1:2)

Figure 6.3: Alternating patch array diagram indicating the required ideal power splitting ratios and all the λ/4 transformer impedances.

6.2.2 Feed Network Design

As described in section 6.2.1, the feed network of the antenna array uses λ/4 impedance transformers, which allows us to use identical interstage phase shifters (i.e. the phase shifters have the same phase shift φPS and the same impedance ZPS). Also, to simplify the design, we use 4 identical antennas which have the same real input impedance, ZA, at the design frequency. Starting the design of the feed network from the right-side of

Fig. 6.3, the characteristic impedance of the ﬁrst λ/4 transformer, ZT 1, should be set to: p ZT 1 = ZAZP S (6.2) in order to guarantee that this interstage phase shifter is properly terminated and consequently eliminate any reﬂections at its input and output ports. On the other hand, the second λ/4 transformer, ZT 2, gives us an additional degree of freedom to adjust the impedance level which is loading the main feed line at junction C. One should design this impedance level for a 1:1 power splitting ratio at junction C to achieve equal amplitude excitations for the last 2 antennas. This, however, is only valid under the assumption that the interstage phase shifters are lossless. Later on we will demonstrate how the phase shifter loss can be incorporated in the design to still 6.2. THEORY 172

maintain the equal amplitude excitation. For the lossless case, the loading impedance

to the left side of junction C, Zin1 in Fig. 6.3, should be set to ZA. This is satisﬁed if the second transformer has an impedance of: p p ZT 2 = Zin1ZP S = ZAZP S. (6.3)

Following the same procedure, one can derive the values of the characteristic impedances of all the λ/4 transformers, which are given by the following equations: r Z Z Z = Z = A P S , (6.4) T 3 T 4 2 and r Z Z Z = Z = A P S . (6.5) T 5 T 6 3 The power splitting ratios are shown in Fig. 6.3. Note how the power splitting ratio changes for each junction; at junction B, 1/3 of the power should be delivered to the antenna whereas 2/3 of it should be directed to the subsequent stages, i.e. the power splitting ratio should be 1:2. Similarly, at junction A, 1/4 of the input power should be delivered to the antenna whereas 3/4 of it should be directed to the subsequent stages, i.e. the power splitting ratio should be 1:3. Constraints represented by Eq.(6.2)-(6.5) ensure the same amount of power is delivered to all the antennas regardless of the power division happening at each junction. An additional λ/4 transformer is added at the input port of the series-fed array in order to match its input impedance to the

source impedance, Zo. Hence, the characteristic impedance of the input transformer is expressed as: r Z Z Z = A o . (6.6) T 7 4 The feed network presented in [98] uses a similar approach to achieve equal power splitting. However, the power splitting ratios at each junction are adjusted by varying the impedance level of the interstage phase shifters. In contrast, in our proposed design, this is achieved by varying the impedance of the interconnecting microstrip TLs while using identical interstage phase shifters, which allows using only one set of control voltages for beam steering. Also, as previously mentioned, the λ/4 transformers inserted before and after each 6.2. THEORY 173

interstage phase shifter ensure matching the phase shifter’s input and output impedance

ZPS to its source and load impedances, respectively. Hence, when the electrical length

(or the phase shift φPS) of the interstage phase shifters is varied to scan the angle of the main beam, the input impedance of the entire series-fed array remains unchanged.

This ensures a low return loss, S11, for the array for all scan angles. However, this is

only valid as long as the interstage phase shifters can provide a ﬁxed impedance ZPS across their entire phase tuning range, which imposes an important constraint on the interstage phase shifter’s design. This will be explored in more detail in section 6.2.3.

If the interstage phase shifters have a finite insertion loss which can be represented by their forward transmission coefficient S21, one can show that the power splitting ratios at junctions A, B, and C should be modified to 1 : (1 + G + G2)/G3, 1 : (1 + G)/G2, and 1 : 1/G, respectively, where the factor G represents the absolute power gain of

S21/10 the interstage phase shifters given by G = 10 , where S21 is in dB. Consequently, the characteristic impedance of the diﬀerent λ/4 transformers need to be adjusted according to the following equations: p p ZT 1 = ZAZP S, and ZT 2 = ZAZP SG, (6.7) r r Z Z G Z Z G2 Z = A P S , and Z = A P S , (6.8) T 3 1 + G T 4 1 + G r r Z Z G2 Z Z G3 Z = A P S , and Z = A P S , (6.9) T 5 1 + G + G2 T 6 1 + G + G2 r Z Z G3 Z = o A . (6.10) T 7 1 + G + G2 + G3 Equation(6.7)-(6.10) ensure delivering the same amount of power to all the antennas regardless of the interstage phase shifter losses, and regardless of the power division taking place at each junction. Furthermore, one can extend this analysis to obtain an expression for the eﬃciency of the proposed feeding network, which can be expressed as follows: P4 3 i=1 Pantenna,i 4G ηfeed = = 2 3 (6.11) Pin 1 + G + G + G

Table 6.1 lists the achievable eﬃciency by the proposed feed network for diﬀerent 6.2. THEORY 174

Table 6.1: Series Feed Network Eﬃciency For Diﬀerent Interstage Phase Shifter Loss Values

S21 G ηfeed 0dB 1 100% -0.5dB 0.89 83% -1dB 0.79 68% -1.5dB 0.71 56% -2dB 0.63 44% values of the interstage phase shifter loss. It is clear from the table that using this series architecture puts tight constraints on the interstage phase shifter losses. To demonstrate how much the antenna power mismatch can be reduced by using the proposed approach, Fig. 6.4 plots the maximum power mismatch, calculated between the first and the fourth antennas versus the interstage phase shifter losses, |S21|. The maximum power mismatch shown in Fig. 6.4 is computed for two different designs. The first design employs only power splitting ratio compensation. Hence, the phase shifters are assumed lossless in the design phase and Eq.(6.2)-(6.5) are used to size the transformers. As the figure indicates, the power mismatch is only zero when the phase shifter losses |S21|=0dB, and increases for higher values of |S21|. On the other hand, the second design employs both phase shifter loss and power splitting ratio compensation. A phase shifter loss of 1.5dB is assumed in the design phase and Eq.(6.7)-(6.10) are used. Here we see that the location of the zero power mismatch has moved to the point where |S21|=1.5dB. Consequently, when the phase shifters have a loss of 1.5dB, this approach reduces the worst case power mismatch between the antennas by 64%. Mismatches in the signal power feeding the antennas will affect the radiation pattern of the array, which is a function of both the amplitude and the phase of the array excitation. Figure 6.5 shows the normalized array factor for the previous two designs (i.e. the design employing only power splitting ratio compensation and the one employing both phase shifter loss and power splitting ratio compensation), and compares them with the array factor of a standard array which does not employ any type of compensation and assumes that the signals split equally at each junction. All three designs assume a 4-element, λo/2 array, and a phase shifter loss |S21| of 1.5dB. As indicated 6.2. THEORY 175

60 ↑

(%) 40 64% reduction 20 in power mismatch↓ 0

Power mismatch −20 w power splitting comp. −40 w PS loss and power splitting comp. −60 0 0.5 1 1.5 2 2.5 3 Interstage phase shifter loss |S | (dB) 21

Figure 6.4: Power mismatch between the ﬁrst and fourth antennas versus the interstage phase shifter insertion loss for two diﬀerent cases: (a) array designed with power splitting ratio compensation, (b) array designed with both phase shifter loss and power splitting ratio compensation.

−15° 0° 15° −30° 30° −45° 45°

−60° 60°

−75° 75° 0 −20 −10 −90° −40 −30 90° w/o comp. w power splitting comp. w PS loss and power splitting comp.

Figure 6.5: Normalized array factors for a 4-element λo/2 antenna array designed for three diﬀerent cases: (a) the standard design without compensation and assuming the signals split equally at each junction, (b) designed with power splitting ratio compensation, (c) designed with both phase shifter loss and power splitting ratio compensation. 6.2. THEORY 176 by the ﬁgure, reducing the power mismatch by employing compensation enhances the quality of the radiation patterns by increasing the antenna rejection at the pattern nulls. This is achieved at the cost of a 0.6dB drop in the gain of the antenna array.

6.2.3 Interstage Phase Shifters

As previously described in section 6.2.1, in order to center the radiation pattern of the proposed antenna array at the broadside direction, tunable zero-degree phase shifters should be used to implement the interstage phase shifters. As demonstrated in chapter 4, PRI/NRI phase shifters are capable of centering their phase response around the zero-degree mark, and are capable of generating both positive and negative phase shifts. This makes tunable PRI/NRI phase shifters a suitable choice to implement the interstage phase shifters. Furthermore, the tunable PRI/NRI phase shifters presented in chapter 4 are capable of maintaining a constant impedance, ZPS, across their entire phase tuning range. This was achieved by employing both varactors and TAIs. Having a constant impedance is important to provide the array with a low return loss across its entire scan-angle range. It also helps to minimize the mismatch in the power level feeding the different antennas, since the power splitting ratios are determined by the impedance levels. Furthermore, these PRI/NRI phase shifters possess small group delays, which is important to achieve low beam squinting. In order to quantify this, Eq.(A-3) in Appendix A gives the relationship between the variation in the azimuthal angle, θ, of the main beam of the proposed antenna array and the group delay, Tgd, of the interstage phase shifters. The key result is that one should try to minimize Tgd in order to reduce the effect of frequency on the direction of the main beam. This makes the tunable PRI/NRI phase shifters of chapter 4 suitable for the implementation of the interstage phase shifters. Among the different tunable PRI/NRI phase shifters presented in chapter 4, the TL-based design seemed a natural choice, due to several reasons. First of all, it can be easily integrated onto the same PCB with the feed network, and the printed antennas. Secondly, it provides the lowest insertion loss, and the highest FOM, i.e. the highest phase tuning range per dB of loss. Also, the TAI package parasitics were already accounted for during the design phase of the TL PRI/NRI phase shifter, and no additional packaging was required. This made the tunable TL PRI/NRI phase shifter 6.2. THEORY 177

Figure 6.6: Transmission-line tunable PRI/NRI metamaterial phase shifter unit-cell. more attractive for the design of the proposed printed antenna array. The design of the TL PRI/NRI phase shifter was described in detail in chapter 4. However, for completeness, some of the relevant design equations are brieﬂy highlighted in this section. Figure 6.6 shows the unit-cell of the TL tunable PRI/NRI phase shifter, which is composed of a regular microstrip line, with a characteristic impedance Zo. The microstrip line is loaded with two series varactors, with capacitance C, and a shunt TAI, L. Cascading the PRI TL with the NRI section (i.e. the series capacitors and shunt inductor in Fig. 6.6) compensates the phase shift incurred by the propagating signal. The phase shift of the PRI/NRI phase shifter unit-cell can be approximated as: √ 2 φ ≈ √ − 2θT L (6.12) ω LC where θTL is the phase lag due to one section of the PRI microstrip TLs, given by

θTL = βTLdPS/2. Equation (6.12) indicates that positive and negative phase shifts can be realized by a single unit-cell without having to go through a complete 360o phase rotation as in traditional high-pass or low-pass architectures. This inherently guarantees a small group delay for these phase shifters, which is expressed as: Ã √ ! dφ 1 2 Tgd = − ≈ √ + 2θTL . (6.13) dω ω ω LC 6.3. ANTENNA ARRAY DESIGN 178

One can intuitively understand this small group delay nature by investigating Eq.(6.12) and Eq.(6.13) simultaneously; Eq.(6.12) indicates that one achieves the zero phase without the need for large values by either of its two terms, i.e. +2π by the NRI section as in a traditional high-pass design, or -2π by the PRI section as in a traditional low- pass design. Alternatively, the zero phase is achieved by having two small and equal contributions from the NRI and PRI sections, which eventually cancel-out due to the negative sign in Eq.(6.12). Now looking at the group delay expression of Eq.(6.13), in which the two terms add-up, one can see that the small phase contributions by the NRI and PRI sections will automatically result in a small group delay. The phase response of the PRI/NRI phase shifter is tuned by simultaneously changing the values of both the loading elements L and C. This is achieved by using both TAIs and varactors, and results in a larger phase tuning range compared to varying C only as was demonstrated in chapter 4. Furthermore, changing L and C simultaneously according to the following equation, r 2L Z = (6.14) o C where Zo is the microstrip TL characteristic impedance, will result in a constant phase

shifter impedance, i.e. ZPS = Zo, and consequently result in a low return loss across the entire phase tuning range.

6.3 Antenna Array Design

A 4-element series-fed array is designed to operate in the 2.4GHz ISM band. The array is based on the proposed alternating architecture of Fig. 6.3, and uses the TL tunable PRI/NRI phase shifters of chapter 4 to implement the three interstage phase shifters. Four identical λ/2 resonant rectangular patches are used as the antenna elements. Although patch antennas have a relatively small impedance bandwidth, they are used here for their simplicity. In order to be able to integrate the patches and the beam steering network onto the same PCB, the interstage phase shifter and the two λ/4 transformers have to ﬁt between each pair of consecutive patches, which might imply increasing the inter-element distance, dE, to accommodate them. On the other hand, it is important to avoid capturing grating lobes in the radiation pattern, which can be 6.3. ANTENNA ARRAY DESIGN 179

guaranteed if the following condition is satisﬁed:

λ d ≤ o , (6.15) E 2 where λo is the free-space wavelength. Eq.(6.15) is a fundamental equation, since it sets the maximum distance between each two consecutive patches. Consequently, this sets tight limitations on the interstage phase shifter dimensions. In this design, the

inter-element distance was chosen to be λo/2 in order to avoid capturing any grating lobes in the radiation pattern, and at the same time provide the maximum allowable space, which corresponds to an inter-element distance dE of 6.25cm at 2.4GHz.

To increase the phase tuning range and consequently the scan-angle range, two unit- cells of the TL PRI/NRI phase shifter shown in Fig. 6.6 are cascaded to form each interstage phase shifter. This will double the phase tuning range, while having a minor eﬀect on the phase shifter return loss S11. However, this will increase the interstage phase shifter insertion loss. The average insertion loss of the PRI/NRI phase shifter unit-cell was extracted from simulations to be 0.77dB, resulting in an average interstage phase shifter loss of 1.55dB. This estimated loss was used in the design of the feed network by using Eq.(6.7)-Eq.(6.10) to size the transformers.

Integrating the antenna array, feed network, and phase shifters onto a single-layer PCB prevents us from designing each one of them independently, and forces us to treat their design as three coupled designs. For instance, if one would design the patches separately, a low substrate relative permittivity, ²r, and would be desirable in order to increase the patch bandwidth and at the same time its radiation efficiency. On the other hand, one has to trade-off between the patch bandwidth and efficiency when choosing the substrate thickness, h [102]. However, a lower ²r entails longer λ/4 impedance transformers and longer PRI/NRI phase shifters, as now we require a longer microstrip TL to compensate for the positive phase shift from the NRI section. This becomes evident by re-writing the phase shift expression of the PRI/NRI unit-cell as: √ 2 ωdPS √ φ ≈ √ − ²eff , (6.16) ω LC c

where ²eff is the eﬀective relative dielectric constant of the phase shifters’s microstrip 6.3. ANTENNA ARRAY DESIGN 180

TLs [24], and is given by:

²r + 1 ²r − 1 1 ²eff = + × p . (6.17) 2 2 1 + 12h/W

In Eq.(6.17), h and W are the substrate height and the microstrip TL width, respectively. Now by looking at Fig. 6.3, one can see that the λ/4 impedance transformers

and the interstage phase shifter have to ﬁt in a ﬁxed distance, dE, to avoid meandering

the lines. Consequently, ²r can not take an arbitrarily small value. Furthermore, we

will show that for a given value of the positive phase shift, φNRI , from the NRI section,

there exists an optimum value for ²r, that will allow centering the radiation around the broadside direction, and at the same time satisfy the physical constraints imposed by the requirement for a single PCB implementation. This physical constraint simply requires that the sum of the lengths of the two λ/4 transformers and the interstage

phase shifter to be λo/2, i.e.:

λ λ d = o = × 2 + 2d , (6.18) E 2 4 PS √ where λ = λo/ ²eff is the guided wavelength, and the factor 2 in the second term is added to account for the cascading of two PRI/NRI unit-cells for each interstage phase shifter. However, this assumes that the two λ/4 transformers have the same ²eff , which neglects the change in their width. For the sake of simplicity, all the microstrip TLs

are assumed to have an equal ²eff , which represents an average value for the diﬀerent width TLs. Equating Eq.(6.16) to zero and solving it with Eq.(6.18) results in the following expression for the optimum substrate dielectric constant: µ ¶ φ 2 ² = 1 + 2 NRI , (6.19) eff π where φNRI is the average phase shift generated by the NRI section, which is expressed as: √ 2 φNRI = √ . (6.20) ω LC Now substituting the result of Eq.(6.19) in Eq.(6.16), one can obtain the length of the TL PRI/NRI phase shifter unit-cell required for broadside radiation. This results in 6.3. ANTENNA ARRAY DESIGN 181

the following expression: φNRI dPS = λo √ . (6.21) 2π ²eff

As Eq.(6.19) and Eq.(6.21) indicate, the design parameters ²eff and dPS are a function of the NRI section’s phase shift, φNRI . The value of φNRI can be calculated using the average TAI inductance and varactor capacitance. The average inductance generated by the TAI chips is obtained from the measurements presented in chapter 3. However, a ﬁxed 2.7nH inductance is added to the inductance values reported in chapter 3 to account for the parasitic bond wire and package inductance. The varactor capacitance values can be obtained from the matching condition, given by Eq.(6.14), 2 which results in C = 2L/ZPS. In this design, the impedance of the PRI/NRI phase

shifters, ZPS, was not set to 50Ω, but was chosen as 75Ω. This choice was made in order to extend the phase tuning range of the phase shifters, which can be expressed as: µ¯ ¯ ¯ ¯¶ Z ¯∆C ¯ ¯∆L¯ |∆φ | = PS ¯ ¯ + ¯ ¯ . (6.22) PS 2ωL ¯ C ¯ ¯ L ¯ Eq.(6.22) indicates that, for a ﬁxed inductance value, the phase tuning range can be increased by designing the phase shifters to exhibit a high impedance level. Note that the matching at the higher impedance level requires smaller capacitance values.

Now we can substitute in Eq.(6.19) to evaluate the optimum ²e, which results in a

value of 3.44. Using Eq.(6.17), one can use the value of ²eff to calculate the optimum substrate ²r. This, however, this requires knowledge of the substrate height and the average TL width. A 125mil thick substrate is chosen for the design. From simulations, this thickness allows us to achieve a reasonable trade-off between the patch bandwidth and its radiation efficiency. As for the average microstrip TL width, a reasonable assumption is to equate it to the desired width of the middle section TLs (i.e. ZT 3 and ZT 4 in Fig. 6.3), which was chosen as 2.5mm. Now one can use the correction factor h/W in Eq.(6.17) to obtain the optimum substrate relative permittivity ²r, which turns out to be 4.9. If the value of ²r obtained does not result in an adequate radiation efficiency or an adequate bandwidth for the patches, one can change the value of φNRI by picking different lumped-element values. In this design, the value of φNRI was dictated by the inductance values obtained from the fabricated TAI chips. Based on these calculations, a 125mil TMM4 Rogers ceramic substrate with an ²r of 4.5 was 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 182 selected for the design of the steerable array. This results in a length of 14.41mm for each of the TL PRI/NRI phase shifters. Electro-magnetic simulations were carried-out in Agilent-Momentum, and the results show that the length of the TL PRI/NRI phase shifters should be 14mm. This shows very good agreement between the value obtained from the theoretical expression of Eq.(6.21) and the value obtained from simulations.

6.4 Physical Implementation and Experimental Results

The proposed steerable antenna array was fabricated on a 125mil TMM4 Rogers ceramic substrate. In order to characterize the electronically steerable array, one ﬁrst needs to determine the appropriate control voltages required to obtain the diﬀerent scan angles. To this end, a separate prototype of the TL PRI/NRI interstage phase shifter was fabricated using the same substrate material and characterized.

6.4.1 Interstage Phase Shifter

A picture of the fabricated interstage phase shifter prototype is given in Fig. 6.7. It is composed of a cascade of two tunable TL PRI/NRI phase shifters. Each stage is composed of a microstrip TL loaded with 2 series SMV1232 silicon hyper-abrupt junction varactor diodes from Skyworks, and the TAI chip which uses a 4mm×4mm high-speed QFN (Quad Flat-Pack No Lead) package to minimize the package parasitics. The input and output of the interstage phase shifter are connected through the surface mount right-angled SMA connectors to the left and right sides of the board, whereas the bias and control lines going to the varactors and the TAI chips are supplied from the upper and lower sides of the board. Printed RF chokes are used to provide the varactor control voltages to the main TL while providing a high impedance at 2.4GHz for the signal on the main TL. This is achieved by connecting radial stubs through high-impedance λ/4 TLs. The minimum reliable trace width (100µm) allowed by the fabrication process was used for these λ/4 TLs to provide high isolation. Also, a set of three parallel de-coupling capacitors, 68pF each, are used to stabilize each of the bias and control voltages by providing a low-impedance path to the ground plane. The interstage phase shifter roughly occupies an area of 3.6cm×6cm. As previously mentioned in section 6.3, the interstage phase shifters are designed to exhibit an impedance of 75Ω, so in order 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 183

Tunable active Bias & control inductor (TAI) chips inputs

6cm

Varactors

Printed RF choke De-coupling 3.6cm capacitors

Figure 6.7: Photograph of the fabricated tunable TL PRI/NRI interstage phase shifter. 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 184

300

200 φ = −97o → +100o PS at 2.4GHz

(deg) ↓

PS 100 V

φ VAR increases 0

−100 ↑ Insertion phase

−200

2 2.5 3 Frequency (GHz)

Figure 6.8: The measured insertion phase φPS vs. freq. for different bias conditions. to characterize the phase shifters in a 50Ω environment, two printed λ/4 transformers were added before and after the phase shifter to match it to the 50Ω equipment. How- ever, the phase shift due to these transformers together with the connectors response were de-embedded by characterizing a TL through connection fabricated on the same substrate material. Figure 6.8 shows the measured phase response of the TL PRI/NRI interstage phase shifter when both the varactor capacitance and the TAI inductance are varied. To generate these different phase responses the varactor control voltage Vvar was swept from 3V to 15V, and for each case, the appropriate TAI control voltages that result in the desired inductance, given by Eq.(6.14), are determined. This, however, requires the characterization of the TAI chips, which was presented in chapter 3. At the design frequency of 2.4GHz, the insertion phase can be varied from -97o to +100o passing through the zero-phase point by changing the varactor control voltage from 3V to 15V, respectively. The interstage phase shifter is capable of achieving both positive and negative phase shifts at the design frequency without going through an entire 360o rotation. Furthermore, across this entire phase tuning range, the matching condition is satisfied, and the return loss, S11, is maintained below -15dB at 2.4GHz. Figure 6.9 shows the measured S11 and S21 at 2.4GHz versus the interstage phase shift. Across the 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 185

−1 −5

←

−2 −10

−3 −15

at 2.4GHz (dB) −4 −20 at 2.4GHz (dB) 21 11 S S → −5 −25

−6 −30 −100 −75 −50 −25 0 25 50 75 100 Insertion phase at 2.4GHz (deg)

Figure 6.9: Measured S21 and S11 at 2.4GHz versus the insertion phase of the interstage phase shifter.

entire phase tuning range S11 varies from -27.5dB to a worst case of -15dB at the two

extremes. Also the interstage phase shifter S21 changes from -1.6dB to a worst case of -2.4dB at the two extremes. The phase shifter achieves a bandwidth of 0.44GHz across which S11 is less than -10dB. Across the phase tuning range, the interstage phase shifter dissipates an average DC current of approximately 116mA from a 1.5V supply, which corresponds to an average power consumption of 174mW. 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 186 T1 Z T2 Z T3 Z Bias &Bias inputscontrol 22.6cm T4 Z T5 phaseshifters Z PRI/NRIinterstage T6 Z T7 Z capacitors De-coupling x PRI/NRI interstage phase shifters. 7.1cm y Steerable Antenna Array z port 6.10: Photograph of the fabricated electronically steerable series-fed patch array utilizing the tunable TL RFRX/TX 6.4.2 Figure 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 187

A picture of the fabricated 2.4GHz electronically steerable antenna array is given in Fig. 6.10. As shown in the ﬁgure, the antennas, the feed network, and the TL PRI/NRI interstage phase shifters are all fabricated on a single-layer PCB and the bottom conductor acts as the ground plane. The core of the antenna array occupies an area of 22.6cm×7.1cm and is fabricated on a 125mil TMM4 Rogers ceramic substrate with an ²r of 4.5. The RF transmit/receive signal is connected through the surface mount right-angled SMA connector on the left side of the PCB, whereas the bias and control lines going to the interstage phase shifters are supplied from the upper and lower sides of the PCB. Note that the array is fed only from one end, making it truly electronically steerable, and it does not require switching the feeding and terminating ports as in the other array designs presented in [98]- [100], where the switching is necessary to center their radiation about the broadside. The proposed array uses four identical alternating rectangular patches. The size of each patch antenna is 2.7cm(L)×3.7cm(W). The patch’s width is chosen to be longer than the length to decrease the real part of the patch impedance at resonance. This, however, is not enough to bring the patch impedance to the desired value and the inset feeding technique, which was brieﬂy described in chapter 2, is used to achieve a patch impedance ZA of 190Ω. To provide good power matching, the patches are then connected to the main feed line through 190Ω microstrip TLs. Using a characteristic impedance equal to ZA allows us to maintain good matching at the design frequency regardless of the length of these interconnecting lines, which are 7.5mm long measured from the center of the feed line to the patch edge. The value of the patch impedance was dictated by the PCB fabrication process, which allows us to use a minimum trace width of 100µm. This, in turn, results in a maximum realizable microstrip TL characteristic impedance of 190Ω. As evident in Fig. 6.10, the width of the λ/4 impedance transformers decrease as we move away from the RF port, which accounts for the increasing characteristic impedances computed from Eq.(6.7)- Eq.(6.10). To avoid having a very wide microstrip

TL for the left-most λ/4 impedance transformer ZT 7, the array is designed to have a

75Ω input impedance (i.e. Zo in Eq.(6.10) is set to 75Ω), and another tapered transformer placed right at the SMA connector is designed to match the array impedance to the 50Ω environment. Also one can see from Fig. 6.10 that the array uses identical TL PRI/NRI interstage phase shifters. The DC bias and control voltages are supplied to the TL PRI/NRI interstage phase shifters using a ribbon cable which runs underneath 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 188

the PCB, and a small 2.5mm×40mm rectangular-shaped cut in the bottom conductor (i.e. the ground plane) allows us to connect these DC voltages to the bias lines on the top side of the PCB. Another set of four parallel de-coupling capacitors (91pF, 1nF, 0.1µF, 10µF) are used to stabilize each of the bias and control voltages in Fig. 6.10 by providing a low-impedance path to the ground plane. Printed RF chokes are used to provide the varactor control voltages to the main TL, while providing a high impedance at 2.4GHz for the signal on the main TL.

Gain Patterns

The fabricated antenna array was characterized in an antenna anechoic chamber while operating in the receive mode. The measured co- and cross-polarization gain patterns and the simulated co-polarization gain patterns in the azimuth plane (i.e. the x-z plane) are presented in Fig. 6.11 for diﬀerent bias conditions. To generate these diﬀerent plots,

the control voltages of the varactors, Vvar, and of the TAI chips were obtained from the characterization of the TL PRI/NRI interstage phase shifter. For each set of control voltages, the interstage phase shifters generate a different phase while maintaining low return and insertion losses. The results in Fig. 6.11 show that the proposed array is capable of continuously steering its main beam from an angle of -27o to an angle of o +22 passing through the broadside direction by simply changing Vvar from 15V to 3.5V and accordingly adjusting the control voltages going to the TAI chips to achieve the desired inductance level. As previously explained in section 6.2, the ability to achieve both negative and positive scan angle is due to the use of the tunable PRI/NRI phase shifters. Across this entire 49o scan angle range, the gain of the antenna array varies from a maximum of 8.4dBi to a worst case of 6.9dBi and the side-lobes are at least 10dB lower than the the main-lobe. Furthermore, the cross-polarization gain is always less than that of the co-polarization by at least 14.7dB measured at the peak angles. It is worth noting that, in the proposed design, the gain variation across the entire 49o scan angle range is less than 1.5dB compared to more than 10dB gain degradation in the leaky-wave design reported in [101] when its beam is merely scanned beyond ±6o off the broadside direction. Note that the radiation patterns are not perfectly symmetric for both positive and negative scan angles. For example Fig. 6.11-b and Fig. 6.11-f have slightly different 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 189

−15° 0° 15° −15° 0° 15° −30° 30° −30° 30° −45° 45° −45° 45°

−60° 60° −60° 60°

−75° 75° −75° 75°

−90° −20 90° −90° −20 90°

−105° 105° −105° 105° −10 −10 −120° 120° −120° 120° 0 0 −135° 135° −135° 135° −150° 150° −150° 150° −165°±18010° 165° −165°±18010° 165° (a) (b)

−15° 0° 15° −15° 0° 15° −30° 30° −30° 30° −45° 45° −45° 45°

−60° 60° −60° 60°

−75° 75° −75° 75°

−90° −20 90° −90° −20 90°

−105° 105° −105° 105° −10 −10 −120° 120° −120° 120° 0 0 −135° 135° −135° 135° −150° 150° −150° 150° −165°±18010° 165° −165°±18010° 165° (c) (d)

−15° 0° 15° −15° 0° 15° −30° 30° −30° 30° −45° 45° −45° 45°

−60° 60° −60° 60°

−75° 75° −75° 75°

−90° −20 90° −90° −20 90°

−105° 105° −105° 105° −10 −10 −120° 120° −120° 120° 0 0 −135° 135° −135° 135° −150° 150° −150° 150° −165°±18010° 165° −165°±18010° 165° (e) (f)

Figure 6.11: Measured co- and cross-polarization and simulated co-polarization gain patterns in the azimuth plane (x-z plane) for different bias conditions: (a)Vvar=15V, (b)Vvar=9.5V, (c)Vvar=7V, (d)Vvar=6.5V, (e)Vvar=5V, (f)Vvar=3.5V. Solid line: measured co-polarization, dashed line: measured cross-polarization, dash dot line: simulated co-polarization. 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 190 gain and side-lobe levels. This can be attributed to two main factors; first of all, one can clearly see from Fig. 6.10 that the antenna array is not fully symmetric around the y-z plane, due to the tapering of the feed line and due to having a single input/output port. Secondly, as indicated by Fig. 6.9, the interstage phase shifters do not have the exact same insertion and reflection losses for both positive and negative phase shifts. Consequently, this would lead to different values for the gain and side-lobe levels. Figure 6.11 also compares the measured co-polarization gains with the results obtained from simulations. The figure shows good agreement between the simulated and measured results for the different bias conditions. The good agreement between the measurements and simulations was achieved by adopting a two step simulation process. First, the patches were simulated together with the feed network using the full-wave simulator of Agilent-Momentum. However, the tunable PRI/NRI phase shifters were excluded from this simulation, and instead, each end of a λ/4 transformer was terminated with a port impedance equal to that of the phase shifter ZPS (i.e. 75Ω), and the following λ/4 transformer was excited by another port with a 75Ω source impedance, and so on. But to obtain the array’s radiation pattern, we still need to determine the appropriate amplitudes and phases for the different ports. To obtain this information, the measured S-parameters of the TL PRI/NRI interstage phase shifter, presented in section 6.4.1, were used to obtain an accurate estimate of the phase shifter’s magnitude and phase responses. One can use this information together with the power splitting ratios at the three junctions of the feed network to calculate the amplitude and phase excitation at each of the ports. These results were provided to the full-wave simulation of the patches and the feed network to obtain the radiation patterns of the array. This two step process was adopted here to obtain accurate simulation results, and more im- portantly, to avoid having to include the patches, the feed network, and the tunable TL PRI/NRI phase shifters into one simulation. This separation is important since it was not possible to obtain the radiation patterns using Agilent-Momentum in the presence of the active lumped-element components, specifically, the varactors and the CMOS TAIs. The simulation procedure which was used to obtain the radiation patterns of the steerable antenna array is briefly summarized in Fig. B-2 in Appendix B. The measured peak gain of the antenna array and the HPBW are plotted in Fig. 6.12 versus the scan angle. The proposed array has a relatively constant gain across its entire 49o scan angle range, with a peak gain of 8.4dBi and a maximum gain variation of 1.5dB. 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 191

8 ← 35

6 30

4 → 2.4GHz (deg) 25

2 HPBW at Peak Gain at 2.4GHz (dBi) 20

0 15 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 Scan angle θ (deg) Figure 6.12: Measured peak gain of the antenna array and the half-power beamwidth versus the scan angle.

° −15° 0 15° −30° 30° −45° 45°

−60° 60°

−75° 75°

° ° −90 −20 90

−105° 105° −10 −120° 120° 0 −135° 135° −150° 150° ° ° −165 ±18010° 165

Figure 6.13: Measured co- and cross-polarization and simulated gain patterns in the y-z plane. Solid line: measured co-polarization, dashed line: measured cross-polarization, dash dot line: simulated co-polarization. 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 192

S < −10dB 11 0 BW = 70MHz

(dB) → ← 11 S −10

−20

−30 Antenna return loss

−40 2 2.2 2.4 2.6 2.8 Frequency (GHz)

Figure 6.14: Input return loss, S11, of the antenna array versus frequency for all the diﬀerent bias conditions given by Fig. 6.11.

This flat gain is a consequence of using the constant-impedance tunable TL PRI/NRI interstage phase shifters employing both varactors and TAIs. The constant-impedance feature is important to minimize reflections and also to minimize the mismatch in the power level feeding the different antennas, since the power splitting ratios depend on the phase shifters’ impedances. Figure 6.12 also shows that the HPBW changes from a nominal value of 25o at broadside to a worst case of 29o for positive scan angles. The measured co- and cross-polarization gain patterns of the antenna array in the y-z plane are plotted in Fig. 6.13 together with the simulated co-polarization gain pattern. These patterns were obtained with the array biased for broadside radiation.

Return Loss

Figure 6.14 shows the measured input return loss of the antenna array, S11, for all the diﬀerent bias conditions given by Fig. 6.11. Across the entire 49o scan angle range the antenna array return loss changes from a best case of -24dB to a worst case of -10dB. This low return loss is a consequence of combining the use of varactors and TAIs to design the constant-impedance tunable PRI/NRI interstage phase shifters. However, the variation in the value of the antenna array return loss for diﬀerent scan angles can 6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS 193

30 10 → 20 5

0 10 (deg)

p −5 θ (dBi) 0 p G −10 →θ = ±2o ← −10 BW = 0.3GHz −15

← Peak Gain

Main Lobe Angle −20 −20

−30 −25

−40 −30 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Frequency (GHz)

Figure 6.15: Beam squinting characteristics: antenna array main-lobe angle, θp, and the peak gain, Gp, versus frequency. be attributed to two main factors; first, as indicated by Fig. 6.9 the input impedance of the interstage phase shifters slightly varies for different phase shifts. Another source of variation for the reflection coefficient of the antenna array is the mutual coupling between the antenna array elements, as typically characterized by the active reflection coefficient. However, this design uses alternating patch antennas which minimizes the coupling between the adjacent array elements. Figure 6.14 also shows that the return loss of the array is less than -10dB across a bandwidth of 70MHz, which corresponds to a fractional bandwidth of approximately 3%. The relatively small bandwidth of the proposed design, is attributed to the narrow- band characteristics of the patch antennas and can be extended by using a more broadband antenna element.

Beam Squinting

To demonstrate the low beam squinting capability of the proposed series-fed antenna array, the array was biased to produce its main beam at the broadside direction for the design frequency (2.4GHz). Then the frequency of the transmitter was swept 6.5. ANTENNA ARRAY LINEARITY 194 from 2 to 2.8GHz, and for each frequency point the co-polarization gain pattern was measured, and these results were used to ﬁnd the angle of the main lobe, i.e. the peak gain angle θP , and the corresponding peak gain Gp. The resulting main lobe angles and peak gains are shown in Fig. 6.15 versus the transmitter frequency. Figure 6.15 o shows that the angle of the main beam, θp, remains within ±2 across a relatively wide bandwidth of 0.3GHz, conﬁrming that the beam squinting is low within this bandwidth. To be precise, the beam squints by an angle of 1.3o for each 100MHz change in the input frequency around the 2.4GHz design frequency, which, as mentioned earlier, is due to the small group delay of the TL PRI/NRI phase shifters used in the design of the series-fed array. The beam squinting can also be estimated from Eq.(A-3) in

Appendix A. The value of the group delay, Tgd, of the TL PRI/NRI phase shifters can be obtained by evaluating the derivative of the measured phase responses in Fig. 6.8. For the broadside case, the measured group delay at 2.4GHz is 0.5ns. Using this value for Tgd, the theoretical expression of Eq.(A-3) results in an estimated beam squinting of 1.29o/100MHz. This shows the very good agreement between the theoretical and measured beam squinting, as well as the accuracy of Eq.(A-3).

Also, Fig. 6.15 shows the measured peak gain Gp versus the transmitter frequency. The peak gain drops at a faster rate compared to the changes occurring in the main lobe angle θp. This, however, is attributed to the narrow band characteristics of the patch antennas, and can be solved by using more wide band antenna elements.

6.5 Antenna Array Linearity

Combining the use of the varactors and the 0.13µm CMOS TAIs to build the TL PRI/NRI interstage phase shifters allowed increasing the scan angle range as opposed to a varactor-based implementation [98–100]. Furthermore, tuning both the inductance and capacitance allowed the antenna array to achieve a low return loss and maintain a relatively ﬂat gain response across this wide scan angle range. However, using these active components imposes limitations on the antenna array’s linearity, especially since the CMOS TAIs operate from a 1.5V supply voltage. To this end, the TAIs have been designed to achieve good linearity by selecting appropriate transistor sizes and bias points, and the linearity performance of the TAIs was reported in chapter 3. To characterize the linearity of the proposed antenna array, the setup shown in 6.5. ANTENNA ARRAY LINEARITY 195

Antenna Anechoic Chamber

RX: TX: Horn Antenna Antenna array RF signal sources

f1 f2

+ RF signal combiner

Agilent E4403B Spectrum Analyzer ~6m

Figure 6.16: Experimental setup used to characterize the linearity of the steerable antenna array.

−30

−35 (dBm)

out −40 P

−45

−50 P = 4.54dBm 1−dB

Horn output power −55

−60 −15 −10 −5 0 5 10 Array input power P (dBm) in

Figure 6.17: Measured output power, Pout, of the horn antenna at 2.4GHz versus the antenna array input power Pin. 6.5. ANTENNA ARRAY LINEARITY 196

−30

−40 P at f −50 out 1 (dBm) −60

−70

−80 P at 2f −f out 1 2 −90 IIP3 = 8.85dBm Horn output power −100

−110 −15 −10 −5 0 5 10 Array input power (dBm)

Figure 6.18: Measured horn output power at the fundamental frequency f1 and at third- order intermodulation frequency 2f1 − f2 versus the antenna array input power.

Fig. 6.16 was used. The antenna array was used as a transmitter, and a standard horn antenna was used as a receiver. For the IIP3 measurement, two input tones at f1 and f2 were applied to the antenna array though an RF signal combiner. On the other hand, for the 1-dB compression point measurement, only one input tone was required, and hence the RF signal combiner was removed. For both measurements, the received signal by the horn antenna was detected using a spectrum analyzer to measure the power at the diﬀerent frequency components. A single tone at 2.4GHz was used for the 1-dB compression point measurement, and the input signal power was swept from -15dBm to 10dBm. Figure 6.17 shows the measured output power Pout, received by the horn antenna, versus the input power of the antenna array Pin. The measured results shows that the output power of the antenna array reaches its 1-dB compression point at 4.5dBm, which corresponds to a

1.1Vpp signal swing at the antenna array input. Note that, not all of this signal swing is seen at the TAI input port, as part of the input power is radiated by the ﬁrst patch.This points out the fact that the linearity of the proposed antenna array is mainly limited by the low supply voltage of the CMOS TAI chips, as it sets a limit on the maximum peak- to-peak signal swing at the TAI input port. For the IIP3 measurement the antenna 6.6. DISCUSSION AND COMPARISON 197

array is used to transmit two tones f1 and f2 at 2.4GHz and 2.41GHz, respectively, and the intermodulation products in the received signal are analyzed. The frequency separation was selected to put the two tones and their third-order intermodulation products within the antenna array bandwidth. The measured output power at the fundamental frequency f1 and at the third-order intermodulation product at 2f1 − f2 are plotted in Fig. 6.18 versus the input power level. By extrapolating the measured results, one can show that the antenna array achieves an IIP3 of 8.8dBm.

6.6 Discussion and Comparison

In the fabricated prototype of the steerable antenna array, the varactors’ and the TAIs’ control voltages going to each of the interstage phase shifters are supplied manually in order to achieve the desired scan angle. However, if this steerable array is used in a practical transceiver, a look-up table together with multiple DACs can be used to set the control voltages for each interstage phase shifter according to a single control voltage. Here, one can see the importance of having identical interstage phase shifters, as all the stages can share a single control voltage. Furthermore, the look-up tables and the DACs can be integrated on the same die with the TAI circuit, which is one of the main advantages of using a standard CMOS technology for the TAIs as opposed to using other high ft technologies such as GaAs. 6.6. DISCUSSION AND COMPARISON 198 o λ o o × 0.57 ⇒ -24dB o ⇒ +22 ⇒ 29 o o 15V 8.4dBi 1.5dB 25 This work 1.81 λ √ 2.4GHz -10dB -14.7dB 3% [email protected] √ -27 o λ o o × 0.33 o ⇒ -12.5dB -10dB ⇒ +21 ⇒ 35 o o 22 18V N/A 0 √ 4.26 λ √ -39 o o ⇒ +32 × 1.35 λ o o λ [99, 100] [101] 30V -18dB ⇒ -22dB -6dB 5 Patches 30 cell Leaky-Wave 4 Patches X 5.8GHz11.3dBi 3.33GHz 0.4dB 18dBi -10dB-12dB 13dB 4.6% -5.5dB – 0 √ +10 – t. PCB) 2.9 (PS PCB) o (An o λ 0.16 λ o × o λ × 0.49 ⇒ -17dB o λ ⇒ +30 0.31 o -10dB across the entire scan angle range. Bandwidth was not reported for the design of [101] Patches o < [98] 4 X X 2.45GHz 0 – – 24 -9dB – -13dB 1.02% 3.5V 0 1.55 + 11 S c a ) b 11 gain > -10dB for some of the reported scan angles. Antenna Arrays. tenna elements ecification 11 S Single PCB impl. Rel. side-lobe Operating frequency Fractional bandwidth Broadside scanning Ave. power dissipation Electronic scan-angle range Rel. cross-pol. Return loss ( S Max control voltage Size Gain variation HPBW Sp An Max is based on the ability to electronically scan in both directions off the broadside, i.e. without physically switching the input and terminating ports. since Gain variation is definedBandwidth here measurement as criterion: the change in the peak gain across the entire scan angle range. This able 6.2: Comparison Between The Proposed Steerable Patch Array And Other Published Series-Fed Steerable c a b T 6.6. DISCUSSION AND COMPARISON 199

Table 6.2 summarizes the performance of the proposed electronically steerable patch array with other series-fed steerable arrays presented in the literature [98–101]. The proposed design is capable of centering its radiation about the broadside direction as opposed to the designs in [98–100], which can only achieve this by physically switching the input and terminating ports. Furthermore, the proposed antenna array achieves a much wider electronic scan-angle range compared to the designs presented in [98–100]. This is due to the use of both varactors and TAIs to design the interstage phase shifters. To the author’s knowledge, the proposed antenna array is the first resonant antenna-element structure that demonstrates electronic beam steering utilizing tunable PRI/NRI phase shifters. Consequently, this series-fed design is capable of centering its radiation at the broadside direction without the need for physically switching the input and terminating ports. Moreover, in this PRI/NRI-based design, the compact size of the TL PRI/NRI phase shifters allows them to fit between the antenna elements, resulting in a compact, planar, PCB implementation. Although the leaky-wave design in [101] achieves a wider scan angle range compared to the proposed resonant antenna design, the proposed design has a relatively flat gain and HPBW across its entire scan angle range. On the other hand, the leaky-wave design in [101] has very large variations in both gain and HPBW as its beam is steered. In addition, the proposed antenna array has a much lower relative side-lobe level and input return loss across its entire scan angle range compared to the design in [101]. The idea of minimizing beam squinting by using PRI/NRI phase shifters for the feed network of series-fed antenna arrays was originally proposed in [103]. Following that, this principle was demonstrated in [6, 104] for a microstrip series-fed dipole antenna array, and then in [105, 106] for a coplanar strip-line leaky-wave antenna array. Table 6.3 summarizes the achieved beam squinting by the proposed antenna array and other published designs in the literature. It is worth mentioning that achieving a lower beam squinting is more challenging at lower frequencies, as evident from Eq.(A-3) in Appendix A. The beam squinting reported in the Table 6.3 is defined as the variation in the main beam angle in degrees for a 100MHz change in the frequency centered around the operating frequency. Compared to the other designs, the proposed design achieves the lowest beam squinting. However, to be fair, note that in the proposed design, the slope of the main beam angle, θp, increases beyond the 300MHz bandwidth, which is evident from Fig. 6.15. Nonetheless, this should not be a big concern since the 6.6. DISCUSSION AND COMPARISON 200

Table 6.3: Comparison Between The Measured Beam Squinting Of The Proposed Array And Other Published Antenna Arrays. Design Array type Squintinga Oper. (deg/100MHz) freq. [100] Series-fed patch array 9.5o 5GHz [101]b Leaky-wave array 8o 3.3GHz [104] Series-fed dipole array 5.7o 5.2GHz [106] Leaky-wave array 3.1o 5GHz This work Series-fed patch array 1.3o 2.4GHz

aBeam squinting is reported as degrees/100MHz variation in frequency centered at the operating frequency. bFor this design, the beam squinting is theoretically estimated by differentiating Eq.(10) in [101]. This is carried-out using the extracted parameters provided in Table I of [101] at a varactor voltage of 5V. bandwidth of the proposed design is limited to 70MHz by its input impedance. The 1-dB compression of the proposed antenna array, as it stands, makes it capable of handling the transmit power for only short range wireless devices. For example it, can be used for wireless devices using Bluetooth or ZigBee. One potential solution to extend the power handling capability of the proposed antenna array is to couple the input signal to the TAI circuits using an on-chip transformer that steps down the voltage swing by the turns ratio. The corresponding increase in the TAI input current swing can be accommodated by increasing the TAI’s bias currents. This, however, will increase the value of the TAI inductance with the square of the turns ratio. But this could be accounted for during the design of the TAI circuit. A related approach has been recently proposed in [107] to couple the outputs of four CMOS power amplifiers to achieve a higher voltage swings than that allowed at the drain of each transistor before breakdown occurs. As described in chapter 3, noise is one of the critical performance limits which should be quantified for TAI-based applications. This was carried out for the 2-port phase shifters in chapter 4 and the 4-port coupler in chapter 5. However, antennas converts electrical signals into electro-magnetic radiation and vise versa. Therefore, from an 6.6. DISCUSSION AND COMPARISON 201 electrical point of view, antennas can be considered 1-port devices. To the author’s knowledge, there is no standard procedure for the experimental characterization of the noise performance of active antennas. However, it is worth mentioning that, in the proposed steerable antenna array, the effect of the added noise generated by the TAIs can be counterbalanced, from a system’s point of view, by having a highly-directive antenna. This highly-directive antenna, when compared to an omni-directional one, would result in a higher signal to noise and interference ratio, and consequently in a lower bit error rate since it minimizes the effect of interference with undesired signals. To know which one of the two effects would dominate, and determine if using TAIs improves the the overall performance requires knowledge of the environment in which the antenna is used and is outside the scope of this thesis. CHAPTER 7

Conclusion

T his chapter summarizes the thesis and outlines its main contributions. In addition, some areas are suggested for future research.

7.1 Summary

This thesis presented the design of RF CMOS TAIs and their applications towards the design of RF metamaterial-based tunable phase shifters, directional couplers, and series-fed steerable antenna arrays for 2.4GHz ISM band applications. The design of the CMOS TAIs was based on a modiﬁed gyrator-C architecture utilizing a feedback resistance, which allows independent control over the inductance and quality factor. The TAI was fabricated in the 1.5V, 0.13µm CMOS process, and its inductance can be tuned from 0.93nH to 2.7nH at 2.4GHz, with a peak-Q of 100 across the entire inductance tuning range. Furthermore, the Q of the TAI can be tuned from a value of 10 to 200 at 2.4GHz with less than 6.7% variation in its inductance. Chapter 4 presented a variety of implementations for bi-directional phase shifters utilizing varactors and TAIs. The focus was directed more towards PRI/NRI phase shifters, which are capable of achieving positive, negative and zero phase shifts without

202 7.1. SUMMARY 203

going through an entire 360o rotation. Hence, they have the capability to achieve low group delays compared to standard low-pass or high-pass phase shifters, which is a necessary feature to minimize the beam squinting in series-fed antenna arrays. Both printed and 0.13µm CMOS, fully-integrated implementations were presented. The former synthesizes the PRI section using microstrip TLs, whereas the latter replaces the TL sections with lumped L−C sections; thus, allowing for a single MMIC implementation. Compared to other implementations having only one tunable element, using varactors and TAIs extended the phase tuning range and at the same time maintained the input and output matching of the phase shifters. The TL PRI/NRI phase shifter presented in this thesis achieved an electronically tunable phase of -40o to +34o at 2.5GHz with less than -19dB return loss from a single stage occupying 10.8mm×10.4mm. On the other hand, the MMIC PRI/NRI phase shifter achieved a phase of -35o to +59o at 2.6GHz with less than -19dB return loss from a single stage occupying 550µm×1300µm. Furthermore, a passive fully-integrated PRI/NRI phase shifter was presented to address some of the drawbacks of the active designs (DC power consumption, noise, and linearity) by eliminating the TAI and using instead a shunt varactor. The resulting topology still exhibits phase compensation properties, which allows one to center its phase response around the zero-degree mark while having a small group delay. Fur- thermore, it is also capable of maintaining the phase shifter matching. The passive MMIC PRI/NRI phase shifter achieved an electronically tunable phase from -25.5o to 27o at 2.6GHz, from a single stage, with better than -21dB return loss across the entire tuning range, while occupying an area of 700µm×1300µm. In chapter 5, a compact, metamaterial-inspired, highly-reconfigurable directional coupler was presented. The coupler was implemented in a standard 0.13µm CMOS process and operates from a 1.5V supply. A lumped-element approach is used to build the directional coupler, which makes it possible to integrate the entire coupler onto a single MMIC. The MMIC coupler occupies an area of 730µm×600µm, which is much smaller compared to printed designs operating at the same frequency range. The MMIC coupler is based on the high-pass architecture and utilizes both varactors and tunable active inductors, which allows simultaneous electronic control over the coupling coefficient as well as the operating frequency of the coupler, while insuring a low return loss and a very high isolation. Furthermore, the symmetric configuration of the coupler allows it to electronically switch from forward to backward operation 7.2. CONTRIBUTIONS 204

by simply exchanging the bias voltages applied across the varactors. The different modes of operation of the proposed MMIC coupler were experimentally verified, and the measured results show that the coupler is capable of achieving a tunable coupling coefficient from 1.4dB to 7.1dB, while maintaining the isolation higher than 41dB. The MMIC coupler is also capable of operating at any center frequency over the 2.1GHz- 3.1GHz frequency range with higher than 40dB isolation. The linearity of the proposed MMIC coupler was experimentally characterized. Chapter 6 of this thesis presented a planar electronically steerable series-fed patch array for 2.4GHz ISM band applications. The proposed steerable array used the zero- degree tunable TL PRI/NRI phase shifters to center its radiation about the broadside direction and allow scanning in both directions off the broadside. Also, using the PRI/NRI phase shifters minimizes the squinting of the main beam across the operating bandwidth. The feed network of the proposed array used λ/4 impedance transformers. This allows using identical interstage phase shifters, which share the same control voltages to tune all stages. Furthermore, using the impedance transformers in combination with the CMOS-based constant-impedance TL PRI/NRI phase shifters guarantees a low return loss for the antenna array across its entire scan angle range. The antenna array was fabricated, and is capable of continuously steering its main beam from -27o to +22o off the broadside direction with a gain of 8.4dBi at 2.4GHz. This was achieved by changing the varactors’ control voltage from 3V to 15V. Across this 49o scan angle range, the array return loss is less than -10dB across a bandwidth of 70MHz, and the side-lobe level is always 10dB lower than the main lobe. Furthermore, the proposed design achieves very low beam squinting of 1.3o/100MHz at broadside and a 1-dB compression point of 4.5dBm.

7.2 Contributions

The main contributions of this thesis are summarized as follows: 1. Development of a novel generalized method, based on the gyrator-C architecture, to design grounded TAIs with independent L and Q tuning capability. 2. Evaluation of the performance of the proposed modiﬁed gyrator-C architecture, by presenting the design and experimental characterization of a grounded 0.13µm CMOS TAI. 7.3. FUTURE WORK 205

3. Design and implementation of four novel wide tuning range phase shifters, a) Fully-integrated, tunable, active high-pass phase shifter. b) Tunable, active, TL PRI/NRI phase shifter. c) Tunable, active, MMIC PRI/NRI phase shifter. d) Tunable, passive, MMIC PRI/NRI phase shifter. 4. Design and implementation of a novel highly-reconﬁgurable directional coupler, which is simultaneously capable of operating with a variable coupling coeﬃcient and a variable center frequency. As well as switching the input power among the through and isolated ports. 5. Design and implementation a 4-element, PCB, electronically steerable, series-fed antenna array. The array is capable of centering its radiation about the broadside direction, and achieves very low beam squinting by utilizing the TL PRI/NRI phase shifters.

7.3 Future Work

There are many areas that can be further investigated. First of all, the generalized gyrator-C architecture with resistive feedback, which was presented in this thesis, can be applied to the different TAI circuit topologies discussed in chapter 2 to obtain a variety of new TAI designs with independent L and Q tuning capability. Secondly, metamaterials is a relatively new research area. In this thesis only two of its applications were extensively investigated; phase shifters and directional couplers. However, there is a broad range of different applications that can use metamaterial concepts and combine them with the capabilities offered by active circuits. For instance, one may replace the fixed capacitors and inductors in the series power divider presented in [13] to make it operate at an arbitrary frequency. Also, TAIs and/or varactors can be used to electronically control the resonance frequency of an antenna. For example, this can be used to electronically tune the resonance of a planar inverted F antenna (PIFA), enabling the design of re-configurable antennas for multi-standard applications. The series-fed patch array presented in this thesis can be very easily modified to achieve a wider bandwidth by replacing the narrow-band patch antennas with more wide-band antenna elements, such as stacked patches. Another possibility is to replace the bulky patch antennas with small metamaterial-based antennas [19,20]. 7.3. FUTURE WORK 206

Furthermore, another area that has not been fully investigated yet is the integration of the entire phased antenna array transceiver on-chip. Scaling-up the operating frequency to the millimeter-wave region allows shrinking the antenna dimensions and the inter-element distance of the array making it feasible to ﬁt onto a single MMIC. One such attempt was reported in [108], where a 16-element 30-50GHz transmit phased array is integrated with the beam forming network on a single chip. However, in order to scale-up the operating frequency appropriate technology nodes with higher transistor

fts would be required. For instance, the 30-50GHz design in [108] is fabricated in a

0.18µm SiGe BiCMOS technology, which oﬀers transistors with peak fts of 155GHz. Another example of frequency scaling is the 12.7GHz and 30GHz metamaterial phase shifter designs which were recently presented in [109] and [110,111] respectively. Since the phase shifters published in [109–111] mostly relay on passive devices such high operating frequencies were possible to achieve using a standard 0.18µm CMOS technology. The majority of the circuits presented in this thesis use the TAI circuit, which will become the design bottleneck when it comes to scaling-up the operating frequency. The

0.13µm CMOS technology provides transistors with peak fts close to 80GHz, which indicates that there should be some room for speed improvement. However, note that other specifications such as the inductance tuning range or the power handling capability might be the limiting factors that determine the speed of the TAI circuit in a specific technology node. In this case, migrating to new technologies with smaller feature sizes and higher fts would be beneficial. In addition, techniques to extend the linearity and noise limitations of TAIs have yet to be investigated. One potential solution to extend the power handling capability of TAIs is by coupling the input signal to the TAIs using an on-chip transformer that steps down the voltage swing by the turns ratio. The corresponding increase in the TAI input current swing can be accommodated by increasing the TAI’s bias currents. This, however, will increase the value of the TAI inductance with the square of the turns ratio, but could be accounted for during the design of the TAI circuit. A similar approach was proposed in [107] to couple the outputs of four CMOS power amplifiers to achieve a higher voltage swing than that allowed at the drain of each transistor before breakdown occurs. Also, a detailed sensitivity analysis of the TAI, and the subsequent circuits presented here using the TAI, would be necessary for determining whether these circuits are 7.3. FUTURE WORK 207 sufficiently robust for use in commercial applications. Any limitations, once identified, could be the subject of further research for developing new tuning and compensation techniques. Finally, the contribution of this thesis has been to establish the feasibility of metamaterial-inspired circuits for wireless applications. This work has demonstrated the strengths of these circuits in enhancing tunability and matching. At the same time, this work has characterized to some extent, some of the limitations of these circuits in terms of noise and distortion. In doing so, this work has laid the foundation for future research aimed at identifying specific, wireless applications that can benefit from these circuits. Appendix A: Beam Squinting Analysis For The Proposed Series-Fed Antenna Array

T his appendix analyzes the relationship between the squinting of the main beam of the proposed series-fed alternating antenna array and the group delay of the interstage phase shifters. The scan angle, θ, of the series-fed antenna array having an

inter-element spacing dE can be expressed as:

π + φ + φ θ = sin−1(−c × TL PS ), (A-1) ωdE where c is the speed of light, φTL is the interconnecting λ/4 TLs phase shift, and φPS is the phase shift of the interstage phase shifters. For broadside radiation, the antenna elements of the alternating architecture should be fed out-of-phase, i.e. φTL = −π and o φPS = 0 . To evaluate the beam squinting around the broadside direction, Eq.(A-1) is used to ﬁnd the derivative of θ with respect to frequency. For small variations in the scan angle, one can approximate the rate of change of the scan angle as:

dθ c π + φP S Tgd ≈ ( 2 + ), (A-2) dω dE ω ω where Tgd is the group delay of the interstage phase shifters. Evaluated at broadside,

208 Appendix A: Beam Squinting Analysis 209

o i.e. φP S = 0 , the expression of Eq.(A-2) results in the following: ¯ dθ ¯ c π T ¯ ≈ ( + gd ). (A-3) ¯ 2 dω broadside dE ω ω

Hence, feeding the antenna elements with interstage phase shifters that have small group delays will result in less beam squinting. Appendix B: Simulation Procedure

T his appendix presents two ﬂow charts to demonstrate the method used to simulate and consequently design the TL PRI/NRI metamaterial phase shifter and the steerable antenna array. Figure B-1 shows the procedure used to simulate the single stage and the 2-stage TL PRI/NRI metamaterial phase shifters. Whereas, Fig. B-2 shows the procedure used to obtain the simulated radiation patterns of the steerable antenna array.

210 Appendix B: Simulation Procedure 211

Electromagnetic simulations

Simulate the printed structure of the TL phase shifter in Momentum ADS (without varactors and TAI)

Experimental characterization

TAI S-parameters files for Model the printed structure of the TL SPICE models of discrete different bias conditions phase shifter with a multi-port S- varactors (obtained from (obtained from experimental parameter file (using the ADS EM/ vendor) characterization) Circuit co-simulation tool)

Combine the S-parameters of TAIs with SPICE models of Circuit the varactors and the S-parameters of the printed simulations structure of the TL phase shifter in ADS’s circuit simulator

Obtain phase response, insertion, and return loss of TL metamaterial phase shifters

Figure B-1: Flow chart showing the procedure used to simulate the TL PRI/NRI metamaterial phase shifters.

Electro-magnetic simulations Simulate the feed network of the steerable array together with the patch antennas in Momentum ADS, but without the PRI/NRI phase shifters EM/Circuit co-simulations plus measurements

Obtain the phase response, Model the entire printed structure insertion, and return loss of the with a multi-port S-parameter file 2-stage TL PRI/NRI (using the ADS EM/Circuit co- metamaterial phase shifters simulation tool)

Combine the 2-stage PRI/NRI phase shifters with the S- parameters of the steerable array in ADS’s circuit Circuit simulation, and obtain the antenna array’s return loss and simulations the maximum and minimum phase states.

Using the information on the maximum and minimum phase states to feed the input ports of the steerable array Electromagnetic with the appropriate signal amplitudes and phases in an simulations EM simulation to obtain the radiation patterns

Figure B-2: Flow chart showing the procedure used to simulate the steerable antenna array. References

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