Execution Time Analysis of Audio Algorithms
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QEMU As a Platform for PLC Virtualization an Analysis from a Cyber Security Perspective
QEMU as a platform for PLC virtualization An analysis from a cyber security perspective HANNES HOLM, MATS PERSSON FOI Swedish Defence Research Agency Phone: +46 8 555 030 00 www.foi.se FOI-R--4576--SE SE-164 90 Stockholm Fax: +46 8 555 031 00 ISSN 1650-1942 April 2018 Hannes Holm, Mats Persson QEMU as a platform for PLC virtualization An analysis from a cyber security perspective Bild/Cover: Hannes Holm FOI-R--4576--SE Titel QEMU as a platform for PLC virtualization Title Virtualisering av PLC:er med QEMU Rapportnr/Report no FOI-R--4576--SE Månad/Month April Utgivningsår/Year 2018 Antal sidor/Pages 36 ISSN 1650-1942 Kund/Customer MSB Forskningsområde 4. Informationssäkerhet och kommunikation FoT-område Projektnr/Project no E72086 Godkänd av/Approved by Christian Jönsson Ansvarig avdelning Ledningssytem Detta verk är skyddat enligt lagen (1960:729) om upphovsrätt till litterära och konstnärliga verk, vilket bl.a. innebär att citering är tillåten i enlighet med vad som anges i 22 § i nämnd lag. För att använda verket på ett sätt som inte medges direkt av svensk lag krävs särskild överenskommelse. This work is protected by the Swedish Act on Copyright in Literary and Artistic Works (1960:729). Citation is permitted in accordance with article 22 in said act. Any form of use that goes beyond what is permitted by Swedish copyright law, requires the written permission of FOI. FOI-R--4576--SE Sammanfattning IT-säkerhetsutvärderingar är ofta svåra att genomföra inom operativa industriella informations- och styrsystem (ICS) då de medför risk för avbrott, vilket kan få mycket stor konsekvens om tjänsten som ett system realiserar är samhällskritisk. -
Efficient Dual-ISA Support in a Retargetable, Asynchronous
Edinburgh Research Explorer Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator Citation for published version: Spink, T, Wagstaff, H, Franke, B & Topham, N 2015, Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator. in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on. Institute of Electrical and Electronics Engineers (IEEE), pp. 103 - 112. https://doi.org/10.1109/SAMOS.2015.7363665 Digital Object Identifier (DOI): 10.1109/SAMOS.2015.7363665 Link: Link to publication record in Edinburgh Research Explorer Document Version: Peer reviewed version Published In: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on General rights Copyright for the publications made accessible via the Edinburgh Research Explorer is retained by the author(s) and / or other copyright owners and it is a condition of accessing these publications that users recognise and abide by the legal requirements associated with these rights. Take down policy The University of Edinburgh has made every reasonable effort to ensure that Edinburgh Research Explorer content complies with UK legislation. If you believe that the public display of this file breaches copyright please contact [email protected] providing details, and we will remove access to the work immediately and investigate your claim. Download date: 28. Sep. 2021 Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator Tom Spink, Harry Wagstaff, Björn Franke and Nigel Topham Institute for Computing Systems Architecture School of Informatics, University of Edinburgh [email protected], [email protected], [email protected], [email protected] Abstract—Dynamic Binary Translation (DBT) allows software compilation task farm [2], each JIT compilation worker may compiled for one Instruction Set Architecture (ISA) to be executed independently change its target ISA based on the encoding of on a processor supporting a different ISA. -
Socrocket - Eine flexible Erweiterbare Virtuelle Plattform Zum Entwurf Robuster Eingebetteter Systeme
SoCRocket - Eine flexible erweiterbare Virtuelle Plattform zum Entwurf robuster Eingebetteter Systeme Von der Carl-Friedrich-Gauß-Fakultät der Technische Universität Carolo-Wilhelmina zu Braunschweig zur Erlangung des Grades eines Doktoringenieurs (Dr.-Ing.) genehmigte Dissertation von Dipl.-Ing. Thomas Schuster geboren am 28.03.1976 in Räckelwitz Eingereicht am: 11.11.2014 Disputation am: 08.04.2015 1. Referent: Prof. Dr.-Ing. Mladen Berekovic 2. Referent: Prof. Dr.-Ing. Harald Michalik (2015) Erklärung der Selbstständigkeit Hiermit versichere ich, die vorliegende Arbeit selbstständig verfasst und keine anderen als die angegebenen Quellen und Hilfsmittel benutzt sowie die Zitate deutlich kenntlich gemacht zu haben. Braunschweig, den 15.05.15 Thomas Schuster Vorwort Diese Doktorarbeit ist der Ergebnis einer langjährigen und fruchtbaren Zusammenarbeit mit Prof. Dr.-Ing. Mladen Berekovic, den ich 2004 als Praktikant und späterer Angestellter am IMEC in Belgien kennenlernte und 2007 als Wissenschaftlicher Mitarbeiter an die Technische Universität Braunschweig begleitete. Ich möchte ihm hier ganz besonders für seine Unterstützung danken. Ganz besonderer Dank gebührt ebenfalls Prof. Dr.-Ing. Harald Michalik, der mich durch einen ge- meinsamen Projektantrag (2009), in Kontakt zur Europäischen Raumfahrtagentur (ESA) brachte und damit nicht nur wesentlich zur Finanzierung, sondern auch zur fachlichen Ausrichtung der vorliegenden Arbeit beitrug. Der Weg zur Entstehung dieser Arbeit war spannend, selten geradlinig und erwies sich als kniffliger Balanceakt zwischen Industrieprojekten, wissenschaftlicher Arbeit, Lehre und Pro- jektorganisation; ein Weg den ich ohne die Unterstützung meiner Kollegen am Lehrstuhl für Technische Informatik nicht hätte bewältigen können. Ganz herzlichen Dank an Rolf Meyer, der mir mit seinen großartigen Ideen und technischem Know-How während der Arbeit an SoCRocket zur Seite stand. -
2015-Samos-13
Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator Tom Spink, Harry Wagstaff, Björn Franke and Nigel Topham Institute for Computing Systems Architecture School of Informatics, University of Edinburgh [email protected], [email protected], [email protected], [email protected] Abstract—Dynamic Binary Translation (DBT) allows software compilation task farm [2], each JIT compilation worker may compiled for one Instruction Set Architecture (ISA) to be executed independently change its target ISA based on the encoding of on a processor supporting a different ISA. Some modern DBT the code fragment it is operating on. Most DBT systems [3], systems decouple their main execution loop from the built-in [4], [5], [6], [7], [8], [9], [1], [10], [11], [12], [13], [14], [15] Just-In-Time (JIT) compiler, i.e. the JIT compiler can operate avoid dealing with this added complexity and do not provide asynchronously in a different thread without blocking program support for dual-ISAs at all. A notable exception is the ARM execution. However, this creates a problem for target architectures EMU RM HUMB with dual-ISA support such as ARM/THUMB, where the ISA of the port of Q [16], which supports both A and T currently executed instruction stream may be different to the one instructions, but tightly couples its JIT compiler and main processed by the JIT compiler due to their decoupled operation execution loop and, thus, misses the opportunity to offload and dynamic mode changes. In this paper we present a new the JIT compiler from the critical path to a separate thread.