IEEE 2008 Custom Intergrated Circuits Conference (CICC)

A 105.5 dB, 0.49 mm2 Audio Σ∆ Modulator using Chopper Stabilization and Fully Randomized DWA

Yi-Gyeong Kim, Min-Hyung Cho, Kwi-Dong Kim, Jong-Kee Kwon, and Jongdae Kim Electronics and Telecommunications Research Institute (ETRI), 138 Gajeongno, Yuseong-gu, Daejeon, 305-700, Korea E-mail: [email protected]

Abstract-An audio Σ∆ modulator achieves 105.5 dB dynamic range technique is used in both the first integrator and the reference over 20 kHz audio bandwidth. A chopper stabilization technique is buffer. The fully randomized data weighted averaging (DWA) used in both the first integrator and the reference buffer to prevent is used as a DEM for suppression of the generation of spurious degradation of the dynamic range and the peak signal-to-noise-plus- tones with a negligible increase of in-band noise. distortion-ratio due to flicker noise. A fully randomized data weighted averaging is used as a dynamic element matching technique II. ARCHITECTURE to suppress the generation of spurious tones with a negligible Fig. 1 shows the architecture of the modulator. The increase in the in-band noise compared to conventional data weighted averaging. The chip was fabricated in 0.13 µm CMOS technology modulator is a second-order single loop design with a feed- (I/O devices) and occupies a small chip area of 0.49 mm2. The total forward path to the input of the second integrator and a 17- power consumption is 9.9 mW from a 3.3 V supply. level quantizer. The feed-forward path makes the first integrator process a second-order high-pass filtered signal I. INTRODUCTION component, thereby reducing the signal swing at the first

The recent growth of digital consumer applications such as integrator output and improving the distortion performance. In digital TV has increased the demand for the technology known addition, the reduced swing range enables the utilization of a as the system-on-chip (SoC), which includes not only digital folded cascode OTA, thus reducing the power consumption. In signal processors but also mixed-mode circuits. An audio order to remove the effect of the flicker noise, the first codec is an essential item among various mixed-mode circuits. integrator and the reference buffer adopt a CHS technique. A The audio codec requires low-cost audio analog-to-digital fully randomized DWA is used as a dynamic element converters (ADC) that are capable of high-performance. These matching technique. The loop filter is implemented with fully audio ADCs must achieve a dynamic range (DR) and a peak differentially switched capacitor circuitry. The modulator is signal-to-noise-plus-distortion-ratio (SNDR) of more than 100 operated with a clock speed of 6.144 MHz which corresponds dB and 95 dB, respectively, at low power. Moreover, the chip to an OSR of 128. The input signal range of the modulator is 2 VRMS and reference voltages are 3.0 V and 0 V. area must be minimized for the low-cost. The Σ∆ modulator is a key block of the audio ADC. The III. CIRCUIT TECHNIQUES AND IMPLEMENTATION multi-bit architecture is a possible route for high-performance. A. Chopper Stabilization Multi-bit modulators have several advantages, including enhanced modulator stability, relaxed settling requirements of Flicker noise occurring in the first integrator goes through the loop filter, and reduced quantization noise compared to the loop filter with the characteristics of a signal transfer single-bit modulators. However, they have mismatch problem function (STF). The flicker noise will then appear at the of a digital-to-analog converter (DAC) in the feedback path. output of the modulator with little attenuation. Therefore, a The DAC has inherently nonlinear characteristics due to a technique for the removal of the flicker noise is needed to device mismatch. In order to resolve the nonlinearity of the achieve a DR of more than 100 dB. CHS is a suitable method internal DAC in the feedback path, a dynamic element for the removal of the flicker noise effect in a Σ∆ modulator matching (DEM) technique is required. In addition, the due to the low-pass filter characteristic of the integrator [2]. generation of unwanted in-band tones and an increase in in- Fig. 2 shows the first integrator and the timing diagram of the band noise by DEM are minimized to achieve the target CHS. The frequency of the CHS is set at a sampling performance. frequency/2 (Fs/2). The CHS makes it possible to increase the

In order to satisfy the target DR and the peak SNDR, the flicker noise has to be minimized. The flicker noise generated

− − in the first integrator and the reference buffer mainly affects z 1 16 z 1 30 the performance of the modulator. The noise generated in the 1−z−1 30 1−z−1 16 first integrator degrades the DR of the modulator. The noise generated in the reference buffer degrades the peak signal-to- noise-ratio (SNR) and peak SNDR. Therefore, a technique is required to reduce the flicker noise effect in a Σ∆ modulator. This paper presents a high-performance low-cost audio Σ∆ modulator with a reference buffer. In order to minimize the Fig. 1. Σ∆ modulator architecture. contribution of the flicker noise, chopper stabilization

978-1-4244-2018-6/08/$25.00 ©2008 IEEE TP-03-1 503 SC DAC P1 Input REFT CML signal Output Loop filter ADC CML signal REFB CHA CHAD P1D P2 INP OUTP DAC CHB CHBD CHB CHBD INN OUTN Reference voltage P1D P2 CHA CHAD REFB CML Input signal Reference voltage Output signal REFT CML P1 SC DAC Flicker Flicker noise noise fin Freq. Freq. fin Freq. P2 P1 P2 P1 Main Clock P2D P1D P2D P1D PSD: Power spectral density

Chopper stabilization timing Fig. 3. Effect of flicker noise in reference buffer.

( CHA, CHAD, CHB, CHBD)

P2 P1 P2 P1 P2D P1D P2D P1D

CHA CHB CHB CHA CHAD CHBD CHBD CHAD

Fig. 2. First integrator and chopping timing diagram. noise in the signal bandwidth, as spectrally shaped high- frequency (Fs/2) quantization noise can be modulated down to the signal bandwidth [3]. To reduce the coupling effect of the shaped high-frequency quantization noise, chopping is performed at a range between Fig. 4. Reference buffer and chopping timing diagram.

P2 and P1D. In addition, to minimize the signal-dependent DC voltage and generates the DAC output signal without charge injection, chopping is performed with non-overlap additive noise. timing. That is, after the P2 phase switches shown in Fig. 2 are B. Fully Randomized DWA opened, CHA (or CHB) switches are opened. Following this, CHAD (or CHBD) switches are opened. Next, CHB (or CHA) The DWA technique, which has a first-order mismatch switches are closed and CHBD (or CHAD) switches are shaping property, is a practical and effective DEM technique. subsequently closed. However, DWA experiences what is known as a tonal Fig. 3 shows the effect of flicker noise in the reference problem, which involves the generation of unwanted in-band buffer. In the time domain, DAC output is generated from the tones due to the periodic property of DWA. Thus, this multiplication of the DAC input signal and the reference problem limits the dynamic performance of a Σ∆ modulator. voltage. In the frequency domain, the output is the result of To overcome the tonal problem of DWA, the periodic convolution between the input spectrum and the reference property of DWA must be removed. In this design, the voltage spectrum. Thus, if the reference voltage contains randomized DWA [1] is used as the DEM. The randomized flicker noise, the noise appears around the input signal DWA can be implemented with either partial randomization frequency in the frequency domain. Due to the input signal [1] or full randomization. In the partially randomized DWA, dependency, although there is only a slight noise effect in case the origin pointer jumps to a new random pointer only in the of a small input signal, there is an increase in the level of noise case of complete rotation, which implies that the start pointer around the input signal frequency in case of a large input equals the origin pointer. Although this implementation signal. Therefore, the noise will degrade the peak SNR and the suppresses the generation of tones, this technique increases the peak SNDR. in-band noise, degrading the SNR. To minimize SNR Fig. 4 shows the reference buffer schematic and the timing degradation, a fully randomized DWA is used here. In the diagram of the CHS. REFT and REFB are set to 3.0 V and 0 fully randomized DWA, the selection of DAC elements is V, respectively. The flicker noise that appears in the reference similar to that of the conventional DWA except that the origin voltage spectrum is mainly generated at the error amplifier. pointer jumps to a new random pointer at every full turn, as Thus, the error amplifier adopts a CHS technique. The shown in T3 code of Fig. 6. The one full turn implies that all chopping is performed at the frequency of Fs/2. The flicker elements are selected 1 time. Fig. 5 (a) shows the simulated noise generated at the error amplifier is modulated up to Fs/2 spectrum of the modulator using the conventional DWA, the via CHS technique. The modulated noise is attenuated by an partially randomized DWA, and the fully randomized DWA off-chip capacitor. Therefore, the DAC is supplied with clean for an input amplitude of -51 dB with a random DAC element mismatch less than 0.2 %. The SNDRs for the conventional

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DWA, the partially randomized DWA, and the fully randomized DWA are 67.1 dB, 66.7 dB, and 68.9 dB, respectively. Although degradation of the SNDR occurs in the case of the conventional DWA and the partially randomized DWA due to spurious tones and an increase in the in-band noise, respectively, there is little degradation of the SNDR in the case of the fully randomized DWA. Fig. 5 (b) shows the SNDR versus the input level. The amplitude level of the input signal is increased in 5 dB steps from -60 dB to 0 dB. The SNDR at each input level is determined by averaging 10 trials (a) of simulation results, performed with a random DAC element mismatch less than 0.2 %. Although the average SNDR for the partially randomized DWA are degraded, the fully randomized DWA results show little degradation of the average SNDR compared to the conventional DWA. Some simulation results of the conventional DWA show the generation of spurious tones. Therefore, these results show that the fully randomized DWA is effective for the suppression of the generation of spurious tones with only a negligible increase in in-band noise. Fig. 6 shows a hardware implementation block diagram of (b) fully randomized DWA, shown for 8-bit input of a Fig. 5. Comparison of DWA, partially randomized DWA, and fully thermometer code for simplicity. For a simple description, the randomized DWA with a random DAC element mismatch less than 0.2 %. values of the input code, T and B, as well as that of a random (a) Output spectrum. (b) SNDR versus input level. number R are set to 5, 5 and 1, respectively. The element marked with slanted lines at the T3 code in Fig. 5 is the origin pointer, which shifts according to a random number, SH2. This random number, SH2, is inserted at every full turn. The hardware implementation of the fully randomized DWA is 5 comprised of three shifters and some logic gates. The first shifter rotates the T code in the same manner as DWA. The Thermometer code, second shifter shifts only the left side elements (dashed border line) among the selected elements to the right by SH2 in case of a full turn of T1. SH2 is generated using a subtractor, AND gates, and OR gates, and are hence a random number so as not to overlap with the selected elements. The third shifter rotates the code T2 by the SH3, which is an accumulation of SH2, to correct the start pointer. These operations are performed by logarithmic shifters and a modified shifter, named a local element shifter in Fig. 6. The local element shifter is constructed from switch units that consist of two NMOS transistors, one NAND gate, and one inverter, shown in Fig. 6. EN&SH C. Integrators and Flash ADC

The integrators employ a fully differential folded-cascode OTA. This OTA does not require an additional compensation EN &SH capacitor and achieves high bandwidth with a capacitor load. Therefore, it has a high level of power efficiency. A fully differential gain boosting technique is used to achieve high DC gain as low DC gain causes a leakage of quantization noise. A gain boosting amplifier dissipates less than 30 % of the total amplifier power. The unity gain bandwidth of the first OTA is 60 MHz and the open loop DC gain is 113 dB. The value of the first sampling capacitor and reference capacitor is Fig. 6. Block diagram of fully randomized DWA and example codes.

4.2 pF and 4.9 pF, respectively, which satisfy a thermal noise target of -108 dB. The second integrator is scaled down to The reference voltages of the flash ADC and common mode reduce the power consumption. The flash ADC consists of 16 voltages of the integrators are generated by resistive dividers. comparators composed of a preamp and a regenerative latch.

TP-03-3 505 IV. MEASUREMENT RESULTS

The prototype modulator was fabricated in 0.13 µm CMOS technology (I/O Devices) and occupies a 0.49 mm2 (0.97 mm x 0.5 mm) active area, as illustrated in Fig. 7. The analog and digital section operates on a 3.3 V supply with a total power consumption of 9.9 mW. The modulator achieves a 97.5 dB peak SNDR (A-weighted) and a 105.5 dB dynamic range (A-weighted) over a bandwidth of 20 kHz. Fig. 8 (a) shows the measured output spectrum of a 1 kHz and 0 dBFS sinusoidal signal. The SNR (A-weighted) values of the reference buffer CHS ON and OFF are 101.9 dB and (a) 99.1 dB, respectively. The SNDR (A-weighted) values of the reference buffer CHS ON and OFF are 97.2 dB and 96.5 dB, respectively. Fig. 8 (b) shows the measured output spectrum of a 1 kHz and -20 dBFS sinusoidal signal. The SNDR (A- weighted) values are 85.5 dB and 76.0 dB with the integrator CHS ON and OFF, respectively. These results show that peak SNR/SNDR and DR are enhanced by the CHS technique in the reference buffer and the integrator. A plot of the SNR and Output spectrum (dB) spectrum Output SNDR values versus input level is shown in Fig. 9. TABLE I gives a summary of the measured performance.

V. CONCLUSIONS (b)

The audio Σ∆ modulator with the reference buffer is Fig. 8. 1 M FFT plot of (a) 0 dB input and (b) -20 dB input, 1 kHz sine wave presented in this paper. The CHS is applied to the first with a sampling frequency of 6.144 MHz. integrator and to the reference buffer to minimize the contribution of the flicker noise. The fully randomized DWA is used to reduce the effect of the nonlinear DAC. The modulator achieves a DR (A-weighted) of 105.5 dB, a peak SNDR of 97.5 dB over an audio bandwidth of 20 kHz with power consumption of 9.9 mW power consumption. The design occupies an active area of 0.49 mm2.

ACKNOWLEDGMENTS

This work was supported by the IT R&D program of

Ministry of Knowledge Economy, Rep. of Korea [2006-S- 006-02, components/Module Technology for Ubiquitous Fig. 9. SNR and SNDR versus the input level.

Terminals]. TABLE I

PERFORMANCE SUMMARY REFERENCES

[1] M. Vadipour, “Techniques for preventing tonal behavior of data weighted Power supply voltage 3.3 V averaging algorithm in Σ-∆ Modulators,” IEEE Transactions on Circuits Signal bandwidth 20 kHz and Systems II: Analog and Digital Signal Processing, Vol. 47, No. 11, pp. 1137-1144, November 2000. Sampling frequency 6.144 MHz [2] A. B. Early, “Chopper stabilized delta-sigma analog-to-digital converter,” Peak SNDR 97.5 dB (A-weighted) U.S. Patent 4 939 516, July 3, 1990. [3] Y. Yang, A. Chokhawala, M. Alexander, J. Melanon, and D. Hester, “A Dynamic range 105.5 dB (A-weighted) 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm2 ,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, pp. 2061– Full scale input 2 VRMS differential 2068, December 2003. 9.9 mW Total power consumption (Analog:5.28 mW, Digital: 4.62 mW) Chip area 0.49 mm2 (0.97 mm x 0.5 mm) 0.13 µm CMOS technology, Technology 3.3 V I/O Devices

Fig. 7. Photograph of the chip.

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