REAR PANEL FRONT PANEL INTERCONNECTS FRONT PANEL FRONT PANEL N5221B and N5222B 2-Port Overall Block Diagram INTERCONNECTS INTERCONNECTS INTERCONNECTS Including Options 200-Standard; 201-Configurable Test Set; A20 IF MULTIPLEXER IF = 0.826 MHz for CW Freq < 53 MHz A27 MIXER BRICK (1) 210-Metrology; 217-Attenuators; and 219-Attenuators and Bias Tees IF = 7.438 MHz for CW Freq > 53 MHz A3 A2 Main IF A A 70.0 MHz USB x 4 W51 A A DISPLAY USB BD 10.7 MHz P1 I R Pulse A PULSE L A12 SIGNAL PROCESSING GATES OPTION 200 OR 210 ADC MODULE (SPAM) IF OUT A Ext IF In A TO A23 A TO A23 A 70.0 MHz P3 Aux R3 W147 W105 R1 R1 FROM A29 USB I R HUB 9 MHz LFE IF A L DISPLAY INVERTER OPTION 200 OR 210 W31 RCVR A IN PROCESSOR POWER KEYPAD TO A23 A OPTION 201 J1 W97 ADC 70.0 MHz FLASH 15 MHz W148 W14 A R2 R2 FROM A29 Port 1 A55 A17 CPU I R RAM Main IF B B HARD DISK L CPLR ARM SPEAKER 9 MHz 10.7 MHz P201 OPTION 201, 217, OR 219 DRIVE Pulse B PULSE W149 GATES 70.0 MHz OPTION 217 J2 A42 STEP USB A1 FRONT PANEL INTERFACE BOARD ADC IF OUT B Ext IF In B B B A33 REF OR 219 USB x 4 EEPROM 15 MHz I R ATTEN INTERFACE B R1 P203 Aux R4 L SWITCH W36 RCVR R1 IN RCVR A IN P411 W37 TO A23 A CONTROLLER GPIB PORT MAIN PCI 9 MHz LFE IF B BRIDGE W30 W30 GPIB INTERFACE CPU REF 1 0-50 dB Port 1 W14 J4 W35 SOURCE OUT CPLR ARM 10/100 BASE-T ROM RAM ADC 15 MHz R2 W13 FROM A29 LAN ETHERNET R P412 Main IF R R EXT TSET DRIVE LO OUT VGA VIDEO PROCESSOR DSP 9 MHz 10.7 MHz FROM VGA INTERFACE Pulse R PULSE A23 VIDEO RAM R3 J5 W150 GATES IF OUT R ADC 15 MHz Ext IF In R P413 A16 RAM C/R1 P403 LFE IF R POWER A15 MIDPLANE SUPPLY 9 MHz Mixer 1 2 3 4 R4 Brick LO AC LINE IN Band J6 P414 LO Synthesizer A25 HMA26.5 RF Synthesizer A5/A10 Source ADC 15 MHz Harmonic D/R2 Number Frequency (GHz) Frequency (GHz) Frequency (GHz) Frequency (GHz) A18 A14 GPIB SYSTEM POWER BUS Main IF C C/R1 0 1 ------10.7 MHz P601 MOTHERBOARD Pulse C PULSE ------GATES 1 1 TALKER/LISTENER GPIB PORT IF OUT C/R1 GPIB INTERFACE LOCAL DIGITAL BUS Ext IF In C 2 1 0.01083 to 0.05383 0.01083 to 0.05383 0.010 to 0.053 0.010 to 0.053 P603 AUX R2 3 0.06044 to 0.18244 0.06044 to 0.18244 0.053 to 0.175 0.053 to 0.175 LFE IF C 1 DITHER PULSE 4 X6 NOISE DRIVE \ 4 10.18244 to 0.25744 0.18244 to 0.25744 0.175 to 0.250 0.175 to 0.250 TO A20 5 10.25744 to 0.50744 0.25744 to 0.50744 0.250 to 0.500 0.250 to 0.500 DIRECT CONNECT 10 MHz REF J3 THRU A14 HIGH DENSITY DATA BUS Main IF D D/R2 TO A4, A5, A7, A8, A19 6 10.50744 to 1.0074 0.50744 to 1.0074 0.500 to 1.000 0.500 to 1.000 10.7 MHz P801 A10, A12, A13, TEST SET Pulse D PULSE A14, A15, A17 POWER BUS MOTHERBOARD GATES 7 1 1.0074 to 2.0074 1.0074 to 2.0074 1.000 to 2.000 1.000 to 2.000 IF OUT D/R2 Ext IF In D 8 1 2.0074 to 3.0074 2.0074 to 3.0074 2.000 to 3.000 2.000 to 3.000 RIBBON CABLE CONNECTIONS P803 Aux R1 LOCAL DIGITAL BUS TO A24, A25, A27, A28, 9 1 3.0074 to 3.2074 3.0074 to 3.2074 3.000 to 3.200 3.000 to 3.200 A37-A41, A46-A53 LFE IF D 10 1 3.2074 to 4.0074 3.2074 to 4.0074 3.200 to 4.000 3.200 to 4.000 MIXED POWER AND CONTROL SIGNALS FROM THE A23 TEST SET MOTHERBOARD 11 1 4.0074 to 5.3394 4.0074 to 5.3394 4.000 to 5.332 4.000 to 5.332 SERIAL TEST BUS NODES FROM A12 4 PULSE DRIVE PULSE 12 1 5.3394 to 6.7594 5.3394 to 6.7594 5.332 to 6.752 5.332 to 6.752 THRU A14 \ MODULATION LOGIC Bx = ACTIVE SOURCE BAND 10 MHz REF P1001 OUT DET A OUTIF P2 OUTIF P202 B OUTIF P402 R OUTIF P602 C OUTIF P802 D

13 1 6.7594 to 8.0074 6.7594 to 8.0074 6.752 to 8.000 6.752 to 8.000 InIF D J802 Ext InIF C J602 Ext InIF R J402 Ext InIF B J202 Ext Ext InIF J2 A LFED IF P804 LFEC IF P604 LFER IF P404 LFEB IF P204 LFE A IF P4 P1 14 1 8.0074 to 10.6714 8.0074 to 10.6714 8.000 to 10.664 8.000 to 10.664 SOURCE FROM A23 15 1 10.6714 to 13.5174 10.6714 to 13.5174 10.664 to 13.510 10.664 to 13.510 PULSE DRIVE OUT 16 1 6.7587 to 7.7037 13.5174 to 15.4074 6.755 to 7.700 13.510 to 15.400 17 1 7.7037 to 8.0037 15.4074 to 16.0074 7.700 to 8.000 15.400 to 16.000 TO A23 B TO A23 B OPTION 200 OR 210 18 1 8.0037 to 10.0037 16.0074 to 20.0074 8.000 to 10.000 16.000 to 20.000 A20 J20 15 15 PULSE I/O \ \ W108 FROM A32 19 110.0037 to 10.6677 20.0074 to 21.3354 10.000 to 10.664 20.000 to 21.328 5 IF INPUTS \ OPTION 200 OR 210 RCVR B IN 20 110.6677 to 12.0037 21.3354 to 24.0074 10.664 to 12.000 21.328 to 24.000 TO A23 B OPTION 201 W100 W26 W30 21 112.0037 to 13.2537 24.0074 to 26.5074 12.000 to 13.250 24.000 to 26.500 A20 J2 FROM A32 Port 2 A OPTION 201, 217, CPLR ARM A20 J202 B OR 219 RCVR R2 IN OPTION 217 A45 STEP A20 J602 OR 219 IF INPUTS C/R1 ATTEN W30 REF 2 W94 W93 RCVR B IN A20 J802 TO A23 B D/R2 SOURCE OUT W30 0-50 dB Port 2 A20 J402 W26 R CPLR ARM FROM A32

LOAD W47 0.01 - 26.5 GHz LO OUT (J5)

LOAD Port 1 EXT 3.2 - 19 GHz RF1 OUT (J6) SOURCE OUT TSET DRIVE W30

OPTION 200 CPLR THRU W101

A25 RECEIVER OPTION 201, To Port 1 A29 COUPLER 217, OR 219 W30 TEST PORT W11 (201) W12 (201,217) COUPLER PORT 1 EXT TEST SET DRIVE LO OUT To Port 1 W30 EXT TEST SET DRIVE RF OUT A34 STEP A38 DC BIAS 1 ATTEN BIAS TEE (217,219) W72 (217,219) (219) (219)

W97 (200,210) W105 (200,210) W13 (201,217,219) 0-50 dB W14 (201,217,219)

OPTION 210 A64 ATTEN W123 Direct Connection A11 13.5 GHz LO SYNTHESIZER A21 LO MULTIPLIER/AMPLIFIER 26.5 (HMA26.5) 6 dB to A29 6.75-8.0 GHz B26-28, 10.66-13.51 GHz 34-36, 2-4 GHz B23,29-30 B24-28, 31-36, 20.0-26.5 GHz ∫ 5.33-6.75 GHz X2 B22,26-28, 8.0-10.66 GHz B21-36 34-36 MAIN X2 B33-35, 16,17 46-48 B24-25, W3 W4 B21,24-25, 4.0-5.33 GHz 31-33, B29-35, 15.4-20.0 GHz φ Frac-N 31-33 1 40-48 26 GHz 0.013 - X2 26.508 GHz ƒ Logic 12.5 MHz B30-32, B2-51 to 42-45 3.0-4.0 GHz 13.518- 0.01-13.51 GHz 13.518 GHz 13.5-15.4 GHz B19-20 26.508 GHz -10 to +10 dBm 2 50 MHz REF B21-23, B29, 14 2.0-3.0 GHz 29-30 J1207 40-41 A10 FREQUENCY REFERENCE J5 B18 10 Assembly Frequency Band 10 MHz 10 MHz ∫ Test Node Error Description ALC 13 GHz 10 MHz J3 10 MHz REF 1.0-2.0 GHz B2-28,36-39 8 Unleveled, Source 1, Out 1 A5 Full Range REF OUT J4 B16-17 ÷2 0.013-13.518 GHz 50 MHz FROM Full Range 10 MHz 9 Unleveled, Source 1, Out 2 A5 50 MHz REF 0.5-1.0 GHz A19 HIGH STAB ÷2 B14-15 10 Unleveled, Source 1 Synthesizer A4 Full Range OCXO J5 250 MHz ÷4 DAC DDS Full Range J6 LOCAL 0.25-0.5 GHz LOCAL 11 Unleveled, Source 2, Out 1 A8 DIGITAL DIGITAL 100 MHz BUS B12-13 BUS Full Range ÷8 12 Unleveled, Source 2, Out 2 A8 B2-11 J102 φ ÷10 J7 POWER POWER Full Range ƒ BUS DDS=Direct Digital Synthesizer BUS 13 Unleveled, Source 2 Synthesizer A13 NC J8 Full Range 10 MHz 14 Unleveled, LO Drive A21 10 MHz J2 0-200 Hz W46 15 Unleveled, LO Synthesizer A11 Full Range REF IN ∫ 16 Unlocked, Source 1 Synthesizer, Integrator Low A4 Full Range 17 Unlocked, Source 1 Synthesizer, Integrator High A4 Full Range 19 Unlocked, Source 2 Synthesizer, Integrator Low A13 Full Range 20 Unlocked, Source 2 Synthesizer, Integrator High A13 Full Range A19 TEST SET MOTHERBOARD 22 Unlocked, LO Synthesizer, Integrator Low A11 Full Range BIAS 1 IN 23 Unlocked, LO Synthesizer, Integrator High A11 Full Range 2 29 Unleveled, Source 1, P4 A5 13.5 - 26.5 GHz \ DC BIAS 1 TO A42 J541 30 Unleveled, Source 2, P4 A8 13.5 - 26.5 GHz BIAS 3 IN

2 \ DC BIAS 3 TO A43 J542

BIAS 4 IN

2 \ DC BIAS 4 TO A44 J543

BIAS 2 IN

2 \ DC BIAS 2 TO A45 J544 Port 2 SOURCE OUT A4 13.5 GHz SOURCE 1 SYNTHESIZER J402 P4 MEAS TRIG RDY MEAS TRIG RDY 6.75-8.0 GHz B26-28, 10.66-13.51 GHz A5 26.5 GHz SOURCE (SOURCE 1) 34-36, 20-26.5 GHz W30 2-4 GHz B23,29-30 B24-28, 20-26.5 GHz AUX TRIG 1 IN AUX TRIG 1 IN CPLR THRU 31-36, 29 ∫ 5.33-6.75 GHz X2 OPTION 200 B22,26-28, 8.0-10.66 GHz 12.8-20 GHz W104 B21-36 34-36 AUX TRIG 1 OUT AUX TRIG 1 OUT MAIN X2 B28 16-20 GHz 16,17 B29-48 B24-25, B31,38,47-48 4.0-5.33 GHz 31-33, X2 B20-48 AUX TRIG 2 IN AUX TRIG 2 IN B21,24-25, 8.5-12.8 GHz To Port 2 φ Frac-N 31-33 A28 RECEIVER OPTION 201, A32 B20-28 B25-27 B20-28 W30 POWER ƒ Logic B29-31, B29-30,37, 13.5-16 GHz BRIDGE 217, OR 219 TEST PORT AUX TRIG 2 OUT AUX TRIG 2 OUT BUS B2-51 37-38,45-48 45-46 ALC 3.0-4.0 GHz 3 W23 (201) W24 (201,217) COUPLER 0.01-13.51 GHz Modulator 5.33-8.5 GHz 8 B2-28 TO B19-20 Pulse 0.01-13.5 GHz -10 to +10 dBm B22-24 PORT 2 28 V 28 V A34 THRU A37, Modulator OUT 1 50 MHz W1 B20-28,32-36,39-44 A42 THRU A49 REF B21-23, P5 2.0-3.0 GHz 29-30 J1207 P1 To Port 2 3.2-5.33 GHz W30 DC BIAS 2 MEAS TRIG IN MEAS TRIG IN LOCAL J5 B18 B2-19 A37 STEP A41 10 B20-21 4 DIGITAL BUS B20-28 ATTEN BIAS TEE ALC B2-28 9 25 1.0-2.0 GHz W83 (217,219) (217,219) (219) (219) TEST SET I/O \ TEST SET I/O B16-17 INTERFACE ÷2 B2-19 W100 (200,210) W108 (200,210) B2-28 ALC W25 (201,217,219) 0-50 dB W26 (201,217,219) 9 0.5-1.0 GHz 0.01-13.5 GHz W10 PWR I/O PWR I/O Modulator OUT 2 \ INTERFACE B14-15 250 MHz ÷4 P3 OPTION 210 3.2 GHz 36 DDS HANDLER I/O LOCAL 0.25-0.5 GHz LOCAL B2-19 B2-19 A67 ATTEN HANDLER I/O \ INTERFACE DIGITAL DIGITAL W124 BUS B12-13 BUS P2 P6 Direct ÷8 Connection POWER B2-11 J102 POWER ALC Pulse Power Limiter 6 dB to A32 BUS DDS=Direct Digital Synthesizer BUS Modulator Modulator

15 Sep 2021 N5222B_blk_2port