Monolithic Optical Receiver in 0.5Μm Bicmos Technology for Wavelengths up to 850Nm

Monolithic Optical Receiver in 0.5µm BiCMOS Technology for Wavelengths up to 850nm

Robert Swoboda and Horst Zimmermann, Senior Member, IEEE

Institute for Electrical Measurements and Circuit Design, Vienna University of Technology Gusshausstrasse 25-29/354, A-1040 Vienna, Austria

monolithically integrated receivers with nearly wavelength Abstract—This work describes a low-noise photodetector independent high sensitivity and high speed is a pin integrated circuit (PDIC) implemented in 0.5µm BiCMOS photodiode realized with a thick low-doped epi-layer proposed technology. At a data rate of 6Gbps it reaches sensitivities of - by [6]. This kind of detector was implemented in [7] and in 21.0dBm and -18.2dBm at wavelengths of 660nm and 850nm, this work. It has the advantage of high quantum efficiency, respectively. inherent suppression of large diffusion tails from the substrate Index Terms—Integrated optoelectronics, optical interconnect and the possibility to supply the photodiode from a higher receiver, photodetector integrated circuits (PDICs), voltage than circuit voltage. Compared to [7] a correction photoreceivers, p-i-n photodiode. circuit for the frequency response was implemented and the front end was optimized, which results in a significantly better I. INTRODUCTION sensitivity and a nearly doubled transimpedance bandwidth ince high speed vertical cavity surface emitting lasers product. The process used here was also used to implement a S(VCSELs) with short wavelength are available, low-cost CD/DVD receiver [8] showing the usability for mass high-performance optical links are coming into sight. production. Table 1 lists all the mentioned publications with Especially because silicon can be used directly for light the most important results. detection, the need for an expensive III-V photodetector and the interfacing to silicon circuits is eliminated. The two most TABLE I OVERVIEW OF PREVIOUSLY PUBLISHED INTEGRATED OPTICAL RECEIVERS IN important attributes the receiver has to fulfill are high speed SILICON TECHNOLOGY (* MODIFIED TECHNOLOGY) and high sensitivity. There is a long tradition in implementing Data Sensi- VPD VDD λ PD Ref. photodiodes together with amplifying circuits in silicon, but rate tivity area TECHNOLOGY 2 high sensitivity at high data rates is not to achieve in standard (Gb/s) (dBm) (V) (V) (nm) (µm ) 0.8 µm Bipolar 5.0 -4.0 -- -- 850 10 [2] technology since integrated photodiodes suffer from low speed 0.13 µm CMOS 3.125 -15.4 24 3.2 850 2500 [3] [1]. The reason for this is that the light penetrates deeper into on SOI 5 -10.9 silicon than the space-charge region of a pn-diode does, 6 +0.9 resulting in a slowdown of the photodiode due to generation of 0.13 µm CMOS 2.0 -21 27 3 850 2500 [4] on SOI diffusion currents. These slow tails of the photocurrent can be 0.18µm CMOS 3.0 -20.0 1.8 1.8 850 2500 [5] suppressed if base-collector diodes in standard-buried 0.6 µm 1.0 -29.3 11 5 660 2070 [7] collector bipolar technology are used as a detector, but due to BiCMOS* 2.5 -24.9 11 5 660 2070 2.5 -22.8 11 5 850 2070 the thin epitaxial layer, capacitance is high and quantum 3.0 -24.3 11 5 660 2070 efficiency is low, leading together to a poor sensitivity [2]. In 4.0 -22.9 11 5 660 2070 [3, 4] lateral photodiodes were implemented in a SOI 5.0 -20.5 11 5 660 2070 0.5 µm 1.0 -30.4 17 5 660 2070 [this technology in a thin silicon layer, whereby the slow diffusion BiCMOS* 2.0 -28.0 17 5 660 2070 work] currents generated deep in the substrate are blocked due to the fT=25GHz 2.5 -27.0 17 5 660 2070 insulating buried oxide layer. For these thin photodiodes the 3.0 -26.1 17 5 660 2070 quantum efficiency is low (10%) leading to a low sensitivity. 4.0 -24.3 17 5 660 2070 5.0 -23.1 17 5 660 2070 To deal with slow photodiodes in an 180nm standard CMOS- 6.0 -21.0 17 5 660 2070 process [5], the response of the photodiode was carefully 1.0 -28.0 17 5 850 2070 analyzed and compensated with an integrated equalizer. The 1.25 -27.1 17 5 850 2070 2.0 -25.1 17 5 850 2070 results showed high speed with good sensitivity. One 2.5 -24.4 17 5 850 2070 disadvantage of this approach is that the equalizer can only be 3.0 -23.8 17 5 850 2070 optimized for one wavelength. A clean solution for 4.0 -21.8 17 5 850 2070 5.0 -20.5 17 5 850 2070 6.0 -18.2 17 5 850 2070

Manuscript received May 20, 2005. This work was supported by the European Community under contract IST 2000-28013. . II. PHOTODIODE reference voltage (VREF), which is the average value of the TIA output voltage. The following stage amplifies and limits the difference of the voltage VDATA-VREF. The controlling circuit consists of a differential integrator and noise reduced dummy-TIA. It controls the voltage (VDATA-VREF) to be in average zero by injecting the average photocurrent into the dummy-TIA. This controlling mechanism was implemented since the optical signal always has an offset and “1” and “0” bits must be limited symmetrically to avoid large jitter and shifting of the eye crossing. The limiting pre-driver and limiting driver together offer a gain of 30dB and are capable to drive a differential load of Figure 1. Cross section of the pin BiCMOS PDIC 100ȍ with a maximum differential voltage of 0.8Vpp.

The pin photodiode proposed by [6] is shown in fig.1. The cathode is formed by an n+ buried layer which is connected to the surface with n+ regions. The thick intrinsic zone was realized with an epitaxial layer with a thickness of about 15µm and an n- doping of the order of 10-13 cm-3 [6]. The anode consists of a p+ doped region to achieve lowest series resistance. At the top of the anode there exists an anti- reflection coating (ARC) to increase the quantum efficiency. The p-type substrate doping concentration is reconstructed with deep p-type regions in the circuit region of the PDIC. In fig.2 the responsivity of an unpackaged photodiode for a wavelength range from 600nm to 850nm is shown. The photodiode offers responsivities of 0.36A/W at 660nm and 0.26A/W at 850nm. Figure 3. Principle schematic diagram of the PDIC

IV. MEASUREMENT RESULTS Generally all measurements were performed at a chip which was bonded on a PCB with 50ȍ microstrip lines and supply blocking capacitors to achieve maximum performance. The frequency response (fig. 4) was measured with a network analyzer HP8753E which was calibrated with a reference detector to remove the influence of cables and of the laser diodes. This measurement was done at the two Figure 2. Wavelength dependent responsivity of the photodiode wavelengths of 660nm and 850nm with minimum gain setting (VT=5V). Upper 3dB cut-off frequencies of 2.64GHz and III. PDIC STRUCTURE 2.35GHz, respectively, were obtained. At 850nm and above The PDIC integrates a PIN photodiode (PD) and an 100MHz a 1dB diffusion tail is visible, lowering the cut-off amplifier in one integrated circuit. The PD was supplied from frequency by about 300MHz and reducing the possible an external 17V source. In fig. 3 the principle schematic of the sensitivity due to a slight ISI. complete receiver can be seen. The photocurrent is amplified Bit error measurements were performed with the help of a by a transimpedance amplifier (TIA) with a variable feedback bit error analyzer which counts the failing bits. For this resistor, realized with an N-MOS transistor (M1). The core purpose the laser diode was directly modulated from a pseudo amplifying element of the transimpedance amplifier is a random bit-sequence (PRBS) generator. Bit error rate was measured for various power levels and two lengths of PRBS bipolar transistor (T1), which is optimized in size and current 15 31 density for lowest noise. The collector network (R1, R2, C1) of 2 -1 and 2 -1, especially at high transimpedances and low ensures the optimum operating condition for the transistor T1. bit rates, since the lower cut-off frequency is significantly The disadvantage of this network is that the frequency higher than 100kHz, so ISI is present for long bit sequences. response shows a slight lag characteristic which reduces the In figure 5 the results of the BER in dependence of incident sensitivity of the receiver in the order of 1dB due to inter- power for various bit rates are shown for a wavelength of 850nm. Table II gives the results for the sensitivity for a BER symbol interference (ISI). To improve the sensitivity of the -9 receiver again the ISI was removed with a correction circuit. of 10 , maximum applicable incident power and optical There exists also a controlling circuit which produces a dynamic range at a wavelength of 850nm together with the reached total transimpedances. The BER measurements were setting voltage VT (bit rate) a transimpedance from 3.2kȍ also done at the wavelength of 660nm, Table III gives the (VT=4.5V, 6Gbps) up to 14kȍ (VT=2.15V, 1Gbps). results for sensitivity, transimpedances, maximum applicable optical power and resulting optical dynamic range for data TABLE III: SUMMARY OF SENSITIVITIES, DIFFERENTIAL TRANSIMPEDANCES AND DYNAMIC RANGES OF THE PDIC FOR BER=10-9, λ=660nm AND rates from 1 to 6Gbps. Under consideration of the bandwidth 50Ω LOAD of the photodiode and at VT=5V a maximum differential transimpedance bandwidth product of 270THz into a Data Length Sensi- Trans- VT Max. avg. Optical ȍ rate of tivity impe- (V) opt.power dynamic differential 100ȍ load was achieved. (Gbps) PRBS (dBm) dance (dBm) range (kΩ) (dB) 1.0 215-1 -30.4 366 2.15 -7 23.4 231-1 -29.2 -7 22.2 1.25 215-1 -29.8 316 2.2 -7 22.8 231-1 -28.9 -7 21.9 2.0 215-1 -28.0 204 2.5 -7 21.0 231-1 -27.2 -7 20.2 2.5 215-1 -27.0 158 2.9 -7 20.0 231-1 -26.7 -7 19.7 3.0 231-1 -26.1 142 3.1 -7 19.1 4.0 231-1 -24.3 114 3.5 -7 17.3 5.0 231-1 -23.1 96 3.8 -7 16.1 6.0 231-1 -21.0 85 4.5 -11.4 9.6

V. CONCLUSION A low-cost high-performance optoelectronic receiver with a modified BiCMOS process was realized. This fully integrated Figure 4. Frequency responses for wavelengths of 660nm and 850nm, VT=5V receiver reaches to our knowledge the best sensitivity at and above 2 Gbps for wavelengths of 660nm and 850nm. At 6Gbps a sensitivity of -18.1dBm at 850nm was achieved which is 19dB better than previously published results. Additionally an overall differential transimpedance bandwidth product of 270THzȍ into a differential 100ȍ load was demonstrated. The chip occupied a total area of 870×720µm².

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