Real Time 3-D Graphics Processing Hardware Design Using Field- Programmable Gate Arrays
REAL TIME 3-D GRAPHICS PROCESSING HARDWARE DESIGN USING FIELD- PROGRAMMABLE GATE ARRAYS. by James Ryan Warner B. S. in Computer Engineering, Pennsylvania State University, 1999 Submitted to the Graduate Faculty of Swanson School of Engineering in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering University of Pittsburgh 2008 i UNIVERSITY OF PITTSBURGH SWANSON SCHOOL OF ENGINEERING This thesis was presented by James Ryan Warner It was defended on September 18, 2008 and approved by Dr. Alexander Jones, Assistant Professor, Department of Electrical and Computer Engineering Dr. Allen Cheng, Assistant Professor, Department of Electrical and Computer Engineering Thesis Advisor: Dr. James T. Cain, Professor Emeritus, Department of Electrical and Computer Engineering ii Copyright © by James Ryan Warner 2008 iii REAL TIME 3-D GRAPHICS PROCESSING HARDWARE DESIGN USING FIELD- PROGRAMMABLE GATE ARRAYS James Ryan Warner, M.S. University of Pittsburgh, 2008 Three dimensional graphics processing requires many complex algebraic and matrix based operations to be performed in real-time. In early stages of graphics processing, such tasks were delegated to a Central Processing Unit (CPU). Over time as more complex graphics rendering was demanded, CPU solutions became inadequate. To meet this demand, custom hardware solutions that take advantage of pipelining and massive parallelism become more preferable to CPU software based solutions. This fact has lead to the many custom hardware solutions that are available today. Since real time graphics processing requires extreme high performance, hardware solutions using Application Specific Integrated Circuits (ASICs) are the standard within the industry. While ASICs are a more than adequate solution for implementing high performance custom hardware, the design, implementation and testing of ASIC based designs are becoming cost prohibitive due to the massive up front verification effort needed as well as the cost of fixing design defects.
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