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Computer Arithmetic (Temporary Title, Work in Progress) Computer Arithmetic (temporary title, work in progress) Current additions done by Hossam A. H. Fahmy with permission from Michael J. Flynn Starting material based partly on the book: Introduction to Arithmetic for Digital Systems Designers by Shlomo Waser and Michael J. Flynn Originally published by Holt, Rinehard & Winston, New York, 1982 (Out of print) ii Contents 1 Numeric Data Representation1 1.1 Infinite aspirations and finite resources........................2 1.2 Natural Numbers, Finitude, and Modular Arithmetic................3 1.2.1 Properties....................................4 1.2.2 Extending Peano's Numbers..........................6 1.3 Integer Representation.................................7 1.3.1 Complement Coding..............................8 1.3.2 Radix Complement Code|Subtraction Using Addition..........8 1.3.3 Diminished Radix Complement Code..................... 10 1.4 Implementation of Integer Operations........................ 15 1.4.1 Negation.................................... 15 1.4.2 Two's Complement Addition......................... 15 1.4.3 Ones Complement Addition.......................... 16 1.4.4 Computing Through the Overflows...................... 17 1.4.5 Arithmetic Shifts................................ 18 1.4.6 Multiplication.................................. 19 1.4.7 Division..................................... 20 1.5 Going far and beyond................................. 21 1.5.1 Fractions.................................... 21 1.5.2 Is the radix a natural number?........................ 22 1.5.3 Redundant representations.......................... 23 1.5.4 Mixed radix systems.............................. 25 iii iv CONTENTS 1.6 Further readings.................................... 28 1.7 Summary........................................ 28 1.8 Problems........................................ 29 2 Floating over the vast seas 33 2.1 Motivation and Terminology; or the why? and what? of floating point....... 33 2.2 Properties of Floating Point Representation..................... 35 2.2.1 Lack of Unique Representation........................ 35 2.2.2 Range and Precision.............................. 37 2.2.3 Mapping Errors: Overflows, Underflows, and Gap.............. 38 2.3 Problems in Floating Point Computations...................... 39 2.3.1 Representational error analysis and radix tradeoffs............. 39 2.3.2 Loss of Significance............................... 44 2.3.3 Rounding: Mapping the Reals into the Floating Point Numbers...... 46 2.4 History of floating point standards.......................... 48 2.4.1 IEEE binary formats.............................. 49 2.4.2 Prior formats.................................. 51 2.4.3 Comparing the different systems....................... 53 2.4.4 Who needs decimal and why?......................... 54 2.4.5 IEEE decimal formats............................. 56 2.5 Floating Point Operations............................... 57 2.5.1 Addition and Subtraction........................... 58 2.5.2 Multiplication.................................. 60 2.5.3 Division..................................... 61 2.5.4 Fused Multiply Add.............................. 61 2.6 Reading the fine print in the standard........................ 62 2.6.1 Rounding.................................... 63 2.6.2 Exceptions and What to Do in Each Case.................. 67 2.6.3 Analysis of the IEEE 754 standard...................... 73 2.7 Cray Floating Point.................................. 76 CONTENTS v 2.7.1 Data Format.................................. 76 2.7.2 Machine Maximum............................... 76 2.7.3 Machine Minimum............................... 76 2.7.4 Treatment of Zero............................... 78 2.7.5 Operations................................... 78 2.7.6 Overflow..................................... 78 2.8 Additional Readings.................................. 80 2.9 Summary........................................ 80 2.10 Problems........................................ 81 3 Are there any limits? 85 3.1 The logic level and the technology level....................... 86 3.2 The Residue Number System............................. 88 3.2.1 Representation................................. 88 3.2.2 Operations in the Residue Number System................. 89 3.2.3 Selection of the Moduli............................ 91 3.2.4 Operations with General Moduli....................... 92 3.2.5 Conversion To and From Residue Representation.............. 93 3.2.6 Uses of the Residue Number System..................... 97 3.3 The limits of fast arithmetic.............................. 98 3.3.1 Background................................... 98 3.3.2 Levels of evaluation.............................. 98 3.3.3 The (r; d) Circuit Model............................ 99 3.3.4 First Approximation to the Lower Bound.................. 101 3.3.5 Spira/Winograd bound applied to residue arithmetic............ 103 3.3.6 Winograd's Lower Bound on Multiplication................. 104 3.4 Modeling the speed of memories........................... 106 3.5 Modeling the multiplexers and shifters........................ 108 3.6 Additional Readings.................................. 110 3.7 Summary........................................ 111 3.8 Problems........................................ 112 vi CONTENTS 4 Addition and Subtraction (Incomplete chapter) 115 4.1 Fixed Point Algorithms................................ 115 4.1.1 Historical Review................................ 115 4.1.2 Conditional Sum................................ 116 4.1.3 Carry-Look-Ahead Addition.......................... 119 4.1.4 Canonic Addition: Very Fast Addition and Incrementation........ 124 4.1.5 Ling Adders................................... 131 4.1.6 Simultaneous Addition of Multiple Operands: Carry-Save Adders..... 135 4.2 Problems........................................ 137 5 Go forth and multiply (Incomplete chapter) 141 5.1 Simple multiplication methods............................ 141 5.2 Simultaneous Matrix Generation and Reduction................... 146 5.2.1 Partial Products Generation: Booth's Algorithm.............. 148 5.2.2 Using ROMs to Generate Partial Products................. 151 5.2.3 Partial Products Reduction.......................... 154 5.3 Iteration and Partial Products Reduction...................... 157 5.3.1 A Tale of Three Trees............................. 157 5.4 Iterative Array of Cells................................. 164 5.5 Detailed Design of Large Multipliers......................... 168 5.5.1 Design Details of a 64 × 64 Multiplier.................... 168 5.5.2 Design Details of a 56 × 56 Single Length Multiplier............ 173 5.6 Problems........................................ 177 6 Division (Incomplete chapter) 181 6.1 Subtractive Algorithms: General Discussion..................... 181 6.1.1 Restoring and Nonrestoring Binary Division................. 181 6.1.2 Pencil and Paper Division........................... 181 6.2 Multiplicative Algorithms............................... 184 6.2.1 Division by Series Expansion......................... 185 6.2.2 The Newton{Raphson Division........................ 187 6.3 Additional Readings.................................. 190 6.4 Exercises........................................ 190 CONTENTS vii 7 Solutions 193 Solutions to Exercises................................. 194 viii CONTENTS List of Figures 2.1 Rounding methods on the real number axis...................... 48 2.2 ieee single (binary32), double (binary64), and quad (binary128) floating point number formats..................................... 50 2.3 IEEE decimal64 and decimal128 floating point formats............... 57 2.4 Alignment shift for the FMA............................. 62 3.1 The (r; d) circuit..................................... 100 3.2 Time delays in a circuit with 10 inputs and (r; d) = (4; 2).............. 102 3.3 The (r; d) network.................................... 103 3.4 A simple memory model................................ 107 4.1 Example of the conditional sum mechanism...................... 116 4.2 4-bit conditional sum adder slice with carry-look-ahead (gate count= 45)..... 118 4.3 16-bit conditional sum adder. The dotted line encloses a 4-bit slice with internal look ahead. The rectangular box (on the bottom) accepts conditional carries and generates fast true carries between slices. The worst case path delay is seven gates.120 4.4 4-bit adder slice with internal carry-look-ahead (gate count = 30)......... 122 4.5 Four group carry-look-ahead generator (gate count = 14).............. 123 4.6 64-bit addition using full carry-look-ahead...................... 123 4.7 Addition of three n-bit numbers............................ 135 4.8 Addition of four n-bit numbers............................. 136 5.1 A simple implementation of the add and shift multiplication............ 144 5.2 A variation of the add and shift multiplication.................... 144 5.3 Multiplying two 8-bit operands............................ 147 ix x LIST OF FIGURES 5.4 Generation of five partial products in 8×8 multiplication, using modified Booth's algorithm (only four partial products are generated if the representation is re- stricted to two's complement)............................. 150 5.5 Implementation of 8×8 multiplication using four 256×8 ROMs, where each ROM performs 4 × 4 multiplication.............................. 152 5.6 Using ROMs for various multiplier arrays...................... 153 5.7 Wallace tree....................................... 155 5.8 Wallace tree reduction of 8 × 8 multiplication,
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