Qoriq Processors Built on Layerscape Architecture

What is New to QorIQ Family - Next Generation LS and LT Multicore Platform Update

N O V . 2 0 1 4

External Use Agenda

• LS1 Product Family • LS1020/1/2 Overview • LS1020/1/2 in Action • Positioning LS102MA and LS1024A Solutions in the Freescale portfolio • LS102MA/LS1024A Overview • LS102MA (aka Comcerto1000) • LS1024A (aka Comcerto2000) • LS1024A Performance • LS1024A in Action • Computex Demonstration • Designing with LS102MA and LS1024A • LS102MA/LS1024A Software • LS1 Product Family and Differentiation • Q&A

TM External Use 1 LS1 Product Family

TM External Use 2 Comparing Price/Performance of Freescale ARM Processors

For High performance, “Packet Centric” applications: • Adds ARM to the QorIQ portfolio starting in 2014 • Extend high-performance networking for industrial and IoT markets • Deliver comprehensive ecosystem for ARM, focus on Ease of Use

• Start with 32-bit, intro 64-bit in next generation

64-bit Performance/Features

Efficient and scalable “pixel-centric” controllers • Extends & accelerates QorIQ • Delivering ARM-based products since 2001 • Focusing on automotive, consumer, and industrial Roadmap • Strong ecosystem with i.MX Community support • Focus remains32-bit on “Packet- • Low-power architecture to meet green strategy centric” reliable throughput / / Lowest Price Highest

TM External Use 3 LS1 Family Overview IoT Industrial Enterprise Energy

1.0 2.0 3.0

Extending our customer reach

ECC Virtualization Efficiency Integration

• Delivers 6,000 CoreMark® in under 3 W (Typ) Highly Efficient • QUICC Engine for protocol offload

• ECC protection on L1/L2 and all SRAM High Reliability • Multicore for redundancy

•DDR4, LCD controller, USB 3.0 w/PHY, SD/MMC, Unmatched Integration CAN and SATA 3

Ease of Use CPU Core High Reliability Robust Ecosystem Services, Arm and CW Linux SDK, 5 EBS form Dual Arm A7 Cores ECC protection tools factors, 3rd party SW for TTM

TM External Use 5 LS1020/1/2 Overview

TM External Use 6

Introducing QorIQ LS1020A, LS1021A and LS1022A ARM-powered networking has arrived!

Leveraging over 20 years of networking expertise, the ARM-based QorIQ LS1 family is optimized to offer unprecedented efficiency and security, together with the broadest array of high-speed interconnects and features ever offered in a sub-3W networking processor.

TM External Use 7 QorIQ LS1020A

• Dual ARM Cortex-A7 cores up to 1.0 GHz . ECC protected L1/L2 caches . DDR3L/4 up to 1.6GHz • Over 5,000 Coremark at under 3.6W (TDP power) • Industry best Coremark / mW ratio • Secure Boot and Trust supported • High integration reduces BOM costs for targeted applications: . 802.11ac AP Routers . Line cards . Multi-service gateways . M2M, Smart “X”

Key Architectural Features: Key System Integration Features: • ARM AMBA4 MPCore™ Virtualization • Low-cost NAND/NOR flash systems • DDR3L/4 32-bit with ECC support • Low-cost DRAM systems Package & Board: • 3-port GigE with IEEE 1588 • USB3.0 Super Speed (5GT/s) Package: 525-pin, 19x19mm, 0.8mm ball • 2x PCI Express Gen2 • SATA III (6GT/s) pitch • Multi-protocol 4-Lane SerDes • Audio networking Power: ~2.6W @1.0GHz Typical • PCIe-2, SATA3, SGMII • QorIQ Trust Architecture and Temp: -40C (TA) to 105C (Tj) • QUICC Engine – HDLC/TDM ARM TrustZone support Boards: Tower low-cost board • EnergyStar support with fast wakeup • Alignment with Kinetis/Vybrid portfolio Freescale Linux BSPs • 2Gbps IP /1Gbps IPSec forwarding

TM External Use 8 QorIQ LS1021A

• Dual ARM Cortex-A7 cores up to 1.0 GHz . ECC protected L1/L2 caches . DDR3L/4 up to 1.6GHz • Over 5,000 Coremark at under 3.7W (TDP power) • Industry best Coremark / mW ratio • Outstanding security and IP forwarding • High integration reduces BOM costs for targeted applications: . Industrial gateways . Industrial Automation . Printing & Imaging . HMI Key Architectural Features: Key System Integration Features: . M2M, Smart “X” • ARM AMBA4 MPCore™ Virtualization • Low-cost NAND/NOR flash systems • DDR3L/4 32-bit with ECC support • Low-cost DRAM systems • 3-port GigE with IEEE 1588 • USB3 SuperSpeed Package & Board: • 2x PCI Express Gen2 • Audio networking and motor control Package: 525-pin, 19x19mm, 0.8mm ball • Multi-protocol 4-Lane SerDes • QorIQ Trust Architecture and pitch • PCIe-2, SATA3, SGMII ARM TrustZone support Power: ~2.8W @1.0GHz Typical • QUICC Engine – HDLC/TDM/ProfiBUS • Alignment with Kinetis/Vybrid portfolio Temp: -40C (TA) to 105C (Tj) • EnergyStar support with fast wakeup Boards: Tower low-cost board Freescale Linux BSPs • 2Gbps IP forwarding

TM External Use 9 QorIQ LS1022A

• Dual ARM Cortex-A7 cores up to 600 MHz • Coherent 512KB L2 cache • DDR3L up to 1GHz • Over 3,000 Coremarks at under 3W (TDP power) • Outstanding Coremark / mW ratio: 1.1 Coremarks / mW • Secure Boot and Trust supported • Excellent IP forwarding • Lowest power-to-performance ratio in class, ideal for targeted applications: Key Architectural Features: Key System Integration Features: . Environmental control • ARM AMBA4 MPCore™ Virtualization • Low-cost NAND/NOR flash systems . Industrial controllers • DDR3L 16-bit with ECC support • Low-cost DRAM systems . M2M, Smart “X” • 2-port GigE with IEEE 1588 • USB2.0 • 1x PCI Express Gen2 • QorIQ Trust Architecture and Package & Board: • Advanced Security engine ARM TrustZone support Package: 525-pin, 19x19mm, 0.8mm ball • 4x CAN ports for industrial applications • Alignment with Kinetis/Vybrid portfolio pitch • EnergyStar support with fast wakeup Power: ~2W @ 600MHz Typical • 2Gbps IP forwarding Temp: -40C (TA) to 105C (Tj) Boards: Tower low-cost board Freescale Linux BSPs

TM External Use 10 LS102x Product Family Snapshot LS1021A LS1020A LS1022A

Core Type ARM Cortex™-A7 MPCore™ + NEON Cores/Threads 2 / 2 Frequency Up to 1GHz Up to 600MHz L1 I/D 32kB / 32kB with ECC L2 (Unified) 512kB Shared with ECC SRAM 128kB with ECC DDR 1x(16/32B +ECC) DDR3L/4 DDR3L (8/16B) up to 1.6GT/s up to 1.0GT/s SerDes 4x up to 6.0GHz 1x up to 5GHz Ethernet 3 x 1GE 2 x 1GE PCIe 2 x Gen 2.0 (up to 5.0GT/s) 1x Gen 2.0 SATA 3.0 1 up to 6.0GHz No USB 1 x USB 3.0 and 1 x USB 2.0 1 x USB 2.0 CAN Up to 4 Up to 4 TDM/HDLC 2 No UART/I2C/SPI Up to 8 / 3 / 2 I2S Up to 4 LCD 1 x Controller No Acceleration SEC,QE SEC Trusted architecture PinTM Compatible 19x19mm, 0.8mm pitch External Use 11 Executive Summary of Software Release Schedule

Release Description Availability Date

First Packaged Parts Available (FPP) 14-Apr-14

LS-1 Bootbox-1 (QDS) 29-Apr-14

LS-1 Bootbox-2 (QDS) 6-May-14

LS-1 BSP EAR-1 (QDS) 13-May-14 (engineering drop)

LS-1 BSP EAR-2 (QDS) 5-Jun-14 (engineering drop) LS-1 BSP EAR-3 (TWR) 12-Jun-14 (engineering drop)

LS-1 BSP Alpha (QDS and TWR) 26-Jun-14 (Yocto release, system test) SDK V1.6.x EAR (TWR) 24-Jul-14

SDK V1.6.x RTM (TWR) 22-Aug-14

SDK V1.7 RTM (TWR, QDS) Nov/Dec

TM External Use 13 LS1 Software - Board Support Package (BSP) Early engineering release for QDS board will be available April 1, 2014

Functionality Supported: • U-Boot • Linux − ARM A7 Core initialization in u-boot − ARM A7 Core initialization in kernel − DDR (static setting) − DUART in kernel − RCW, Serdes − RAMDISK − UART − LPUART − FlexTimer in u-boot (2-signals output) − I2C controller & I2C EEPROMs − PCIe RC, Ethernet(e1000) − WDOG − NOR boot − eSDHC (SD) − I2C and EEPROM − DSPI in kernel − DDR (SPD) − eDMA & DMAMUX (Same as in Faraday) − SD − QE (UART) − VeTSEC − Power Management (TMU) − IFC NAND & NOR (Flash programming) − PCIe (RC mode) − USB 2.0 − eSDHC (SDIO, SDXC) − NAND boot − VeTSEC − SD boot − IFC NAND & NOR − ESBC − USB 2.0 (Host, Gadget mode, OTG) − SATA3 − GPIO − DSPI driver − SATA3.0 − SEC 5.5 − FlexCAN

TM External Use 14 LS1020/1/2 in Action

TM External Use 15 Mobile Wireless Gateway [Car]

> 3Watts Trusted Node Crypto Connectivity

TM External Use 16 Point of Sale Station

Connectivity Trusted Node Crypto

TM External Use 17 Automatic Teller Machine

Connectivity Trusted Node Crypto

TM External Use 18 Human Machine Interface

Protocols Trusted Node Connectivity

TM External Use 19 LS1020/1/2 Target Applications

Multi-service IoT Gateway

Industrial automation & control

Point of Sale terminals

ATM Machines

Secure Access Point

Hot Spots

Management processor

Smart Energy Gateway

Robotics

TM External Use 20 Positioning LS102MA and LS1024A Solutions in the Freescale portfolio

TM External Use 21 Go to Market Model for LS102MA & LS1024A

• Acquisition Status − CCP business now fully owned by Freescale, employees have been transferred − Please see separate communication for operational migration of existing customers

• Collateral − Product summary pages & fact sheets available on freescale.com − Re-branded datasheets & reference manuals expected by end May

• Software approach 1. Continue existing Mindspeed model with application-specific SDKs for BHR & NAS . Customers pay for SDK & associated support . Features exposed via API,not direct HW access . New features can be requested by customers and may be subject to NRE . Available now 2. Generic BSP aligned with Digital Networking SDK . Lacks specific optimizations and middleware . Features exposed via API,not direct HW access . New features can still be requested by customers and may be subject to NRE . Availability TBD

TM External Use 23 LS102MA/LS1024A Overview

TM External Use 24

LS102MA/LS1024A Communications Processors

Software API Compatible

Proc.

NAS, VoIP NAS,

EAP, Security EAP,

Comm

C100 LS1024A “Comcerto 2000” DUAL Cortex A9 Home Home LS102MA (“Comcerto 1000”) M821xx Comcerto 100 Routers Single/dual core ARM11 1200MHz Dual core ARM11 Broadband Broadband 650MHz PPFE, DPI, Security, 450MHz Turnkey JVM/OSGI CNAS IPSEC/SSL, 256MB DDR2

IPSEC/SSL, 512MB DDR2 IPSEC/SSL, 2GB DDR3

Offload Offload

Service Service Platforms

2008 Production 2010 Production 2013 Production

TM External Use 25 LS102MA and LS1024A Target Applications Broadband Home Router Smart Home Gateway

Synergy with Existing FSL Networked Attached Storage customer Mobile LTE Router relationships

LS102MA and LS1024A already have strong traction in target applications

TM External Use 26 Market Expansion with Freescale Acquisition

• Broadband Home Router • Mobile LTE Broadband Home Router • Networked Attached Storage • IoT Gateway / Services Offload Platform • Wireless Access Points • Industrial Control • Single Board Computers • Others ??

TM External Use 27 CCP customers – Home Router market

Operators Served

Customers

CCP is established with market leading customers and operators

TM External Use 28 CCP customers – NAS and VoIP

Network Attached Storage

VoIP Gateways

CCP is established with leading customers in Networked Storage and VoIP

TM External Use 29 LS102MA and LS1024A ODMs

TM External Use 30 LS102MA (aka Comcerto1000)

TM External Use 31 LS102MA Block Diagram Application Media & Control Stream General Purpose Processing Processor Processor • 1 x ARM1136 CPU, up to 650MHz • 16/32b DDR2 up to 800MT/s ARM1136 ARM1136

6432-bit 128KB Accelerated Packet Processing DDR2 SRAM DDR2/3 32KB 64KB 64KB 32KB 64KB 64KB MemoryMemory Controller • 1 x ARM1136 CPU, up to 650MHz TCM L1-I L1-D TCM L1-I L1-D Controller • SSL/IPSec crypto acceleration

Flash Controller TDM AMBA AHB crossbar High-speed Interfaces 2x UART • 2x PCIe 2.0, 1 lane each 1x I2C • 1x USB 2.0 (Host/Device) with PHY 1xSPI, GPIO, JTAG CE • 2x GbE (RGMII or RMII)

1x USB2.0 + PHY

GbE GbE PCIe PCIe

2-Lane 2.5GHz SERDES

Key Differentiators: Datapath Acceleration - Dedicated processor for • MSP – Media Stream Processor packet acceleration (& • CE - crypto engine VoIP) - Hardware Security Acceleration

TM External Use 32 LS102MA High Level Features

• Processing Unit • Advanced QoS Features − Dual ARM1136J-S with DSP extensions − HW QoS compliant to HGI2.0 . AMP mode and up to 650MHz . 64KB/64KB L1 Cache & 32KB DTCM − Eight HW Queues and HW four Shapers per GMAC − Internal 128KB ARAM − HW Admittance block for classification and policing • Data Interfaces • Telephony Functions − 2x GMII/RGMII − Full-duplex TDM bus − 1x USB 2.0 with integrated PHY . (1.5444MHz, 2.048MHz, 4.096MHz, or 8.192MHz) − 2x PCIe 1.1, 1 lane each − Wideband Voice Support • Memory Interfaces − Carrier Class Voice quality − Expansion bus interface for expansion devices such as NOR & NAND Flash − Advanced EC technology optimized for DECT − Multiple boot options: • Security Hardware Engines . 8-bit or 16-bit Expansion bus (NOR), I2C, SPI − Full IPSec offload delivers 2Gbps at 512-byte − DDR2-800 up to 1GBytes − Full SSL offload delivers 200Mbps at 1500-byte − Memory DMA engine • Control I/Os • Power Features − 1x I2C, 1x SPI − Low Power Consumption − 2x UARTs . 1-1.6W typical − Watchdog/6x 32-bit Timers − Dynamic clock gating for unused blocks − 31 GPIOs − Dynamic and independent CPU clock adjustment − JTAG

TM External Use 33 LS102MA Software Architecture

. AMP Architecture allows for a separation of core functions from user Applications

. ACP – Application and Control Processor, runs our reference OpenWRT (Linux 2.6.33.5 C1k, 3.2.54 C2k)

. MSP – Media Stream Processor, runs our FPP (Fast Packet Processor) and MSP (Voice Module)

. A Shared memory interface is used for inter-chip communication

. C interface given to our VoIP module and integration to Asterisk for reference

. Linux modules for interfacing with FPP (CMM Conntrack Monitor Module) given as modules and open-source TM 34 External Use 34 LS102MA Ethernet WAN-LAN peformance

2500 5% ) IP forwarding

(Mbps 2000 3% 1500 2% 1000

1% CPU utilization utilization (%) CPU

500 % directionalthroughput

DUT (LS102MA) - B 0 -1% 0 200 400 600 800 1000 1200 1400 1600 Frame Size (bytes) Bi-dir throughput (IPv4) Bi-dir throughput (IPv6) WAN-Eth LAN-Eth CPU util (%), IPv4 CPU util (%), IPv6

2500 5% ) NAT routing

Spirent Test

(Mbps 2000 4% Center 1500 3%

1000 2%

500 1% utilization CPU (%)

directionalthroughput - B 0 % 0 200 400 600 800 1000 1200 1400 1600 Frame Size (bytes) Bi-dir throughput CPU util (%), IPv4

TM External Use 35 LS102MA Wi-Fi performance (dual band)

Setup

AR9380 EVM Linux • (STA) PC2 Wi-Fi 802.11n (3x3, 2.4GHz & 5GHz) AR9380 • Linux EVM Client card: XB113 (AR9380) PC1 (AP) AR9380 • Access points XB112 (AR9380)

AR9380 EVM Linux • iperf, Wi-Fi measurement over the air (STA) PC3

Dual-band concurrent WiFi

450 405 450

400 400

350 335 350 145 300 300 250 145 250 200 200 150 150 260 100 100 Throughput (Mbps)Throughput 190 50 50 0 0 WLAN -> LAN LAN->WLAN

Link 1 Link 2

TM External Use 36 LS102MA CPE Demo

11n AP (Ralink2860) PC-WAN iPod DLNA client WiFi

C1K EVM

PC-LAN Console 10.0.0.1 (iperf -s / 10.0.0.20 GbE 192.168.3.1 WAN vlc client) USB2.0 Stick; .mp4, m4a, wmv content GbE LAN

. C1K EVM running OpenWRT linux (kernel 2.6.21) . VLC server on PC-WAN streaming videos to VLC server on PC-LAN . QoS enabled for video traffic - Ingress video from WAN marked DSCP EF , HW Admittance block prioritising video and voice. . Best effort Data traffic (IPerf TCP) PC-WAN to PC-LAN via C1K ~850Mbps (FPP offload) 192.168.3.166 . Streaming video via ushare DLNA media server running on C1K (USB-Stick content) to iPod via WiFi . JavaVM (IBM’s J9VM compatible with Sun’s J2ME CDC HotSpot VM v 1.1) - CaffeineBenchmark + OSGI (Equinox R4) Push demo . VoIP (POTs-POTs + POTs-SIP call via Asterisk) . Host CPU usage <7% ! (exc JVM benchmark)

TM External Use 37 LS102MA Multi Function EVM

mPCIe & PCIe Connectors

SiLabs FXS Zarlink FXS 2xUSB2.0 2xWAN or WAN+DMZ 4xGE LAN

Additional functionality via daughter boards: PCIe 802.11n WiFi PCIe to SATA II bridge Zarlink SLICs DSPG DECT

TM External Use 38 LS1024A (aka Comcerto2000)

TM External Use 39 LS1024A Block Diagram

ARM ARM General Purpose Processing Cortex-A9 Cortex-A9 • 2 x ARM A9 CPUs, up to 1.2GHz

• 256KB L2 cache 32KB 32KB 32KB 32KB • Neon SIMD & FPU in all CPUs L1-D L1-I L1-D L1-I 64-bit 32-bit 64KB DDR2/3 • 16/32b DDR3 up to 1066MT/s DDR3 Memory 256KB L2 SRAM Memory Controller Controller Accelerated Packet Processing • 2Gbps PPPoE/NAT routing with 64B Secure Boot packets Trust Zone AMBA AXI / AHB crossbar • 2Gbps crypto acceleration Flash Controller • Deep Packet Inspection Engine Power Management • Antivirus SPI/TDM, MS/ProSlic I/F • Application-specific QoS 2x UART DPIE PPFE • Advanced Diagnostics 1x I2C, 1x I2S

2xSPI, GPIO, JTAG

CE DECT 1x USB2.0 + PHY

• Integrated DECT and DECT-ULE

SATA2 SATA2

PCIe GbE GbE GbE 1x USB3.0 + PHY PCIe baseband processor DECT / DECT-ULE 3-Lane 5GHz SERDES Baseband High-speed Interfaces • 2x PCIe 2.0, 1 lane each Datapath Acceleration Key Differentiators: • 2x SATA 2.0 with RAID 0/1/5 • CE - crypto acceleration • Hardware Packet • 1x USB 3.0 with PHY • PPFE - Programmable Packet Forwarding EngineAcceleration & • 1x USB 2.0 (Host/Device) with PHY • DPIE – Deep Packet Inspection Engine Inspection • 3x GbE (3x RGMII or 2x RGMII and 1x SGMII)

TM External Use 40 LS1024A High Level Features

• Processing Unit . Packet Accelerators − Dual ARM Cortex A9 SMP/AMP up to 1.2GHz with NEON . Programmable Packet Forwarding Engine (PPFE) DSP and FPU - 2Gbps of PPPoE/NAT routing with 64B packets − 32KB/32KB L1 Cache & 256KB L2 Cache - HW QoS compliant to HGI2.0 on all data • Data Interfaces interfaces − 3x RGMII or 2x RGMII + 1x SGMII - TCP Offload Engine − IEEE Std. 1588-2007 PTP V2 and 802.1AS . Hardware Security Engine − 1x USB3.0 + 1x USB2.0 (Host/Device) with PHYs - Full IPSec offload delivers 2Gbps at 512-byte − 2x PCIe Gen2 (5 GHz) - Full SSL offload delivers 200Mbps at 1500-byte − 2x SATA2 with RAID 0/1/5 CTRL - Deep Packet Inspection Engine (DPI) up to 200Mbps − XOR engine - A/V across several packets • Memory Interfaces - Application Specific QoS − Glue-less boot from NOR . Telephony Functions − MLC support - DECT base station CAT-iq 2.0 compliant • SW upgradeable to 2.1 and 3.0 − DDR3-1066 with ECC • Supports DECT-ULE • Control I/Os - TDM supports wideband Voice − 1x I2C, 1xI2S, 2x SPI (up to 50 MHz with DMA) . Hardware/Silicon Security − 2x UARTs (1x BT-capable + 1x Regular) - Secure Boot, JTAG Blocking, 8Kb OTP Memory − Watchdog/Timers, RTC . Extensive Power Management Features − 16 dedicated GPIOs (+ 48 more mux’d), - Power islands • Boot Source Selction - Dynamic Voltage and Frequency Scaling (DVFS) − NOR, I2C, SPI, UART, SATA - Power Management Unit (PMU)

TM External Use 41 LS1024A Processing Units • Dual ARM Cortex A9 SMP/AMP up to 1.2GHz Comcerto 2000 X2 X2 JTAG X2 X2 I2C I2S GPIO Timers RTC UARTs SPIs JTAG GPIO Timers RTC•NEON DSP and FPU I2C I2S (oneUARTs High (one SPIsup to JTAG speed)(one High 50MHz)(one up to BlockingJTAG • 32KB/32KBspeed) L1 Cache50MHz) Blocking DECT X 2 (Digital)DECT • 256KB L2 Cache (Digital) Deep Packet Deep Packet Crypto ARM Inspection Crypto Inspection Engine 8kb OTP • High performanceEngine AXI bus Engine SLIC / SLAC Cortex A9 8kb OTP Engine LowSLIC Cost / SLAC interfaceLow Cost (upto 900MHz) interface 32KB 32KB FPU / Internal 64KB RAM Internal L1 32KB L1 32KB NeonFPU / DMAC Boot 256 KB DMAC 64KB RAM Boot ICacheL1 DCacheL1 DSPNeon ROM TDM ICache DCache DSP L2 Cache ROM TDM

AMBA AXI / AHB cross-connect

Programmable Expansion Bus X2 X2 DDR2 / DDR3 PCIeX2 X2 Programmable NORExpansion / NAND Bus SATA2 Packet ControllerDDR2 / DDR3 USB 3.0 ControllerPCIe Packet NOR / NAND USB 2.0 ControllerSATA2 Forwarding controller with (DDR2Controller - 800 / USB 2.0 USB 3.0 (Gen2)Controller Forwarding controller with Controller Controller Controller Engine ECC DDR3(DDR2 - 1066) - 800 / Controller Controller (Gen2) Engine ECC DDR3 - 1066) x3 x3 X3 GEMAC USB 2.0 USB 3.0 X3 (SGMII,GEMAC GMII, DDR2 / DDR3 USB 2.0 USB 3.0 DDR2 / DDR3 PHY PHY PCIe/SATA2/SGMII (SGMII,RGMII)GEMAC GMII, PHY PHY PHY PCIe/SATA2/SGMII PHY SerDes (SGMII,RGMII) GMII, 16 / 32 bit + ECC SerDes RGMII) 16 / 32 bit + ECC

TM External Use 42 LS1024A Interfaces

Comcerto 2000 X2 X2 JTAG X2 X2 I2C I2S • 3x RGMII or 2x RGMIIGPIO + 1x SGMIITimers RTC UARTs SPIs JTAG GPIO Timers RTC I2C I2S (oneUARTs High (one SPIsup to • IEEE Std.JTAG 1588-2007 PTP V2 and 802.1AS speed)(one High 50MHz)(one up to BlockingJTAG speed) 50MHz) Blocking •DECT 2x USB (Host/Device)X 2 with PHYs (Digital)DECT X 2 (Digital) Deep Packet Deep Packet Crypto • 1x USB3.0 + ARM1x USB2.0 Inspection Crypto Inspection Engine ARM 8kb OTP Engine Engine SLIC / SLAC Cortex A9 8kb OTP Engine LowSLIC Cost / SLAC Cortex A9 interface•Low 2x Cost PCIe Gen2 (5(upto GHz) 900MHz) interface (upto 900MHz) 32KB 32KB FPU / Internal 32KB FPU / 64KB RAM Internal L1 32KB L1 32KB NeonFPU / DMAC Boot • 2x SATA2 L1 Neon 256 KB DMAC 64KB RAM Boot ICacheL1 DCacheL1 DSPNeon ROM DCache DSP 256 KB TDM ICache DCache DSP L2 Cache ROM TDM • Capable of RAID 0, 1 or JBODL2 Cache

• XOR engine forAMBA RAID 5 AXI / AHB cross-connect AMBA AXI / AHB cross-connect

Programmable Expansion Bus X2 X2 DDR2 / DDR3 PCIe Programmable NORExpansion / NAND Bus SATA2 Packet ControllerDDR2 / DDR3 USB 3.0 Controller Packet NOR / NAND USB 2.0 Controller Forwarding controller with (DDR2Controller - 800 / (Gen2) Forwarding controller with Controller Controller Engine ECC DDR3(DDR2 - 1066) - 800 / Engine ECC DDR3 - 1066) x3 X3 GEMAC USB 2.0 USB 3.0 (SGMII,GEMAC GMII, DDR2 / DDR3 DDR2 / DDR3 PHY PHY PCIe/SATA2/SGMII (SGMII,RGMII) GMII, PHY PHY SerDes RGMII) 16 / 32 bit + ECC 16 / 32 bit + ECC

TM External Use 43 LS1024A Interfaces

Comcerto 2000 X2 X2 JTAG I2C I2S GPIO Timers RTC UARTs SPIs (one High (one up to JTAG speed) 50MHz) BlockingJTAG Blocking DECT X 2 (Digital)DECT X 2 (Digital) • 1x I2C Deep Packet Deep Packet Crypto ARM Inspection Crypto Inspection Engine ARM 8kb OTP Engine Engine SLIC / SLAC Cortex A9 8kb OTP Engine LowSLIC Cost / SLAC • 1xI2S Cortex A9 interfaceLow Cost (upto 900MHz) interface (upto 900MHz) • 2x SPI32KB 32KB FPU / Internal 32KB FPU / 64KB RAM Internal L1 32KB L1 32KB NeonFPU / DMAC Boot L1 Neon 256 KB DMAC 64KB RAM Boot ICacheL1 DCacheL1 DSPNeon ROM DCache DSP 256 KB TDM ICache DCache DSP L2 Cache ROM TDM • 1x up to 50 MHz withL2 DMA Cache • 2x UARTs AMBA AXI / AHB cross-connect • 1x BT-capableAMBA AXI / AHB cross-connect

Programmable Expansion Bus X2 X2 • Watchdog / TimersDDR2 / DDR3 PCIeX2 X2 Programmable NORExpansion / NAND Bus SATA2 Packet ControllerDDR2 / DDR3 USB 3.0 ControllerPCIe Packet NOR / NAND USB 2.0 ControllerSATA2 Forwarding controller with (DDR2Controller - 800 / USB 2.0 USB 3.0 (Gen2)Controller Forwarding controller with Controller Controller Controller Engine • RTCECC DDR3(DDR2 - 1066) - 800 / Controller Controller (Gen2) Engine ECC DDR3 - 1066) x3 x3 • 64 GPIOs X3 GEMAC USB 2.0 USB 3.0 X3 (SGMII,GEMAC GMII, DDR2 / DDR3 USB 2.0 USB 3.0 DDR2 / DDR3 PHY PHY PCIe/SATA2/SGMII (SGMII,RGMII)GEMAC GMII, • PHY PHY PHY PCIe/SATA2/SGMII 16 dedicated GPIOsPHY SerDes (SGMII,RGMII) GMII, 16 / 32 bit + ECC SerDes 16 / 32 bit + ECC RGMII) • 48 mux’d • 6 PWM Capable TM External Use 44 LS1024A Memory

Comcerto 2000 X2 X2 JTAG X2 X2 I2C I2S GPIO Timers RTC UARTs SPIs • Up to 32 bitsJTAG ECC GPIOadded toTimers NAND controllerRTC I2C I2S (oneUARTs High (one SPIsup to JTAG speed)(one High 50MHz)(one up to • BlockingJTAG speed) 50MHz) DDR2-800Blocking & DDR3-1066 with ECC DECT X 2 (Digital)DECT•Glue-less boot fromX 2 SATA (Digital) Deep Packet Deep Packet Crypto ARM Inspection Crypto Inspection Engine ARM 8kb OTP Engine Engine SLIC / SLAC Cortex A9 8kb OTP Engine LowSLIC Cost / SLAC Cortex A9 interfaceLow Cost (upto 900MHz) interface (upto 900MHz) 32KB 32KB FPU / Internal 32KB FPU / 64KB RAM L1 32KB L1 32KB NeonFPU / DMAC Boot L1 Neon 256 KB ICacheL1 DCacheL1 DSPNeon ROM DCache DSP 256 KB TDM ICache DCache DSP L2 Cache TDM L2 Cache

AMBA AXI / AHB cross-connect AMBA AXI / AHB cross-connect

Programmable Expansion Bus X2 X2 DDR2 / DDR3 PCIeX2 X2 Programmable NOR / NAND SATA2 Packet Controller USB 3.0 ControllerPCIe Packet USB 2.0 ControllerSATA2 Forwarding controller with (DDR2 - 800 / USB 2.0 USB 3.0 (Gen2)Controller Forwarding Controller Controller Controller Engine ECC DDR3 - 1066) Controller Controller (Gen2) Engine x3 x3 X3 GEMAC USB 2.0 USB 3.0 X3 GEMAC DDR2 / DDR3 (SGMII,GEMAC GMII, PHYUSB 2.0 PHYUSB 3.0 PCIe/SATA2/SGMII (SGMII,RGMII)GEMAC GMII, PHY PHY PHY PCIe/SATA2/SGMIISerDes (SGMII,RGMII) GMII, 16 / 32 bit + ECC SerDes RGMII)

TM External Use 45 LS1024A Programmable Packet Forwarding Engine (PPFE)

Comcerto 2000 X2 X2 JTAG X2 X2 I2C I2S GPIO Timers RTC UARTs SPIs JTAG GPIO Timers RTC I2C I2S (oneUARTs High (one SPIsup to JTAG speed)(one High 50MHz)(one up to BlockingJTAG speed) 50MHz) Blocking DECT X 2 (Digital)DECT X 2 (Digital) Deep Packet Deep Packet Crypto ARM Inspection Crypto Inspection Engine ARM• Delivers 2Gbps8kb OTP of PPPoEEngine / NAT routing Enginewith 64- SLIC / SLAC Cortex A9 8kb OTP Engine LowSLIC Cost / SLAC Cortexbyte A9 packets interfaceLow Cost (upto 900MHz) interface (upto 900MHz) 32KB 32KB FPU / Internal 32KB• HWFPU / QoS compliant to HGI2.0 on64KB all RAM data Internal L1 32KB L1 32KB NeonFPU / DMAC Boot L1 Neon 256 KB DMAC 64KB RAM Boot ICacheL1 DCacheL1 DSPNeon ROM DCache DSP 256 KB TDM ICache DCache interfacesDSP L2 Cache ROM TDM L2 Cache • Programmable QoS for further flexibility AMBA• Option AXI to / AHB run ascross-connect a TCP Offload Engine AMBA AXI / AHB cross-connect • CNAS applications

Programmable Expansion Bus X2 X2 Expansion Bus DDR2 / DDR3 PCIeX2 X2 Packet NOR / NAND DDR2 / DDR3 PCIe SATA2 NOR / NAND Controller USB 2.0 USB 3.0 Controller SATA2 Forwarding controller with Controller USB 2.0 USB 3.0 Controller Controller controller with (DDR2 - 800 / Controller Controller (Gen2) Controller Engine ECC DDR3(DDR2 - 1066) - 800 / Controller Controller (Gen2) ECC DDR3 - 1066) x3 x3 X3 GEMAC USB 2.0 USB 3.0 X3 (SGMII,GEMAC GMII, DDR2 / DDR3 USB 2.0 USB 3.0 DDR2 / DDR3 PHY PHY PCIe/SATA2/SGMII (SGMII,RGMII)GEMAC GMII, PHY PHY PHY PCIe/SATA2/SGMII PHY SerDes (SGMII,RGMII) GMII, 16 / 32 bit + ECC SerDes RGMII) 16 / 32 bit + ECC

TM External Use 46 LS1024A Telephony

Comcerto 2000 X2 X2 JTAG X2 X2 I2C I2S GPIO Timers RTC UARTs SPIs JTAG GPIO Timers RTC I2C I2S (oneUARTs High (one SPIsup to JTAG speed)(one High 50MHz)(one up to BlockingJTAG speed) 50MHz) Blocking DECT X 2 (Digital) • XCarrier 2 Class VoIP Deep Packet Deep Packet Crypto ARM Inspection Crypto • Indemnification of G.729 Inspection Engine ARM 8kb OTP Engine Engine SLIC / SLAC Cortex A9 8kb OTP Cortex A9 Engine Low Cost (upto• TDM900MHz) supports wideband Voice interface (upto 900MHz) 32KB •32KBIntegrationFPU / of SLIC/SLAC Low Cost Interface Internal 32KB FPU / 64KB RAM Internal L1 32KB L1 32KB NeonFPU / DMAC Boot L1 Neon 256 KB DMAC 64KB RAM Boot ICacheL1 DCacheL1 DSPNeon ROM • DCacheIntegrationDSP of digital256 KB portion of DECT base station TDM ICache DCache DSP L2 Cache ROM • CAT-iq 2.0L2 compliant Cache (SW upgradeable to 2.1 and 3.0)

AMBA AXI / AHB cross-connect AMBA AXI / AHB cross-connect

TM External Use 47 LS1024A Security

Comcerto 2000 X2 X2 JTAG X2 X2 I2C I2S GPIO Timers RTC UARTs SPIs JTAG GPIO Timers RTC I2C I2S (oneUARTs High (one SPIsup to JTAG speed)(one High 50MHz)(one up to Blocking speed) 50MHz)

DECT X 2 (Digital)DECT X 2 (Digital) Deep Packet Crypto Inspection ARM Engine ARM 8kb OTP Engine SLIC / SLAC Cortex A9 LowSLIC Cost / SLAC Cortex A9 interfaceLow Cost (upto 900MHz) interface (upto 900MHz) 32KB 32KB FPU / Internal 32KB FPU / 64KB RAM Internal L1 32KB L1 32KB NeonFPU / DMAC Boot L1 Neon 256 KB DMAC 64KB RAM Boot ICacheL1 DCacheL1 DSPNeon ROM DCache DSP 256 KB TDM ICache DCache DSP L2 Cache ROM TDM • Full IPSec offload deliversL2 Cache 2Gbps at 256-byte • Full SSL offload delivers 200Mbps at 1500-byte AMBA AXI / AHB cross-connect • Deep AMBAPacket Inspection AXI / AHB up cross-connect to 200Mbps • A/V across several packets Programmable Expansion Bus X2 X2 DDR2 / DDR3 PCIeX2 X2 Programmable NORExpansion / NAND• BusApplication Specific QoS SATA2 Packet ControllerDDR2 / DDR3 USB 3.0 ControllerPCIe Packet NOR / NAND USB 2.0 ControllerSATA2 Forwarding controller with (DDR2Controller - 800 / USB 2.0 USB 3.0 (Gen2)Controller Forwarding • controllerSecure with Boot Controller Controller Controller Engine ECC DDR3(DDR2 - 1066) - 800 / Controller Controller (Gen2) Engine ECC DDR3 - 1066) x3 • Addition of Trust Zone x3 X3 GEMAC • JTAG Blocking USB 2.0 USB 3.0 X3 (SGMII,GEMAC GMII, DDR2 / DDR3 USB 2.0 USB 3.0 DDR2 / DDR3 PHY PHY PCIe/SATA2/SGMII (SGMII,RGMII)GEMAC GMII, PHY PHY PHY PCIe/SATA2/SGMII • 8Kb OTP (One PHYTime Programmable) Memory SerDes (SGMII,RGMII) GMII, 16 / 32 bit + ECC SerDes RGMII) 16 / 32 bit + ECC

TM External Use 48 LS1024A Performance

TM External Use 49 LS1024A Applications Headroom

PacketPacket 2Gbps IPv6 Processing Programmable Processi forwarding, Packet Forwarding ng PPPoE, NAT Engine for 64byte packets, with Neon DSP QoS Neon DSP Dual Cortex A9 6000 DMIPS @ 1.2GHz+

Available For Apps For Example: Management & Control plane;

Dual ARM11 @ 650MHz Enterprise Wi-Fi, Packet OSGi, Energy Dual ARM11 Processing monitoring, etc. @ 450MHz 1560 DMIPS Packet Processing 1080 DMIPS Available For Apps eg. WiFi, OSGi LS102MA LS1024A TM C100 External Use 50 Ethernet WAN-LAN performance

LS1024A EVM WAN-Eth LAN-Eth

Spirent Test Center

IP forwarding NAT routing Bi-dir Bi-dir Bi-dir Bi-dir Frame CPU CPU Frame CPU CPU throughput throughput throughput throughput size utilization utilization size utilization utilization (IPv4) (IPv6) (IPv4) (IPv6) 64 2000 <2% 2000 <2% 64 2000 <2% 2000 <2% 128 2000 <2% 2000 <2% 128 2000 <2% 2000 <2% 256 2000 <2% 2000 <2% 256 2000 <2% 2000 <2% 512 2000 <2% 2000 <2% 512 2000 <2% 2000 <2% 1024 2000 <2% 2000 <2% 1024 2000 <2% 2000 <2% 1280 2000 <2% 2000 <2% 1280 2000 <2% 2000 <2% 1518 2000 <2% 2000 <2% 1518 2000 <2% 2000 <2% LS1024A delivers wirespeed performance for 64B packets without utilizing Cortex A9 CPU

TM External Use 51 LS1024A Wi-Fi 802.11ac Performance

Spirent Test Center Wi-Fi : Eth • QCA9880 for 802.11ac 3x3 LS1024A QCA9880 QCA9880 LS1024A Eth

Target and Measured Rates 1000 1000 1000 1000 850 850 875 850 800 800 720 707 Tx (Target) Rx (Target) 600 600 Tx (Measured) 400 400 Rx (Measured)

Throughput (Mbps) Throughput 200 200

0 0 TCP UDP

LS1024A achieves full rate 802.11n 802.11ac performance currently limited by WiFi chipset

TM External Use 52 NAS Performance Test setup •WD Red drives Windows 1GB Ethernet •4GB file copy •Robocopy PC-1 LS1024A WD (Robocopy) Red •SMB2 •Intel i7 PC SATA- •Second PC for 2-stream test 1GB SATA WD Windows Ethernet cable PC-2 Red (Robocopy)

TM External Use 53 LS1024A in Action

TM External Use 54 EAP example Block Diagram

TM External Use 55 LS1024A BHR Typical Example

NAND DDR3 up High performance (unlimited) to 3GB Java support with

extended memory

DDR

NAND

RJ45 ECC RJ45 RGMII - LAN RJ45 RJ45 OSGI DLNA 2.4GHz WiFi

4 Gig E LAN E Gig 4 JVM

RGMII PCIe AR9380 Gigabit Switch Switch Gigabit

1 Gig E WAN RJ45 Cortex Cortex 3x3 802.11n 4 x LAN + 1 xWAN + LAN 1 x 4

A9 A9 PMU Neon Neon 5GHz WiFi PCIe 4x4 802.11 ac DPI IPSEC/SSL PPFE TOE

Dual TDM/ISI/ZSI 4x4 802.11ac ready

SLIC LS1024A

USB 2.0 USB USB 3.0 USB

USB 3.0 USB 2.0 host conn. host conn.

TM External Use 56 BHR example Block Diagram

TM External Use 57 C2K Headless Gateway Block Diagram

TM External Use 58 C1000 OSGi Home Automation Demo

TM External Use 59 Consumer NAS Example Block Diagram

TM External Use 60 Wireless NAS – Architecture (1-bay)

NAND DDR3 (unlimited up to

size) 2GB

DDR NAND

Gigabi ECC tGigabi Eth RGMII SATA SATA0 PHYt Eth RGMII HDD PHY JVM IPSEC/S DPI S PMU RTC Optional USB WiFi TOE HDD 3.0 PCIe AR9380 Corte Corte 3x3 802.11n USB 2.0 USB host x A9 x A9 WiFi conn. 2.0 Neon Neon QCA988x PCIe 3x3 M86293 802.11ac

JVM = Java Virtual Machine DPI = Deep Packet Inspection RTC = Real-time clock PMU = Power Management Unit

TM External Use 61 61 Wireless NAS – Architecture (2-bay)

NAND DDR3 up (unlimited

size) to 2GB

DDR NAND

EC Gigabit C GigabitEth RGMII SATA SATA0 SATA HDD PHYEth RGMII HDD PHY JVM DPI IPSEC/SS L SATA1 SATA HDD PMU RTC Optional USB HDD 3.0 TOE Cortex Cortex OptionalUSB 2.0 USB A9 A9 hostHDD conn. 2.0 Neon Neon WiFi PCIe QCA988x M86293 3x3 802.11ac

JVM = Java Virtual Machine DPI = Deep Packet Inspection RTC = Real-time clock PMU = Power Management Unit

TM External Use 62 62 C-NAS with Optional Video Transcoding

TM External Use 63 Computex Demonstration

TM External Use 64 TM External Use 65 Android

LS1024A running Android

TM External Use 66 66 VoLTE / MBR C2000 MBR

Connections Data path

Client PC

IMS phone

LTE Network

Host

(VoLTE Media Server) CNE

TM External Use 67 Designing with LS102MA and LS1024A

TM External Use 68 LS102MA and LS1024A Documentation

• Software Documentation − BSP Architecture Specification − SDK Programmer’s Guide − MSP API − VAPI User Guide (html) − Debug Guide • Hardware Documentation − Datasheet − Thermal Application Considerations − Hardware Requirements Specification − Reference Board Hardware Description − Register Reference Guide − Errata • EVM Schematic, Layout, Gerbers, BOM

TM External Use 69 LS1024A deliverables

Engineering samples Production samples Available Silicon Volume

Functionality Demos (with PAE) Customer software dev vehicle Available Hardware (EVM)

Schematics, Layout Guide, BOM Available Preliminary Data Sheet, Application Available notes and Documentation Documentation

OpenWRT Linux-based SDKs for Available HGW and NAS

Software

TM External Use 70 TM External Use 71 71 TM External Use 72 72 TM