HDMI/DVI TMDS Equalizer Data Sheet ADV3003

FEATURES FUNCTIONAL BLOCK DIAGRAM One input, one output HDMI/DVI high speed signal PE_EN TX_EN

equalizer/driver PARALLEL CONTROL AVCC Enables HDMI 1.3 receive-compliant input ADV3003 AVEE VTTI Four TMDS channels per input/output CONTROL LOGIC Supports 250 Mbps to 2.25 Gbps data rates VTTO Supports 25 MHz to 225 MHz pixel clocks + 4 4 + IP[3:0] OP[3:0] Fully buffered unidirectional inputs/outputs BUFFER – 4 4 – Equalized inputs for operation with long HDMI cables IN[3:0] EQ PE ON[3:0] HIGH SPEED BUFFERED (20 meters at 2.25 Gbps) 7212-001

0 Pre-emphasized outputs Figure 1. Matched 50 Ω input and output on-chip terminations Low added jitter TYPICAL APPLICATION DIAGRAM

Transmitter disable feature HDTV SET Reduces power dissipation MEDIA CENTER Disables input terminations HDMI RECEIVER GAME Single-supply operation (3.3 V) CONSOLE SET-TOP BOX Standards compliant: HDMI receiver, DVI 4:1 HDMI ADV3003 40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP SWITCH DVD PLAYER APPLICATIONS BACK PANEL FRONT PANEL CONNECTORS CONNECTOR Multiple input displays 07212-002 Advanced television set (HDTV) front panel connectors Figure 2. HDMI/DVI cable extenders GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADV3003 is a 4-channel transition minimized differential 1. Supports data rates up to 2.25 Gbps, enabling 1080p deep signaling (TMDS) buffer featuring equalized inputs and color (12-bit color) HDMI formats and greater than UXGA pre-emphasized outputs. The ADV3003 features 50 Ω input (1600 × 1200) DVI resolutions. and output terminations, providing full-swing output signal 2. The 12 dB input cable equalizer enables the use of long recovery and minimizing reflections for improved system cables at the input. For a typical 24 AWG cable, the signal integrity. The ADV3003 is targeted at HDMI™/DVI ADV3003 compensates for more than 20 meters at data applications and is ideal for use in systems with long cable rates up to 2.25 Gbps. runs, long PCB traces, and designs with interior cabling. 3. The selectable 6 dB of output pre-emphasis allows the The ADV3003 is provided in a 40-lead, LFCSP, surface-mount, ADV3003 to drive high loss output cables or long PCB traces. RoHS-compliant, plastic package and is specified to operate 4. Matched 50 Ω on-chip input and output terminations over the −40°C to +85°C temperature range. improve system signal integrity. 5. An external control pin, PE_EN, sets the output pre-emphasis to either 0 dB or 6 dB. 6. An external control pin, TX_EN, simultaneously disables both the transmitter and the on-chip input terminations. This feature reduces the power dissipation of the ADV3003 and indicates to a connected source when the ADV3003 is disabled.

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADV3003 Data Sheet

TABLE OF CONTENTS Features ...... 1 Typical Performance Characteristics ...... 6 Applications ...... 1 Theory of Operation ...... 10 Functional Block Diagram ...... 1 Introduction ...... 10 Typical Application Diagram ...... 1 Input Channels ...... 10 General Description ...... 1 Output Channels ...... 10 Product Highlights ...... 1 Application Notes ...... 12 Revision History ...... 2 Pinout ...... 12 Specifications ...... 3 Cable Lengths and Equalization ...... 12 Absolute Maximum Ratings ...... 4 Pre-Emphasis ...... 12 Thermal Resistance ...... 4 PCB Layout Guidelines ...... 12 Maximum Power Dissipation ...... 4 Outline Dimensions ...... 15 ESD Caution ...... 4 Ordering Guide ...... 15 Pin Configuration and Function Descriptions ...... 5

REVISION HISTORY 6/2017—Rev. 0 to Rev. A Changes to Figure 3 ...... 5 Updated Outline Dimensions ...... 15 Changes to Ordering Guide ...... 15

2/2008—Revision 0: Initial Version

Rev. A | Page 2 of 16 Data Sheet ADV3003

SPECIFICATIONS

7 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

Table 1. Parameter Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps Bit Error Rate (BER) PRBS 223 − 1 10−9 Added Deterministic Jitter DR ≤ 2.25 Gbps, PRBS 27 − 1 25 ps (p-p) Added Random Jitter 1 ps (rms) Differential Intrapair Skew At output 1 ps Differential Interpair Skew1 At output 50 ps EQUALIZATION PERFORMANCE Receiver (Fixed Setting)2 Boost frequency = 1.125 GHz 12 dB Transmitter (Pre-Emphasis On)3 Boost frequency = 1.125 GHz 6 dB INPUT CHARACTERISTICS Input Voltage Swing Differential 150 1200 mV

Input Common-Mode Voltage (VICM) AVCC − 800 AVCC mV OUTPUT CHARACTERISTICS4 High Voltage Level Single-ended high speed channel AVCC − 200 AVCC + 10 mV Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV Rise/Fall Time (20% to 80%) 75 178 ps TERMINATION Input Termination Resistance Single-ended 50 Ω Output Termination Resistance Single-ended 50 Ω POWER SUPPLY AVCC Operating range (3.3 V ± 10%) 3 3.3 3.6 V QUIESCENT CURRENT AVCC Output disabled 20 40 mA Output enabled, pre-emphasis off 32 50 mA Output enabled, pre-emphasis on 66 80 mA VTTI Input termination on5 40 54 mA VTTO Output termination on, pre-emphasis off 40 50 mA Output termination on, pre-emphasis on 80 100 mA Output disabled 0 1 mA POWER DISSIPATION6 Output disabled 66 148 mW Output enabled, pre-emphasis off 370 553 mW Output enabled, pre-emphasis on 686 937 mW PARALLEL CONTROL INTERFACE TX_EN, PE_EN

Input High Voltage, VIH 2 V

Input Low Voltage, VIL 0.8 V

1 Differential interpair skew is measured between the TMDS pairs of the HDMI/DVI link. 2 ADV3003 output meets the transmitter eye diagram mask as defined in the HDMI Standard Version 1.3a and the DVI Standard Version 1.0. 3 Cable output meets the receiver eye diagram mask as defined in the HDMI Standard Version 1.3a and the DVI Standard Version 1.0. 4 PE = 0 dB. 5 Typical value assumes the HDMI/DVI link is active with nominal signal swings. Minimum and maximum limits are measured at the extremes of input termination resistance and input voltage swing, respectively. 6 The total power dissipation excludes power dissipated in the 50 Ω off-chip loads.

Rev. A | Page 3 of 16 ADV3003 Data Sheet

ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Rating θJA is specified for the worst-case conditions, that is, a device AVCC to AVEE 3.7 V soldered in a 4-layer JEDEC circuit board for surface-mount VTTI AVCC + 0.6 V packages. JC is specified for the exposed pad soldered to the VTTO AVCC + 0.6 V circuit board with no airflow. Internal Power Dissipation 2.0 W Table 3. High Speed Input Voltage AVCC − 1.4 V < VIN < Package Type θJA θJC Unit AVCC + 0.6 V 40-Lead LFCSP 31.9 2.6 °C/W High Speed Differential Input Voltage 2.0 V

Parallel Interface (TX_EN, PE_EN) AVEE − 0.3 V < VIN < AVCC + 0.6 V MAXIMUM POWER DISSIPATION Storage Temperature Range −65°C to +125°C The maximum power that can be safely dissipated by the ADV3003 Operating Temperature Range −40°C to +85°C is limited by the associated rise in junction temperature. The Junction Temperature 150°C maximum safe junction temperature for plastic encapsulated Stresses at or above those listed under Absolute Maximum devices is determined by the glass transition temperature of the Ratings may cause permanent damage to the product. This is a plastic, approximately 150°C. Temporarily exceeding this limit stress rating only; functional operation of the product at these may cause a shift in parametric performance due to a change or any other conditions above those indicated in the operational in the stresses exerted on the die by the package. Exceeding a section of this specification is not implied. Operation beyond junction temperature of 175°C for an extended period can result the maximum operating conditions for extended periods may in device failure. To ensure proper operation, it is necessary to affect product reliability. observe the maximum power derating as determined by the thermal resistance coefficients. ESD CAUTION

Rev. A | Page 4 of 16 Data Sheet ADV3003

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1 NC NC NC AVEE NC NC NC NC AVCC NC INDICATOR 32 31 40 39 38 37 36 35 34 33

IN0 1 30 AVCC IP0 2 29 PE_EN IN1 3 28 TX_EN IP1 4 27 AVEE VTTI 5 ADV3003 26 AVCC IN2 6 TOP VIEW 25 AVCC IP2 7 (Not to Scale) 24 AVEE IN3 8 23 AVCC IP3 9 22 AVCC AVCC 10 21 NC 11 12 13 14 15 16 17 18 19 20 OP0 OP1 OP2 OP3 ON0 ON1 ON2 ON3 VTTO AVCC NOTES 1. NC = NO CONNECT. 2. THE ADV3003 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE, WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE TO MEET

ELECTRICAL AND THERMAL SPECIFICATIONS. 07212-003 Figure 3. Pin Configuration

Table 4. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 IN0 HS, I High Speed Input Complement. 2 IP0 HS, I High Speed Input. 3 IN1 HS, I High Speed Input Complement. 4 IP1 HS, I High Speed Input. 5 VTTI Power Input Termination Supply. Nominally connected to AVCC. 6 IN2 HS, I High Speed Input Complement. 7 IP2 HS, I High Speed Input. 8 IN3 HS, I High Speed Input Complement. 9 IP3 HS, I High Speed Input. 10, 16, 22, 23, 25, 26, 30, 32 AVCC Power Positive Analog Supply. 3.3 V nominal. 11 ON0 HS, O High Speed Output Complement. 12 OP0 HS, O High Speed Output. 13 VTTO Power Output Termination Supply. Nominally connected to AVCC. 14 ON1 HS, O High Speed Output Complement. 15 OP1 HS, O High Speed Output. 17 ON2 HS, O High Speed Output Complement. 18 OP2 HS, O High Speed Output. 19 ON3 HS, O High Speed Output Complement. 20 OP3 HS, O High Speed Output. 24, 27, 37, ePAD AVEE Power Negative Analog Supply. 0 V nominal. 28 TX_EN Control High Speed Output Enable Parallel Interface. 29 PE_EN Control High Speed Pre-Emphasis Enable Parallel Interface. 21, 31, 33, 34, 35, 36, 38, 39, 40 NC NC No Connect.

1 HS = high speed, I = input, O = output.

Rev. A | Page 5 of 16 ADV3003 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

7 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

DIGITAL ADV3003 SERIAL DATA PATTERN EVALUATION ANALYZER GENERATOR BOARD

SMA COAX CABLE

REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07212-004 Figure 4. Test Circuit Diagram for Rx Eye Diagrams V V 250mV/DI 250mV/DI

0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps 07212-005 07212-007 Figure 5. Rx Eye Diagram at TP2 (Cable = 2 Meters, 24 AWG) Figure 7. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 2 Meters, 24 AWG)

V V 250mV/DI 250mV/DI

0.125UI/DIV AT 2.25Gbps 07212-006 0.125UI/DIV AT 2.25Gbps 07212-008 Figure 6. Rx Eye Diagram at TP2 (Cable = 20 Meters, 24 AWG) Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 Meters, 24 AWG)

Rev. A | Page 6 of 16 Data Sheet ADV3003

7 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

HDMI CABLE

DIGITAL ADV3003 SERIAL DATA PATTERN EVALUATION ANALYZER GENERATOR BOARD

SMA COAX CABLE

REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 07212-009 Figure 9. Test Circuit Diagram for Tx Eye Diagrams V V 250mV/DI 250mV/DI

0.125UI/DIV AT 2.25Gbps 07212-010 0.125UI/DIV AT 2.25Gbps 07212-012 Figure 10. Tx Eye Diagram at TP2, PE = 0 dB Figure 12. Tx Eye Diagram at TP3, PE = 0 dB (Cable = 6 Meters, 24 AWG)

V V 250mV/DI 250mV/DI

0.125UI/DIV AT 2.25Gbps 07212-011 0.125UI/DIV AT 2.25Gbps 07212-013 Figure 11. Tx Eye Diagram at TP2, PE = 6 dB Figure 13. Tx Eye Diagram at TP3, PE = 6 dB (Cable = 10 Meters, 24 AWG)

Rev. A | Page 7 of 16 ADV3003 Data Sheet

7 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

0.6 0.6 ALL CABLES = 24 AWG ALL CABLES = 24 AWG PE = 6dB

0.5 0.5

0.4 0.4

1080p, 12-BIT 0.3 0.3 1.65Gbps JITTER (UI) JITTER JITTER (UI) JITTER 1080p, 12-BIT 0.2 0.2 1080p, 8-BIT 1.65Gbps 1080p, 8-BIT 720p/1080i, 720p/1080i, 8-BIT 0.1 8-BIT 0.1

480p, 8-BIT 480p, 8-BIT 0 0 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 INPUT CABLE LENGTH (m) OUTPUT CABLE LENGTH (m) 07212-014 07212-017 Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup) Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)

50 1.2

1.0 40 1080p, 12-BIT

0.8 1080p, 8-BIT 30

720p/1080i, 0.6 8-BIT

JITTER (ps) JITTER 20 EYE HEIGHT (V) 0.4 DJ p-p 10 0.2 RJ rms

0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 DATA RATE (Gbps) DATA RATE (Gbps) 07212-018 07212-015 Figure 15. Jitter vs. Data Rate Figure 18. Eye Height vs. Data Rate

50 1.2

1.0 40 DJ p-p 0.8 30

0.6

JITTER (ps) JITTER 20 EYE HEIGHT (V) 0.4

10 0.2

RJ rms 0 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 07212-016 07212-019 Figure 16. Jitter vs. Supply Voltage Figure 19. Eye Height vs. Supply Voltage

Rev. A | Page 8 of 16 Data Sheet ADV3003

7 TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.

80 50

45 70 40 60 35 50 DJ p-p 30

40 25 DJ p-p JITTER (ps) JITTER JITTER (ps) JITTER 20 30 15 20 10 10 5 RJ rms RJ rms 0 0 0 0.5 1.0 1.5 2.0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 DIFFERENTIAL INPUT VOLTAGE SWING (V) INPUT COMMON-MODE VOLTAGE (V) 07212-023 07212-020 Figure 20. Jitter vs. Differential Input Voltage Swing Figure 23. Jitter vs. Input Common-Mode Voltage

50 120

115 40 110

105 30

DJ p-p 100

JITTER (ps) JITTER 20 95

90 10

DIFFERENTIAL INPUT RESISTANCE (Ω) RESISTANCE INPUT DIFFERENTIAL 85 RJ rms 0 80 –40 –15 10 35 60 85 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) 07212-021 07212-024 Figure 21. Jitter vs. Temperature Figure 24. Differential Input Resistance vs. Temperature

160 140 RISE 120

100

FALL 80

60

RISE AND FALL TIME (ps) TIME FALL AND RISE 40

20

0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 07212-022 Figure 22. Rise and Fall Time vs. Temperature

Rev. A | Page 9 of 16 ADV3003 Data Sheet

THEORY OF OPERATION INTRODUCTION The input equalizer provides 12 dB of high frequency boost. The primary function of the ADV3003 is to buffer the four high No specific cable length is suggested for this equalization level speed channels of a single HDMI or DVI link. The HDMI/DVI because cable performance varies widely among manufacturers; link consists of four differential, high speed channels and four however, in general, the ADV3003 does not degrade input auxiliary single-ended, low speed control signals. The high signals, even for short input cables. The ADV3003 can equalize speed channels include a data-word clock and three transition more than 20 meters of a 24 AWG cable at 2.25 Gbps, for minimized differential signaling (TMDS) data channels reference cables that exhibit an insertion loss of −15 dB at the running at 10× the data-word clock frequency for data rates fundamental frequency of this data rate. up to 2.25 Gbps. OUTPUT CHANNELS All four high speed TMDS channels on the ADV3003 are Each high speed output differential pair of the ADV3003 identical; that is, the pixel clock can be run on any of the four terminates to the 3.3 V VTTO power supply through two TMDS channels. Receive channel compensation (12 dB of single-ended 50 Ω on-chip resistors, as shown in Figure 26. fixed equalization) is provided for the high speed channels VTTO to support long input cables. The ADV3003 also includes selectable pre-emphasis for driving high loss output cables 50Ω 50Ω or long PCB traces. OP[3:0] ON[3:0] In the intended application, the ADV3003 is placed between a source and a sink, with long cable runs at both the input and the output. TX_EN

INPUT CHANNELS IOUT Each high speed input differential pair terminates to the 3.3 V AVEE VTTI power supply through a pair of single-ended 50 Ω on-chip 07212-026 Figure 26. High Speed Output Simplified Schematic resistors, as shown in Figure 25. When the transmitter of the ADV3003 is disabled by setting the TX_EN control pin as shown in The output termination resistors of the ADV3003 back-terminate Table 5, the input termination resistors are also disabled to the output TMDS transmission lines. These back-terminations, provide a high impedance node at the inputs. Disabling the as recommended in the HDMI 1.3 specification, act to absorb input terminations when the transmitter is disabled indicates to reflections from impedance discontinuities on the output traces, any connected HDMI sources that the link through the improving the signal integrity of the output traces and adding ADV3003 is inactive. flexibility to how the output traces can be routed. For example, VTTI interlayer vias can be used to route the ADV3003 TMDS outputs on multiple layers of the PCB without severely degrading the 50Ω 50Ω quality of the output signal. TX_EN

IP[3:0] CABLE IN[3:0] EQ

AVEE 07212-025 Figure 25. High Speed Input Simplified Schematic

Rev. A | Page 10 of 16 Data Sheet ADV3003

The ADV3003 has an external control pin, TX_EN. The The ADV3003 also includes two levels of programmable output TX_EN pin must be connected to either a logic high (1) or pre-emphasis, 0 dB and 6 dB. The output pre-emphasis level can low (0), in accordance with the logic values set forth in Table 1. be manually configured by setting the PE_EN pin. The PE_EN The use of the TX_EN pin is described in Table 5. When the pin must be connected to either a logic high (1) or low (0), in transmitter is enabled by setting TX_EN to 1, both the input accordance with the logic values set forth in Table 1. The use of and output terminations are enabled. Setting TX_EN to 0 the PE_EN pin is described in Table 6. No specific cable length disables the transmitter, reducing power when the transmitter is suggested for use with either pre-emphasis setting, because is not in use. When the transmitter is disabled, the input termi- cable performance varies widely among manufacturers. nation resistors are also disabled to present a high impedance state at the input and indicate to any connected HDMI sources Table 6. Pre-Emphasis Enable Setting that the link through the ADV3003 is inactive. PE_EN Boost 0 0 dB Table 5. Transmitter Enable Setting 1 6 dB Input Transmitter Output TX_EN Termination State Termination In a typical application, the output of the ADV3003 is connected to the input of an HDMI/DVI receiver, which 0 Off Off On provides a second set of matched terminations in accordance 1 On On On with the HDMI 1.3 specification. If neither receiver nor receiver termination is connected to the output of the ADV3003 in the end-application, each ADV3003 output pin should be tied to 3.3 V through a 50 Ω resistor.

Rev. A | Page 11 of 16 ADV3003 Data Sheet

APPLICATION NOTES The ADV3003 is a TMDS buffer featuring equalized inputs PRE-EMPHASIS and pre-emphasized outputs. It is intended for use as a buffer The pre-emphasis of the ADV3003 acts to boost the initial in HDMI/DVI systems with long input cable runs, and is fully voltage swing of the output signals. Pre-emphasis provides a HDMI 1.3 receive-compliant. distinct advantage in systems where the ADV3003 is driving PINOUT either high loss cables or long PCB traces, because the added The ADV3003 is designed to have an HDMI/DVI receiver boost helps to ensure that the data eye at the far end of the pinout at its input and a transmitter pinout at its output. This output cables or PCB traces meets the HDMI receive mask. The makes the ADV3003 ideal for use in advanced TV front-panel use of pre-emphasis in a system is highly application specific. connectors and AVR-type applications where a designer routes PCB LAYOUT GUIDELINES both the inputs and the outputs directly to HDMI/DVI connec- The ADV3003 is a 4-channel TMDS buffer, targeted for use in tors—all of the high speed signals can be routed on one side of HDMI and DVI video applications. Although the HDMI/DVI the board. link consists of four differential, high speed channels and four The ADV3003 provides 12 dB of input equalization, so it can single-ended, low speed auxiliary control signals, the ADV3003 compensate for the signal degradation of long input cables. In buffers only the high speed signals. addition, the ADV3003 can also provide up to 6 dB of The high speed signals carry the audiovisual (AV) data, which pre-emphasis that boosts the output TMDS signals and allows is encoded by a technique called TMDS. For HDMI, the TMDS the ADV3003 to precompensate when driving long PCB traces data is further encrypted in accordance with the high bandwidth or high loss output cables. The net effect of the input equalization digital content protection (HDCP) standard. and output pre-emphasis is that the ADV3003 can compensate for signal degradation of both the input and output cables; it The TMDS signals are differential, unidirectional, and high acts to reopen a closed input data eye and transmit a full-swing speed (up to 2.25 Gbps). The channels that carry the video data HDMI signal to an end receiver. must have a controlled impedance, be terminated at the receiver, and be capable of operating up to at least 2.25 Gbps. It is especially CABLE LENGTHS AND EQUALIZATION important to note that the PCB traces that carry the TMDS The 12 dB equalizer of the ADV3003 is optimized for video signals should be designed with a controlled differential data rates of 2.25 Gbps and can equalize more than 20 meters impedance of 100 Ω. The ADV3003 provides single-ended of 24 AWG HDMI cable at the input at 2.25 Gbps, the data rate 50 Ω terminations on chip for both its inputs and outputs. corresponding to the video format 1080p with 12-bit deep color. Transmitter termination is not fully specified by the HDMI The length of cable that can be used in a typical HDMI/DVI standard, but its inclusion in the ADV3003 improves the application depends on a large number of factors including overall system signal integrity. TMDS Signals • Cable quality: The quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors In the HDMI/DVI standard, four differential pairs carry the have lower signal degradation per unit length. TMDS signals. In DVI, three of these pairs are dedicated to • Data rate: The data rate being sent over the cable. The signal carrying RGB video and sync data. For HDMI, audio data is degradation over HDMI cables increases with data rate. also interleaved with the video data; the DVI standard does • Edge rates: The edge rates of the source. Slower input edges not incorporate audio information. The fourth high speed result in more significant data eye closure at the differential pair is used for the AV data-word clock, which end of a cable. runs at one-tenth the speed of the video data channels. • Receiver sensitivity: The sensitivity of the terminating The four high speed channels of the ADV3003 are identical. receiver. No concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any Because of these considerations, specific cable types and lengths TMDS signal; the user chooses which signal is routed over are not recommended for use with this equalizer. The ADV3003 which channel. In addition, the TMDS channels are symmetric; equalizer does not degrade signal integrity, even for short input therefore, the p and n of a given differential pair are inter- cables. changeable, provided the inversion is consistent across all inputs and outputs of the ADV3003.

Rev. A | Page 12 of 16 Data Sheet ADV3003

The ADV3003 buffers the TMDS signals; therefore, the input Controlling the Characteristic Impedance of a TMDS traces can be considered electrically independent of the output Differential Pair traces. In most applications, the quality of the signal on the input The characteristic impedance of a differential pair depends on a TMDS traces is more sensitive to the PCB layout. Regardless of number of variables including the trace width, the distance the data being carried on a specific TMDS channel, or whether between the two traces, the height of the dielectric material the TMDS line is at the input or the output of the ADV3003, all between the trace and the reference plane below it, and the four high speed signals should be routed on a PCB in accordance dielectric constant of the PCB binder material. To a lesser with the same RF layout guidelines. extent, the characteristic impedance also depends upon the Layout for the TMDS Signals trace thickness and the presence of solder mask. The TMDS differential pairs can either be microstrip traces, Many combinations can produce the correct characteristic imped- routed on the outer layer of a board, or stripline traces, routed ance. It is generally required to work with the PC board fabri- on an internal layer of the board. If microstrip traces are used, cator to obtain a set of parameters to produce the desired results. there should be a continuous reference plane on the PCB layer One consideration is how to guarantee a differential pair with a directly below the traces. If stripline traces are used, they must differential impedance of 100 Ω over the entire length of the be sandwiched between two continuous reference planes in the trace. One technique to accomplish this is to change the width PCB stack-up. Additionally, the p and n of each differential pair of the traces in a differential pair based on how closely one trace must have a controlled differential impedance of 100 Ω. The is coupled to the other. When the two traces of a differential characteristic impedance of a differential pair is a function of pair are close and strongly coupled, they should have a width several variables including the trace width, the distance separating that produces a 100 Ω differential impedance. When the traces the two traces, the spacing between the traces and the reference split apart, for example, to go into a connector, and are no plane, and the dielectric constant of the PC board binder material. longer so strongly coupled, the width of the traces should be Interlayer vias introduce impedance discontinuities that can increased to yield a differential impedance of 100 Ω in the new cause reflections and jitter on the signal path; therefore, it is configuration. preferable to route the TMDS lines exclusively on one layer of the Ground Current Return board, particularly for the input traces. In addition, to prevent unwanted signal coupling and interference, route the TMDS In some applications, it may be necessary to invert the output signals away from other signals and noise sources on the PCB. pin order of the ADV3003. This requires routing of the TMDS traces on multiple layers of the PCB. When routing differential Both traces of a given differential pair must be equal in length pairs on multiple layers, it is also necessary to reroute the corres- to minimize intrapair skew. Maintaining the physical symmetry ponding reference plane to provide one continuous ground of a differential pair is integral to ensuring its signal integrity; current return path for the differential signals. Standard plated excessive intrapair skew can introduce jitter through duty cycle through-hole vias are acceptable for both the TMDS traces and distortion (DCD). The p and n of a given differential pair should the reference plane. An example of this routing is illustrated in always be routed together to establish the required 100 Ω Figure 27. To lower the impedance between the two ground differential impedance. Enough space should be left between planes, additional through-hole vias should be used to stitch the the differential pairs of a given group so that the n of one pair planes together, as space allows. does not couple to the p of another pair. For example, one tech- THROUGH-HOLE VIAS nique is to make the interpair distance 4× to 10× wider than the intrapair spacing. SILKSCREEN Any group of four TMDS channels (input or output) should LAYER 1: SIGNAL (MICROSTRIP) have closely matched trace lengths to minimize interpair skew. Severe interpair skew can cause the data on the four different PCB DIELECTRIC channels of a group to arrive out of alignment with one another. LAYER 2: GND (REFERENCE PLANE) A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on FR4 material. PCB DIELECTRIC LAYER 3: PWR The length of the TMDS traces should be minimized to (REFERENCE PLANE) reduce overall signal degradation. Commonly used PC board PCB DIELECTRIC material such as FR4 is lossy at high frequencies, so long traces LAYER 4: SIGNAL (MICROSTRIP) on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through intersymbol SILKSCREEN interference (ISI). KEEP REFERENCE PLANE ADJACENT TO SIGNAL ON ALL LAYERS TO PROVIDE CONTINUOUS GROUND CURRENT RETURN PATH. 07212-027 Figure 27. Example Routing of Reference Plane

Rev. A | Page 13 of 16 ADV3003 Data Sheet

TMDS Terminations In a typical application, all pins labeled AVEE, including the The ADV3003 provides internal 50 Ω single-ended ePAD, should be connected directly to ground. All pins labeled terminations for all its high speed inputs and outputs. AVCC, VTTI, or VTTO should be connected to 3.3 V. The The output termination resistors are always enabled and act supplies can also be powered individually, but care must be to back-terminate the output TMDS transmission lines. These taken to ensure that each stage of the ADV3003 is powered back-terminations act to absorb reflections from impedance correctly. discontinuities on the output traces, improving the signal Power Supply Bypassing integrity of the output traces and adding flexibility to how the The ADV3003 requires minimal supply bypassing. When output traces can be routed. For example, interlayer vias can be powering the supplies individually, place a 0.01 μF capacitor used to route the ADV3003 TMDS outputs on multiple layers of between each 3.3 V supply pin (AVCC, VTTI, and VTTO) and the PCB without severely degrading the quality of the output ground to filter out supply noise. Generally, bypass capacitors signal. should be placed near the power pins and should connect In a typical application, the ADV3003 output is connected to an directly to the relevant supplies (without long intervening HDMI/DVI receiver or another device with a 50 Ω single-ended traces). For example, to improve the parasitic inductance of the input termination. It is recommended that the outputs be power supply decoupling capacitors, minimize the trace length terminated with external 50 Ω on-board resistors when the between capacitor landing pads and the vias as shown in ADV3003 is not connected to another device. Figure 28. Auxiliary Control Signals RECOMMENDED There are four low-speed, single-ended control signals associated with each source or sink in an HDMI/DVI application. These control signals are hot plug detect (HPD), consumer electronics EXTRA ADDED INDUCTANCE control (CEC), and two display data channel (DDC) lines. The two signals on the DDC bus are serial data and serial clock (SDA and SCL, respectively). The ADV3003, which is a TMDS-only part, does not buffer these low speed signals. If the end application NOT RECOMMENDED requires it, use other means to buffer these signals. 07212-028 Power Supplies Figure 28. Recommended Pad Outline for Bypass Capacitors The ADV3003 has three separate power supplies referenced In applications where the ADV3003 is powered by a single 3.3 V to a single ground, AVEE. The supply/ground pairs are as supply, it is recommended to use two reference supply planes follows: AVCC/AVEE, VTTI/AVEE, and VTTO/AVEE. and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF The AVCC/AVEE supply (3.3 V) powers the core of the capacitors. The capacitors should via down directly to the ADV3003. The VTTI/AVEE supply (3.3 V) powers the input supply planes and be placed within a few centimeters of the termination (see Figure 25). Similarly, the VTTO/AVEE supply ADV3003. (3.3 V) powers the output termination (see Figure 26).

Rev. A | Page 14 of 16 Data Sheet ADV3003

OUTLINE DIMENSIONS

DETAIL A (JEDEC 95) 6.10 0.30 6.00 SQ 0.23 PIN 1 5.90 0.18 INDICATOR PIN 1 31 40 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 30 1 0.50 BSC EXPOSED 4.45 PAD 4.30 SQ 4.25

21 10 20 11 0.45 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.35 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE PKG-003438 COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5. 01-25-2017-A Figure 29. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.75 mm Package Height (CP-40-10) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Ordering Model1 Range Package Description Option Quantity ADV3003ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-10 490 ADV3003ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP], Reel 7 CP-40-10 1500 ADV3003-EVALZ Evaluation Board

1 Z = RoHS Compliant Part.

Rev. A | Page 15 of 16 ADV3003 Data Sheet

NOTES

©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07212-0-6/17(A)

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