Connecting EPSON Display Controllers to Casio LCD Panels

Rev.1.00

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Table of Contents

1. INTRODUCTION ...... 1 2. DISPLAY CONTROLLER COMPATIBILITY...... 1 3. CONNECTING TO THE CASIO COM27T2984...... 3 3.1 COM27T2984 Pin Mapping ...... 3 3.2 Connection Examples ...... 4 3.2.1 Connecting the COM27T2984 to the S1D13513 ...... 5 3.2.2 Connecting the COM27T2984 to the S1D13706 ...... 7 3.2.3 Connecting the COM27T2984 to the S1D13A05...... 9 3.3 Example Register Settings...... 11 4. CONNECTING TO THE CASIO COM41T4148...... 13 4.1 COM41T4148 Pin Mapping ...... 13 4.2 Connection Examples ...... 15 4.2.1 Connecting the COM41T4148 to the S1D13513 ...... 15 4.2.2 Connecting the COM41T4148 to the S1D13719 ...... 20 4.2.3 Connecting the COM41T4148 to the S1D13748 ...... 26 4.3 Example Register Settings...... 32 5. CONNECTING TO THE CASIO COM35H3827...... 36 5.1 COM35H3827 Pin Mapping...... 36 5.2 Connection Examples ...... 37 5.2.1 Connecting the COM35H3827 to the S1D13513...... 37 5.2.2 Connecting the COM35H3827 to the S1D13748...... 39 5.3 Example Register Settings...... 41 6. CONNECTING TO THE CASIO COM55T5108...... 43 6.1 COM55T5108 Pin Mapping ...... 43 6.2 Connection Examples ...... 44 6.2.1 Connecting the COM55T5108 to the S1D13513 ...... 44 6.2.2 Connecting the COM55T5108 to the S1D13706 ...... 46 6.2.3 Connecting the COM55T5108 to the S1D13A05...... 48 6.2.4 Connecting the COM55T5108 to the S1D13719 ...... 50 6.2.5 Connecting the COM55T5108 to the S1D13742 ...... 52 6.2.6 Connecting the COM55T5108 to the S1D13743 ...... 54 6.2.7 Connecting the COM55T5108 to the S1D13748 ...... 56 6.3 Example Register Settings...... 58 7. CONNECTING TO THE CASIO COM57T5120...... 62 7.1 COM57T5120 Pin Mapping ...... 62 7.2 Connection Examples ...... 63 7.2.1 Connecting the COM57T5120 to the S1D13513 ...... 64 7.2.2 Connecting the COM57T5120 to the S1D13748 ...... 69 7.3 Example Register Settings...... 74 8. CONNECTING TO THE CASIO COM65T6111 ...... 77 8.1 COM65T6111 Pin Mapping ...... 77 8.2 Connection Examples ...... 79 8.2.1 Connecting the COM65T6111 to the S1D13513...... 79 8.2.2 Connecting the COM65T6111 to the S1D13742...... 82

Connecting EPSON Display Controllers EPSON i to Casio LCD Panels (Rev 1.00)

8.2.3 Connecting the COM65T6111 to the S1D13748...... 85 8.3 Example Register Settings...... 88 9. CONNECTING TO THE CASIO COM80T8102...... 90 9.1 COM80T8102 Pin Mapping ...... 90 9.2 Connection Examples ...... 91 9.2.1 Connecting the COM80T8102 to the S1D13513 ...... 92 9.3 Example Register Settings...... 94

ii EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 1. INTRODUCTION

1. INTRODUCTION

This document provides connection information enabling EPSON Display Controllers to control a variety of Casio Computer Co., Ltd LCD panels. This document includes connector details, pin mappings, and example register settings.

For detailed technical information on EPSON Display Controllers or Casio LCD panels, please refer to the specification or technical manual for each product.

This document is updated as appropriate. Please check for the latest revision of this document before beginning any development. The latest revision can be downloaded at .

2. DISPLAY CONTROLLER COMPATIBILITY

This document discusses the following Casio TFT panels. COM27T2984 (TFT 2.7inch, QVGA, portrate) COM41T4148 (TFT 4.1inch, QVGA) COM35H3827(TFT 3.5inch, QVGA, portrate) COM55T5108 (TFT 5.5inch, QVGA) COM57T5120 (TFT 5.7inch, QVGA) COM65T6111 (TFT 6.5inch, VGA) COM80T8102 (TFT 8.0inch, VGA)

Each Casio TFT panel is compatible with one or more of the following EPSON display controllers. S1D13513 (QFP 208-pin or PBGA 256-pin) S1D13706 (TQFP 100-pin) S1D13A05 (PFBGA 121-pin or QFP 128-pin) S1D13719 (PFBGA 180-pin or FCBGA 240-pin or QFP 208-pin) S1D13742 (FCBGA 121-pin or QFP 144-pin) S1D13743 (FCBGA 121-pin or QFP 144-pin) S1D13748 (PFBGA 121-pin or QFP 144-pin)

Connecting EPSON Display Controllers EPSON 1 to Casio LCD Panels (Rev 1.00) 2. DISPLAY CONTROLLER COMPATIBILITY

The following table summarizes which EPSON display controllers are compatible with each Casio TFT panels.

Casio Panel S1D13513 S1D13706 S1D13A05 S1D13719 S1D13742 S1D13743 S1D13748 COM27T2984 √ √ √ √ √ √ √ COM35H3827 √ √ √ √ √ √ √ COM41T4148 √ √ √ √ √ √ √ COM55T5108 √ √ √ √ √ √ √ COM57T5120 √ √ √ √ √ √ √ COM65T6111 √ √ √ √ √ - √ COM80T8102 √ √ √ √ √ - √

The following table shows other compatible panels with above listed standard panels. These panels can also be connected to EPSON display controllers.

Casio Panel Same interface model COM27T2984 COM27T2940 COM27H2M90 COM35H3827 COM35H3833 COM22T2M59, COM35T3829, COM35T3830, COM35T3831, COM35T3832, COM41T4148 COM35T3818, COM35T3149, COM41T4150, COM50T5119, COM50T5117,COM50T5123 COM55T5108 - COM57T5120 COM57T5127, COM57T5135, COM57H5139 COM65T6111 COM65H6114 COM80T8102 -

Link for Casio computer corporation LCD products web site http://device.casio.jp/en/products/prd_1.html

2 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

3. CONNECTING TO THE CASIO COM27T2984

The Casio COM27T2984 TFT panel is compatible with the S1D13513, S1D13706, and S1D13A05 display controllers. The following sections will provide connector details, pin mappings, and example register settings for these combinations.

3.1 COM27T2984 Pin Mapping

The COM27T2984 TFT panel uses a 45-pin connector with the following pin mapping.

COM27T2984 Pin Mapping Connector Pin Name Pin Description Pin# 1 VSS GND 2 COMOUT Rectangular wave output for common driver 3 VSS GND 4 VCOM Common driver signal 5 VSS GND 6 V13 Gamma generation reference for negative side 7 V7 Gamma generation reference for negative side 8 V6 Gamma generation reference for positive side 9 VDD VDD (Logic) 3.0V±0.3V 10 CLK Dot clock 11 V0 Gamma generation reference for positive side 12 VSS GND 13 D20 RED data signal (LSB) 14 D21 RED data signal 15 D22 RED data signal 16 D23 RED data signal 17 D24 RED data signal 18 D25 RED data signal (MSB) 19 D10 GREEN data signal (LSB) 20 D11 GREEN data signal 21 D12 GREEN data signal 22 D13 GREEN data signal 23 D14 GREEN data signal 24 D15 GREEN data signal (MSB) 25 D00 BLUE data signal (LSB) 26 D01 BLUE data signal 27 D02 BLUE data signal 28 D03 BLUE data signal 29 D04 BLUE data signal 30 D05 BLUE data signal (MSB) 31 VSS GND 32 AVDD VDD (analog) 5.0V±0.2V 33 HSYNC Horizontal synchronous signal 34 VGL Power for gate driver (-) -15V（±1.0V） 35 DE Input data enable (Hi-active) 36 VGH Power for gate driver (+) +15V（±1.0V） 37 VSYNC Vertical synchronous signal 38 VSS GND 39 YU OPEN 40 XR OPEN 41 YD OPEN 42 XL OPEN 43 VSS GND

Connecting EPSON Display Controllers EPSON 3 to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

Connector Pin Name Pin Description Pin# 44 BLL LED driver power (cathode side) 45 BLH LED driver power (anode side)

Note The recommended connector is a FH23-45S-0.3SHW(0.5) from Hirose Electric Co., Ltd. The connector is a 0.3mm pitch 45-pin FPC connector (13.8mm x 0.2mm gold plate).

3.2 Connection Examples

The information in this section provides connection examples for the S1D13513, S1D13706, and S1D13A05 display controllers. For the S1D13513 and S1D13A05, the display controller is available in two packages. The connection information differs for each package and is listed separately.

In addition to the pin connections for the selected display controller, the COM27T2984 requires the following power supplies.

VDD +3.0V (±0.3V) AV D D + 5 .0 V ( ±0.2V) VGH +15V (±1.0V) VGL -15V (±1.0V)

For VDD, select a voltage within the supportable range of the Display Controller.

For further details on the COM27T2984, such as power consumption and absolute maximum ratings, please contact your Casio representative.

4 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

3.2.1 Connecting the COM27T2984 to the S1D13513

The following diagram shows an example implementation of the COM27T2984 panel connected to the S1D13513.

COM27T2984 S1D13513 3.0V

VDD HVDD2

DE FPDRDY D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17] HSYNC FPLINE

VSYNC FPFRAME CLK FPSHIFT

GND VSS

The following table provides a detailed pin listing for the required connections between the COM27T2984 and the S1D13513. Pin mappings are shown for both S1D13513 package types.

Connecting the COM27T2984 to the S1D13513 LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector LCD Panel Pin Description Pin Name QFP Pin# PBGA Ball# Pin Name Pin# 1 VSS GND Note Note VSS 2 COMOUT Rectangular wave output for common driver - - - 3 VSS GND Note Note VSS 4 VCOM Common driver signal - - - 5 VSS GND Note Note VSS Gamma generation reference for negative 6 V13 - - - side Gamma generation reference for negative 7 V7 - - - side Gamma generation reference for positive 8 V6 - - - side 9 VDD VDD (Logic) +3.0V to +3.3V 57,65,75 L5,L8,T6 HVDD2 10 CLK CLK 77 P8 FPSHIFT Gamma generation reference for positive 11 V0 - - - side

Connecting EPSON Display Controllers EPSON 5 to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector LCD Panel Pin Description Pin Name QFP Pin# PBGA Ball# Pin Name Pin# 12 VSS GND Note Note VSS 13 D20 RedD02 61 N5 FPDAT11 14 D21 Red D03 62 M5 FPDAT10 15 D22 Red D04 63 P6 FPDAT9 16 D23 Red D05 72 T7 FPDAT2 17 D24 Red D06 73 N7 FPDAT1 18 D25 Red D07 74 M7 FPDAT0 19 D10 Green D12 56 R4 FPDAT14 20 D11 Green D13 59 T4 FPDAT13 21 D12 Green D14 60 T5 FPDAT12 22 D13 Green D15 69 L7 FPDAT5 23 D14 Green D16 70 P7 FPDAT4 24 D15 Green D17 71 R7 FPDAT3 25 D00 Blue D02 53 N4 FPDAT17 26 D01 Blue D03 54 P4 FPDAT16 27 D02 Blue D04 55 T2 FPDAT15 28 D03 Blue D05 64 R6 FPDAT8 29 D04 Blue D06 67 K6 FPDAT7 30 D05 Blue D07 68 M6 FPDAT6 31 VSS GND Note Note VSS 32 AVDD VDD (analog) 5.0V±0.2V - - - 33 HSYNC HSYNC 79 T8 FPLINE 34 VGL Power for gate driver (-) -15V (±1.0V) - - - 35 DE DE 80 M8 FPDRDY 36 VGH Power for gate driver (+) +15V (±1.0V) - - - 37 VSYNC VSYNC 78 R8 FPFRAME 38 VSS GND Note Note VSS 39 YU not connected - - - 40 XR not connected - - - 41 YD not connected - - - 42 XL not connected - - - 43 VSS GND Note Note VSS 44 BLL LED driver power (cathode side) - - - 45 BLH LED driver power (anode side) - - - S1D13513 HVDD2 and COM27T2984 VDD must be configured between +3.0V to +3.3V.

Note Allocation of VSS pin for each packages are as follows. QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16

6 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

3.2.2 Connecting the COM27T2984 to the S1D13706

The following diagram shows an example implementation of the COM27T2984 panel connected to the S1D13706.

COM27T2984 3.0V S1D13706

VDD NIOVDD

DE DRDY D[25:23] (R) FPDAT[0:2]

D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17] HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT

VSS VSS

The following table provides a detailed pin listing for the required connections between the COM27T2984 and the S1D13706. Pin mappings are shown for both S1D13706 package types.

Connecting the COM27T2984 to the S1D13706 LCD Panel LCD Panel S1D13706 S1D13706 Connector LCD Panel Pin Description Pin Name TQFP Pin# Pin Name Pin# 1 VSS GND Note VSS 2 COMOUT Rectangular wave output for common driver - - 3 VSS GND Note VSS 4 VCOM Common driver signal - - 5 VSS GND Note VSS 6 V13 Gamma generation reference for negative side - - 7 V7 Gamma generation reference for negative side - - 8 V6 Gamma generation reference for positive side - - 9 VDD VDD (Logic) 3.0V±0.3V 37,49,63,76 NIOVDD 10 CLK Dot clock 54 FPSHIFT 11 V0 Gamma generation reference for positive side - - 12 VSS GND Note VSS 13 D20 RED data signal (LSB) 68 FPDAT11 14 D21 RED data signal 67 FPDAT10 15 D22 RED data signal 66 FPDAT9

Connecting EPSON Display Controllers EPSON 7 to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

LCD Panel LCD Panel S1D13706 S1D13706 Connector LCD Panel Pin Description Pin Name TQFP Pin# Pin Name Pin# 16 D23 RED data signal 57 FPDAT2 17 D24 RED data signal 56 FPDAT1 18 D25 RED data signal (MSB) 55 FPDAT0 19 D10 GREEN data signal (LSB) 71 FPDAT14 20 D11 GREEN data signal 70 FPDAT13 21 D12 GREEN data signal 69 FPDAT12 22 D13 GREEN data signal 60 FPDAT5 23 D14 GREEN data signal 59 FPDAT4 24 D15 GREEN data signal (MSB) 58 FPDAT3 25 D00 BLUE data signal (LSB) 74 FPDAT17 26 D01 BLUE data signal 73 FPDAT16 27 D02 BLUE data signal 72 FPDAT15 28 D03 BLUE data signal 65 FPDAT8 29 D04 BLUE data signal 64 FPDAT7 30 D05 BLUE data signal (MSB) 61 FPDAT6 31 VSS GND Note VSS 32 AVDD VDD (analog) 5.0V±0.2V - - 33 HSYNC Horizontal synchronous signal 53 FPLINE 34 VGL Power for gate driver (-) -15V（±1.0V） - - 35 DE Input data enable (Hi-active) 48 DRDY 36 VGH Power for gate driver (+) +15V（±1.0V） - - 37 VSYNC Vertical synchronous signal 52 FPFRAME 38 VSS GND Note VSS 39 YU OPEN - - 40 XR OPEN - - 41 YD OPEN - - 42 XL OPEN - - 43 VSS GND Note VSS 44 BLL LED driver power (cathode side) - - 45 BLH LED driver power (anode side) - - S1D13706 NIOVDD and COM27T2984 VDD must be configured between +3.0V to +3.3V.

Note Allocation of VSS pin are as follows. 14,25,36,50,62,75,100

8 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

3.2.3 Connecting the COM27T2984 to the S1D13A05

The following diagram shows an example implementation of the COM27T2984 panel connected to the S1D13A05.

COM27T2984 S1D13A05 3.0V

VDD IOVDD

DE DRDY D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17] HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT

VSS VSS

The following table provides a detailed pin listing for the required connections between the COM27T2984 and the S1D13A05. Pin mappings are shown for both S1D13A05 package types.

Connecting the COM27T2984 to the S1D13A05 LCD Panel S1D13A05 LCD Panel S1D13A05 S1D13A05 Connecto LCD Panel Pin Description PFBGA Pin Name QFP Pin# Pin Name r Pin# Ball# 1 VSS GND Note Note VSS 2 COMOUT Rectangular wave output for common driver - - - 3 VSS GND Note Note VSS 4 VCOM Common driver signal - - - 5 VSS GND Note Note VSS Gamma generation reference for negative 6 V13 - - - side Gamma generation reference for negative 7 V7 - - - side 8 V6 GND - - - 3,4,17,33, L2,G4,H6, 9 VDD Rectangular wave output for common driver IOVDD 52,69,122 L9,A10,F11 10 CLK GND 43 H10 FPSHIFT 11 V0 Common driver signal - - - 12 VSS GND Note Note VSS 13 D20 Gamma generation reference for negative 55 E10 FPDAT11

Connecting EPSON Display Controllers EPSON 9 to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

LCD Panel S1D13A05 LCD Panel S1D13A05 S1D13A05 Connecto LCD Panel Pin Description PFBGA Pin Name QFP Pin# Pin Name r Pin# Ball# side Gamma generation reference for negative 14 D21 56 E11 FPDAT10 side Gamma generation reference for positive 15 D22 57 E8 FPDAT9 side 16 D23 VDD (Logic) 3.0V±0.3V 46 G9 FPDAT2 17 D24 Dot clock 45 G8 FPDAT1 Gamma generation reference for positive 18 D25 44 H11 FPDAT0 side 19 D10 GND 60 D11 FPDAT14 20 D11 RED data signal (LSB) 72 D8 FPDAT13 21 D12 RED data signal 54 E9 FPDAT12 22 D13 RED data signal 29 G7 FPDAT5 23 D14 RED data signal 48 G11 FPDAT4 24 D15 RED data signal 47 G10 FPDAT3 25 D00 RED data signal (MSB) 63 C10 FPDAT17 26 D01 GREEN data signal (LSB) 61 D9 FPDAT16 27 D02 GREEN data signal 59 D10 FPDAT15 28 D03 GREEN data signal 53 F7 FPDAT8 29 D04 GREEN data signal 51 F10 FPDAT7 30 D05 GREEN data signal 49 F8 FPDAT6 31 VSS GREEN data signal (MSB) Note Note VSS 32 AVDD BLUE data signal (LSB) - - - 33 HSYNC BLUE data signal 42 H9 FPLINE 34 VGL BLUE data signal - - - 35 DE BLUE data signal 34 K9 DRDY 36 VGH BLUE data signal - - - 37 VSYNC BLUE data signal (MSB) 40 J9 FPFRAME 38 VSS GND Note Note VSS 39 YU VDD (analog) 5.0V±0.2V - - - 40 XR Horizontal synchronous signal - - - 41 YD Power for gate driver (-) -15V（±1.0V） - - - 42 XL Input data enable (Hi-active) - - - 43 VSS Power for gate driver (+) +15V（±1.0V） Note Note VSS 44 BLL Vertical synchronous signal - - - 45 BLH GND - - - S1D13A05 IOVDD and COM27T2984 VDD must be configured between +3.0V to +3.3V.

Note Allocation of VSS pin for each packages are as follows. QFP: 1,13,35,50,65,101,114 BGA: B2,F2,K2,G5,F9,B10,K10

10 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

3.3 Example Register Settings

In addition to the pin connections, the S1D13513/S1D13706/S1D13A05 internal registers must be configured appropriately for the COM27T2984 LCD panel. The following tables provide example settings for each display controller. However, these values are for reference only and may differ according to each specific implementation. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx. For details on configuring the S1D13706 register values, see the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx. For details on configuring the S1D13A05 register values, see the S1D13A05 Hardware Functional Specification, document number X40A-A-001-xx.

Also included in the table is an example clock configuration designed to achieve a 60Hz or greater LCD refresh.

Example Register Settings for the S1D13513 Parameter Register Register Index and Name Value Setting (see Note) REG[0800h] LCD Panel Type Select Register 0300h - REG[0802h] LCD Horizontal Total Register 285 286 REG[0804h] LCD Horizontal Display Period Register 119 240 REG[0806h] LCD Horizontal Display Period Start Position Register 16 17 REG[0808h] LCD Horizontal Pulse Width Register 9 10 REG[080Ah] LCD Horizontal Pulse Start Position Register 0 0 REG[080Ch] LCD Vertical Total Register 325 326 REG[080Eh] LCD Vertical Display Period Resister 319 320 REG[0810h] LCD Vertical Display Period Start Position Register 5 5 REG[0812h] LCD Vertical Pulse Width Register 1 2 REG[0814h] LCD Vertical Pulse Start Position Register 1 1 PLL2 output frequency in MHz - 90 REG[0446h] LCD Clock Control Register 0 15 16 FPSHIFT in MHz - 5.63 LCD Refresh in Hz - 60.3

Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx.

Connecting EPSON Display Controllers EPSON 11 to Casio LCD Panels (Rev 1.00) 3. CONNECTING TO THE CASIO COM27T2984

Example Register Settings for the S1D13706 Register Parameter Register Index and Name Setting Value (see Note) REG[10h] Panel Type Register 61h - REG[12h] Horizontal Total Register (280/8-1) 280 REG[14h] Horizontal Display Period Register (240/8-1) 240 REG[16h] Horizontal Display Period Start Position Register 0 (22-5) 22 REG[20h] FPLINE Pulse Width Register 9 10 REG[22h] FPLINE Pulse Start Position Register 0 16 17 REG[18h] Vertical Total Register 0 (326-1) 326 REG[1Ch] Vertical Display Period Resister 0 320 320 REG[1Eh] Vertical Display Period Start Position Register 0 5 5 REG[24h] FPFRAME Pulse Width Register 1 2 REG[26h] FPFRAME Pulse Start Position Register 0 2 2 CLKI2 frequency in MHz - 6.5 REG[05h] Pixel Clock Configuration Register 3 1 FPSHIFT in MHz - 6.5 LCD Refresh in Hz - 71.2

Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13706 register values, see the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.

Example Register Settings for the S1D13A05 Parameter Value Register Index and Name Register Setting (see Note) REG[000Ch] Panel Type & MOD Rate Register 000000E1h - REG[0020h] Horizontal Total Register (288/8-1) 288 REG[0024h] Horizontal Display Period Register (240/8-1) 240 REG[0028h] Horizontal Display Period Start Position Register (22-5) 22 REG[002Ch] FPLINE Register 00090000h Pulse Width10 Start Position 1 REG[0030h] Vertical Total Register 325 326 REG[0034h] Vertical Display Period Resister 319 320 REG[0038h] Vertical Display Period Start Position Register 5 5 REG[003Ch] FPFRAME Register 00010002h Pulse Width 2 Start Position 2 CLKI2 frequency in MHz - 6.5 REG[0008h] Pixel Clock Configuration Register 3 1 FPSHIFT in MHz - 6.5 LCD Refresh in Hz - 69.2

Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13A05 register values, see the S1D13A05 Hardware Functional Specification, document number X40A-A-001-xx.

12 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

4. CONNECTING TO THE CASIO COM41T4148

The Casio COM41T4148 TFT panel is compatible with the S1D13513, S1D13719, and S1D13748 display controllers. The following sections will provide connector details, pin mappings, and example register settings for these combinations.

4.1 COM41T4148 Pin Mapping

The COM41T4148 TFT panel uses a 67-pin connector with the following pin mapping.

COM41T4148 Pin Mapping Connector Pin Name Pin Description Pin# 1 VCOM Common driver signal 2 D27 BLUE data signal (MSB) 3 D26 BLUE data signal 4 D25 BLUE data signal 5 D24 BLUE data signal 6 D23 BLUE data signal 24bit mode: BLUE data signal 7 D22 18bit mode: BLUE data signal (LSB) 24bit mode: BLUE data signal 8 D21 18bit mode: Connect to VSS 24bit mode: BLUE data signal (LSB) 9 D20 18bit mode: Connect to VSS 10 D17 GREEN data signal (MSB) 11 D16 GREEN data signal 12 D15 GREEN data signal 13 D14 GREEN data signal 14 D13 GREEN data signal 24bit mode: GREEN data signal 15 D12 18bit mode: GREEN data signal (LSB) 24bit mode: GREEN data signal 16 D11 18bit mode: Connect to VSS 24bit mode: GREEN data signal (LSB) 17 D10 18bit mode: Connect to VSS 18 D07 RED data signal (MSB) 19 D06 RED data signal 20 D05 RED data signal 21 D04 RED data signal 22 D03 RED data signal 24bit mode: RED data signal 23 D02 18bit mode: RED data signal (LSB) 24bit mode: RED data signal 24 D01 18bit mode: Connect to VSS 24bit mode: RED data signal (LSB) 25 D00 18bit mode: Connect to VSS 24bit mode: External back light control logic output signal 26 BLON 18bit mode: Open 24bit mode: Serial chip select (Lo-active) 27 CS / STBY 18bit mode: Standby control signal input (Lo: Normal, Hi: Standby) 24bit mode: Serial data input 28 DI / DE 18bit mode: Input data enable (Hi-active) 24bit mode: Serial clock 29 SCK / REV 18bit mode: Vertical and Horizontal reverse control signal input (Lo: Normal, Hi:Reverse)

Connecting EPSON Display Controllers EPSON 13 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

Connector Pin Name Pin Description Pin#

24bit mode: Vertical synchronous signal 30 VSYNC 18bit mode: Vertical synchronous signal (Negative) 24bit mode: Horizontal synchronous signal 31 HSYNC 18bit mode: Horizontal synchronous signal (Negative) 24bit mode: Dot clock 32 CLK 18bit mode: Dot clock (Capture at the falling edge) 33 VSS GND 34 MODE Input mode select, Lo: 24bit, Hi: 18bit 35 POCB Power on clear input (Lo-active) 36 NC OPEN 37 RVDD Internal power 38 COMDC Common driver DC output 39 NC OPEN 40 VSREF Internal DAC reference power 41 C1P For charge pump capacitor connection 42 C1M For charge pump capacitor connection 43 C2M For charge pump capacitor connection 44 C2P For charge pump capacitor connection 45 VDD Power +3.0V(+2.7V≦VDD≦+3.6V） 46 COMOUT Rectangular wave output for common driver 47 VDD2 Internal power 48 VSS GND 49 VSS GND 50 VSS GND 51 C3M For charge pump capacitor connection 52 C3P For charge pump capacitor connection 53 C4M For charge pump capacitor connection 54 C4P For charge pump capacitor connection 55 VVCOM COMOUT power output 56 NC OPEN 57 NC OPEN 58 VGH Gate driver power(+) 59 C5P For charge pump capacitor connection 60 C5M For charge pump capacitor connection 61 VGL Gate driver power(-) 62 BLL2 LED drive power2(cathode) 63 BLH2 LED drive power2(anode) 64 NC OPEN 65 NC OPEN 66 BLH1 LED drive power1(anode) 67 BLL1 LED drive power1(cathode)

Note The recommended connectors are FH26G-67S-0.3SHBW(0.5) from Hirose Electric Co., Ltd. or 04-6281-267-2X2-846+ from Kyocera elco. The connector is a 0.3mm pitch 67-pin FPC connector (20.8mm x 0.2mm gold plate).

14 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

4.2 Connection Examples

The information in this section provides connection examples for the S1D13513, S1D13719, and S1D13748 display controllers. Each display controller is available in two packages. The connection information differs for each package and is listed separately.

In addition to the pin connections for the selected display controller, the COM41T4148 requires the following power supply.

VDD +3.0V (2.7V ≤ VDD ≤ 3.6V)

For VDD, select a voltage within the supportable range of the Display Controller.

For further details on the COM41T4148, such as power consumption, absolute maximum ratings, and charge pump capacitor connections (see pins 41-44, 51-54, 59-60), please contact your Casio representative.

4.2.1 Connecting the COM41T4148 to the S1D13513

The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13513. This example is for the setting of 18-bit panel mode (MODE=”VDD”) on COM41T4148.

COM41T4148 3.0V S1D13513

VDD HVDD2

D[27:25] (B) FPDAT[6:8] D[24:22] (B) FPDAT[15:17] D[21:20] (B) D[17:15] (G) FPDAT[3:5] D[14:12] (G) FPDAT[12:14] D[11:10] (G) D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11] D[1:0] (R) HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT STBY DE FPDRDY REV MODE VSS VSS

Connecting EPSON Display Controllers EPSON 15 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13513. This example is for the setting of 24-bit panel mode (MODE=”VSS”) on COM41T4148.

COM41T4148 3.0V S1D13513

VDD HVDD2

D[27:25] (B) FPDAT[6:8]

D[24:22] (B) FPDAT[15:17] D[21:20] (B) FPDAT[22:23] D[17:15] (G) FPDAT[3:5]

D[14:12] (G) FPDAT[12:14] D[11:10] (G) FPDAT[20:21]

D[7:5] (R) FPDAT[0:2]

D[4:2] (R) FPDAT[9:11] D[1:0] (R) FPDAT[18:19]

HSYNC FPLINE VSYNC FPFRAME

CLK FPSHIFT

CS CS# DI SO

SCK SCK MODE VSS VSS

The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13513. This table is for the setting of 18-bit panel mode (MODE=”VDD”) on COM41T4148. Pin mappings are shown for both S1D13513 package types.

Connecting the COM41T4148 to the S1D13513 (18-bit panel mode (MODE=”VDD”)) LCD Panel LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 1 VCOM Common driver signal - - - 2 D27 BLUE data signal (MSB) - M6 FPDAT6 3 D26 BLUE data signal - K6 FPDAT7 4 D25 BLUE data signal - R6 FPDAT8 5 D24 BLUE data signal - T2 FPDAT15 6 D23 BLUE data signal 57,65,75 P4 FPDAT16 7 D22 BLUE data signal (LSB) - N4 FPDAT17 8 D21 Connect to VSS - Note VSS 9 D20 Connect to VSS Note Note VSS 10 D17 GREEN data signal (MSB) Note R7 FPDAT3 11 D16 GREEN data signal Note P7 FPDAT4 12 D15 GREEN data signal - L7 FPDAT5 13 D14 GREEN data signal - T5 FPDAT12

16 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Panel LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 14 D13 GREEN data signal - T4 FPDAT13 15 D12 GREEN data signal (LSB) - R4 FPDAT14 16 D11 Connect to VSS - Note VSS 17 D10 Connect to VSS - Note VSS 18 D07 RED data signal (MSB) - M7 FPDAT0 19 D06 RED data signal - N7 FPDAT1 20 D05 RED data signal - T7 FPDAT2 21 D04 RED data signal - P6 FPDAT9 22 D03 RED data signal - M5 FPDAT10 23 D02 RED data signal (LSB) - N5 FPDAT11 24 D01 Connect to VSS - Note VSS 25 D00 Connect to VSS - Note VSS 26 BLON Open - - - Standby control signal input 27 STBY - Note VSS (Lo: Normal, Hi: Standby) 28 DE Input data enable (Hi-active) - M8 FPDRDY Vertical and Horizontal reverse control 29 REV signal input - Note VSS (Lo: Normal, Hi:Reverse) 30 VSYNC Vertical synchronous signal (Negative) - T8 FPFRAME Horizontal synchronous signal 31 HSYNC - R8 FPLINE (Negative) 32 CLK Dot clock (Capture at the falling edge) - P8 FPSHIFT 33 VSS GND - Note VSS 34 MODE Input mode select, Lo: 24bit, Hi: 18bit 57,65,75 L5,L8,T6 HVDD2 35 POCB Power on clear input (Lo-active) - - - 36 NC OPEN - - - 37 RVDD Internal power Note - - 38 COMDC Common driver DC output Note - - 39 NC OPEN Note - - 40 VSREF Internal DAC reference power - - - 41 C1P For charge pump capacitor connection - - - 42 C1M For charge pump capacitor connection - - - 43 C2M For charge pump capacitor connection - - - 44 C2P For charge pump capacitor connection - - - 45 VDD Power +3.0V(+2.7V VDD +3.6V） - L5,L8,T6 HVDD2 COMOU Rectangular wave output for common 46 - - - T driver 47 VDD2 Internal power - - - 48 VSS GND - Note VSS 49 VSS GND - Note VSS 50 VSS GND - Note VSS 51 C3M For charge pump capacitor connection - - - 52 C3P For charge pump capacitor connection - - - 53 C4M For charge pump capacitor connection - - - 54 C4P For charge pump capacitor connection - - - 55 VVCOM COMOUT power output - - - 56 NC OPEN - - - 57 NC OPEN - - - 58 VGH Gate driver power(+) - - - 59 C5P For charge pump capacitor connection - - - 60 C5M For charge pump capacitor connection - - - 61 VGL Gate driver power(-) - - -

Connecting EPSON Display Controllers EPSON 17 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Panel LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 62 BLL2 LED drive power2(cathode) 57,65,75 - - 63 BLH2 LED drive power2(anode) - - - 64 NC OPEN - - - 65 NC OPEN Note - - 66 BLH1 LED drive power1(anode) Note - - 67 BLL1 LED drive power1(cathode) Note - - S1D13513 HVDD2 and COM41T4148 VDD must be configured between +3.0V to +3.6V.

The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13513. This table is for the setting of 24-bit panel mode (MODE=”VSS”) on COM41T4148. Pin mappings are shown for both S1D13513 package types.

Connecting the COM41T4148 to the S1D13513 (24-bit panel mode (MODE=”VSS”)) LCD Pane LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 1 VCOM Common driver signal - - - 2 D27 BLUE data signal (MSB) 68 M6 FPDAT6 3 D26 BLUE data signal 67 K6 FPDAT7 4 D25 BLUE data signal 64 R6 FPDAT8 5 D24 BLUE data signal 55 T2 FPDAT15 6 D23 BLUE data signal 54 P4 FPDAT16 7 D22 BLUE data signal (LSB) 53 N4 FPDAT17 8 D21 Connect to VSS Note 2 R3 FPDAT22 9 D20 Connect to VSS Note 2 K4 FPDAT23 10 D17 GREEN data signal (MSB) 71 R7 FPDAT3 11 D16 GREEN data signal 70 P7 FPDAT4 12 D15 GREEN data signal 69 L7 FPDAT5 13 D14 GREEN data signal 60 T5 FPDAT12 14 D13 GREEN data signal 59 T4 FPDAT13 15 D12 GREEN data signal (LSB) 56 R4 FPDAT14 16 D11 Connect to VSS Note 2 P5 FPDAT20 17 D10 Connect to VSS Note 2 T3 FPDAT21 18 D07 RED data signal (MSB) 74 M7 FPDAT0 19 D06 RED data signal 73 N7 FPDAT1 20 D05 RED data signal 72 T7 FPDAT2 21 D04 RED data signal 63 P6 FPDAT9 22 D03 RED data signal 62 M5 FPDAT10 23 D02 RED data signal (LSB) 61 N5 FPDAT11 24 D01 Connect to VSS Note 2 R5 FPDAT18 25 D00 Connect to VSS Note 2 K5 FPDAT19 26 BLON Open 57,65,75 L5,L8,T6 HVDD2 Standby control signal input 27 STBY 85 L9 CS# (Lo: Normal, Hi: Standby) 28 DE Input data enable (Hi-active) 82 T9 SO Vertical and Horizontal reverse control 29 REV signal input 84 P9 SCK (Lo: Normal, Hi:Reverse)

18 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Pane LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 30 VSYNC Vertical synchronous signal (Negative) 78 T8 FPFRAME Horizontal synchronous signal 31 HSYNC 79 R8 FPLINE (Negative) 32 CLK Dot clock (Capture at the falling edge) 77 P8 FPSHIFT 33 VSS GND Note 1 Note 1 VSS 34 MODE Input mode select, Lo: 24bit, Hi: 18bit 57,65,75 L5,L8,T6 HVDD2 35 POCB Power on clear input (Lo-active) - - - 36 NC OPEN - - - 37 RVDD Internal power - - - 38 COMDC Common driver DC output - - - 39 NC OPEN - - - 40 VSREF Internal DAC reference power - - - 41 C1P For charge pump capacitor connection - - - 42 C1M For charge pump capacitor connection - - - 43 C2M For charge pump capacitor connection - - - 44 C2P For charge pump capacitor connection - - - 45 VDD Power +3.0V(+2.7V≦VDD≦+3.6V） 57,65,75 L5,L8,T6 HVDD2 COMOU Rectangular wave output for common 46 - - - T driver 47 VDD2 Internal power - - - 48 VSS GND Note 1 Note 1 VSS 49 VSS GND Note 1 Note 1 VSS 50 VSS GND Note 1 Note 1 VSS 51 C3M For charge pump capacitor connection - - - 52 C3P For charge pump capacitor connection - - - 53 C4M For charge pump capacitor connection - - - 54 C4P For charge pump capacitor connection - - - 55 VVCOM COMOUT power output - - - 56 NC OPEN - - - 57 NC OPEN - - - 58 VGH Gate driver power(+) - - - 59 C5P For charge pump capacitor connection - - - 60 C5M For charge pump capacitor connection - - - 61 VGL Gate driver power(-) - - - 62 BLL2 LED drive power2(cathode) - - - 63 BLH2 LED drive power2(anode) - - - 64 NC OPEN - - - 65 NC OPEN - - - 66 BLH1 LED drive power1(anode) - - - 67 BLL1 LED drive power1(cathode) - - - S1D13513 HVDD2 and COM41T4148 VDD must be configured between +3.0V to +3.6V.

Connecting EPSON Display Controllers EPSON 19 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

4.2.2 Connecting the COM41T4148 to the S1D13719

The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13719. This example is for the setting of 18-bit panel mode (MODE=”VDD”) on COM41T4148.

COM41T4148 3.0V S1D13719

VDD PIOVDD

20 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13719. This example is for the setting of 24-bit panel mode (MODE=”VSS”) on COM41T4148 .

COM41T4148 3.0V S1D13719

VDD HVDD2

D[27:25] (B) FPDAT[6:8] D[24:22] (B) FPDAT[15:17] D[21:20] (B) FPDAT[22:23] D[17:15] (G) FPDAT[3:5] D[14:12] (G) FPDAT[12:14] D[11:10] (G) FPDAT[20:21] D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11] D[1:0] (R) FPDAT[18:19] HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT CS GPIO0 DI GPIO3 SCK GPIO1 MODE VSS VSS

The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13719. This table is for the setting of 18-bit panel mode (MODE=”VDD”) on COM41T4148. Pin mappings are shown for both S1D13719 package types.

Connecting the COM41T4148 to the S1D13719 (18-bit panel mode (MODE=”VDD”)) LCD Panel LCD Pane S1D13719 S1D13719 S1D13719 S1D13719 Connector LCD Panel Pin Description Pin Name PFBGA Pin# FCBGA Ball# QFP Pin# Pin Name Pin# 1 VCOM Common driver signal - - - - 2 D27 BLUE data signal (MSB) M3 D15 56 FPDAT6 3 D26 BLUE data signal L6 G15 68 FPDAT7 4 D25 BLUE data signal L2 B14 45 FPDAT8 5 D24 BLUE data signal M4 F16 60 FPDAT15 6 D23 BLUE data signal L7 J15 74 FPDAT16 7 D22 BLUE data signal (LSB) N6 H17 73 FPDAT17 8 D21 Connect to VSS Note Note Note VSS 9 D20 Connect to VSS Note Note Note VSS 10 D17 GREEN data signal (MSB) P2 C16 53 FPDAT3 11 D16 GREEN data signal N2 C17 54 FPDAT4 12 D15 GREEN data signal N3 D16 55 FPDAT5 13 D14 GREEN data signal P8 K15 81 FPDAT12

Connecting EPSON Display Controllers EPSON 21 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Panel LCD Pane S1D13719 S1D13719 S1D13719 S1D13719 Connector LCD Panel Pin Description Pin Name PFBGA Pin# FCBGA Ball# QFP Pin# Pin Name Pin# 14 D13 GREEN data signal N8 K17 80 FPDAT13 15 D12 GREEN data signal (LSB) M7 J17 79 FPDAT14 16 D11 Connect to VSS Note Note Note VSS 17 D10 Connect to VSS Note Note Note VSS 18 D07 RED data signal (MSB) L3 B15 47 FPDAT0 19 D06 RED data signal N1 C14 48 FPDAT1 20 D05 RED data signal K4 A15 49 FPDAT2 21 D04 RED data signal M6 H15 72 FPDAT9 22 D03 RED data signal M8 K14 83 FPDAT10 23 D02 RED data signal (LSB) L8 K16 82 FPDAT11 24 D01 Connect to VSS Note Note Note VSS 25 D00 Connect to VSS Note Note Note VSS 26 BLON Open - - - - Standby control signal input 27 STBY Note Note Note VSS (Lo: Normal, Hi: Standby) 28 DE Input data enable (Hi-active) M1 C13 44 DRDY Vertical and Horizontal reverse 29 REV control signal input Note Note Note VSS (Lo: Normal, Hi:Reverse) Vertical synchronous signal FPFRAM 30 VSYNC P3 D17 57 (Negative) E Horizontal synchronous signal 31 HSYNC P4 E17 58 FPLINE (Negative) 32 CLK Dot clock (Capture at the falling edge) P5 F17 66 FPSHIFT 33 VSS GND Note Note Note VSS C11,D14, J3,H4,P6, C15,E15, 34 MODE Input mode select, Lo: 24bit, Hi: 18bit 35,52,71,96 PIOVDD M10 H16,P15, R15 35 POCB Power on clear input (Lo-active) - - - - 36 NC OPEN - - - - 37 RVDD Internal power - - - - 38 COMDC Common driver DC output - - - - 39 NC OPEN - - - - 40 VSREF Internal DAC reference power - - - - For charge pump capacitor 41 C1P - - - - connection For charge pump capacitor 42 C1M - - - - connection For charge pump capacitor 43 C2M - - - - connection For charge pump capacitor 44 C2P - - - - connection C11,D14, J3,H4,P6, C15,E15, 35,52,71, 45 VDD Power +3.0V(+2.7V≦VDD≦+3.6V） PIOVDD M10 H16,P15, 96 R15 Rectangular wave output for common 46 COMOUT - - - - driver 47 VDD2 Internal power - - - - 48 VSS GND Note Note Note VSS 49 VSS GND Note Note Note VSS 50 VSS GND Note Note Note VSS 51 C3M For charge pump capacitor - - - -

22 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Panel LCD Pane S1D13719 S1D13719 S1D13719 S1D13719 Connector LCD Panel Pin Description Pin Name PFBGA Pin# FCBGA Ball# QFP Pin# Pin Name Pin# connection For charge pump capacitor 52 C3P - - - - connection For charge pump capacitor 53 C4M - - - - connection For charge pump capacitor 54 C4P - - - - connection 55 VVCOM COMOUT power output - - - - 56 NC OPEN - - - - 57 NC OPEN - - - - 58 VGH Gate driver power(+) - - - - For charge pump capacitor 59 C5P - - - - connection For charge pump capacitor 60 C5M - - - - connection 61 VGL Gate driver power(-) - - - - 62 BLL2 LED drive power2(cathode) - - - - 63 BLH2 LED drive power2(anode) - - - - 64 NC OPEN - - - - 65 NC OPEN - - - - 66 BLH1 LED drive power1(anode) - - - - 67 BLL1 LED drive power1(cathode) - - - - S1D13719 PIOVDD and COM41T4148 VDD must be configured between +2.75V to +3.25V.

Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,J2,E10,K2,M5,P9,H10,L11,B14 FCBGA: H2,P2,R2,C3,P3,K4,P5,R5,C9,P9,T9,,C10,C12,E14,R14,F15,L15,M15,N15 QFP: 2,31,43,65,85,112,131,149,158,188

The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13719. This table is for the setting of 24-bit panel mode (MODE=”VSS”) on COM41T4148. Pin mappings are shown for both S1D13719 package types.

Connecting the COM41T4148 to the S1D13719 (24-bit panel mode (MODE=”VSS”)) LCD Panel S1D13719 S1D13719 LCD Pane S1D13719 S1D13719 Connector LCD Panel Pin Description PFBGA FCBGA Pin Name QFP Pin# Pin Name Pin# Pin# Ball# 1 VCOM Common driver signal - - - - 2 D27 BLUE data signal (MSB) M3 D15 56 FPDAT6 3 D26 BLUE data signal L6 G15 68 FPDAT7 4 D25 BLUE data signal L2 B14 45 FPDAT8 5 D24 BLUE data signal M4 F16 60 FPDAT15 6 D23 BLUE data signal L7 J15 74 FPDAT16 7 D22 BLUE data signal (LSB) N6 H17 73 FPDAT17 8 D21 Connect to VSS N12 P17 98 FPDAT22 9 D20 Connect to VSS P10 M17 89 FPDAT23 10 D17 GREEN data signal (MSB) P2 C16 53 FPDAT3 11 D16 GREEN data signal N2 C17 54 FPDAT4 12 D15 GREEN data signal N3 D16 55 FPDAT5 13 D14 GREEN data signal P8 K15 81 FPDAT12 14 D13 GREEN data signal N8 K17 80 FPDAT13 15 D12 GREEN data signal (LSB) M7 J17 79 FPDAT14

Connecting EPSON Display Controllers EPSON 23 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Panel S1D13719 S1D13719 LCD Pane S1D13719 S1D13719 Connector LCD Panel Pin Description PFBGA FCBGA Pin Name QFP Pin# Pin Name Pin# Pin# Ball# 16 D11 Connect to VSS M11 N16 100 FPDAT20 17 D10 Connect to VSS P12 R16 99 FPDAT21 18 D07 RED data signal (MSB) L3 B15 47 FPDAT0 19 D06 RED data signal N1 C14 48 FPDAT1 20 D05 RED data signal K4 A15 49 FPDAT2 21 D04 RED data signal M6 H15 72 FPDAT9 22 D03 RED data signal M8 K14 83 FPDAT10 23 D02 RED data signal (LSB) L8 K16 82 FPDAT11 24 D01 Connect to VSS M13 P16 102 FPDAT18 25 D00 Connect to VSS M12 R17 101 FPDAT19 C11,D14, J3,H4,P6, C15,E15, 35,52, 26 BLON Open PIOVDD M10 H16,P15, 71,96 R15 Standby control signal input 27 STBY L1 A13 39 GPIO0 (Lo: Normal, Hi: Standby) 28 DE Input data enable (Hi-active) P13 T15 105 GPIO3 Vertical and Horizontal reverse 29 REV control signal input L10 T14 108 GPIO1 (Lo: Normal, Hi:Reverse) Vertical synchronous signal 30 VSYNC P3 D17 57 FPFRAME (Negative) Horizontal synchronous signal 31 HSYNC P4 E17 58 FPLINE (Negative) 32 CLK Dot clock (Capture at the falling edge) P5 F17 66 FPSHIFT 33 VSS GND Note Note Note VSS 34 MODE Input mode select, Lo: 24bit, Hi: 18bit Note Note Note VSS 35 POCB Power on clear input (Lo-active) - - - - 36 NC OPEN - - - - 37 RVDD Internal power - - - - 38 COMDC Common driver DC output - - - - 39 NC OPEN - - - - 40 VSREF Internal DAC reference power - - - - For charge pump capacitor 41 C1P - - - - connection For charge pump capacitor 42 C1M - - - - connection For charge pump capacitor 43 C2M - - - - connection For charge pump capacitor 44 C2P - - - - connection C11,D14, J3,H4, C15,E15, 35,52, 45 VDD Power +3.0V(+2.7V VDD +3.6V） PIOVDD P6,M10 H16,P15, 71,96 R15 Rectangular wave output for common driver 46 COMOUT - - - -

47 VDD2 Internal power - - - - 48 VSS GND Note Note Note VSS 49 VSS GND Note Note Note VSS 50 VSS GND Note Note Note VSS 51 C3M For charge pump capacitor - - - -

24 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD Panel S1D13719 S1D13719 LCD Pane S1D13719 S1D13719 Connector LCD Panel Pin Description PFBGA FCBGA Pin Name QFP Pin# Pin Name Pin# Pin# Ball# connection For charge pump capacitor 52 C3P - - - - connection For charge pump capacitor 53 C4M - - - - connection For charge pump capacitor 54 C4P - - - - connection 55 VVCOM COMOUT power output - - - - 56 NC OPEN - - - - 57 NC OPEN - - - - 58 VGH Gate driver power(+) - - - - For charge pump capacitor 59 C5P - - - - connection For charge pump capacitor 60 C5M - - - - connection 61 VGL Gate driver power(-) - - - - 62 BLL2 LED drive power2(cathode) - - - - 63 BLH2 LED drive power2(anode) - - - - 64 NC OPEN - - - - 65 NC OPEN - - - - 66 BLH1 LED drive power1(anode) - - - - 67 BLL1 LED drive power1(cathode) - - - - S1D13719 PIOVDD and COM41T4148 VDD must be configured between +2.75V to +3.25V.

Connecting EPSON Display Controllers EPSON 25 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

4.2.3 Connecting the COM41T4148 to the S1D13748

The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13748. This example is for the setting of 18-bit panel mode (MODE=”VDD”) on COM41T4148.

COM41T4148 3.0V S1D13748

VDD PIOVDD

26 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

The following diagram shows an example implementation of the COM41T4148 panel connected to the S1D13748. This example is for the setting of 24-bit panel mode (MODE=”VSS”) on COM41T4148.

COM41T4148 3.0V S1D13748

VDD PIOVDD

D[27:25] (B) FPDAT[6:8]

D[24:22] (B) FPDAT[15:17] D[21:20] (B) FPDAT[22:23] D[17:15] (G) FPDAT[3:5] D[14:12] (G) FPDAT[12:14] D[11:10] (G) FPDAT[20:21] D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11] D[1:0] (R) FPDAT[18:19] HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT CS FPCS1# DI FPSO SCK FPSCK MODE VSS VSS

The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13748. This table is for the setting of 18-bit panel mode (MODE=”VDD”) on COM41T4148. Pin mappings are shown for both S1D13748 package types.

Connecting the COM41T4148 to the S1D13748 (18-bit panel mode (MODE=”VDD”))

Connecting EPSON Display Controllers EPSON 27 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 11 D16 GREEN data signal 53 J6 FPDAT4 12 D15 GREEN data signal 54 L6 FPDAT5 13 D14 GREEN data signal 64 L9 FPDAT12 14 D13 GREEN data signal 68 K9 FPDAT13 15 D12 GREEN data signal (LSB) 69 H8 FPDAT14 16 D11 Connect to VSS Note Note VSS 17 D10 Connect to VSS Note Note VSS 18 D07 RED data signal (MSB) 49 J5 FPDAT0 19 D06 RED data signal 50 L5 FPDAT1 20 D05 RED data signal 51 K5 FPDAT2 21 D04 RED data signal 61 K8 FPDAT9 22 D03 RED data signal 62 J8 FPDAT10 23 D02 RED data signal (LSB) 63 L8 FPDAT11 24 D01 Connect to VSS Note Note VSS 25 D00 Connect to VSS Note Note VSS 26 BLON Open - - - Standby control signal input Note Note VSS 27 STBY (Lo: Normal, Hi: Standby) 28 DE Input data enable (Hi-active) 78 G7 FPDRDY Vertical and Horizontal reverse control Note Note VSS 29 signal input REV (Lo: Normal, Hi:Reverse) 30 VSYNC Vertical synchronous signal (Negative) 76 J10 FPFRAME Horizontal synchronous signal 77 H10 FPLINE 31 HSYNC (Negative) 32 CLK Dot clock (Capture at the falling edge) 75 J11 FPSHIFT 33 VSS GND Note Note VSS 19,26,35, E8,F4,H7, PIOVDD 40,46,55, J4 34 67,73,83, MODE Input mode select, Lo: 24bit, Hi: 18bit 87 35 POCB Power on clear input (Lo-active) - - - 36 NC OPEN - - - 37 RVDD Internal power - - - 38 COMDC Common driver DC output - - - 39 NC OPEN - - - 40 VSREF Internal DAC reference power - - - 41 C1P For charge pump capacitor connection - - - 42 C1M For charge pump capacitor connection - - - 43 C2M For charge pump capacitor connection - - - 44 C2P For charge pump capacitor connection - - - 19,26,35, E8,F4,H7, PIOVDD 40,46,55, J4 45 67,73,83, VDD Power +3.0V(+2.7V VDD +3.6V） 87 COMO Rectangular wave output for common driver - - - 46 UT 47 VDD2 Internal power - - - 48 VSS GND Note Note VSS 49 VSS GND Note Note VSS 50 VSS GND Note Note VSS 51 C3M For charge pump capacitor connection - - -

28 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 52 C3P For charge pump capacitor connection - - - 53 C4M For charge pump capacitor connection - - - 54 C4P For charge pump capacitor connection - - - 55 VVCOM COMOUT power output - - - 56 NC OPEN - - - 57 NC OPEN - - - 58 VGH Gate driver power(+) - - - 59 C5P For charge pump capacitor connection - - - 60 C5M For charge pump capacitor connection - - - 61 VGL Gate driver power(-) - - - 62 BLL2 LED drive power2(cathode) - - - 63 BLH2 LED drive power2(anode) - - - 64 NC OPEN - - - 65 NC OPEN - - - 66 BLH1 LED drive power1(anode) - - - 67 BLL1 LED drive power1(cathode) - - - S1D13748 PIOVDD and COM41T4148 VDD must be configured between +3.0V to +3.6V.

Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

The following table provides a detailed pin listing for the required connections between the COM41T4148 and the S1D13748. This table is for the setting of 24-bit panel mode (MODE=”VSS”) on COM41T4148. Pin mappings are shown for both S1D13748 package types.

Connecting the COM41T4148 to the S1D13748 (24-bit panel mode (MODE=”VSS”))

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 1 VCOM Common driver signal - - - 2 D27 BLUE data signal (MSB) 58 L7 FPDAT6 3 D26 BLUE data signal 59 J7 FPDAT7 4 D25 BLUE data signal 60 K7 FPDAT8 5 D24 BLUE data signal 70 L10 FPDAT15 6 D23 BLUE data signal 71 K10 FPDAT16 7 D22 BLUE data signal (LSB) 72 J9 FPDAT17 8 D21 Connect to VSS 45 L4 FPDAT22 9 D20 Connect to VSS 48 H5 FPDAT23 10 D17 GREEN data signal (MSB) 52 H6 FPDAT3 11 D16 GREEN data signal 53 J6 FPDAT4 12 D15 GREEN data signal 54 L6 FPDAT5 13 D14 GREEN data signal 64 L9 FPDAT12 14 D13 GREEN data signal 68 K9 FPDAT13 15 D12 GREEN data signal (LSB) 69 H8 FPDAT14 16 D11 Connect to VSS 43 K4 FPDAT20 17 D10 Connect to VSS 44 G6 FPDAT21

Connecting EPSON Display Controllers EPSON 29 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 18 D07 RED data signal (MSB) 49 J5 FPDAT0 19 D06 RED data signal 50 L5 FPDAT1 20 D05 RED data signal 51 K5 FPDAT2 21 D04 RED data signal 61 K8 FPDAT9 22 D03 RED data signal 62 J8 FPDAT10 23 D02 RED data signal (LSB) 63 L8 FPDAT11 24 D01 Connect to VSS 41 K3 FPDAT18 25 D00 Connect to VSS 42 L3 FPDAT19 19,26,35, E8,F4, PIOVDD 40,46,55, H7,J4 26 67,73,83, BLON Open 87 Standby control signal input 80 G9 FPCS1# 27 STBY (Lo: Normal, Hi: Standby) 28 DE Input data enable (Hi-active) 86 G11 FPSO Vertical and Horizontal reverse control 84 H11 FPSCK 29 signal input REV (Lo: Normal, Hi:Reverse) 30 VSYNC Vertical synchronous signal (Negative) 76 J10 FPFRAME Horizontal synchronous signal 77 H10 FPLINE 31 HSYNC (Negative) 32 CLK Dot clock (Capture at the falling edge) 75 J11 FPSHIFT 33 VSS GND Note Note VSS 34 MODE Input mode select, Lo: 24bit, Hi: 18bit Note Note VSS 35 POCB Power on clear input (Lo-active) - - - 36 NC OPEN - - - 37 RVDD Internal power - - - 38 COMDC Common driver DC output - - - 39 NC OPEN - - - 40 VSREF Internal DAC reference power - - - 41 C1P For charge pump capacitor connection - - - 42 C1M For charge pump capacitor connection - - - 43 C2M For charge pump capacitor connection - - - 44 C2P For charge pump capacitor connection - - - 19,26,35, E8,F4, PIOVDD 40,46,55, H7,J4 45 67,73,83, VDD Power +3.0V(+2.7V VDD +3.6V） 87 COMO Rectangular wave output for common driver - - - 46 UT 47 VDD2 Internal power - - - 48 VSS GND Note Note VSS 49 VSS GND Note Note VSS 50 VSS GND Note Note VSS 51 C3M For charge pump capacitor connection - - - 52 C3P For charge pump capacitor connection - - - 53 C4M For charge pump capacitor connection - - - 54 C4P For charge pump capacitor connection - - - 55 VVCOM COMOUT power output - - - 56 NC OPEN - - - 57 NC OPEN - - - 58 VGH Gate driver power(+) - - -

30 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 59 C5P For charge pump capacitor connection - - - 60 C5M For charge pump capacitor connection - - - 61 VGL Gate driver power(-) - - - 62 BLL2 LED drive power2(cathode) - - - 63 BLH2 LED drive power2(anode) - - - 64 NC OPEN - - - 65 NC OPEN - - - 66 BLH1 LED drive power1(anode) - - - 67 BLL1 LED drive power1(cathode) - - - S1D13748 PIOVDD and COM41T4148 VDD must be configured between +3.0V to +3.6V.

Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

Connecting EPSON Display Controllers EPSON 31 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

4.3 Example Register Settings

In addition to the pin connections, the S1D13513/S1D13719/S1D13748 internal registers must be configured appropriately for the COM41T4148 LCD panel. The following tables provide example settings for each display controller. However, these values are for reference only and may differ according to each specific implementation. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx. For details on configuring the S1D13719 register values, see the S1D13719 Hardware Functional Specification, document number X59A-A-001-xx. For details on configuring the S1D13748 register values, see the S1D13748 Hardware Functional Specification, document number X80A-A-001-xx.

Also included in the table is an example clock configuration designed to achieve a 50Hz or greater LCD refresh.

Example Register Settings for the S1D13513 Parameter Register Index and Name Register Setting Value (see Note) REG[0800h] LCD Panel Type Select Register 0300h - REG[0802h] LCD Horizontal Total Register 511 512 REG[0804h] LCD Horizontal Display Period Register 159 320 REG[0806h] LCD Horizontal Display Period Start Position Register 10 10 REG[0808h] LCD Horizontal Pulse Width 8000h+13 14 REG[080Ah] LCD Horizontal Pulse Start Position 0t 0 REG[080Ch] LCD Vertical Total Register 240 241 REG[080Eh] LCD Vertical Display Period Resister 239 240 REG[0810h] Vertical Display Period Start Position Register 0t 0 REG[0812h] LCD Vertical Pulse Width 8000h+0 0 REG[0814h] LCD Vertical Pulse Start Position 0 0 PLL2 output frequency in MHz - 90 REG[0446h] LCD Clock Control Register 15 16 FPSHIFT in MHz - 6.67 LCD Refresh in Hz - 54

32 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

Example Serial Output Sequence for the S1D13513 Sequence Register Data Contents 1 0448h 000Eh LCD serial clock divide 100MHz/15 2 0816h 00A3h LCD serial 24-bit command interface setting 3 081Ch 0016h Command 4 081Ch 0835h Command 5 081Ch 0471h Command 6 081Ch 0C00h Command 7 081Ch 0210h Command 8 081Ch 0A4Ch Command 9 081Ch 0618h Command 10 081Ch 0ED0h Command 11 081Ch 0100h Command 12 081Ch 0980h Command 13 081Ch 0500h Command 14 081Ch 0D40h Command 15 081Ch 0300h Command 16 081Ch 0B00h Command 17 081Ch 0700h Command 18 081Ch 0F02h Command

Example Register Settings for the S1D13719 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] Horizontal Total Register 53 432 REG[0042h] Horizontal Display Period Register 159 320 REG[0044h] Horizontal Display Period Start Position Register 11 20 REG[0046h] LCD1 FPLINE Register 0080h+1 2 REG[0048h] LCD1 FPLINE Pulse Position Register 17 18 REG[004Ah] Vertical Total Register 242 243 REG[004Ch] Vertical Display Period Resister 240 241 REG[004E] Vertical Display Period Start Position Register 2 2 REG[0050h] LCD1 FPFRAME Register 0080h+1 2 REG[0052h] LCD1 FPFRAME Pulse Position Register 2 2 PLL output in MHz - 54 REG[0030h] LCD Interface Clock Configuration Register 0503h 8 FPSHIFT in MHz - 6.75 LCD Refresh in Hz - 64.3

Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13719 register values, see the S1D13719 Hardware Functional Specification, document number X59A-A-001-xx.

Connecting EPSON Display Controllers EPSON 33 to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

Example Serial Output Sequence for the S1D13719 Sequence Register Data Contents 1 030Ch 0016h Command 2 030Ch 0835h Command 3 030Ch 0471h Command 4 030Ch 0C00h Command 5 030Ch 0210h Command 6 030Ch 0A4Ch Command 7 030Ch 0618h Command 8 030Ch 0ED0h Command 9 030Ch 0100h Command 10 030Ch 0980h Command 11 030Ch 0500h Command 12 030Ch 0D40h Command 13 030Ch 0300h Command 14 030Ch 0B00h Command 15 030Ch 0700h Command 16 030Ch 0F02h Command

Note GPIO0, GPIO1, and GPIO3 are used for serial communications.

Example Register Settings for the S1D13748 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] LCD1 Horizontal Total Register 63 512 REG[0042h] LCD1 Horizontal Display Period Register 159 320 REG[0044h] LCD1 Horizontal Display Period Start Position 2 10 Register REG[0046h] LCD1 Horizontal Pulse Register 0080h+13 14 REG[0048h] LCD1 Horizontal Pulse Start Position Register 0 1 REG[004Ah] LCD1 Vertical Total Register 240 241 REG[004Ch] LCD1 Vertical Display Period Resister 239 240 REG[004Eh] LCD1 Vertical Display Period Start Position 0 0 Register REG[0050h] LCD1 Vertical Pulse Register 0080h+0 1 REG[0052h] LCD1 Vertical Pulse Start Position Register 0 1 REG[0246h] Main1 Window Image Horizontal Size Register 319 320 REG[0248h] Main1 Window Image Vertical Size Register 239 240 PLL output frequency in MHz - 50 REG[0030h] LCD Interface Clock Setting Register 0507h 8 FPSHIFT in MHz - 6.25 LCD Refresh in Hz - 50.7

Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13748 register values, see the S1D13748 Hardware Functional Specification, document number X80A-A-001-xx.

34 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 4. CONNECTING TO THE CASIO COM41T4148

Example Serial Output Sequence for the S1D13748 Sequence Register Data Contents 1 0034h 0016h Command 2 0034h 0835h Command 3 0034h 0471h Command 4 0034h 0C00h Command 5 0034h 0210h Command 6 0034h 0A4Ch Command 7 0034h 0618h Command 8 0034h 0ED0h Command 9 0034h 0100h Command 10 0034h 0980h Command 11 0034h 0500h Command 12 0034h 0D40h Command 13 0034h 0300h Command 14 0034h 0B00h Command 15 0034h 0700h Command 16 0034h 0F02h Command

Connecting EPSON Display Controllers EPSON 35 to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

5. CONNECTING TO THE CASIO COM35H3827

The Casio COM35H3827 TFT panel is compatible with the S1D13513 and S1D13748 display controllers. The following sections will provide connector details, pin mappings, and example register settings for these combinations.

5.1 COM35H3827 Pin Mapping

The COM35H3827 TFT panel uses a 39-pin connector with the following pin mapping.

COM35H3827 Pin Mapping Connector Pin Name Pin Description Pin# 1 VSS GND 2 VSS GND 3 VDD Power supply for logic +2.7V～+3.6V 4 VDD Power supply for logic +2.7V～+3.6V 5 VSS GND 6 RESETB RESET(Lo-active) 7 HSYNC Horizontal synchronous signal (Negative) 8 VSYNC Vertical synchronous signal (Negative) 9 CLK Dot clock (Capture at the falling edge) 10 VSS GND 11 D00 BLUE data signal (LSB) 12 D01 BLUE data signal 13 D02 BLUE data signal 14 D03 BLUE data signal 15 D04 BLUE data signal 16 D05 BLUE data signal (MSB) 17 D10 GREEN data signal (LSB) 18 D11 GREEN data signal 19 D12 GREEN data signal 20 D13 GREEN data signal 21 D14 GREEN data signal 22 D15 GREEN data signal (MSB) 23 D20 RED data signal (LSB) 24 D21 RED data signal 25 D22 RED data signal 26 D23 RED data signal 27 D24 RED data signal 28 D25 RED data signal (MSB) 29 VSS GND 30 DE Input data enable (Hi-active) 31 STBYB Display control signal Lo:Standby, Hi:Normal 32 TEST1 Connect to GND 33 NC OPEN 34 NC OPEN 35 NC OPEN 36 NC OPEN 37 TEST2 Connect to GND 38 BLH Power supply for back light LED(anode) 39 BLL Power supply for back light LED(cathode)

Note The recommended connector is a FH23-39S-0.3SHW(0.5) from Hirose Electric Co., Ltd. The connector is a 0.3mm pitch 39-pin FPC connector (12.0mm x 0.2mm gold plate).

36 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

5.2 Connection Examples

The information in this section provides connection examples for the S1D13513 and S1D13748 display controllers. For the S1D13513 and S1D13748, the display controller is available in two packages. The connection information differs for each package and is listed separately.

In addition to the pin connections for the selected display controller, the COM35H3827 requires the following power supplies.

VDD +3.0V (2.7V ≤ VDD ≤ 3.6V)

For VDD, select a voltage within the supportable range of the Display Controller.

For further details on the COM35H3827, such as power consumption and absolute maximum ratings, please contact your Casio representative.

5.2.1 Connecting the COM35H3827 to the S1D13513

The following diagram shows an example implementation of the COM35H3827 panel connected to the S1D13513.

3.0V COM35H3827 S1D13513

VDD HVDD2 STBYB

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5]

D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8]

D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAME

CLK FPSHIFT

TEST1 TEST2

VSS VSS

Connecting EPSON Display Controllers EPSON 37 to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

The following table provides a detailed pin listing for the required connections between the COM35H3827 and the S1D13513. Pin mappings are shown for both S1D13513 package types.

Connecting the COM35H3827 to the S1D13513 LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector LCD Panel Pin Description Pin Name QFP Pin# PBGA Ball# Pin Name Pin# 1 VSS GND Note Note VSS 2 VSS GND Note Note VSS 3 VDD Power supply for logic +2.7V～+3.6V 57,65,75 L5,L8,T6 HVDD2 4 VDD Power supply for logic +2.7V～+3.6V 57,65,75 L5,L8,T6 HVDD2 5 VSS GND Note Note VSS 6 RESETB RESET(Lo-active) - - - 7 HSYNC Horizontal synchronous signal (Negative) 79 R8 FPLINE 8 VSYNC Vertical synchronous signal (Negative) 78 T8 FPFRAME 9 CLK Dot clock (Capture at the falling edge) 77 P8 FPSHIFT 10 VSS GND Note Note VSS 11 D00 BLUE data signal (LSB) 53 N4 FPDAT17 12 D01 BLUE data signal 54 P4 FPDAT16 13 D02 BLUE data signal 55 T2 FPDAT15 14 D03 BLUE data signal 64 R6 FPDAT8 15 D04 BLUE data signal 67 K6 FPDAT7 16 D05 BLUE data signal (MSB) 68 M6 FPDAT6 17 D10 GREEN data signal (LSB) 56 R4 FPDAT14 18 D11 GREEN data signal 59 T4 FPDAT13 19 D12 GREEN data signal 60 T5 FPDAT12 20 D13 GREEN data signal 69 L7 FPDAT5 21 D14 GREEN data signal 70 P7 FPDAT4 22 D15 GREEN data signal (MSB) 71 R7 FPDAT3 23 D20 RED data signal (LSB) 61 N5 FPDAT11 24 D21 RED data signal 62 M5 FPDAT10 25 D22 RED data signal 63 P6 FPDAT9 26 D23 RED data signal 72 T7 FPDAT2 27 D24 RED data signal 73 N7 FPDAT1 28 D25 RED data signal (MSB) 74 M7 FPDAT0 29 VSS GND Note Note VSS 30 DE Input data enable (Hi-active) 80 M8 FPDRDY Display control signal Lo:Standby, 31 STBYB 57,65,75 L5,L8,T6 HVDD2 Hi:Normal 32 TEST1 Connect to GND Note Note VSS 33 NC OPEN - - - 34 NC OPEN - - - 35 NC OPEN - - - 36 NC OPEN - - - 37 TEST2 Connect to GND Note Note VSS 38 BLH Power supply for back light LED(anode) - - - 39 BLL Power supply for back light LED(cathode) - - - S1D13513 HVDD2 and COM35H3827 VDD must be configured between +3.0V to +3.6V.

38 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

5.2.2 Connecting the COM35H3827 to the S1D13748

The following diagram shows an example implementation of the COM35H3827 panel connected to the S1D13748.

3.0V COM35H3827 S1D13748

VDD PIOVDD STBYB

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5]

D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8]

D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAME

CLK FPSHIFT

TEST1 TEST2

VSS VSS

The following table provides a detailed pin listing for the required connections between the COM35H3827 and the S1D13748. Pin mappings are shown for both S1D13748 package types.

Connecting the COM35H3827 to the S1D13748 LCD Panel S1D13748 LCD Panel S1D13748 S1D13513 Connector LCD Panel Pin Description PFBGA Pin Name QFP Pin# Pin Name Pin# Ball# 1 VSS GND Note Note VSS 2 VSS GND Note Note VSS 19,26,35 E8,F4, 3 VDD Power supply for logic +2.7V～+3.6V ,40,46,55,6 H7,J4 PIOVDD 7,73,83,87 19,26,35 E8,F4. 4 VDD Power supply for logic +2.7V～+3.6V ,40,46,55,6 H7,J4 PIOVDD 7,73,83,87 5 VSS GND Note Note VSS 6 RESETB RESET(Lo-active) - - -

Connecting EPSON Display Controllers EPSON 39 to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

LCD Panel S1D13748 LCD Panel S1D13748 S1D13513 Connector LCD Panel Pin Description PFBGA Pin Name QFP Pin# Pin Name Pin# Ball# 7 HSYNC Horizontal synchronous signal (Negative) 77 H10 FPLINE 8 VSYNC Vertical synchronous signal (Negative) 76 J10 FPFRAME 9 CLK Dot clock (Capture at the falling edge) 75 J11 FPSHIFT 10 VSS GND Note Note VSS 11 D00 BLUE data signal (LSB) 53 N4 FPDAT17 12 D01 BLUE data signal 54 P4 FPDAT16 13 D02 BLUE data signal 55 T2 FPDAT15 14 D03 BLUE data signal 64 R6 FPDAT8 15 D04 BLUE data signal 67 K6 FPDAT7 16 D05 BLUE data signal (MSB) 68 M6 FPDAT6 17 D10 GREEN data signal (LSB) 69 H8 FPDAT14 18 D11 GREEN data signal 68 K9 FPDAT13 19 D12 GREEN data signal 64 L9 FPDAT12 20 D13 GREEN data signal 54 L6 FPDAT5 21 D14 GREEN data signal 53 J6 FPDAT4 22 D15 GREEN data signal (MSB) 52 H6 FPDAT3 23 D20 RED data signal (LSB) 61 N5 FPDAT11 24 D21 RED data signal 62 M5 FPDAT10 25 D22 RED data signal 63 P6 FPDAT9 26 D23 RED data signal 72 T7 FPDAT2 27 D24 RED data signal 73 N7 FPDAT1 28 D25 RED data signal (MSB) 74 M7 FPDAT0 29 VSS GND Note Note VSS 30 DE Input data enable (Hi-active) 78 G7 FPDRDY 19,26,35 E8,F4,H Display control signal Lo:Standby, 31 STBYB ,40,46,55,6 7,J4 PIOVDD Hi:Normal 7,73,83,87 32 TEST1 Connect to GND Note Note VSS 33 NC OPEN - - - 34 NC OPEN - - - 35 NC OPEN - - - 36 NC OPEN - - - 37 TEST2 Connect to GND Note Note VSS 38 BLH Power supply for back light LED(anode) - - - 39 BLL Power supply for back light LED(cathode) - - - S1D13748 PIOVDD and COM41T4148 VDD must be configured between +3.0V to +3.6V.

Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

40 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

5.3 Example Register Settings

In addition to the pin connections, the S1D13513/S1D13748 internal registers must be configured appropriately for the COM35H3827 LCD panel. The following tables provide example settings for each display controller. However, these values are for reference only and may differ according to each specific implementation. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx. For details on configuring the S1D13748 register values, see the S1D13748 Hardware Functional Specification, document number X80A-A-001-xx.

Also included in the table is an example clock configuration designed to achieve a 50Hz or greater LCD refresh.

Example Register Settings for the S1D13513 Parameter Register Index and Name Register Setting Value (see Note) REG[0800h] LCD Panel Type Select Register 0280h - REG[0802h] LCD Horizontal Total Register 286t 287 REG[0804h] LCD Horizontal Display Period Register 119t 240 REG[0806h] LCD Horizontal Display Period Start Position Register 1t 2 REG[0808h] LCD Horizontal Pulse Width 9t 10 REG[080Ah] LCD Horizontal Pulse Start Position 0 0 REG[080Ch] LCD Vertical Total Register 324t 325 REG[080Eh] LCD Vertical Display Period Resister 319 320 REG[0810h] Vertical Display Period Start Position Register 2t 2 REG[0812h] LCD Vertical Pulse Width 0t 1 REG[0814h] LCD Vertical Pulse Start Position 0t 0 PLL2 output frequency in MHz - 100 REG[0446h] LCD Clock Control Register 17 18 FPSHIFT in MHz - 5.56 LCD Refresh in Hz - 59.6

Connecting EPSON Display Controllers EPSON 41 to Casio LCD Panels (Rev 1.00) 5. CONNECTING TO THE CASIO COM35H3827

Example Register Settings for the S1D13748 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] LCD1 Horizontal Total Register 35 287 REG[0042h] LCD1 Horizontal Display Period Register 119 240 REG[0044h] LCD1 Horizontal Display Period Start Position 0 9 Register REG[0046h] LCD1 Horizontal Pulse Register 0 1 REG[0048h] LCD1 Horizontal Pulse Start Position Register 0 1 REG[004Ah] LCD1 Vertical Total Register 324 325 REG[004Ch] LCD1 Vertical Display Period Resister 319 320 REG[004Eh] LCD1 Vertical Display Period Start Position 2 2 Register REG[0050h] LCD1 Vertical Pulse Register 0 1 REG[0052h] LCD1 Vertical Pulse Start Position Register 0 1 REG[0246h] Main1 Window Image Horizontal Size Register 239 240 REG[0248h] Main1 Window Image Vertical Size Register 319 320 PLL output frequency in MHz - 50 REG[0030h] LCD Interface Clock Setting Register 0507h 9 FPSHIFT in MHz - 5.56 LCD Refresh in Hz - 59.6

42 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6. CONNECTING TO THE CASIO COM55T5108

The Casio COM55T5108 TFT panel is compatible with the S1D13513, S1D13706, S1D13A05, S1D13719, S1D13742, S1D13743, and S1D13748 display controllers. The following sections will provide connector details, pin mappings, and example register settings for these combinations.

6.1 COM55T5108 Pin Mapping

The COM55T5108 TFT panel uses a 36-pin connector with the following pin mapping.

COM55T5108 Pin Mapping Connector Pin# Pin Name Pin Description 1 VSS GND for digital 2 CLK Dot clock (Capture at the falling edge) 3 DE Input data enable (Hi-active) 4 HSYNC Horizontal synchronous signal 5 VSYNC Vertical synchronous signal 6 VSS GND for digital 7 D20 RED data signal (LSB) 8 D21 RED data signal 9 D22 RED data signal 10 D23 RED data signal 11 D24 RED data signal 12 D25 RED data signal (MSB) 13 D10 GREEN data signal (LSB) 14 D11 GREEN data signal 15 D12 GREEN data signal 16 D13 GREEN data signal 17 D14 GREEN data signal 18 D15 GREEN data signal (MSB) 19 D00 BLUE data signal (LSB) 20 D01 BLUE data signal 21 D02 BLUE data signal 22 D03 BLUE data signal 23 D04 BLUE data signal 24 D05 BLUE data signal (MSB) 25 VSS GND for digital Vertical and Horizontal reverse control signal input 26 REV (Lo: Normal, Hi:Reverse) 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） 28 STBYB Standby control signal input (Lo: Normal, Hi: Standby) 29 VSS GND for analog Back light dimmer control pulse input 30 PDM (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light 32 VSS_B GND for back light 33 VSS_B GND for back light 34 VBL Power supply for back light 35 VBL Power supply for back light 36 VBL Power supply for back light

Note The recommended connector is a Molex 52559-3652.

Connecting EPSON Display Controllers EPSON 43 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2 Connection Examples

The information in this section provides connection examples for the S1D13513, S1D13706, S1D13A05, S1D13719, S1D13742, S1D13743, and S1D13748 display controllers. Some display controllers are available in two packages. The connection information differs for each package and is listed separately.

In addition to the pin connections for the selected display controller, the COM55T5108 requires the following power supply.

VDD +3.3V(±0.3V) VBL +12V(±1.2V)

For VDD, select a voltage within the supportable range of the Display Controller.

For further details on the COM55T5108, such as power consumption and absolute maximum ratings, please contact your Casio representative.

6.2.1 Connecting the COM55T5108 to the S1D13513

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13513.

3.3V COM55T5108 S1D13513

VDD HVDD2 STBYB

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAM CLK FPSHIFT

REV

PDM

VSS_B

VSS VSS

44 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13513. Pin mappings are shown for both S1D13513 package types.

Connecting the COM55T5108 to the S1D13513 LCD LCD Panel S1D13513 Panel S1D13513 S1D13513 Connector LCD Panel Pin Description PBGA Pin QFP Pin# Pin Name Pin# Ball# Name 1 VSS GND for digital Note Note VSS 2 CLK Dot clock (Capture at the falling edge) 77 P8 FPSHIFT 3 DE Input data enable (Hi-active) 80 M8 FPDRDY 4 HSYNC Horizontal synchronous signal 79 R8 FPLINE 5 VSYNC Vertical synchronous signal 78 T8 FPFRAME 6 VSS GND for digital Note Note VSS 7 D20 RED data signal (LSB) 61 N5 FPDAT11 8 D21 RED data signal 62 M5 FPDAT10 9 D22 RED data signal 63 P6 FPDAT9 10 D23 RED data signal 72 T7 FPDAT2 11 D24 RED data signal 73 N7 FPDAT1 12 D25 RED data signal (MSB) 74 M7 FPDAT0 13 D10 GREEN data signal (LSB) 56 R4 FPDAT14 14 D11 GREEN data signal 59 T4 FPDAT13 15 D12 GREEN data signal 60 T5 FPDAT12 16 D13 GREEN data signal 69 L7 FPDAT5 17 D14 GREEN data signal 70 P7 FPDAT4 18 D15 GREEN data signal (MSB) 71 R7 FPDAT3 19 D00 BLUE data signal (LSB) 53 N4 FPDAT17 20 D01 BLUE data signal 54 P4 FPDAT16 21 D02 BLUE data signal 55 T2 FPDAT15 22 D03 BLUE data signal 64 R6 FPDAT8 23 D04 BLUE data signal 67 K6 FPDAT7 24 D05 BLUE data signal (MSB) 68 M6 FPDAT6 25 VSS GND for digital Note Note VSS Vertical and Horizontal reverse control signal Note Note VSS 26 input REV (Lo: Normal, Hi:Reverse) 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） 57,65,75 L5,L8,T6 HVDD2 Standby control signal input (Lo: Normal, Hi: 57,65,75 L5,L8,T6 HVDD2 28 STBYB Standby) 29 VSS GND for analog Note Note VSS Back light dimmer control pulse input Note Note VSS 30 PDM (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light Note Note VSS 32 VSS_B GND for back light Note Note VSS 33 VSS_B GND for back light Note Note VSS 34 VBL Power supply for back light - - - 35 VBL Power supply for back light - - - 36 VBL Power supply for back light - - - Note Allocation of VSS pin for each packages are as follows. QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16

Connecting EPSON Display Controllers EPSON 45 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2.2 Connecting the COM55T5108 to the S1D13706

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13706.

3.3V COM55T5108 S1D13706

VDD NIOVDD STBYB

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAM CLK FPSHIFT

REV

PDM

VSS_B

VSS VSS

46 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13706.

Connecting the COM55T5108 to the S1D13706 LCD Panel LCD Panel S1D13706 S1D13706 Connector LCD Panel Pin Description Pin Name TQFP Pin# Pin Name Pin# 1 VSS GND for digital Note VSS 2 CLK Dot clock (Capture at the falling edge) 54 FPSHIFT 3 DE Input data enable (Hi-active) 48 FPDRDY 4 HSYNC Horizontal synchronous signal 53 FPLINE 5 VSYNC Vertical synchronous signal 52 FPFRAME 6 VSS GND for digital Note VSS 7 D20 RED data signal (LSB) 68 FPDAT11 8 D21 RED data signal 67 FPDAT10 9 D22 RED data signal 66 FPDAT9 10 D23 RED data signal 57 FPDAT2 11 D24 RED data signal 56 FPDAT1 12 D25 RED data signal (MSB) 55 FPDAT0 13 D10 GREEN data signal (LSB) 71 FPDAT14 14 D11 GREEN data signal 70 FPDAT13 15 D12 GREEN data signal 69 FPDAT12 16 D13 GREEN data signal 60 FPDAT5 17 D14 GREEN data signal 59 FPDAT4 18 D15 GREEN data signal (MSB) 58 FPDAT3 19 D00 BLUE data signal (LSB) 74 FPDAT17 20 D01 BLUE data signal 73 FPDAT16 21 D02 BLUE data signal 72 FPDAT15 22 D03 BLUE data signal 65 FPDAT8 23 D04 BLUE data signal 64 FPDAT7 24 D05 BLUE data signal (MSB) 61 FPDAT6 25 VSS GND for digital Note VSS Vertical and Horizontal reverse control signal input Note VSS 26 REV (Lo: Normal, Hi:Reverse) 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） 37,49,63,76 NIOVDD 28 STBYB Standby control signal input (Lo: Normal, Hi: Standby) 37,49,63,76 NIOVDD 29 VSS GND for analog Note VSS Note VSS 30 Back light dimmer control pulse input PDM (Lo:100%, Hi:0%(Back light off)) VSS_B GND for back light Note VSS 31 VSS_B GND for back light Note VSS 32 VSS_B GND for back light Note VSS 33 VBL Power supply for back light - - 34 VBL Power supply for back light - - 35 VBL Power supply for back light - - 36 VSS GND for digital Note VSS Note Allocation of VSS pin are as follows. 14,25,36,50,62,75,100

Connecting EPSON Display Controllers EPSON 47 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2.3 Connecting the COM55T5108 to the S1D13A05

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13A05.

COM55T5108 3.3V S1D13A05

VDD IOVDD STBYB

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAM CLK FPSHIFT

REV

PDM

VSS_B

VSS VSS

48 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13A05.

Connecting the COM55T5108 to the S1D13A05 LCD LCD Panel Panel S1D13A05 S1D13A05 S1D13A05 Connector LCD Panel Pin Description Pin QFP Pin# PFBGA Ball# Pin Name Pin# Name 1 VSS GND for digital Note Note VSS Dot clock (Capture at the 2 CLK 43 H10 FPSHIFT falling edge) 3 DE Input data enable (Hi-active) 34 K9 FPDRDY Horizontal synchronous 4 HSYNC 42 H9 FPLINE signal 5 VSYNC Vertical synchronous signal 40 J9 FPFRAME 6 VSS GND for digital Note Note VSS 7 D20 RED data signal (LSB) 55 E10 FPDAT11 8 D21 RED data signal 56 E11 FPDAT10 9 D22 RED data signal 57 E8 FPDAT9 10 D23 RED data signal 46 G9 FPDAT2 11 D24 RED data signal 45 G8 FPDAT1 12 D25 RED data signal (MSB) 44 H11 FPDAT0 13 D10 GREEN data signal (LSB) 60 D11 FPDAT14 14 D11 GREEN data signal 72 D8 FPDAT13 15 D12 GREEN data signal 54 E9 FPDAT12 16 D13 GREEN data signal 29 G7 FPDAT5 17 D14 GREEN data signal 48 G11 FPDAT4 18 D15 GREEN data signal (MSB) 47 G10 FPDAT3 19 D00 BLUE data signal (LSB) 63 C10 FPDAT17 20 D01 BLUE data signal 61 D9 FPDAT16 21 D02 BLUE data signal 59 D10 FPDAT15 22 D03 BLUE data signal 53 F7 FPDAT8 23 D04 BLUE data signal 51 F10 FPDAT7 24 D05 BLUE data signal (MSB) 49 F8 FPDAT6 25 VSS GND for digital Note Note VSS Vertical and Horizontal 26 REV reverse control signal input Note Note VSS (Lo: Normal, Hi:Reverse) Power 3,4,17,33, L2,G4,H6,L9 27 VDD IOVDD +3.3V(+3.0V≤VDD≤+3.6V） 52,69,122 ,A10,F11 Standby control signal input 28 STBYB Note Note VSS (Lo: Normal, Hi: Standby) 29 VSS GND for analog Note Note VSS Back light dimmer control pulse input 30 PDM Note Note VSS (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light Note Note VSS 32 VSS_B GND for back light Note Note VSS 33 VSS_B GND for back light Note Note VSS 34 VBL Power supply for back light - - - 35 VBL Power supply for back light - - - 36 VBL Power supply for back light - - - Note Allocation of VSS pin for each packages are as follows. QFP: 1,13,35,50,65,101,114 BGA: B2,F2,K2,G5,F9,B10,K10

Connecting EPSON Display Controllers EPSON 49 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2.4 Connecting the COM55T5108 to the S1D13719

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13719.

COM55T5108 3.3V S1D13719

VDD PIOVDD STBYB

DE DRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAM CLK FPSHIFT

REV

PDM

VSS_B

VSS VSS

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13719.

Connecting the COM55T5108 to the S1D13719 LCD LCD S1D13719 S1D13719 S1D13719 Panel S1D13719 Panel Pin LCD Panel Pin Description PFBGA FCBGA QFP Connector Pin Name Name Ball# Ball# Pin# Pin# 1 VSS GND for digital Note Note Note VSS Dot clock (Capture at the falling 2 CLK P5 F17 66 FPSHIFT edge)

3 DE Input data enable (Hi-active) M1 C13 44 DRDY

4 HSYNC Horizontal synchronous signal P4 E17 58 FPLINE 5 VSYNC Vertical synchronous signal P3 D17 57 FPFRAME 6 VSS GND for digital Note Note Note VSS 7 D20 RED data signal (LSB) L8 K16 82 FPDAT11 8 D21 RED data signal M8 K14 83 FPDAT10 9 D22 RED data signal M6 H15 72 FPDAT9 10 D23 RED data signal K4 A15 49 FPDAT2 11 D24 RED data signal N1 C14 48 FPDAT1 12 D25 RED data signal (MSB) L3 B15 47 FPDAT0 13 D10 GREEN data signal (LSB) M7 J17 79 FPDAT14 14 D11 GREEN data signal N8 K17 80 FPDAT13 15 D12 GREEN data signal P8 K15 81 FPDAT12

50 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

LCD LCD S1D13719 S1D13719 S1D13719 Panel S1D13719 Panel Pin LCD Panel Pin Description PFBGA FCBGA QFP Connector Pin Name Name Ball# Ball# Pin# Pin# 16 D13 GREEN data signal N3 D16 55 FPDAT5 17 D14 GREEN data signal N2 C17 54 FPDAT4 18 D15 GREEN data signal (MSB) P2 C16 53 FPDAT3 19 D00 BLUE data signal (LSB) N6 H17 73 FPDAT17 20 D01 BLUE data signal L7 J15 74 FPDAT16 21 D02 BLUE data signal M4 F16 60 FPDAT15 22 D03 BLUE data signal L2 B14 45 FPDAT8 23 D04 BLUE data signal L6 G15 68 FPDAT7 24 D05 BLUE data signal (MSB) M3 D15 56 FPDAT6 25 VSS GND for digital Note Note Note VSS Vertical and Horizontal reverse 26 REV control signal input Note Note Note VSS (Lo: Normal, Hi:Reverse) C11,D14, J3,H4, C15,E15, 35,52, 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） PIOVDD P6,M10 H16,P15, 71,96 R15 C11,D14, Standby control signal input (Lo: J3,H4, C15,E15, 35,52, 28 STBYB PIOVDD Normal, Hi: Standby) P6,M10 H16,P15, 71,96 R15 29 VSS GND for analog Note Note Note VSS Back light dimmer control pulse 30 PDM input Note Note Note VSS (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light Note Note Note VSS 32 VSS_B GND for back light Note Note Note VSS 33 VSS_B GND for back light Note Note Note VSS 34 VBL Power supply for back light - - - - 35 VBL Power supply for back light - - - - 36 VBL Power supply for back light - - - - S1D13719 PIOVDD must be configured between +3.0V to +3.25V to be connected to the COM55T5108.

Connecting EPSON Display Controllers EPSON 51 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2.5 Connecting the COM55T5108 to the S1D13742

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13742.

3.3V COM55T5108 S1D13742

VDD PIOVDD STBYB

DE DE

D[25:20] (R) VD[17:12]

D[15:10] (G) VD[11:6]

D[5:0] (B) VD[5:0]

HSYNC HS VSYNC VS CLK PCLK

REV

PDM

VSS_B

VSS VSS

52 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13742.

Connecting the COM55T5108 to the S1D13742 LCD S1D13742 LCD Panel S1D13742 S1D13742 Panel LCD Panel Pin Description FCBGA Connector Pin# QFP Pin# Pin Name Pin Name Ball# 1 VSS GND for digital Note Note VSS 2 CLK Dot clock (Capture at the falling edge) 11 D11 PCLK 3 DE Input data enable (Hi-active) 8 C11 DE 4 HSYNC Horizontal synchronous signal 9 D9 HS 5 VSYNC Vertical synchronous signal 10 D10 VS 6 VSS GND for digital Note Note VSS 7 D20 RED data signal (LSB) 61 K5 VD12 8 D21 RED data signal 64 K4 VD13 9 D22 RED data signal 30 J11 VD14 10 D23 RED data signal 29 J10 VD15 11 D24 RED data signal 43 J9 VD16 12 D25 RED data signal (MSB) 47 J8 VD17 13 D10 GREEN data signal (LSB) 66 L3 VD6 14 D11 GREEN data signal 42 K10 VD7 15 D12 GREEN data signal 44 K9 VD8 16 D13 GREEN data signal 48 K8 VD9 17 D14 GREEN data signal 51 K7 VD10 18 D15 GREEN data signal (MSB) 58 K6 VD11 19 D00 BLUE data signal (LSB) 45 L9 VD0 20 D01 BLUE data signal 49 L8 VD1 21 D02 BLUE data signal 54 L7 VD2 22 D03 BLUE data signal 59 L6 VD3 23 D04 BLUE data signal 62 L5 VD4 24 D05 BLUE data signal (MSB) 65 L4 VD5 25 VSS GND for digital Note Note VSS Vertical and Horizontal reverse control 26 REV signal input Note Note VSS (Lo: Normal, Hi:Reverse) 4,17,20, E8,G4,H5 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） 33,38,52,5 PIOVDD ,H7 5,69 4,17,20, Standby control signal input (Lo: E8,G4,H5 28 STBYB 33,38,52,5 PIOVDD Normal, Hi: Standby) ,H7 5,69 29 VSS GND for analog Note Note VSS Back light dimmer control pulse input 30 PDM Note Note VSS (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light Note Note VSS 32 VSS_B GND for back light Note Note VSS 33 VSS_B GND for back light Note Note VSS 34 VBL Power supply for back light - - - 35 VBL Power supply for back light - - - 36 VBL Power supply for back light - - - Note Allocation of VSS pin for each packages are as follows. QFP: 5,7,18,21,32,34,39,41,53,56,68,70,78,90,103,105,112,116,119,129,135,144 FCBGA: C5,C6,E5,E6,E7,F4,F5,F6,F7,G5,G6

Connecting EPSON Display Controllers EPSON 53 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2.6 Connecting the COM55T5108 to the S1D13743

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13743.

3.3V COM55T5108 S1D13743

VDD PIOVDD STBYB

DE DE

D[25:20] (R) VD[17:12]

D[15:10] (G) VD[11:6]

D[5:0] (B) VD[5:0]

HSYNC HS VSYNC VS CLK PCLK

REV

PDM

VSS_B

SS VSS V

54 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13743.

Connecting the COM55T5108 to the S1D13743 LCD LCD S1D13743 Panel S1D13743 S1D13743 Panel Pin LCD Panel Pin Description FCBGA Connector QFP Pin# Pin Name Name Ball# Pin# 1 VSS GND for digital Note Note VSS 2 CLK Dot clock (Capture at the falling edge) 8 D11 PCLK 3 DE Input data enable (Hi-active) 3 C11 DE 4 HSYNC Horizontal synchronous signal 4 D9 HS 5 VSYNC Vertical synchronous signal 5 D10 VS 6 VSS GND for digital Note Note VSS 7 D20 RED data signal (LSB) 56 K5 VD12 8 D21 RED data signal 61 K4 VD13 9 D22 RED data signal 15 J11 VD14 10 D23 RED data signal 14 J10 VD15 11 D24 RED data signal 20 J9 VD16 12 D25 RED data signal (MSB) 40 J8 VD17 13 D10 GREEN data signal (LSB) 63 L3 VD6 14 D11 GREEN data signal 21 K10 VD7 15 D12 GREEN data signal 38 K9 VD8 16 D13 GREEN data signal 44 K8 VD9 17 D14 GREEN data signal 48 K7 VD10 18 D15 GREEN data signal (MSB) 51 K6 VD11 19 D00 BLUE data signal (LSB) 39 L9 VD0 20 D01 BLUE data signal 43 L8 VD1 21 D02 BLUE data signal 49 L7 VD2 22 D03 BLUE data signal 54 L6 VD3 23 D04 BLUE data signal 57 L5 VD4 24 D05 BLUE data signal (MSB) 62 L4 VD5 25 VSS GND for digital Note Note VSS Vertical and Horizontal reverse control 26 REV signal input Note Note VSS (Lo: Normal, Hi:Reverse) E8,G4,H 1,9,18,28 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） 5, PIOVDD ,46,58 H7 E8,G4,H Standby control signal input (Lo: 1,9,18,28 28 STBYB 5, PIOVDD Normal, Hi: Standby) ,46,58 H7 29 VSS GND for analog Note Note VSS Back light dimmer control pulse input 30 PDM Note Note VSS (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light Note Note VSS 32 VSS_B GND for back light Note Note VSS 33 VSS_B GND for back light Note Note VSS 34 VBL Power supply for back light - - - 35 VBL Power supply for back light - - - 36 VBL Power supply for back light - - - Note Allocation of VSS pin for each packages are as follows. QFP: 2,7,10,19,27,42,47,53,59,65,69,75,80,86,92,96,99,104,113,116,129,134,140 FCBGA: C5,C6,E5,E6,E7,F4,F5,F6,F7,G5,G6

Connecting EPSON Display Controllers EPSON 55 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.2.7 Connecting the COM55T5108 to the S1D13748

The following diagram shows an example implementation of the COM55T5108 panel connected to the S1D13748.

3.3V COM55T5108 S1D13748

VDD PIOVDD STBYB

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAM CLK FPSHIFT

REV

PDM

VSS_B

VSS VSS

56 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

The following table provides a detailed pin listing for the required connections between the COM55T5108 and the S1D13748.

Connecting the COM55T5108 to the S1D13748 LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 1 VSS GND for digital Note Note VSS 2 CLK Dot clock (Capture at the falling edge) 75 J11 FPSHIFT 3 DE Input data enable (Hi-active) 78 G7 FPDRDY 4 HSYNC Horizontal synchronous signal 77 H10 FPLINE 5 VSYNC Vertical synchronous signal 76 J10 FPFRAME 6 VSS GND for digital Note Note VSS 7 D20 RED data signal (LSB) 63 L8 FPDAT11 8 D21 RED data signal 62 J8 FPDAT10 9 D22 RED data signal 61 K8 FPDAT9 10 D23 RED data signal 51 K5 FPDAT2 11 D24 RED data signal 50 L5 FPDAT1 12 D25 RED data signal (MSB) 49 J5 FPDAT0 13 D10 GREEN data signal (LSB) 69 H8 FPDAT14 14 D11 GREEN data signal 68 K9 FPDAT13 15 D12 GREEN data signal 64 L9 FPDAT12 16 D13 GREEN data signal 54 L6 FPDAT5 17 D14 GREEN data signal 53 J6 FPDAT4 18 D15 GREEN data signal (MSB) 52 H6 FPDAT3 19 D00 BLUE data signal (LSB) 72 J9 FPDAT17 20 D01 BLUE data signal 71 K10 FPDAT16 21 D02 BLUE data signal 70 L10 FPDAT15 22 D03 BLUE data signal 60 K7 FPDAT8 23 D04 BLUE data signal 59 J7 FPDAT7 24 D05 BLUE data signal (MSB) 58 L7 FPDAT6 25 VSS GND for digital Note Note VSS Vertical and Horizontal reverse control signal 26 REV input Note Note VSS (Lo: Normal, Hi:Reverse) 19,26,35, E8,F4, 40,46,55, 27 VDD Power +3.3V(+3.0V≤VDD≤+3.6V） H7,J4 PIOVDD 67,73,83,

87 Standby control signal input (Lo: Normal, Hi: 28 STBYB Note Note VSS Standby) 29 VSS GND for analog Note Note VSS Back light dimmer control pulse input 30 PDM Note Note VSS (Lo:100%, Hi:0%(Back light off)) 31 VSS_B GND for back light Note Note VSS 32 VSS_B GND for back light Note Note VSS 33 VSS_B GND for back light Note Note VSS 34 VBL Power supply for back light - - - 35 VBL Power supply for back light - - - 36 VBL Power supply for back light - - - Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

Connecting EPSON Display Controllers EPSON 57 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

6.3 Example Register Settings

In addition to the pin connections, the S1D13513/S1D13706/S1D13A05/S1D13719/S1D13742/S1D1374 3/S1D13748 internal registers must be configured appropriately for the COM55T5108 LCD panel. The following tables provide example settings for each display controller. However, these values are for ref erence only and may differ according to each specific implementation.

Also included in the table is an example clock configuration designed to achieve a typical LCD refresh.

Example Register Settings for the S1D13513 Parameter Register Index and Name Register Setting Value (see Note) REG[0800h] LCD Panel Type Select Register 0300h - REG[0802h] LCD Horizontal Total Register 427 428 REG[0804h] LCD Horizontal Display Period Register 159 320 REG[0806h] LCD Horizontal Display Period Start Position 91 92 Register REG[0808h] LCD Horizontal Pulse Width 8000h+(90-1) 90 REG[080Ah] LCD Horizontal Pulse Start Position 0 0 REG[080Ch] LCD Vertical Total Register 242 243 REG[080Eh] LCD Vertical Display Period Resister 240 241 REG[0810h] LCD Vertical Display Period Start Position Register 1 1 REG[0812h] LCD Vertical Pulse Width 8000h+0 0 REG[0814h] LCD Vertical Pulse Start Position 0 0 PLL2 output frequency in MHz - 90 REG[0446h] LCD Clock Control Register 9 10 FPSHIFT in MHz - 9 LCD Refresh in Hz - 59.9

Example Register Settings for the S1D13706 Parameter Value Register Index and Name Register Setting (see Note) REG[0010h] Panel Type Register 61h - REG[0012h] Horizontal Total Register (424/8-1) 424 REG[0014h] Horizontal Display Period Register (320/8-1) 320 REG[0016h] Horizontal Display Period Start Position Register 0 (93-5) 93 REG[0020h] FPLINE Pulse Width Register 9 10 REG[0022h] FPLINE Pulse Start Pos Register 0 0 1 REG[0018h] Vertical Total Register 0 (250-1) 250 REG[001Ch] Vertical Display Period Resister 0 (240-1) 240 REG[001Eh] Vertical Display Period Start Position Register 0 0 0 REG[0024]h Vertical Sync Pulse Width Register 80h+0 1 REG[0026h] Vertical Sync Pulse Start Pos Register 0 0 0 CLKI2 frequency in MHz - 6.5 REG[0005h] Pixel Clock Configuration Register 3 1 FPSHIFT in MHz - 6.5 LCD Refresh in Hz - 61.3

Note Parameter values are determined using a formula based on the register setting. For details on configuring the

58 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

S1D13706 register values, see the S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.

Example Register Settings for the S1D13A05 Parameter Value Register Index and Name Register Setting (see Note) REG[000Ch] Panel Type & MOD Rate Register 000000E1h - REG[0020h] Horizontal Total Register (424/8-1) 424 REG[0024h] Horizontal Display Period Register (320/8-1) 320 REG[0028h] Horizontal Display Period Start Position Register (85－5) 85 Pulse Width90 REG[002Ch] FPLINE Register 00D90000h Start Position 1 REG[0030h] Vertical Total Register 241 242 REG[0034h] Vertical Display Period Resister 240 240 REG[0038h] Vertical Display Period Start Position Register 1 1 Pulse Width 1 REG[003Ch] FPFRAME Register 00800001h Start Position 1 CLKI2 frequency in MHz - 6.5 REG[0008h] Pixel Clock Configuration Register 3 1 FPSHIFT in MHz - 6.5 LCD Refresh in Hz - 63.3

Example Register Settings for the S1D13719 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] LCD1 Horizontal Total Register 53 432 REG[0042h] LCD1 Horizontal Display Period Register 159 320 REG[0044h] LCD1 Horizontal Display Period Start Position 11 20 Register REG[0046h] LCD1 FPLINE Register 0080h+12 13 REG[0048h] LCD1 FPLINE Pulse Position Register 15 16 REG[004Ah] LCD1 Vertical Total Register 242 243 REG[004Ch] LCD1 Vertical Display Period Resister 240 241 REG[004Eh] LCD1 Vertical Display Period Start Position Register 2 2 REG[0050h] LCD1 FPFRAME Register 0080h+1 2 REG[0052h] LCD1 FPFRAME Pulse Position Register 16 17 PLL output frequency in MHz - 54 REG[0030h] LCD Interface Clock Setting Register 0503h 8 FPSHIFT in MHz - 6.75 LCD Refresh in Hz - 64.3

Connecting EPSON Display Controllers EPSON 59 to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

Example Register Settings for the S1D13742 Parameter Value Register Index and Name Register Setting (see Note) REG[14h] Panel Type Register 00h - REG[16h] Horizontal Display Width Register 40 320 REG[18h] Horizontal Non-Display Period Register 132 132 REG[1Ah][1Ch] Vertical Display Height Registers 280 280 REG[1Eh] Vertical Non-Display Period Register 2 2 REG[20h] HS Pulse Width Register 80h+13 13 REG[22h] HS Pulse Start Position Register 0 1 1 REG[24h] VS Pulse Width Register 80h+1 1 REG[26h] VS Pulse Start Position Register 0 1 1 PLL frequency in MHz - 63 REG[12h] Pixel Clock Configuration Register 49h 10 FPSHIFT in MHz - 6.3 LCD Refresh in Hz - 49.4

Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13742 register values, see the S1D13742 Hardware Functional Specification, document number X63A-A-001-xx.

Example Register Settings for the S1D13743 Parameter Value Register Index and Name Register Setting (see Note) REG[14h] Panel Type Register 00h - REG[16h] Horizontal Display Width Register 40 320 REG[18h] Horizontal Non-Display Period Register 132 132 REG[1Ah][1Ch] Vertical Display Height Register0,1 480 480 REG[1Eh] Vertical Non-Display Period Register 2 2 REG[20h] HS Pulse Width Register 80h+13 13 REG[22h] HS Pulse Start Position Resister 1 1 REG[24h] VS Pulse Width Register 80h+1 1 REG[26h] VS Pulse Start Position Resister 1 1 PLL frequency in MHz - 63 REG[12h] Clock Source Select Register 49h 10 FPSHIFT in MHz - 6.3 LCD Refresh in Hz - 70.3 Note Parameter values are determined using a formula based on the register setting. For details on configuring the S1D13743 register values, see the S1D13743 Hardware Functional Specification, document number X70A-A-001-xx.

60 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 6. CONNECTING TO THE CASIO COM55T5108

Example Register Settings for the S1D13748 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] LCD1 Horizontal Total Register 53 432 REG[0042h] LCD1 Horizontal Display Period Register 159 320 REG[0044h] LCD1 Horizontal Display Period Start Position 91 92 Register REG[0046h] LCD1 Horizontal Pulse Register 0080h+89 90 REG[0048h] LCD1 Horizontal Pulse Start Position Register 0 1 REG[004Ah] LCD1 Vertical Total Register 242 243 REG[004Ch] LCD1 Vertical Display Period Resister 239 240 REG[004Eh] LCD1 Vertical Display Period Start Position Register 1 1 REG[0050h] LCD1 Vertical Pulse Register 0080h+0 1 REG[0052h] LCD1 Vertical Pulse Start Position Register 0 1 REG[0246h] Main1 Window Image Horizontal Size Register 319 320 REG[0248h] Main1 Window Image Vertical Size Register 239 240 PLL output frequency in MHz - 50 REG[0030h] LCD Interface Clock Setting Register 0507h 8 FPSHIFT in MHz - 6.25 LCD Refresh in Hz - 59.5

Connecting EPSON Display Controllers EPSON 61 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

7. CONNECTING TO THE CASIO COM57T5120

The Casio COM57T5120 TFT panel is compatible with the S1D13513 and S1D13748 display controllers. The following sections will provide connector details, pin mappings, and example register settings for these combinations.

7.1 COM57T5120 Pin Mapping

The COM57T5120 TFT panel uses a 45-pin connector with the following pin mapping.

COM57T5120 Pin Mapping Connector Pin Name Pin Description Pin# 1 VSS GND 24bit mode: Dot clock 2 CLK 18bit mode: Dot clock (Capture at the falling edge) 3 VSS GND 24bit mode: Horizontal synchronous signal 4 HSYNC 18bit mode: Horizontal synchronous signal (Negative) 24bit mode: Vertical synchronous signal 5 VSYNC 18bit mode: Vertical synchronous signal (Negative) 6 VSS GND 24bit mode: BLUE data signal (LSB) 7 D20 18bit mode: Connect to VSS 24bit mode: BLUE data signal 8 D21 18bit mode: Connect to VSS 24bit mode: BLUE data signal 9 D22 18bit mode: BLUE data signal (LSB) 10 D23 BLUE data signal 11 D24 BLUE data signal 12 D25 BLUE data signal 13 D26 BLUE data signal 14 D27 BLUE data signal (MSB) 15 VSS GND 24bit mode: GREEN data signal (LSB) 16 D10 18bit mode: Connect to VSS 24bit mode: GREEN data signal 17 D11 18bit mode: Connect to VSS 24bit mode: GREEN data signal 18 D12 18bit mode: GREEN data signal (LSB) 19 D13 GREEN data signal 20 D14 GREEN data signal 21 D15 GREEN data signal 22 D16 GREEN data signal 23 D17 GREEN data signal (MSB) 24 VSS GND 24bit mode: RED data signal (LSB) 25 D00 18bit mode: Connect to VSS 24bit mode: RED data signal 26 D01 18bit mode: Connect to VSS 24bit mode: RED data signal 27 D02 18bit mode: RED data signal (LSB) 28 D03 RED data signal 29 D04 RED data signal 30 D05 RED data signal 31 D06 RED data signal

62 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

Connector Pin Name Pin Description Pin# 32 D07 RED data signal (MSB) 33 VSS GND 34 MODE Input mode select, Lo: 24bit Hi: 18bit 35 VDD Power supply for logic（+3.3V±0.3V） 36 VDD Power supply for logic（+3.3V±0.3V） 24bit mode: Serial chip select (Lo-active) 37 CS/STBY 18bit mode: Standby control signal input (Lo: Normal, Hi: Standby) 24bit mode: Serial data input 38 DI/DE 18bit mode: DATA ENABLE (Hi-active) 24bit mode: Serial clock 39 SCK/REV 18bit mode: Vertical and Horizontal reverse control signal input (Lo: Normal, Hi:Reverse) 40 VSS GND 41 VBL Power supply for back light（+12V±1.2V） 42 VBL Power supply for back light（+12V±1.2V） Back light pulse input, 43 PDM Lo: OFF（0%）, Hi: ON（100%） 44 VSS GND 45 VSS GND Note The recommended connector is a 04-6240-045-023-846+ from Kyocera elco.

7.2 Connection Examples

In addition to the pin connections for the selected display controller, the COM57T5120 requires the following power supplies.

VDD +3.3V (±0.3V) VBL +12V (±1.2V)

For VDD, select a voltage within the supportable range of the Display Controller.

For further details on the COM57T5120, such as power consumption and absolute maximum ratings, please contact your Casio representative.

Connecting EPSON Display Controllers EPSON 63 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

7.2.1 Connecting the COM57T5120 to the S1D13513

The following diagram shows an example implementation of the COM57T5120 panel connected to the S1D13513. This example is for the setting of 18-bit panel mode (MODE=”VDD”) on COM57T5120.

3.3V COM57T5120 S1D13513

VDD HVDD2 MODE

CS/STBY

PDM

DI/DE FPDRDY

D[27:25] (B) FPDAT[6:8] D[24:22] (B) FPDAT[15:17] D[17:15] (G) FPDAT[3:5] D[14:12] (G) FPDAT[12:14] D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11]

HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT

D[21:20]

D[11:10]

D[1:0] SCK/REV

VSS VSS

64 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

The following diagram shows an example implementation of the COM57T5120 panel connected to the S1D13513. This example is for the setting of 24-bit panel mode (MODE=”VSS”) on COM57T5120.

3.3V COM57T5120 S1D13513

VDD HVDD2 MODE

CS/STBY CS#

PDM

DI/DE SO

D[27:25] (B) FPDAT[6:8]

FPDAT[15:17] D[24:22] (B) D[21:20] (B) FPDAT[22:23] D[17:15] (G) FPDAT[3:5]

D[14:12] (G) FPDAT[12:14] D[11:10] (G) FPDAT[20:21]

D[7:5] (R) FPDAT[0:2]

D[4:2] (R) FPDAT[9:11] D[1:0] (R) FPDAT[18:19]

HSYNC FPLINE VSYNC FPFRAME

CLK FPSHIFT

SCK/REV SCK

VSS

The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13513. This table is for the setting of 18-bit panel mode (MODE=”VDD”) on COM57T5120. Pin mappings are shown for both S1D13513 package types.

Connecting the COM57T5120 to the S1D13513 (18-bit panel mode (MODE=”VDD”)) LCD Pane LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 1 VSS GND Note Note VSS 2 CLK Dot clock (Capture at the falling edge) 77 P8 FPSHIFT 3 VSS GND Note Note VSS 4 HSYNC Horizontal synchronous signal (Negative) 79 R8 FPLINE 5 VSYNC Vertical synchronous signal (Negative) 78 T8 FPFRAME 6 VSS GND Note Note VSS 7 D20 Connect to VSS Note Note VSS 8 D21 Connect to VSS Note Note VSS

Connecting EPSON Display Controllers EPSON 65 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

LCD Pane LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 9 D22 BLUE data signal (LSB) 53 N4 FPDAT17 10 D23 BLUE data signal 54 P4 FPDAT16 11 D24 BLUE data signal 55 T2 FPDAT15 12 D25 BLUE data signal 64 R6 FPDAT8 13 D26 BLUE data signal 67 K6 FPDAT7 14 D27 BLUE data signal (MSB) 68 M6 FPDAT6 15 VSS GND Note Note VSS 16 D10 Connect to VSS Note Note VSS 17 D11 Connect to VSS Note Note VSS 18 D12 GREEN data signal (LSB) 56 R4 FPDAT14 19 D13 GREEN data signal 59 T4 FPDAT13 20 D14 GREEN data signal 60 T5 FPDAT12 21 D15 GREEN data signal 69 L7 FPDAT5 22 D16 GREEN data signal 70 P7 FPDAT4 23 D17 GREEN data signal (MSB) 71 R7 FPDAT3 24 VSS GND Note Note VSS 25 D00 Connect to VSS Note Note VSS 26 D01 Connect to VSS Note Note VSS 27 D02 RED data signal (LSB) 61 N5 FPDAT11 28 D03 RED data signal 62 M5 FPDAT10 29 D04 RED data signal 63 P6 FPDAT9 30 D05 RED data signal 72 T7 FPDAT2 31 D06 RED data signal 73 N7 FPDAT1 32 D07 RED data signal (MSB) 74 M7 FPDAT0 33 VSS GND Note Note VSS 34 MODE Input mode select. Lo: 24bit, Hi: 18bit 57,65,75 L5,L8,T6 HVDD2 35 VDD Power supply for logic（+3.3V±0.3V） 57,65,75 L5,L8,T6 HVDD2 36 VDD Power supply for logic（+3.3V±0.3V） 57,65,75 L5,L8,T6 HVDD2 Standby control signal input Note Note VSS 37 STBY (Lo: Normal, Hi: Standby) 38 DE Input data enable (Hi-active) 80 M8 FPDRDY Vertical and Horizontal reverse control Note Note VSS 39 signal input REV (Lo: Normal, Hi:Reverse) 40 VSS GND Note Note VSS 41 VBL Power supply for back light（+12V±1.2V） - - - 42 VBL Power supply for back light（+12V±1.2V） - - - Back light pulse input. 57,65,75 L5,L8,T6 HVDD2 43 PDM Lo: OFF（0%）, Hi: ON（100%） 44 VSS GND Note Note VSS 45 VSS GND Note Note VSS Note Allocation of VSS pin for each packages are as follows. QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16

The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13513. This table is for the setting of 24-bit panel mode (MODE=”VSS”) on COM57T5120. Pin mappings are shown for both S1D13513 package types.

66 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

Connecting the COM57T5120 to the S1D13513 (24-bit panel mode (MODE=”VSS”)) LCD Pane LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 Connector Pin Name Pin Description QFP Pin# PBGA Ball# Pin Name Pin# 1 VSS GND Note 1 Note 1 VSS 2 CLK Dot clock (Capture at the falling edge) 77 P8 FPSHIFT 3 VSS GND Note 1 Note 1 VSS 4 HSYNC Horizontal synchronous signal (Negative) 79 R8 FPLINE 5 VSYNC Vertical synchronous signal (Negative) 78 T8 FPFRAME 6 VSS GND Note 1 Note 1 VSS 7 D20 Connect to VSS Note 2 K4 FPDAT23 8 D21 Connect to VSS Note 2 R3 FPDAT22 9 D22 BLUE data signal (LSB) 53 N4 FPDAT17 10 D23 BLUE data signal 54 P4 FPDAT16 11 D24 BLUE data signal 55 T2 FPDAT15 12 D25 BLUE data signal 64 R6 FPDAT8 13 D26 BLUE data signal 67 K6 FPDAT7 14 D27 BLUE data signal (MSB) 68 M6 FPDAT6 15 VSS GND Note 1 Note 1 VSS 16 D10 Connect to VSS Note 2 T3 FPDAT21 17 D11 Connect to VSS Note 2 P5 FPDAT20 18 D12 GREEN data signal (LSB) 56 R4 FPDAT14 19 D13 GREEN data signal 59 T4 FPDAT13 20 D14 GREEN data signal 60 T5 FPDAT12 21 D15 GREEN data signal 69 L7 FPDAT5 22 D16 GREEN data signal 70 P7 FPDAT4 23 D17 GREEN data signal (MSB) 71 R7 FPDAT3 24 VSS GND Note 1 Note 1 VSS 25 D00 Connect to VSS Note 2 K5 FPDAT19 26 D01 Connect to VSS Note 2 R5 FPDAT18 27 D02 RED data signal (LSB) 61 N5 FPDAT11 28 D03 RED data signal 62 M5 FPDAT10 29 D04 RED data signal 63 P6 FPDAT9 30 D05 RED data signal 72 T7 FPDAT2 31 D06 RED data signal 73 N7 FPDAT1 32 D07 RED data signal (MSB) 74 M7 FPDAT0 33 VSS GND Note 1 Note 1 VSS 34 MODE Input mode select. Lo: 24bit, Hi: 18bit Note 1 Note 1 VSS 35 VDD Power supply for logic（+3.3V±0.3V） 57,65,75 L5,L8,T6 HVDD2 36 VDD Power supply for logic（+3.3V±0.3V） 57,65,75 L5,L8,T6 HVDD2 Standby control signal input 85 L9 CS# 37 STBY (Lo: Normal, Hi: Standby) 38 DE Input data enable (Hi-active) 82 T9 SO Vertical and Horizontal reverse control 84 P9 SCK 39 signal input REV (Lo: Normal, Hi:Reverse) 40 VSS GND Note 1 Note 1 VSS 41 VBL Power supply for back light（+12V±1.2V） - - - 42 VBL Power supply for back light（+12V±1.2V） - - - Back light pulse input. 57,65,75 L5,L8,T6 HVDD2 43 PDM Lo: OFF（0%）, Hi: ON（100%） 44 VSS GND Note 1 Note 1 VSS 45 VSS GND Note 1 Note 1 VSS Note 1 Allocation of VSS pin for each packages are as follows.

Connecting EPSON Display Controllers EPSON 67 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

QFP: 10,20,38,58,66,76,92,99,106,120,133,139,151,163,169,175,184,197 BGA: A1,A16,D4,D8,D13,G7-G10,G13,H7-H10,J1,J7-J10,K2,K7-K10,K13,N3,N6,N9,N13,T1,T16

Note 2 For QFP package, please connect to S1D13513 VSS pin.

68 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

7.2.2 Connecting the COM57T5120 to the S1D13748

The following diagram shows an example implementation of the COM57T5120 panel connected to the S1D13748. This example is for the setting of 18-bit panel mode (MODE=”VDD”) on COM57T5120.

3.3V COM57T5120 S1D13748

VDD PIOVDD MODE

CS/STBY

PDM

DI/DE FPDRDY D[27:25] (B) FPDAT[6:8] D[24:22] (B) FPDAT[15:17]

D[17:15] (G) FPDAT[3:5] D[14:12] (G) FPDAT[12:14] D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11]

HSYNC FPLINE VSYNC FPFRAME CLK FPSHIFT

D[21:20] D[11:10]

D[1:0]

SCK/REV VSS VSS

Connecting EPSON Display Controllers EPSON 69 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

The following diagram shows an example implementation of the COM57T5120 panel connected to the S1D13748. This example is for the setting of 24-bit panel mode (MODE=”VSS”) on COM57T5120.

3.3V COM57T5120 S1D13748

VDD PIOVDD MODE

CS/STBY FPCS1#

PDM

DI/DE FPSO

D[27:25] (B) FPDAT[6:8]

D[24:22] (B) FPDAT[15:17] D[21:20] (B) FPDAT[22:23]

D[17:15] (G) FPDAT[3:5] D[14:12] (G) FPDAT[12:14]

D[11:10] (G) FPDAT[20:21]

D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11]

D[1:0] (R) FPDAT[18:19]

HSYNC FPLINE

VSYNC FPFRAME CLK FPSHIFT

SCK/REV FPSCK VSS VSS

The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13748. This table is for the setting of 18-bit panel mode (MODE=”VDD”) on COM57T5120. Pin mappings are shown for both S1D13748 package types.

Connecting the COM57T5120 to the S1D13748 (18-bit panel mode (MODE=”VDD”))

LCD Panel S1D13748 LCD Panel S1D13748 S1D13748 Connector LCD Panel Pin Description PFBGA Pin Name QFP Pin# Pin Name Pin# Ball# 1 VSS GND Note Note VSS 2 CLK Dot clock (Capture at the falling edge) 75 J11 FPSHIFT 3 VSS GND Note Note VSS 4 HSYNC Horizontal synchronous signal (Negative) 77 H10 FPLINE 5 VSYNC Vertical synchronous signal (Negative) 76 J10 FPFRAME 6 VSS GND Note Note VSS 7 D20 Connect to VSS Note Note VSS 8 D21 Connect to VSS Note Note VSS

70 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

LCD Panel S1D13748 LCD Panel S1D13748 S1D13748 Connector LCD Panel Pin Description PFBGA Pin Name QFP Pin# Pin Name Pin# Ball# 9 D22 BLUE data signal (LSB) 72 J9 FPDAT17 10 D23 BLUE data signal 71 K10 FPDAT16 11 D24 BLUE data signal 70 L10 FPDAT15 12 D25 BLUE data signal 60 K7 FPDAT8 13 D26 BLUE data signal 59 J7 FPDAT7 14 D27 BLUE data signal (MSB) 58 L7 FPDAT6 15 VSS GND Note Note VSS 16 D10 Connect to VSS Note Note VSS 17 D11 Connect to VSS Note Note VSS 18 D12 GREEN data signal (LSB) 69 H8 FPDAT14 19 D13 GREEN data signal 68 K9 FPDAT13 20 D14 GREEN data signal 64 L9 FPDAT12 21 D15 GREEN data signal 54 L6 FPDAT5 22 D16 GREEN data signal 53 J6 FPDAT4 23 D17 GREEN data signal (MSB) 52 H6 FPDAT3 24 VSS GND Note Note VSS 25 D00 Connect to VSS Note Note VSS 26 D01 Connect to VSS Note Note VSS 27 D02 RED data signal (LSB) 63 L8 FPDAT11 28 D03 RED data signal 62 J8 FPDAT10 29 D04 RED data signal 61 K8 FPDAT9 30 D05 RED data signal 51 K5 FPDAT2 31 D06 RED data signal 50 L5 FPDAT1 32 D07 RED data signal (MSB) 49 J5 FPDAT0 33 VSS GND Note Note VSS 19,26,35, E8,F4, 40,46,55, 34 MODE Input mode select. Lo: 24bit, Hi: 18bit H7,J4 PIOVDD 67,73,83,

87 19,26,35, E8,F4, 40,46,55, 35 VDD Power supply for logic（+3.3V±0.3V） H7,J4 PIOVDD 67,73,83,

87 19,26,35, E8,F4, 40,46,55, 36 VDD Power supply for logic（+3.3V±0.3V） H7,J4 PIOVDD 67,73,83,

87 Standby control signal input 37 STBY Note Note VSS (Lo: Normal, Hi: Standby) 38 DE Input data enable (Hi-active) 78 G7 FPDRDY Vertical and Horizontal reverse control 39 REV signal input Note Note VSS (Lo: Normal, Hi:Reverse) 40 VSS GND Note Note VSS 41 VBL Power supply for back light（+12V±1.2V） - - - 42 VBL Power supply for back light（+12V±1.2V） - - - 19,26,35, E8,F4,H7 Back light pulse input. 43 PDM 40,46,55,67 ,J4 PIOVDD Lo: OFF（0%）, Hi: ON（100%） ,73,83,87 44 VSS GND Note Note VSS 45 VSS GND Note Note VSS Note Allocation of VSS pin for each packages are as follows.

Connecting EPSON Display Controllers EPSON 71 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

The following table provides a detailed pin listing for the required connections between the COM57T5120 and the S1D13748. This table is for the setting of 24-bit panel mode (MODE=”VSS”) on COM57T5120. Pin mappings are shown for both S1D13748 package types.

Connecting the COM57T5120 to the S1D13748 (24-bit panel mode (MODE=”VSS”))

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 1 VSS GND Note Note VSS 2 CLK Dot clock 75 J11 FPSHIFT 3 VSS GND Note Note VSS 4 HSYNC Horizontal synchronous signal 77 H10 FPLINE FPFRAM 5 VSYNC Vertical synchronous signal 76 J10 E 6 VSS GND Note Note VSS FPDAT2 7 D20 BLUE data signal (LSB) 48 H5 3 FPDAT2 8 D21 BLUE data signal 45 L4 2 FPDAT1 9 D22 BLUE data signal 72 J9 7 FPDAT1 10 D23 BLUE data signal 71 K10 6 FPDAT1 11 D24 BLUE data signal 70 L10 5 12 D25 BLUE data signal 60 K7 FPDAT8 13 D26 BLUE data signal 59 J7 FPDAT7 14 D27 BLUE data signal (MSB) 58 L7 FPDAT6 15 VSS GND Note Note VSS FPDAT2 16 D10 GREEN data signal (LSB) 44 G6 1 FPDAT2 17 D11 GREEN data signal 43 K4 0 FPDAT1 18 D12 GREEN data signal 69 H8 4 FPDAT1 19 D13 GREEN data signal 68 K9 3 FPDAT1 20 D14 GREEN data signal 64 L9 2 21 D15 GREEN data signal 54 L6 FPDAT5 22 D16 GREEN data signal 53 J6 FPDAT4 23 D17 GREEN data signal (MSB) 52 H6 FPDAT3 24 VSS GND Note Note VSS FPDAT1 25 D00 RED data signal (LSB) 42 L3 9 FPDAT1 26 D01 RED data signal 41 K3 8 FPDAT1 27 D02 RED data signal 63 L8 1 28 D03 RED data signal 62 J8 FPDAT1

72 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 0 29 D04 RED data signal 61 K8 FPDAT9 30 D05 RED data signal 51 K5 FPDAT2 31 D06 RED data signal 50 L5 FPDAT1 32 D07 RED data signal (MSB) 49 J5 FPDAT0 33 VSS GND Note Note VSS 34 MODE Input mode select, Lo: 24bit, Hi: 18bit Note Note VSS 19,26,35, E8,F4,H7 35 VDD Power supply for logic（+3.3V±0.3V） 40,46,55,67 ,J4 PIOVDD ,73,83,87 19,26,35, E8,F4,H7 36 VDD Power supply for logic（+3.3V±0.3V） 40,46,55,67 ,J4 PIOVDD ,73,83,87 37 CS Serial chip select (Lo-active) 80 G9 FPCS1# 38 DI Serial data input 86 G11 FPSO 39 SCK Serial clock 84 H11 FPSCK 40 VSS GND Note Note VSS 41 VBL Power supply for back light（+12V±1.2V） - - - 42 VBL Power supply for back light（+12V±1.2V） - - - 19,26,35, E8,F4,H7 Back light pulse input, 43 PDM 40,46,55,67 ,J4 PIOVDD Lo:OFF（0%）, Hi:ON（100%） ,73,83,87 44 VSS GND Note Note VSS 45 VSS GND Note Note VSS Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

Connecting EPSON Display Controllers EPSON 73 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

7.3 Example Register Settings

In addition to the pin connections, the S1D13513/S1D13748 internal registers must be configured appropriately for the COM57T5120 LCD panel. The following tables provide example settings for each display controller. However, these values are for reference only and may differ according to each specific implementation. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx. For details on configuring the S1D13748 register values, see the S1D13748 Hardware Functional Specification, document number X80A-A-001-xx.

Also included in the table is an example clock configuration designed to achieve a 50Hz or greater LCD refresh.

Example Register Settings for the S1D13513 Parameter Register Index and Name Register Setting Value (see Note) REG[0800h] LCD Panel Type Select Register 0280h - REG[0802h] LCD Horizontal Total Register 428 429 REG[0804h] LCD Horizontal Display Period Register 159 320 REG[0806h] LCD Horizontal Display Period Start Position Register 41 42 REG[0808h] LCD Horizontal Pulse Width 10 11 REG[080Ah] LCD Horizontal Pulse Start Position 0 0 REG[080Ch] LCD Vertical Total Register 261 262 REG[080Eh] LCD Vertical Display Period Resister 239 240 REG[0810h] Vertical Display Period Start Position Register 6 6 REG[0812h] LCD Vertical Pulse Width 2 3 REG[0814h] LCD Vertical Pulse Start Position 0 0 PLL2 output frequency in MHz - 80 REG[0446h] LCD Clock Control Register 11 12 FPSHIFT in MHz - 6.67 LCD Refresh in Hz - 59.3

74 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

Example Serial Output Sequence for the S1D13513 Sequence Register Data Contents 1 0448h 000Eh LCD serial clock divide 100MHz/15 2 0816h 00A3h LCD serial 24bit command I/F setting 3 081Ch 0016h Command 4 081Ch 083Fh Command 5 081Ch 0671h Command 6 081Ch 0C00h Command 7 081Ch 0210h Command 8 081Ch 0A4Ch Command 9 081Ch 0618h Command 10 081Ch 0ED0h Command 11 081Ch 0100h Command 12 081Ch 0980h Command 13 081Ch 0501h Command 14 081Ch 0D40h Command 15 081Ch 0300h Command 16 081Ch 0B00h Command 17 081Ch 0700h Command 18 081Ch 0F02h Command

Example Register Settings for the S1D13748 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] LCD1 Horizontal Total Register 53 429 REG[0042h] LCD1 Horizontal Display Period Register 159 320 REG[0044h] LCD1 Horizontal Display Period Start Position 33 42 Register REG[0046h] LCD1 Horizontal Pulse Register 10 11 REG[0048h] LCD1 Horizontal Pulse Start Position Register 0 1 REG[004Ah] LCD1 Vertical Total Register 261 262 REG[004Ch] LCD1 Vertical Display Period Resister 239 240 REG[004Eh] LCD1 Vertical Display Period Start Position 6 6 Register REG[0050h] LCD1 Vertical Pulse Register 2 3 REG[0052h] LCD1 Vertical Pulse Start Position Register 0 1 REG[0246h] Main1 Window Image Horizontal Size Register 319 320 REG[0248h] Main1 Window Image Vertical Size Register 279 280 PLL output frequency in MHz - 54 REG[0030h] LCD Interface Clock Setting Register 0506h 8 FPSHIFT in MHz - 6.75 LCD Refresh in Hz - 60.1

Connecting EPSON Display Controllers EPSON 75 to Casio LCD Panels (Rev 1.00) 7. CONNECTING TO THE CASIO COM57T5120

Example Serial Output Sequence for the S1D13748 Sequence Register Data Contents 1 0034h 0016h Command 2 0034h 083Fh Command 3 0034h 0671h Command 4 0034h 0C00h Command 5 0034h 0210h Command 6 0034h 0A4Ch Command 7 0034h 0618h Command 8 0034h 0ED0h Command 9 0034h 0100h Command 10 0034h 0980h Command 11 0034h 0501h Command 12 0034h 0D40h Command 13 0034h 0300h Command 14 0034h 0B00h Command 15 0034h 0700h Command 16 0034h 0F02h Command

76 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

8. CONNECTING TO THE CASIO COM65T6111

The Casio COM65T6111 TFT panel is compatible with the S1D13513, S1D13742 and S1D13748 display controllers. The following sections will provide connector details, pin mappings, and example register settings for these combinations.

8.1 COM65T6111 Pin Mapping

The COM65T6111 TFT panel uses a 45-pin connector with the following pin mapping.

COM65T6111 Pin Mapping Connector Pin# Pin Name Pin Description 1 VSS GND 2 CLK Dot clock 3 VSS GND 4 HSYNC Horizontal synchronous signal (Negative) 5 VSYNC Vertical synchronous signal (Negative) 6 VSS GND 7 TEST1 Connect to VSS 8 TEST2 Connect to VSS 9 D20 BLUE data signal (LSB) 10 D21 BLUE data signal 11 D22 BLUE data signal 12 D23 BLUE data signal 13 D24 BLUE data signal 14 D25 BLUE data signal (MSB) 15 VSS GND 16 TEST3 Connect to VSS 17 TEST4 Connect to VSS 18 D10 GREEN data signal (LSB) 19 D11 GREEN data signal 20 D12 GREEN data signal 21 D13 GREEN data signal 22 D14 GREEN data signal 23 D15 GREEN data signal (MSB) 24 VSS GND 25 TEST5 Connect to VSS 26 TEST6 Connect to VSS 27 D00 RED data signal (LSB) 28 D01 RED data signal 29 D02 RED data signal 30 D03 RED data signal 31 D04 RED data signal 32 D05 RED data signal (MSB) 33 VSS GND Horizontal reverse display control 34 RL (Lo: Reverse, Hi: Normal) 35 VDD Power supply for logic（+3.3V±0.3V） 36 VDD Power supply for logic（+3.3V±0.3V） 37 DISP Display control signal Lo:OFF, Hi:ON 38 DE Input data enable (Hi-active) Vertical reverse display control 39 UD (Lo: Normal, Hi: Reverse) 40 VSS GND 41 VBL Power supply for back light（+12V±1.2V） 42 VBL Power supply for back light（+12V±1.2V）

Connecting EPSON Display Controllers EPSON 77 to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

Connector Pin# Pin Name Pin Description Back light dimmer control pulse input 43 PDM (Lo: 0%(Back light off), Hi:100%) 44 VSS GND 45 VSS GND Note The recommended connector is a 04-6240-045-023-846+ from Kyocera elco.

78 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

8.2 Connection Examples

The information in this section provides connection examples for the S1D13513, S1D13742 and S1D13748 display controllers. Some display controllers are available in two packages. The connection information differs for each package and is listed separately.

In addition to the pin connections for the selected display controller, the COM65T6111 requires the following power supply.

VDD +3.3V(±0.3V) VBL +12V(±1.2V)

For VDD, select a voltage within the supportable range of the Display Controller.

For further details on the COM65T6111, such as power consumption and absolute maximum ratings, please contact your Casio representative.

8.2.1 Connecting the COM65T6111 to the S1D13513

The following diagram shows an example implementation of the COM65T6111 panel connected to the S1D13513. 3.3V COM65T6111 S1D13513

VDD HVDD2 RL

DISP PDM

DE FPDRDY D[27:25] (B) FPDAT[6:8]

D[24:22] (B) FPDAT[15:17] D[17:15] (G) FPDAT[3:5]

D[14:12] (G) FPDAT[12:14]

D[7:5] (R) FPDAT[0:2] D[4:2] (R) FPDAT[9:11]

HSYNC FPLINE

VSYNC FPFRAME CLK FPSHIFT

TEST[1:6]

UD VSS VSS

Connecting EPSON Display Controllers EPSON 79 to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

The following table provides a detailed pin listing for the required connections between the COM65T6111 and the S1D13513. Pin mappings are shown for both S1D13513 package types.

Connecting the COM65T6111 to the S1D13513 LCD LCD Panel S1D13513 Panel S1D13513 S1D13513 Connector LCD Panel Pin Description PBGA Pin QFP Pin# Pin Name Pin# Ball# Name 1 VSS GND - - VSS 2 CLK Dot clock 77 P8 FPSHIFT 3 VSS GND - - VSS 4 HSYNC Horizontal synchronous signal (Negative) 79 R8 FPLINE 5 VSYNC Vertical synchronous signal (Negative) 78 T8 FPFRAME 6 VSS GND - - VSS 7 TEST1 Connect to VSS - - VSS 8 TEST2 Connect to VSS - - VSS 9 D20 BLUE data signal (LSB) 53 N4 FPDAT17 10 D21 BLUE data signal 54 P4 FPDAT16 11 D22 BLUE data signal 55 T2 FPDAT15 12 D23 BLUE data signal 64 R6 FPDAT8 13 D24 BLUE data signal 67 K6 FPDAT7 14 D25 BLUE data signal (MSB) 68 M6 FPDAT6 15 VSS GND - - VSS 16 TEST3 Connect to VSS - - VSS 17 TEST4 Connect to VSS - - VSS 18 D10 GREEN data signal (LSB) 56 R4 FPDAT14 19 D11 GREEN data signal 59 T4 FPDAT13 20 D12 GREEN data signal 60 T5 FPDAT12 21 D13 GREEN data signal 69 L7 FPDAT5 22 D14 GREEN data signal 70 P7 FPDAT4 23 D15 GREEN data signal (MSB) 71 R7 FPDAT3 24 VSS GND - - VSS 25 TEST5 Connect to VSS - - VSS 26 TEST6 Connect to VSS - - VSS 27 D00 RED data signal (LSB) 61 N5 FPDAT11 28 D01 RED data signal 62 M5 FPDAT10 29 D02 RED data signal 63 P6 FPDAT9 30 D03 RED data signal 72 T7 FPDAT2 31 D04 RED data signal 73 N7 FPDAT1 32 D05 RED data signal (MSB) 74 M7 FPDAT0 33 VSS GND - - VSS Horizontal reverse display control 34 RL 57,65,75 L5,L8,T6 HVDD2 (Lo: Reverse, Hi: Normal) 35 VDD Power supply for logic（+3.3V±0.3V） 57,65,75 L5,L8,T6 HVDD2 36 VDD Power supply for logic（+3.3V±0.3V） 57,65,75 L5,L8,T6 HVDD2 37 DISP Display control signal Lo:OFF, Hi:ON 57,65,75 L5,L8,T6 HVDD2 38 DE Input data enable (Hi-active) 80 M8 FPDRDY Vertical reverse display control 39 UD - - VSS (Lo: Normal, Hi: Reverse) 40 VSS GND - - VSS 41 VBL Power supply for back light（+12V±1.2V） - - - 42 VBL Power supply for back light（+12V±1.2V） - - - Back light dimmer control pulse input 43 PDM 57,65,75 L5,L8,T6 HVDD2 (Lo: 0%(Back light off), Hi:100%) 44 VSS GND - - VSS 45 VSS GND - - VSS

80 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

Connecting EPSON Display Controllers EPSON 81 to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

8.2.2 Connecting the COM65T6111 to the S1D13742

The following diagram shows an example implementation of the COM65T6111 panel connected to the S1D13742.

3.3V COM65T6111 S1D13742

VDD PIOVDD RL

DISP

PDM

DE DE

D[27:22] (B) VD[5:0]

D[17:12] (G) VD[11:6] D[7:2] (R) VD[17:12]

HSYNC HS VS VSYNC CLK PCLK

TEST[1:6]

VSS VSS

82 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

The following table provides a detailed pin listing for the required connections between the COM65T6111 and the S1D13742.

Connecting the COM65T6111 to the S1D13742 LCD S1D13742 LCD Panel S1D13742 S1D13742 Panel LCD Panel Pin Description FCBGA Connector Pin# QFP Pin# Pin Name Pin Name Ball# 1 VSS GND - - VSS 2 CLK Dot clock 11 D11 PCLK 3 VSS GND - - VSS Horizontal synchronous signal 4 HSYNC 9 D9 HS (Negative) 5 VSYNC Vertical synchronous signal (Negative) 10 D10 VS 6 VSS GND - - VSS 7 TEST1 Connect to VSS - - VSS 8 TEST2 Connect to VSS - - VSS 9 D20 BLUE data signal (LSB) 45 L9 VD0 10 D21 BLUE data signal 49 L8 VD1 11 D22 BLUE data signal 54 L7 VD2 12 D23 BLUE data signal 59 L6 VD3 13 D24 BLUE data signal 62 L5 VD4 14 D25 BLUE data signal (MSB) 65 L4 VD5 15 VSS GND - - VSS 16 TEST3 Connect to VSS - - VSS 17 TEST4 Connect to VSS - - VSS 18 D10 GREEN data signal (LSB) 66 L3 VD6 19 D11 GREEN data signal 42 K10 VD7 20 D12 GREEN data signal 44 K9 VD8 21 D13 GREEN data signal 48 K8 VD9 22 D14 GREEN data signal 51 K7 VD10 23 D15 GREEN data signal (MSB) 58 K6 VD11 24 VSS GND - - VSS 25 TEST5 Connect to VSS - - VSS 26 TEST6 Connect to VSS - - VSS 27 D00 RED data signal (LSB) 61 K5 VD12 28 D01 RED data signal 64 K4 VD13 29 D02 RED data signal 30 J11 VD14 30 D03 RED data signal 29 J10 VD15 31 D04 RED data signal 43 J9 VD16 32 D05 RED data signal (MSB) 47 J8 VD17 33 VSS GND - - VSS 4,17,20, Horizontal reverse display control E8,G4,H5 34 RL 33,38,52,5 PIOVDD (Lo: Reverse, Hi: Normal) ,H7 5,69 4,17,20, E8,G4,H5 35 VDD Power supply for logic（+3.3V±0.3V） 33,38,52,5 PIOVDD ,H7 5,69 4,17,20, E8,G4,H5 36 VDD Power supply for logic（+3.3V±0.3V） 33,38,52,5 PIOVDD ,H7 5,69 4,17,20, E8,G4,H5 37 DISP Display control signal Lo:OFF, Hi:ON 33,38,52,5 PIOVDD ,H7 5,69 38 DE Input data enable (Hi-active) 8 C11 DE 39 UD Vertical reverse display control - - VSS

Connecting EPSON Display Controllers EPSON 83 to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

LCD S1D13742 LCD Panel S1D13742 S1D13742 Panel LCD Panel Pin Description FCBGA Connector Pin# QFP Pin# Pin Name Pin Name Ball# (Lo: Normal, Hi: Reverse) 40 VSS GND - - VSS Power supply for back light 41 VBL - - - （+12V±1.2V） Power supply for back light 42 VBL - - - （+12V±1.2V） 4,17,20, Back light dimmer control pulse input E8,G4,H5 43 PDM 33,38,52,5 PIOVDD (Lo: 0%(Back light off), Hi:100%) ,H7 5,69 44 VSS GND - - VSS 45 VSS GND - - VSS Note Allocation of VSS pin for each packages are as follows. QFP: 5,7,18,21,32,34,39,41,53,56,68,70,78,90,103,105,112,116,119,129,135,144 FCBGA: C5,C6,E5,E6,E7,F4,F5,F6,F7,G5,G6

84 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

8.2.3 Connecting the COM65T6111 to the S1D13748

The following diagram shows an example implementation of the COM65T6111 panel connected to the S1D13748.

3.3V COM65T6111 S1D13748

VDD HVDD2 RL

DISP

PDM

DE FPDRDY

D[27:25] (B) FPDAT[6:8]

D[24:22] (B) FPDAT[15:17] D[17:15] (G) FPDAT[3:5]

D[14:12] (G) FPDAT[12:14] D[7:5] (R) FPDAT[0:2]

D[4:2] (R) FPDAT[9:11]

HSYNC FPLINE VSYNC FPFRAME

FPSHIFT CLK TEST[1:6]

VSS VSS

Connecting EPSON Display Controllers EPSON 85 to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

The following table provides a detailed pin listing for the required connections between the COM65T6111 and the S1D13748.

Connecting the COM65T6111 to the S1D13748 LCD LCD S1D13748 Panel Panel S1D13748 S1D13748 LCD Panel Pin Description PFBGA Connector Pin QFP Pin# Pin Name Ball# Pin# Name 1 VSS GND - - VSS 2 CLK Dot clock 75 J11 FPSHIFT 3 VSS GND - - VSS 4 HSYNC Horizontal synchronous signal (Negative) 77 H10 FPLINE 5 VSYNC Vertical synchronous signal (Negative) 76 J10 FPFRAME 6 VSS GND - - VSS 7 TEST1 Connect to VSS - - VSS 8 TEST2 Connect to VSS - - VSS 9 D20 BLUE data signal (LSB) 72 J9 FPDAT17 10 D21 BLUE data signal 71 K10 FPDAT16 11 D22 BLUE data signal 70 L10 FPDAT15 12 D23 BLUE data signal 60 K7 FPDAT8 13 D24 BLUE data signal 59 J7 FPDAT7 14 D25 BLUE data signal (MSB) 58 L7 FPDAT6 15 VSS GND - - VSS 16 TEST3 Connect to VSS - - VSS 17 TEST4 Connect to VSS - - VSS 18 D10 GREEN data signal (LSB) 69 H8 FPDAT14 19 D11 GREEN data signal 68 K9 FPDAT13 20 D12 GREEN data signal 64 L9 FPDAT12 21 D13 GREEN data signal 54 L6 FPDAT5 22 D14 GREEN data signal 53 J6 FPDAT4 23 D15 GREEN data signal (MSB) 52 H6 FPDAT3 24 VSS GND - - VSS 25 TEST5 Connect to VSS - - VSS 26 TEST6 Connect to VSS - - VSS 27 D00 RED data signal (LSB) 63 L8 FPDAT11 28 D01 RED data signal 62 J8 FPDAT10 29 D02 RED data signal 61 K8 FPDAT9 30 D03 RED data signal 51 K5 FPDAT2 31 D04 RED data signal 50 L5 FPDAT1 32 D05 RED data signal (MSB) 49 J5 FPDAT0 33 VSS GND - - VSS 19,26,35, E8,F4,H7,J Horizontal reverse display control 40, 46,55, 34 RL 4 PIOVDD (Lo: Reverse, Hi: Normal) 67,73,83,

87 E8,F4,H7,J 19,26,35, 4 40, 46,55, 35 VDD Power supply for logic（+3.3V±0.3V） PIOVDD 67,73,83,

19,26,35, E8,F4,H7,J 40, 46,55, 36 VDD Power supply for logic（+3.3V±0.3V） 4 PIOVDD 67,73,83,

87 19,26,35, E8,F4,H7,J 37 DISP Display control signal Lo:OFF, Hi:ON PIOVDD 40, 46,55, 4

86 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

67,73,83, 67,73,83, 87 38 DE Input data enable (Hi-active) 78 G7 FPDRDY Vertical reverse display control 39 UD - - VSS (Lo: Normal, Hi: Reverse) 40 VSS GND - - VSS 41 VBL Power supply for back light（+12V±1.2V） - - - 42 VBL Power supply for back light（+12V±1.2V） - - - 19,26,35, E8,F4,H7,J Back light dimmer control pulse input 40, 46,55, 43 PDM 4 PIOVDD (Lo: 0%(Back light off), Hi:100%) 67,73,83,

87 44 VSS GND - - VSS 45 VSS GND - - VSS Note Allocation of VSS pin for each packages are as follows. PFBGA: B1,C4,C8,D10,E6,F2,F8,G4,K6,K11 QFP: 6,13,20,31,36,39,47,56,66,74,82,91,97,102,108,115,129,138,144

Connecting EPSON Display Controllers EPSON 87 to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

8.3 Example Register Settings

In addition to the pin connections, the S1D13513/S1D13742/S1D13748 internal registers must be con figured appropriately for the COM65T6111 LCD panel. The following tables provide example settings f or each display controller. However, these values are for reference only and may differ according to ea ch specific implementation.

Also included in the table is an example clock configuration designed to achieve a typical LCD refresh.

Example Register Settings for the S1D13513 Parameter Register Index and Name Register Setting Value (see Note) REG[0800h] LCD Panel Type Select Register 0200h - REG[0802h] LCD Horizontal Total Register 799 800 REG[0804h] LCD Horizontal Display Period Register 319 640 REG[0806h] LCD Horizontal Display Period Start Position 143 144 Register REG[0808h] LCD Horizontal Pulse Width 29 30 REG[080Ah] LCD Horizontal Pulse Start Position 0 0 REG[080Ch] LCD Vertical Total Register 524 525 REG[080Eh] LCD Vertical Display Period Resister 479 480 REG[0810h] LCD Vertical Display Period Start Position 35 35 Register REG[0812h] LCD Vertical Pulse Width 2 3 REG[0814h] LCD Vertical Pulse Start Position 0 0 PLL2 output frequency in MHz - 100 REG[0446h] LCD Clock Control Register 3t 4 FPSHIFT in MHz - 25.0 LCD Refresh in Hz - 59.5

88 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 8. CONNECTING TO THE CASIO COM65T6111

Example Register Settings for the S1D13742 Parameter Value Register Index and Name Register Setting (see Note) REG[14h] Panel Type Register 00h - REG[16h] Horizontal Display Width Register 80 640 REG[18h] Horizontal Non-Display Period Register 240 240 REG[1Ah][1Ch] Vertical Display Height Registers 480 480 REG[1Eh] Vertical Non-Display Period Register 45 45 REG[20h] HS Pulse Width Register 30 30 REG[22h] HS Pulse Start Position Register 0 30 30 REG[24h] VS Pulse Width Register 3 3 REG[26h] VS Pulse Start Position Register 0 10 10 PLL frequency in MHz - 50 REG[12h] Pixel Clock Configuration Register 09h 2 FPSHIFT in MHz - 25 LCD Refresh in Hz - 54.1

Example Register Settings for the S1D13748 Parameter Value Register Index and Name Register Setting (see Note) REG[0040h] LCD1 Horizontal Total Register 99 800 REG[0042h] LCD1 Horizontal Display Period Register 319 640 REG[0044h] LCD1 Horizontal Display Period Start Position 135 144 Register REG[0046h] LCD1 Horizontal Pulse Register 29 30 REG[0048h] LCD1 Horizontal Pulse Start Position Register 0 1 REG[004Ah] LCD1 Vertical Total Register 524 525 REG[004Ch] LCD1 Vertical Display Period Resister 479 480 REG[004Eh] LCD1 Vertical Display Period Start Position 35 35 Register REG[0050h] LCD1 Vertical Pulse Register 2 3 REG[0052h] LCD1 Vertical Pulse Start Position Register 0 1 REG[0246h] Main1 Window Image Horizontal Size Register 639 640 REG[0248h] Main1 Window Image Vertical Size Register 479 480 PLL output frequency in MHz - 50 REG[0030h] LCD Interface Clock Setting Register 0500h 2 FPSHIFT in MHz - 25 LCD Refresh in Hz - 59.5

Connecting EPSON Display Controllers EPSON 89 to Casio LCD Panels (Rev 1.00) 9. CONNECTING TO THE CASIO COM80T8102

9. CONNECTING TO THE CASIO COM80T8102

The Casio COM80T8102 TFT panel is compatible with the S1D13513 display controller. The following sections will provide connector details, pin mappings, and example register settings.

9.1 COM80T8102 Pin Mapping

The COM80T8102 TFT panel uses a 32-pin connector for the LCD signals and a 2-pin connector for the power supply. The following pin mapping applies.

COM80T8102 Pin Mapping (Signal Connector) Connector Pin# Pin Name Pin Description 1 VSS GND 2 CLK CLK 3 HSYNC HSYNC 4 VSYNC VSYNC 5 VSS GND 6 D20 Red D02 7 D21 Red D03 8 D22 Red D04 9 D23 Red D05 10 D24 Red D06 11 D25 Red D07 12 VSS GND 13 D10 Green D12 14 D11 Green D13 15 D12 Green D14 16 D13 Green D15 17 D14 Green D16 18 D15 Green D17 19 VSS GND 20 D00 Blue D02 21 D01 Blue D03 22 D02 Blue D04 23 D03 Blue D05 24 D04 Blue D06 25 D05 Blue D07 26 VSS GND 27 DE DE Back light pulse input 28 PDM Low: 100% bright, High: 0% bright (back light off) 29 NC - Horizontal reverse display control 30 RL Low: Reverse, High: Normal Vertical reverse display control 31 UD Low: Reverse, High: Normal 32 VSS GND

Note The recommended connector is a Molex 52559-3252. The connector is a 0.5mm pitch 32-pin FPC connector (16.5mm x 0.3mm gold plate).

90 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 9. CONNECTING TO THE CASIO COM80T8102

COM80T8102 Pin Mapping (Power Supply Connector) Connector Pin# Pin Name Pin Description 1 VDD +12.0V (±1.2V) 2 GND GND

Note The recommended connectors are: Mounting Side: B2B-PH-SM4TBT(LF) Cable Side: PHR-2 (housing) and SPH-002T-P0.5 or SPH-004T-P0.5 (contact)

9.2 Connection Examples

The information in this section provides a connection example for the S1D13513 display controller. The S1D13513 display controller is available in two packages. The connection information differs for each package and is listed separately.

In addition to the pin connections for the selected display controller, the COM80T8102 requires the following power supplies.

VDD +12.0V(±1.2V)

The COM80T8102 generates 3.3V logic voltage internally. Therefore, the display controller VDD must be configured within the range of 3.3V±0.3V.

For further details on the COM80T8102, such as power consumption and absolute maximum ratings, please contact your Casio representative.

Connecting EPSON Display Controllers EPSON 91 to Casio LCD Panels (Rev 1.00) 9. CONNECTING TO THE CASIO COM80T8102

9.2.1 Connecting the COM80T8102 to the S1D13513

The following diagram shows an example implementation of the COM80T8102 panel connected to the S1D13513.

3.3V COM80T8102 S1D13513

RL HVDD2 UD

DE FPDRDY

D[25:23] (R) FPDAT[0:2] D[22:20] (R) FPDAT[9:11] D[15:13] (G) FPDAT[3:5] D[12:10] (G) FPDAT[12:14] D[5:3] (B) FPDAT[6:8] D[2:0] (B) FPDAT[15:17]

HSYNC FPLINE VSYNC FPFRAM CLK FPSHIFT

PDM

VSS VSS

92 EPSON Connecting EPSON Display Controllers to Casio LCD Panels (Rev 1.00) 9. CONNECTING TO THE CASIO COM80T8102

The following table provides a detailed pin listing for the required connections between the COM80T8102 and the S1D13513. Pin mappings are shown for both S1D13513 package types.

Connecting the COM80T8102 to the S1D13513 (Signal Connector) LCD Panel LCD Panel S1D13513 S1D13513 S1D13513 LCD Panel Pin Description Connector Pin# Pin Name QFP Pin# PBGA Ball# Pin Name 1 VSS GND - - VSS 2 CLK CLK 75 J11 FPSHIFT 3 HSYNC HSYNC 77 H10 FPLINE 4 VSYNC VSYNC 76 J10 FPFRAME 5 VSS GND - - VSS 6 D20 Red D02 63 L8 FPDAT11 7 D21 Red D03 62 J8 FPDAT10 8 D22 Red D04 61 K8 FPDAT9 9 D23 Red D05 51 K5 FPDAT2 10 D24 Red D06 50 L5 FPDAT1 11 D25 Red D07 49 J5 FPDAT0 12 VSS GND - - VSS 13 D10 Green D12 69 H8 FPDAT14 14 D11 Green D13 68 K9 FPDAT13 15 D12 Green D14 64 L9 FPDAT12 16 D13 Green D15 54 L6 FPDAT5 17 D14 Green D16 53 J6 FPDAT4 18 D15 Green D17 52 H6 FPDAT3 19 VSS GND - - VSS 20 D00 Blue D02 72 J9 FPDAT17 21 D01 Blue D03 71 K10 FPDAT16 22 D02 Blue D04 70 L10 FPDAT15 23 D03 Blue D05 60 K7 FPDAT8 24 D04 Blue D06 59 J7 FPDAT7 25 D05 Blue D07 58 L7 FPDAT6 26 VSS GND VSS 27 DE DE 78 G7 FPDRDY Back light pulse input 28 PDM Low: 100% bright, High: 0% - - VSS bright (back light off) 29 NC - - - - Horizontal reverse display 30 RL contro - - HVDD2 Low: Reverse, High: Normal l Vertical reverse display control 31 UD - - HVDD2 Low: Reverse, High: Normal 32 VSS GND - - VSS

Connecting the COM80T8102 to the S1D13513 (Power Supply Connector) LCD Panel LCD Panel LCD Panel Pin S1D13513 S1D13513 S1D13513 Connector Pin# Pin Name Description QFP Pin# PBGA Ball# Pin Name 1 VDD +12.0V (±1.2V) - - - 2 GND GND - - VSS

Connecting EPSON Display Controllers EPSON 93 to Casio LCD Panels (Rev 1.00) 9. CONNECTING TO THE CASIO COM80T8102

9.3 Example Register Settings

In addition to the pin connections, the S1D13513 internal registers must be configured appropriately for the COM80T8102 LCD panel. The following tables provide example settings for each display controller. However, these values are for reference only and may differ according to each specific implementation. For details on configuring the S1D13513 register values, see the S1D13513 Hardware Functional Specification, document number X78B-A-001-xx.

Also included in the table is an example clock configuration designed to achieve a typical LCD refresh.

Example Register Settings for the S1D13513 Parameter Value Register Index and Name Register Setting (see Note) REG[0800h] LCD Panel Type Select Register 0280h - REG[0802h] LCD Horizontal Total Register 849 850 REG[0804h] LCD Horizontal Display Period Register 319 640 REG[0806h] LCD Horizontal Display Period Start Position Register 140 141 REG[0808h] LCD Horizontal Pulse Width 95 96 REG[080Ah] LCD Horizontal Pulse Start Position 0 0 REG[080Ch] LCD Vertical Total Register 514 515 REG[080Eh] LCD Vertical Display Period Resister 479 480 REG[0810h] LCD Vertical Display Period Start Position Register 34 34 REG[0812h] LCD Vertical Pulse Width 16 16 REG[0814h] LCD Vertical Pulse Start Position 0 0

PLL2 output frequency in MHz - 100 REG[0446h] LCD Clock Control Register 3 4 FPSHIFT in MHz - 25 LCD Refresh in Hz - 57.1

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Document Code: 411572501 First issue September 2008 in JAPAN Revised issue March 2009 in JAPAN