Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

applied sciences

Article Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

Kaipei Liu 1, Qing Huai 1,* , Liang Qin 1,* , Shu Zhu 1, Xiaobing Liao 1, Yuye Li 1 and Hua Ding 2

1 School of Electrical Engineering, Wuhan University, Wuhan 430072, China; [email protected] (K.L.); [email protected] (S.Z.); [email protected] (X.L.); [email protected] (Y.L.) 2 State Grid Energy Conservation Service Co., Ltd., Beijing 100052, China; [email protected] * Correspondence: [email protected] (Q.H.); [email protected] (L.Q.); Tel.: +86-1347-683-0019 (Q.H.); +86-1898-617-2977 (L.Q.) Received: 20 March 2019; Accepted: 18 April 2019; Published: 22 April 2019

Abstract: The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Specifically, the EFCLC consists of fault current-limiting inductance LFCL and energy dissipation resistance RFCL in parallel with surge arrestor. LFCL reduces the fault current rising speed, together with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, LFCL will be bypassed via parallel-connected thyristors after blocking converter to prevent the effect on fault interruption speed. RFCL shares the stress on energy absorption device (metal oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisfied effortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its effectiveness is verified by simulation in RT-LAB and MATLAB software platforms.

Keywords: fault current-limiting circuit; DC circuit breaker; MMC-HVDC; fault protection

1. Introduction Fault vulnerability and protection immaturity constrain the development of the voltage source converter-based high-voltage direct current (VSC-HVDC) system, especially in terms of DC side fault at high power levels. Thus, reliability has become an important challenge in multilevel converter-based (MMC)-HVDC with long-distance transmission lines [1,2]. The lack of a perfect fault isolation scheme and mature DC switchgear products are the primary issues [3]. However, the VSC-HVDC system has attracted worldwide attention and research interests due to its advantages with respect to control ﬂexibility and interconnection feasibility. A related analysis of DC faults has been performed to enhance its fault ride through (FRT) ability under DC fault in the VSC-HVDC system [4,5]. An overview of HVDC system protection mentions that the major limitation in development of VSC-HVDC is the inability to limit fault current, given the limitation of the DC circuit breaker (DCCB) in interruption capability and operation speed [6]. Moreover, limiting fault current can protect the semiconductor device from excessive electrical pressure, particularly insulated gate bipolar thyristor (IGBT) and

Appl. Sci. 2019, 9, 1661; doi:10.3390/app9081661 www.mdpi.com/journal/applsci Appl. Sci. 2019, 9, 1661 2 of 26 freewheeling diode in a converter sub-module (SM). Furthermore, restriction of fault current can provide additional time for fault detection and operation delay. Therefore, limiting fault current development and propagation in the VSC-HVDC and multi-terminal HVDC (MTDC) systems is essential. State-of-the-art fault current-limiting (FCL) techniques can be classified into improved SM topologies [7–12], auxiliary FCL circuits (FCLC) [13–20], and fault current limiters [21–25]. The SM topology has been modified to reinforce its fault handling ability, because the classical half-bridge SM (HBSM) is likely to be destroyed under overcurrent if no proper protection scheme is applied, even if insulated gate bipolar translators (IGBTs)are blocked in a timely fashion [26]. Thus, several innovative improvements, including full-bridge SM (FBSM) [7,8], clamp double SM (CDSM) [9], and hybrid SM, which combines FBSM and HBSM, have been conceived in the SM topology design [10]. Although the FBSM solution can ride through faults without blocking the converter, given its ability to output bipolar voltage, regardless of arm current direction [9], the doubled number and on-state loss of semiconductors are their main drawbacks. A CDSM solution only has 50% higher semiconduction than the HBSM to extinguish the DC arc by blocking IGBTs under nonpermanent fault [10]. However, the MMC converter has generally been regarded as the most appropriate static synchronous compensator to support alternating current (AC) grids in DC pole-to-pole fault scenarios [11]. Thus, enhancing the FRT capability without blocking the converter is crucial. A hybrid MMC topology requires each arm to have the same amount of FBSM and HBSM by considering their nature [10,12]. Thus, the cost of semiconductor devices and conduction losses have been reduced in comparison with those in the FBSM. However, further research on control strategies in terms of dynamic characteristics and SM voltage balancing is required [2]. Overall, control complexity and high cost are the weaknesses of SM topology-based solutions. Another FCL technology relies on an auxiliary circuit, which consistently includes energy dissipation resistance and an FCL reactor. For example, a hybrid current-limiting circuit (Figure1a) has been designed to restrain the DC line fault current in the MTDC system [13], which is settled at the end of the DC line between the DCCB and DC converter ports. The energy dissipation resistance Rr is equipped to share the stress on energy absorption element in the DCCB, and the fault current interruption speed is accelerated. However, the tradeoff between FCL performance and the extra cost of the resistor must be considered. In addition, a bridge-type FCLC is composed of a DC voltage source, a DC reactor, and four groups of diodes (Figure1b) [ 14]. Reference [14] shows that the DC biased current given by the DC power supply is considered to be the threshold value of the DC fault current in order to automatically activate the FCLC itself. The main advantage is that the DC reactor can be bypassed in its normal state and after turning off the main breaker of the DCCB. In addition, the idea of the FCLC is also reflected in the form of an SM [15], which is inserted into each arm in series. However, the FCL-SM can only limit a unidirectional fault current, and the surge voltage across FCL-SM must be given further attention. Moreover, an enhanced reverse blocking SM (ERBSM) topology has been proposed to extinguish a fault current arc by inverse voltage [16]. Control complexity is reduced because the ERBSM adopts the same modulation strategy. In Reference [17], thyristors have better performance than diode in withstanding overcurrent (Figure1e), and the overcurrent pressure on freewheeling diode has been relieved via the shunting effect of a single-thyristor switch scheme (STSS) [17–19]. Although the STSS can protect semiconductor devices, the AC grid current fed into the DC side cannot be prevented. Thus, the double-thyristor switch scheme (DTSS) has been introduced to protect the DC overhead line (Figure1f), which can eliminate the freewheeling e ffect of diodes, and the DC line fault current can freely decay to zero [20]. Then, the DC fault is transformed into an AC short circuit fault that can be cleared by switching off the thyristor. However, the high dv/dt across thyritors and the sharing current effect of bypassed diodes are ignored in the DTSS solution. To solve this problem, double-thyristor switches are combined and connected at the AC port of the converter instead of across the diode in the SM to isolate the AC side from the DC side when a fault occurs. Moreover, the feasibility of such a scheme has been verified via a case study that considers STSS and DTSS in a classical VSC-HVDC system, as well as MMC-HVDC. Appl. Sci. 2019, 9, 1661 3 of 26

The superconducting fault limiter (SFCL) has attracted considerable attention because its nonlinear impedance characteristics can be used to limit the increase in fault current rate to provide a necessary time for relay protection. The SFCL can mainly be divided into resistive-SFCL (R-SFCL) and inductive-SFCL (I-SFCL) [21]. The study concludes that R-SFCL can constrain the amplitude of fault current, but reduces the increase in fault current rate differently, and I-SFCL can delay the increase in fault rate significantly [22]. Related research has been performed on the basis of the unique characteristics in SFCL. For example, R-SFCL has been thoroughly investigated on the basis of the current-limiting capability comparison and parameter influence, thus indicating that the use of R-SFCL is suggested for real applications, provided that it is sufficiently sensitive to develop an adequate quenching resistance [23]. Hybrid DCCB has been equipped with SFCL in the main line to limit the fault current until a fault is completely interrupted [24,25]. In addition, the superconducting magnetic energy storage technique has been adopted to limit fault current, which is achieved via a power transform between the power system and superconducting coil [26]. A rapid limitation can be realized when controlled FCL (molded as pancakes) is isolated to maintain its dynamic stability. In contrast to the AC line fault current, the fault current under DC short circuit fault in the MMC-HVDC system does not have a natural zero crossing. Thus, applying DCCB has been limited given its high cost and technical immaturity [27]. Mechanical breakers can limit fault current in a few tens of milliseconds but cannot satisfy the demand in the VSC-HVDC system protection [28]. Although semiconductor circuit breakers have a large on-state loss, the operation speed requirement is satisfied. The hybrid HVDC breaker has been proposed and investigated in References [29–31] to eliminate on-state power loss and limit fault current within several milliseconds. Parametric analysis of hybrid DCCB has also been conducted thoroughly considering the influence of the main parameters on the system and the breaker design [32]. Moreover, an interlink DCCB has been proposed to maintain the fault current interruption ability with a few components to reduce the overall cost of the DCCB in the DC grid [33]. In Reference [24], varying the DC current is considered an underdamping decay process, given the small resistance in the fault circuit. Thus, the fault current-limiting inductance LFCL cannot change the damping characteristics which refer to criterion R < 2 √L/C. That is, LFCL can only limit DC fault current, but not relieve the overcurrent effect in the converter and AC sides [24]. The SFCL has not been applied extensively in real projects because of its high cost and lack of maturity, particularly with respect to SFCL recovery after being activated. The main advantage of the SFCL is that it does not influence the dynamic response under normal state. The direct installation of the DC reactor affects the system’s normal operation and DCCB isolation speed [34]. Therefore, the present study proposes an enhanced fault current-limiting circuit (EFCLC) that primarily consists of energy dissipation resistance, limiting reactor, surge arrester, and semiconductor switches on the basis of existing works. The EFCLC aims to limit fault current through converter arms and DC line before the DCCB operates, thereby decreasing the peak current for fault interruption and reducing overcurrent effect on converter arms. Moreover, the required DCCB capability could be reduced, given limited fault current with EFCLC and more time is saved for fault detection, since fault current rising speed is more or less restricted. The remainder of this paper is organized as follows. Section2 thoroughly analyzes DC fault current on the basis of theoretical calculation and simulation verification. Section3 presents the topology and working principle of EFCLC. Section4 performs the parametric design study of EFCLC. Section5 further investigates the proposed scheme with EFCLC in terms of FCL ability and cost. Finally, Section6 summarizes the conclusion and future scope.

2. DC Fault Current Analysis

2.1. Test System Introduction The scheme of the MMC-HVDC system can be categorized into monopolar and bipolar symmetrical wiring systems (Figure1). The monopolar symmetrical HVDC system is also known as the pseudo Appl. Sci. 2019, 9, 1661 4 of 26

Appl.bipolar Sci. 2019 HVDC, 9, x system, which typically adopts a cable as a DC line. However, a real bipolar HVDC4 of 26 system is commonly applied in the HVDC transmission system with a high-capacity and overhead DC bipolarline. The HVDC main disystemﬀerence is commonly between the applied two schemes in the HVDC lies in operation transmission mode. system Bipolar with systems a high-capacity can work andunder overhead both monopolar DC line. The mode main and difference bipolar mode. between Namely, the two the schemes power transmission lies in operation of the mode. positive Bipolar pole systemsoverhead can line work and under negative both pole monopolar overhead mode line is an independent.d bipolar mode. Therefore, Namely, bipolar the power systems transmission can work ofduring the positive fault by pole transferring overhead power line and through negative healthy pole overhead line (monopolar line is independent. mode). In contrast, Therefore, monopolar bipolar systems cannotcan work maintain during power fault by transmission transferring under power fault, through since theyhealthy only line operate (monopolar under monopolar mode). In contrast,mode. Hence, monopolar the bipolar systems system cannot demonstrates maintain advantagespower transmission in terms of under power fault, supply since reliability they only and operateFRT capability. under monopolar mode. Hence, the bipolar system demonstrates advantages in terms of power supply reliability and FRT capability. Positive pole cable

MMC Negative pole cable MMC

(a) Positive pole overhead line MMC MMC

Metallic return

MMC MMC Negative pole overhead line

(b)

Figure 1. Diagram ofof thethe modularmodular multilevel multilevel converter-based converter-based high-voltage high-voltage direct direct current current system system in (ina) (monopolara) monopolar symmetrical symmetrical wiring wiring and and (b) ( bipolarb) bipolar symmetrical symmetrical wiring. wiring.

The MMC-HVDC system mainly consists of modular multilevel converter stations and DC line parts. The topology structure ofof MMC,MMC, whichwhich includesincludes three three converter converter units, units, is is displayed displayed in in Figure Figure2.

2.Each Each unit unit involves involves upper upper and and lower lower bridge bridge arms arms that that areare connectedconnected withwith the bridge arm reactor reactor 𝐿L0.. The SMsSMs areare connected connected in in series series in everyin every bridge bridge arm, arm, which which consists consists of two of switches, two switches, namely, namely,T1 and T𝑇2 (IGBT);and 𝑇 (IGBT); anti-parallel anti-parallel connected connected diodes, diodes, namely, namely,D1 and D𝐷2; andand energy𝐷; and storageenergy capacitorstorage capacitorC0. The DC𝐶. Thevoltage DC isvoltage maintained is maintained by switching by switchingT1 and T2 𝑇on and o𝑇ff in on every and off SM in tripped every bySM a tripped control signal.by a control If the signal.amount If of the SMs amount in each ofconverter SMs in each unit converter is 2N, then unit it hasis 2N, N switched-onthen it has N and switched-on N switched-o andff NSMs switched- during offnormal SMs operation.during normal The DC operat sideion. voltage The UDCDC sideis equal voltage to the 𝑈 sum is of equal the switched-on to the sum SMof the voltage switched-onU0. The SMmain voltage modulation 𝑈. The modes main are modulation divided into modes pulse are width divided modulation into pulse and width nearest modulation level modulation. and nearest The levelconverter modulation. stations The are blockedconverter by stations turning are off blockedIGBTs in by all turning SMs given off IGBTs the local in all overcurrent SMs given protection the local whenovercurrent a current protection reaches awhen threshold a current value reaches (normally a threshold twice the value value (normally of the nominal twice current). the value of the nominal current). Appl. Sci. 2019, 9, 1661 5 of 26 Appl. Sci. 2019, 9, x 5 of 26

FigureFigure 2. TopologyTopology structure of the MMC.

2.2. 2.2. DCDC FaultFault AnalysisAnalysis ofof thethe TestTest System System InIn the monopolar MMC-HVDC system, the the DC DC line line is typically composed of cables because because the faultfault possibilitypossibility is is considered considered much much lower lower in cables in cables than inthan overhead in overhead lines [35 lines]. However, [35]. However, an overhead an overheadline is typically line adoptedis typically in the adopted bipolar system,in the bipolar especially system, in long-distance especially power in long-distance transmission power with a transmissionhigh capacity. with Given a thathigh an capacity. overhead Given line is that likely an to overhead be aﬀected line by is a shortlikely circuit, to be groundedaffected by fault, a short and circuit,nonpermanent grounded fault, fault, analyzing and nonper the faultmanent characteristics fault, analyzing for protection the fault relayingcharacteristics is necessary. for protection The DC relayingline faults is arenecessary. mainly classiﬁedThe DC line into faults a single are pole-to-groundmainly classified fault, into pole-to-pole a single pole-to-ground short-circuit fault, fault (PPF),pole- to-poleand line short-circuit disconnection. fault The (PPF), PPF isand regarded line disconnection. as a serious faultThe consideringPPF is regarded an extremely as a serious high fault consideringcurrent within an aextremely few milliseconds high fault after current fault occurrence.within a few In milliseconds Figure2, the after MMC-HVDC fault occurrence. scheme indicatesIn Figure 2,that the the MMC-HVDC single pole-to-ground scheme indicates fault in that the bipolarthe single system pole-to-ground can be equivalent fault in to the the bipolar PPF given system bipolar can besystem’s equivalent metallic to the return PPF given is connected bipolar tosystem’s ground. meta Therefore,llic return the is PPFconnected is selected to ground. to be investigated Therefore, the in PPFthis study,is selected especially to be ininvestigated terms of fault in this current. study, Fault especially current in propagation terms of fa canult becurrent. segmented Fault intocurrent SM propagationcapacitor discharging can be beforesegmented blocking into IGBT, SM decayedcapacito freewheelingr discharging current, before and blocking AC gird IGBT, in-feed decayed current freewheelingafter blocking current, IGBT. Before and AC blocking gird in-feed IGBT, thecurrent discharging after blocking capacitor IGBT. in inserted Before blocking SMs leads IGBT, to surge the dischargingcurrent, which capacitor provides in a highinserted electrical SMs pressureleads to onsurge semiconductor current, which devices. provides Thus, froma high a protectionelectrical pressureperspective, on IGBTsemiconductor is blocked devices. with a control Thus, signalfrom a when protection the arm perspective, current reaches IGBT the is thresholdblocked with value. a control signal when the arm current reaches the threshold value. 2.2.1. Submodule Capacitor Discharging Period

2.2.1.At Submodule the beginning Capacitor of the PPF,Discharging the capacitor Period in every inserted SM discharges and bridge arm current surges. Figure3 depicts the fault current circuit, in which the capacitor discharging current flows At the beginning of the PPF, the capacitor in every inserted SM discharges and bridge arm through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each converter current surges. Figure 3 depicts the fault current circuit, in which the capacitor discharging current unit. The fault occurs at point A and point B, which are connected with dashed line in Figure3. flows through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each Considering that converter includes six arms with same topology, hence, only the upper arm of phase converter unit. The fault occurs at point A and point B, which are connected with dashed line in A is shown with insert SMs and removed SMs due to the space of figure and simplicity. All the IGBT Figure 3. Considering that converter includes six arms with same topology, hence, only the upper can be turned off as the bridge arm current reaches the threshold value to protect the IGBT from arm of phase A is shown with insert SMs and removed SMs due to the space of figure and simplicity. overcurrent damage. The voltage cross converter unit v decreases with SM capacitor discharging All the IGBT can be turned off as the bridge arm currentconv reaches the threshold value to protect the until the IGBT is blocked. In contrast to the two-level VSC-HVDC system under the PPF, in which a IGBT from overcurrent damage. The voltage cross converter unit 𝑣 decreases with SM capacitor large capacitor connected to the DC side discharges to zero, even if IGBT is blocked (assuming the discharging until the IGBT is blocked.p In contrast to the two-level VSC-HVDC system under the PPF, resistance in fault circuit R < 2 L /C ), the voltage of the SM capacitor is normally maintained in which a large capacitoreq connectedeq toeq the DC side discharges to zero, even if IGBT is blocked given the blocked IGBTs in the MMC-HVDC system. If vconv is higher than the AC grid line voltage (assuming the resistance in fault circuit 𝑅 <2𝐿/𝐶 ), the voltage of the SM capacitor is vsj_line (j indicates phases a, b, and c), then the AC grid current cannot be fed in the fault current loop. normally maintained given the blocked IGBTs in the MMC-HVDC system. If 𝑣 is higher than the If Vconv is lower than the AC grid line voltage, then the AC grid begins to feed the AC current isj (j AC grid line voltage 𝑣 (j indicates phases a, b, and c), then the AC grid current cannot be fed in indicates phases a, b, and_ c) into the fault current loop. In Figure3, the red dashed line indicates the the fault current loop. If 𝑉 is lower than the AC grid line voltage, then the AC grid begins to feed the AC current 𝑖 (j indicates phases a, b, and c) into the fault current loop. In Figure 3, the red Appl. Sci. 2019, 9, x 6 of 26 Appl.Appl. Sci.Sci. 20192019,, 99,, 1661x 66 of 2626 𝑖 dasheddashed lineline indicatesindicates thethe faultfault currentscurrents 𝑖 fedfed fromfrom thethe ACAC grid;grid; thesethese faultfault currentscurrents areare equallyequally 𝑖 𝑖 faultdivideddivided currents intointo ananisj upperfedupper from armarm the currentcurrent AC grid; 𝑖__ these andand fault aa lowerlower currents armarm current arecurrent equally 𝑖__ divided (not(not markedmarked into an inin upper thethe figurefigure arm 𝑖 currentduedue toto complexity).icomplexity).pj_ac and a lower TheThe blueblue arm dashed–dotted currentdashed–dottedinj_ac (not lineline marked representsrepresents in the thethe figure capacitorcapacitor due todischargingdischarging complexity). path,path, The andand blue 𝑖 dashed–dottedexpressesexpresses the the discharging discharging line represents arm arm currents. thecurrents. capacitor Both Both discharging AC AC fe feedingeding path,current current and in in ired cjredexpresses and and SM SM capacitor capacitor the discharging discharging discharging arm currents.currentcurrent inin Both blueblue AC flowflow feeding throughthrough current insertedinserted in red SMsSMs and and SMand capacitor removedremoved discharging SMsSMs inin eacheach current arm.arm. Specifically, inSpecifically, blue flow the throughthe faultfault insertedcurrentcurrent SMsflowsflows and throughthrough removed freewheelingfreewheeling SMs in each diodediode arm. Specifically, inin removedremoved the SMsSMs fault andand current capacitorcapacitor flows and throughand on-stateon-state freewheeling IGBTIGBT inin diodeinsertedinserted in SMs, removedSMs, shown shown SMs in in andFigure Figure capacitor 3. 3. The The equivalent andequivalent on-state ci circuitsrcuits IGBT of of in the the inserted two two fault fault SMs, current current shown paths paths in Figure are are exhibited exhibited3. The equivalentinin FigureFigure 4a,b. circuits4a,b. However,However, of the two thethe fault ACAC current feedingfeeding paths currentcurrent are canexhibitedcan bebe ignoredignored in Figure inin 4 comparisoncomparisona,b. However, withwith the thethe AC capacitorcapacitor feeding currentdischargingdischarging can be current current ignored during during in comparison this this period. period. with the capacitor discharging current during this period.

i Phase-B Phase-C i pa ipb Phase-B i Phase-C A pa TT1 D ipb upper arm ipcpc upper arm i A InsertedInserted 1 D 1 C upper arm upper arm idcdc11 1 C00 SMsSMs TT2 i i i 2 DD2 i ca i cb i cc vvconv 2 ca cb cc conv T T11 D RemovedRemoved D11 SMsSMs T T22 DD2 C 2 C00 uv>> uvsa_ line convLLsa L L Pole-to- sa_ line conv sa LL0 L 0 L 0 Pole-to- > 0 0 0 pole Fault uvsb_ line> convLsb isa i i pole Fault uvsb_ line convLsb isa inana isbsb > i i uvuvsc_ line> convLLsc i nb i sc sc_ line conv sc nb sc i incnc L0 L L0 L00 L L00

Phase-A Phase-C Phase-A Phase-BPhase-B Phase-C lower arm lower arm lower arm lowerlower arm arm lower arm BB

FigureFigureFigure 3.3. 3. DirectDirect Direct currentcurrent current pole-to-polepole-to-pole pole-to-pole faultfault fault circuitcircui circuitdiagramt diagram diagrambefore before before blocking blocking blocking submodules. submodules submodules

iipa_ ac pa_ ac i Ldc Rdc uusa LLsa RRsa i i dis Ldc Rdc Ceq sa sa sa isasa dis Ceq i LL0 i inana__ ac ac 0 i i i idisdis L RRdc i ca i cb i cc Ldcdc dc ca cb cc −− iipb_ ac ++ u L R pb_ ac I + u sb L sb R sbiisb C C C I dis0 + sb sb sb sb C eqa Ceqbeqb Ceqceqc dis0 iinb_ ac L eqa Req nb_ ac L00 R R − Req R faultfault R faultfault − iipc_ ac L R 2L − pc_ ac Ldcdc Rdcdc 22LL0 22LL0 2L 0 − + u Lsc R isc 0 0 0 + uscsc Lsc R scscisc LLdc RRdc L iinc_ ac LL0 dc dc L eq nc_ ac 0 eq

((aa)) ((bb)) ((cc))

FigureFigureFigure 4. 4.4. ( (a(a))) Equivalent EquivalentEquivalent ACACAC grid gridgrid feeding feedingfeeding current currentcurrent circuit, circuit,circuit, ( (b(bb))) equivalent equivalentequivalent SM SMSM capacitor capacitorcapacitor discharging dischargingdischarging currentcurrentcurrent circuit,circuit, circuit, ((c (c)c) simpliﬁed)simplified simplified SM SM SM capacitor capacitor capacitor discharging di dischargingscharging current current current circuit. circuit. circuit.

2C0 The equivalent phase capacitor Ceq demonstrated in Figure4b is normally considered N in the ππ existing references4.42 [5,6,15,17]. However, Reference（， [36）] proposed that the calculation value of the 4.42 C0 （，4.41944.4194） 1.4 C0 fault current with Ceq = N is close to the simulation33 value. Furthermore, Ceq is obtained as N for the optimal approximation of the discharging current via a tracing point method [37]. Consequently, 4.44.4 Reference [38] verified that Ceq of the three converter units depends on the fault time t f and modulation ratio m, as expressed in Equation (1). Thus, the selection of fault time t and modulation ratio m should 4.384.38 f be reconsidered in this paper. Based on equivalent capacitor expression in Equation (2), the relationship between discharging coefficient σ andππ time is shown in Figure5, given the preset modulation ratio 4.364.36 （，4.3536 ） m (0.93) of test system. From the perspective（，4.3536 ） of fault protection, the most serious situation must be Discharging coefficient Discharging 6 Discharging coefficient Discharging 6 considered in selecting4.34 t f . According to the red curve in Figure5, the maximum discharging coe fficient 4.34 0 kπ 0.002 0.004 0.006 0.008 0.01 σ is obtained when t0f = , k =0.0020, 1, 2 .... Namely,0.004 the maximum0.006 Ceq equals0.008 1.473, since0.01 the fault time 3 Time(s)Time/sTime(s)Time/s of the simulation is set at 1.2 s. FigureFigure 5. 5. Relationship Relationship between between discharging discharging coe coefficientfficient and and fault fault time time (m (m = = 0.93). 0.93). 2C0 2C0 2C0 Ceq = + + (1) [1 + m2 sin2(ωt)]N [1 + m2 sin2(ωt 2 π)]N [1 + m2 sin2(ωt + 2 π)]N − 3 3 Appl. Sci. 2019, 9, x 6 of 26

dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally divided into an upper arm current 𝑖_ and a lower arm current 𝑖_ (not marked in the figure due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 expresses the discharging arm currents. Both AC feeding current in red and SM capacitor discharging current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault current flows through freewheeling diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor discharging current during this period.

i Phase-B Phase-C pa T ipb ipc A Inserted 1 D upper arm upper arm idc1 1 C0 SMs T2 i i i D2 ca cb cc vconv T1 Removed D1 SMs T 2 D2 C > 0 uvsa_ line conv L Pole-to- sa L L0 L0 > 0 pole Fault uvsb_ line convLsb isa ina isb > i i uvsc_ line convLsc nb sc inc L0 L0 L0

Phase-A Phase-B Phase-C lower arm lower arm lower arm B

Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules

i pa_ ac L R u L R i idis dc dc C sa sa sa sa L eq ina_ ac 0 idis L R ica icb icc i dc dc − + pb_ ac + usb Lsb Rsb i C C C Idis0 sb i eqa eqb eqc nb_ ac L0 Req R fault R fault − ipc_ ac L R − dc dc 2L0 2L0 2L0 + usc Lsc R sc isc i L Ldc Rdc L nc_ ac 0 eq Appl. Sci. 2019, 9, 1661 7 of 26 (a) (b) (c)

Figure 4. (a) Equivalent AC grid feeding current circuit,C (b) equivalent SM capacitor discharging C = σ 0 (2) current circuit, (c) simplified SM capacitor dischargingeq N current circuit.

π 4.42 （，4.4194） 3 4.4

4.38

π 4.36 （，4.3536 ）

Discharging coefficient Discharging 6 4.34 0 0.002 0.004 0.006 0.008 0.01 Time(s)Time/s FigureFigure 5. 5.Relationship Relationship between between discharging discharging coe coeﬃfficientcient and and fault fault time time (m (m= =0.93). 0.93).

During the SM capacitor discharging period, the AC feeding current can be ignored, because the discharging current is dominant. For example, the Phase-A discharging circuit can be regarded as a second-order RLC circuit (circuit consisting of a resistor, an inductor and a capacitor), as displayed in Figure4c. Here, the resistance in the arms is neglected. The initial voltage and current of the capacitor discharging circuit are expressed by Equations (3) and (4), respectively.

uc(0+) = uc(0 ) = Udc (3) −

duc idis(0+) = idis(0 ) = Ceq = Idis0 (4) − − dt The equivalent capacitor, inductance, and resistance presented in Figure4c are obtained as follows:

σC C = 0 (5) eq N 2 L = L + 2L (6) eq 3 0 dc

Req = R f ault + 2Rdc (7) The second-order equation of the RLC circuit is expressed in Equation (8) as follows:

2 d idis Req didis 1 + + idis = 0 (8) dt Leq dt LeqCeq s t Ceq Idis0ω0 idis(t) = e− τ [Udc sin(ω1t) sin(ω1t θ)] (9) Leq − ω1 −

2 2Leq 2( L0 + 2Ldc) τ = = 3 (10) Req 2Rdc + R f ault s !2 1 Req ω1 = (11) LeqCeq − 2Leq s 1 ω0 = (12) LeqCeq

θ = arctan(ωτ) (13) Appl. Sci. 2019, 9, 1661 8 of 26

where τ is the attenuation coeﬃcient of the capacitor discharging current, ω1 is the oscillating current angular frequency, ω0 is the inherent angular frequency of the circuit, and θ is the initial phase angle of the initial current. The capacitor discharges until the capacitor voltage decreases to 0. The maximum discharging current can be obtained at tdis_peak without blocking IGBT. s 1 Udc Ceq tdis_peak = arctan( ) (14) ω0 Idis0 Leq

s tv t 2 dis_peak Ceq Idis0ω0Leq Udc Idis_peak = e− τ (Udc + ) (15) Leq U I2 2L2 + U2 dc dis0ω0 eq dc The AC side can be considered a three-phase short-circuit fault under the DC pole-to-pole fault, and the DC fault current only consists of the discharging currents of the three converter units, given the balance fault on the AC side. Thus, the fault current through DC line is deﬁned as

idc(t) = idis(t) (16)

For example, Phase-A arm current during this period can be decomposed using Equations (17) and (18). 1 1 i (t) = i (t) + i (t) (17) pa 3 dc 2 sa 1 1 ina(t) = i (t) isa(t) (18) 3 dc − 2 The Phase-A voltage on the AC side is set as

usa = √2Us sin(ωst + θa) (19) where θa is the phase angle (taken as 0 for convenience in calculation afterward), and ωs is the fundamental angular frequency. Then, the Phase-A current can be obtained using Equation (20).

√2Us isa = sin(ωst + θa ϕ) (20) Zeq − where ϕ is the impedance angle. The AC feeding current in each phase is equally divided into upper and lower arms. 1 √2Us ipa_ac(t) = ina_ac(t) = sin(ωst + θa ϕ) (21) 2 Zeq − s 1 2 Z = R2 + ω L + L (22) eq sa s s 2 0

1 Lsa + L0 ϕ= arctan( 2 ) (23) Rsa In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current can be obtained. s 1 t Ceq Idis0ω0 1 √2Us ipa = e− τ [Udc sin(ω1t) sin(ω1t θ)] + sin(ωst + θa ϕ) (24) 3 Leq − ω1 − 2 Zeq − s 1 t Ceq Idis0ω0 1 √2Us ina = e− τ [Udc sin(ω1t) sin(ω1t θ)] sin(ωst + θa ϕ) (25) 3 Leq − ω1 − − 2 Zeq − Appl. Sci. 2019, 9, 1661 9 of 26

2.2.2. Freewheeling Current and AC Feeding Current Period Appl. Sci. 2019, 9, x 9 of 26 The fault current circuit after completely discharging IGBT blocks or capacitor to Vconv = 0 is depictedAppl. Sci. 2019 in, Figure9, x 6, in which the red dotted line indicates the AC feeding current, and the9 blue of 26 dash-dotted line represents the freewheeling current given1 the stored energy in the arm reactors. The LL+ equivalent circuits of the AC feeding and freewheelingsa 2 DC0 currents are illustrated in Figure7a,b, ϕ=arctan(+ 1 ) (23) LLsa 0 respectively. The fault current can be considered a superpositionRsa of the three-phase short-circuit fault ϕ=arctan(2 ) (23) and decayed freewheeling currents. Thus, the faultR currents in the upper and lower arms can be In accordance with Equations (9), (16)–(18), and (21),sa the expression of the Phase-A arm current deﬁned as can beIn obtained. accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current ipj = i f wj + ipj_ac (26) can be obtained. 11− t C IUω 2 =−−++−τ eq ωωθωθdis=00 s ϕ ieUpa[ dc sin(11 t )inj i f wjsin(inj t_ac )] sin(sa t ) (24)(27) 3211− t LZC IUω ω − 2 ieU=−−++−τ [eqeq sin(ωωθωθ t )dis100 sin( t )] eq s sin( t ϕ ) where i f wj denotespa the freewheeling dc current11 inω each converter phase. ipj_ac andsainj_ac indicate the(24) AC 32LZeq1 eq feeding current via the upper and lower arms of each phase, respectively. The analysis during the SM − t C IUω 2 =−−−+−11τ eq ωωθωθdis00 s ϕ capacitor dischargingieUna period[ dc shows sin( that11 t ) the initial sin( freewheeling t )] current sin( is equalsa t to the ) peak value(25) of 3211− t LZC IUω ω 2 the discharging current=−−−+− inτ each convertereqeq ωωθωθ phase.dis100 eq s ϕ ieUna[ dc sin(11 t ) sin( t )] sin(sa t ) (25) 32LZω eq1 eq 1 2.2.2. Freewheeling Current and AC FeedingI f wCurrent0 = Idis Period_peak (28) 3 2.2.2. Freewheeling Current and AC Feeding Current Period

Phase-B ipa T1 ipb i Phase-C A D1 pc idc2 C0 upper arm upper arm i T i Phase-B Phase-C pa 1 D pb ipc A T 1 C upper arm upper arm idc2 2 D2 i0 i fwb i fwc vconv Blocked fwa T2 D i SMs T1 2 i fwa i fwb fwc vconv Blocked D1 SMs T1 D T2 1 D2 C0 > T uvsa_ line conv L 2 D C Pole-to- sa L 2 0 L0 L0 > 0 uvuv> LL polePole-to- Fault sbsa__ line line conv conv sbsaisa L0 L0 L0 uv>> L pole Fault uvscsb_ line_ line conv convLscsb isa ina isb inb > inc uvL ina i i i sc_ line conv sc L0 sb L0nb sc Li0 i nc L0 L0 sc L0

Phase-A Phase-B Phase-C lower arm lower arm lower arm Phase-A Phase-B Phase-C B lower arm lower arm lower arm B Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. FigureFigure 6.6. Diagram ofof thethe DCDC pole-to-polepole-to-pole faultfault circuitcircuit afterafter blockingblocking SMs.SMs.

ipa_ ac u L R i i fw Ldc Rdc sa sa sa sa i L inapa_ ac_ ac 0 i i i fwc i L R u L R i L Rdc fwa fwb fw dc dc sa sa sa sai L dc pbina_ ac_ ac 0 i u L R I i fwa I i fwb I fwc sb sb sb isb Ldc Rdc fw0 fw0 fw0 inbi _ ac L pb_ ac 0 R R fault usb Lsb Rsb i fault I I I sbi i L fw0 fw0 fw0 pcnb_ ac_ ac 0 Ldc Rdc 2L 2L 2L R R fault 0 0 0 fault usc Lsc R sc isc i L R Ldc Rdc incpc_ ac_ ac L0 dc dc 2L0 2L0 2L0 usc Lsc R sc isc Ldc Rdc inc_ ac L0 (a) (b)

FigureFigure 7. 7. EquivalentEquivalent circuit(a) circuit of of the the (a (a) )AC AC feeding feeding current current and and (b (b) )freewheeling freewheeling(b) DC DC current. current. Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. The fault current circuit after completely discharging IGBT blocks or capacitor to 𝑉 =0 is depictedThe in fault Figure current 6, in whichcircuit the after red completely dotted line discharging indicates the IGBT AC feeding blocks current,or capacitor and theto 𝑉blue dash-=0 is dotteddepicted line in represents Figure 6, in the which freewheeling the red dotted current line givenindicates the the stored AC feedingenergy current,in the arm and reactors.the blue dash-The equivalentdotted line circuits represents of the the AC freewheeling feeding and freewheelingcurrent given DC the currents stored energyare illustrated in the armin Figure reactors. 7a and The Figureequivalent 7b, respectively. circuits of the The AC fault feeding current and can freewheeling be considered DC a currentssuperposition are illustrated of the three-phase in Figure short-7a and Figure 7b, respectively. The fault current can be considered a superposition of the three-phase short- Appl. Sci. 2019, 9, 1661 10 of 26

Thus, the freewheeling current of each arm and the DC line current can be obtained using Equations (29) and (30). t τ i f wj(t) = I f w0e− 1 (29)

t τ idc(t) = 3I f w0e− 1 (30) For example, the initial arm current of the freewheeling period of Phase A is expressed as follows:

1 I = I + i (t ) (31) pa_bk f w0 2 sa dis_peak 1 I = I isa(t ) (32) na_bk f w0 − 2 dis_peak Similarly, the arm currents can be decomposed as Equations (33) and (34).

ipa(t) = i f wa(t) + ipa_ac(t) (33)

ina(t) = i (t) ina_ac(t) (34) f wa − In reference to Equations (21) and (28), the arm currents can be deﬁned as

t √ 1 τ 1 2Us ipa(t) = Idis_peake− 1 + sin(ωst + θa ϕ) (35) 3 2 Zeq −

t √ 1 τ 1 2Us ina(t) = Idis_peake− 1 sin(ωst + θa ϕ) (36) 3 − 2 Zeq −

2(2L0+2Ldc) τ1 = (37) 2Rdc + R f ault where τ1 is the attenuation coeﬃcient of the freewheeling current. Equivalent impedance is expressed in Equation (22), and the peak value of the discharging current can be obtained via Equation (15).

2.3. Simulation Verification The analyses of the arm and DC line currents have been verified via a simulation. The monopolar MMC-HVDC system is adopted in this study, and the model parameters are listed in Table1. The rectifier side takes DC voltage and active power control, and the inverter side adopts active and reactive power controls. The protection action, including blocking IGBTs, is disregarded in the simulation to investigate the natural response to a fault. A completely discharged SM capacitor can be equivalent to blocking IGBTs at tdis_peak. The comparison between the calculation and the simulation in terms of DC line and arm currents (Phase-A upper arm) is depicted in Figures8 and9, respectively. Figure8 demonstrated that the DC line current increases to a high level in a few milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The DC line current decays after completely discharging the SM capacitor. Similarly, the arm current accelerates during the discharging period (Figure9) but involves the AC feeding component after completely discharging the SM capacitor at 1.213 s. The difference between the simulation and calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the calculation, thereby leading to more or less error. However, the overall accuracy of the calculation analysis can be accepted for fault study on the basis of the general consistency between the simulation and calculation curves in Figures8 and9. Appl.Appl. Sci. Sci. 2019 2019, ,9 9, ,x x 1111 ofof 2626 rectifierrectifier sideside takestakes DCDC voltagevoltage andand activeactive powerpower control,control, andand thethe inverterinverter sideside adoptsadopts activeactive andand reactivereactive powerpower controls.controls. TheThe protectionprotection action,action, inincludingcluding blockingblocking IGBTs,IGBTs, isis disregardeddisregarded inin thethe simulationsimulation to to investigate investigate the the natural natural response response to to a a fault. fault. A A completely completely discharged discharged SM SM capacitor capacitor can can bebe equivalentequivalent toto blockingblocking IGBTsIGBTs atat 𝑡𝑡__. . TheThe comparisoncomparison betweenbetween thethe calculationcalculation andand thethe simulationsimulation in in terms terms of of DC DC line line and and arm arm currents currents (Phase-A (Phase-A upper upper arm) arm) is is depicted depicted in in Figure Figure 8 8 and and 9, 9, respectively.respectively. FigureFigure 88 demonstrateddemonstrated thatthat thethe DCDC lineline currentcurrent increasesincreases toto aa highhigh levellevel inin aa fewfew milliseconds.milliseconds. The The IGBTs IGBTs must must be be blocked blocked rapidly rapidly due due to to the the electrical electrical pressure pressure on on the the DC DC line. line. The The DCDC lineline currentcurrent decaysdecays afterafter completelycompletely dischargindischargingg thethe SMSM capacitor.capacitor. Similarly,Similarly, thethe armarm currentcurrent acceleratesaccelerates during during the the discharging discharging period period (Figure (Figure 9) 9) but but involves involves the the AC AC feeding feeding component component after after completelycompletely dischargingdischarging thethe SMSM capacitorcapacitor atat 1.21.21313 s.s. TheThe differencedifference betweenbetween thethe simulationsimulation andand calculationcalculation values values in in the the arm arm current current before before 1.213 1.213 s s may may be be attributed attributed to to the the imbalance imbalance shunt shunt current current amongamong the the converter converter units. units. In In addition, addition, the the initial initial AC AC current current at at fault fault time time (1.2 (1.2 s) s) is is ignored ignored in in the the calculation,calculation, thereby thereby leading leading to to more more or or less less error. error. However, However, the the overall overall accuracy accuracy of of the the calculation calculation analysisanalysis can can be be accepted accepted for for fault fault study study on on the the basis basis of of the the general general consistency consistency between between the the simulation simulation Appl.andand calculation Sci.calculation2019, 9, 1661 curves curves in in Figure Figure 8 8 and and 9. 9. 11 of 26

TableTable 1. 1. Parameters Parameters of of the the modular modular multilevel multilevel converter- converter-basedbased high-voltage high-voltage direct direct current current system’s system’s Table 1. Parameters of the modular multilevelsimulationsimulation converter-based model. model. high-voltage direct current system’s simulation model. SystemSystem Parameters Parameters DCDC voltage voltage ± ± 420 420System kV kV Parameters SM SM number number (2 (2 N) N) 60 60 DCRatedRated voltage power power 1250 1250420 kVMW MW SM Arm Arm number inductance inductance (2 N) 140 140 60 mH mH ± Short-circuitShort-circuitRated power ratio ratio 1250 20MW 20 Internal Internal Arm inductance grounding grounding 140 Yg mH Yg Short-circuit ratio 20 Internal grounding Yg ACAC voltage voltage 450 450 kV kV AC AC line line length length 10 10 km km AC voltage 450 kV AC line length 10 km 12.73 m/kmΩΩ FrequencyFrequencyFrequency 50 50 50 Hz Hz Hz Line Line Line resistance resistance resistance 12.73 mm/kmΩ/km TransformerTransformerTransformer voltage voltage voltage 525 525 525 kV kV/450 kV/450/450 kV kV kV Line Line Line inductance inductance inductance 0.9937 0.9937 0.9937 mH mH mH TransformerTransformer grounding grounding grounding Yn Yn/yn Yn/yn/yn Line Line Line capacitance capacitance capacitance 12.74 12.74 12.74 nF nF/km nF/km/km SmoothingSmoothingSmoothing inductance inductance inductance 20 20 20 mH mH mH DC DC DC line line line length length length 200 200 200 km km km

44 xx 10 10 55 simulationsimulation value value 44 calculationcalculation value(discharging) value(discharging) calculationcalculation value(freewheeling) value(freewheeling) 33

22 DC current/A DC DC current/A DC DC Current(A) DC DC Current(A) DC 1 1 ts== 1.213 tsdisdis_ _ peak peak 1.213

00 1.21.2 1.221.22 1.241.24 1.261.26 1.281.28 1.31.3 Time(s)Time/s Time(s)Time/s FigureFigure 8. 8. Simulation Simulation and and calculation calculation values values of of the the DC DC line line current. current.

4 x 104 x 10 22 calculationcalculation value(discharging) value(discharging) calculationcalculation value(freewheeeling+AC value(freewheeeling+AC feeding) feeding) 1.51.5 simulationsimulation value value

0.50.5 Arm current(A) Arm current(A) ts== 1.213 tsdisdis_ peak_ peak 1.213

Phase-A upper arm current/A 0

Phase-A upper arm current/A 0 1.21.2 1.221.22 1.241.24 1.261.26 1.281.28 1.31.3 Time(s)Time/sTime(s)Time/s FigureFigure 9. 9. Simulation Simulation and and calculation calculation values values of of the the arm arm current current (Phase-A (Phase-A upper upper arm). arm). 2.4. Protection Demand The MMC-HVDC system focuses on the protection and healthy part safety of the converter station. Speciﬁcally, the IGBTs are regarded as important components in the converter station given their high cost but low electrical withstanding ability. IGBTs and freewheeling diodes are destroyed due to overheating under extremely high arm current. Another point in protection relaying is that the DCCB occupies a large portion of the cost in the HVDC project considering its high interruption capacity. Therefore, the arm and DC line currents under a fault must be investigated, and the limitation of fault current methods is required to satisfy protection demands. In accordance with the fault current analysis discussed in Section2, the anti-parallel diodes in removed SMs and IGBTs in inserted SMs experience a dramatic overcurrent before blocking IGBTs. Moreover, the diode D2 in inserted SMs can withstand the peak value of the discharging current when the IGBTs T1 are blocked; this issue is considered an essential challenge to the DC fault protection of the MMC-HVDC system [4]. Considering the action of blocking IGBTs, the arm current under the DC pole-to-pole fault has been simulated (Figure 10). Using Equations (16) and (28), the DC current reaches 30 kA when the Appl. Sci. 2019, 9, x 12 of 26

2.4. Protection Demand The MMC-HVDC system focuses on the protection and healthy part safety of the converter station. Specifically, the IGBTs are regarded as important components in the converter station given their high cost but low electrical withstanding ability. IGBTs and freewheeling diodes are destroyed due to overheating under extremely high arm current. Another point in protection relaying is that the DCCB occupies a large portion of the cost in the HVDC project considering its high interruption capacity. Therefore, the arm and DC line currents under a fault must be investigated, and the limitation of fault current methods is required to satisfy protection demands. In accordance with the fault current analysis discussed in Section 2, the anti-parallel diodes in removed SMs and IGBTs in

inserted SMs experience a dramatic overcurrent before blocking IGBTs. Moreover, the diode 𝐷 in inserted SMs can withstand the peak value of the discharging current when the IGBTs 𝑇 are blocked; this issue is considered an essential challenge to the DC fault protection of the MMC-HVDC system [4]. Considering the action of blocking IGBTs, the arm current under the DC pole-to-pole fault has Appl.been Sci. simulated2019, 9, 1661 (Figure 10). Using Equations (16) and (28), the DC current reaches 30 kA when12 of the 26 IGBT is blocked beyond the maximum interruption capacity of 16 kA [33]. When a fault occurs, the IGBTarm current is blocked mainly beyond consists the maximum of the capacitor interruption discharging capacity and of AC 16 feeding kA [33]. currents When a in fault the occurs,initial stage. the armSpecifically, current mainly the SM consists capacitor of thebegins capacitor to discharg discharginge the current and AC through feeding arms currents and inDC the loops, initial and stage. the Specifically,IGBTs are blocked the SM capacitorwith a triggering begins to signal discharge while the the current arm current through reaches arms the and threshold DC loops, value. and theThe IGBTsIGBT are blocking blocked time with is a set triggering to 1.205 signal s, that while is, 5 ms the after arm currentfault occurrence reaches the to threshold provide value.a distinguishable The IGBT blockingvision on time the is current set to 1.205 development; s, that is, 5this ms aftertimeframe fault occurrenceis slightly tolonger provide than a that distinguishable in the real project vision on(2– the3ms). current In addition, development; the AC thisside timeframe begins to feed is slightly current longer into the than fault that current in the circuit real project while (2–3a fault ms). occurs In 𝑉 = 450𝑘𝑉, 𝑉 = addition,because the ACrated side AC begins line voltage to feed is current set to more into the than fault half current of the circuitDC voltage while ( a_ fault occurs because ±420𝑘𝑉). However, if 𝑉_ < 𝑉 =0.5𝑈, then the AC feeding current will appear as 𝑉_ > the rated AC line voltage is set to more than half of the DC voltage (VAC_line = 450 kV, VDC = 420 kV). 𝑉 given the SM capacitor’s discharging effect. In Figure 10, the AC feed current (red line)± in the However, if VAC_line < VDC = 0.5UDC, then the AC feeding current will appear as VAC_line > VDC given thethree-phase SM capacitor’s uncontrolled discharging rectifier effect. bridge, In Figure and the 10 energy, the AC stored feed currentin the arm (red reactors line) in begin the three-phase to freewheel uncontrolleddecayed current rectifier (blue bridge, line) andthrough the energy anti-parallel stored diodes in the armbecause reactors the beginIGBTs to are freewheel blocked. decayed The AC currentcircuit (bluebreaker line) (ACCB) through is anti-paralleltriggered to diodesisolate becausethe fault the section IGBTs after are blocked.a fault is The detected. AC circuit The breakerdelay in (ACCB)the ACCB is triggered is normally to isolate 4–5 cycles. the fault Thus, section the triggeri after ang fault time is detected.point is set The to delay100 ms in after the ACCB the fault is normallyoccurrence. 4–5 Figure cycles. 10 Thus, demonstrates the triggering that time the arm point current is set to reaches 100 ms approximately after the fault occurrence. 10 kA while Figure the IGBT 10 demonstratesblocks and decays that the slowly arm current with the reaches AC feeding approximately component. 10 kA The while limitation the IGBT of blocksthe fault and current decays is slowlyessential with to therealize AC feedingprotection component. considering The the limitation limitation of in the the fault DCCB current capability. is essential The AC to realizefeeding protectioncurrent can considering be restrained the limitation using a parallel-connected in the DCCB capability. thyristor The in AC previous feeding works current [18–21]. can be restrainedTherefore, usingthe discharging a parallel-connected current limitation thyristor inand previous rapid deca worksying [18 freewheeling–21]. Therefore, current the dischargingare the focus current in the limitationpresent study. and rapid decaying freewheeling current are the focus in the present study.

12000 AC feeding current Capacitor discharging current & reactor freewheeling current 10000 Arm current (phase-A upper arm) 8000

6000

4000

2000

0 Arm current(A) Arm

-2000 Fault occurence IGBT blocked（1.205s) -4000 ACCB triggered

1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 Time(s) FigureFigure 10. 10.Phase-A Phase-A upper upper arm arm current current under under the the DC DC pole-to-pole pole-to-pole fault. fault.

3.3. Enhanced Enhanced Fault Fault Current Current Limiting Limiting Circuit Circuit 3.1. Fault Current-Limiting Characteristics 3.1. Fault Current-Limiting Characteristics The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. Thus, investigating the influence of the two elements on the fault current development is important. The related simulation was performed under controlled conditions. Figure 11a displays that limiting inductance can help slow down the accelerating speed of the fault current but increase the time spent in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation resistance facilitates the constraining fault current peak value and the accelerating extinguishment of the freewheeling current. The adoption of the reactor and resistance in the discharging period is suitable, considering that the maximum fault current will flow through the freewheeling diode while the IGBTs are blocked or the SM capacitors are completely discharged. However, the limiting inductance can affect the dynamic response speed and prolong the recovery time. Therefore, further study on the FCLC design is required. A series of simulations was conducted under controlled conditions to obtain the expected fault current limitation and rapid recovery. The simulation conditions are divided into resistance and reactor groups as follows: the former is labeled with “a”, “b”, “c”, and “d”, and the latter with “e”, “f”, “g”, and “h”. Specifically, the related explanations of the conditions are listed in Table2.“ X” indicates that Appl. Sci. 2019, 9, 1661 13 of 26 Appl. Sci. 2019, 9, x 13 of 26

theThe resistance FCLC mainly or reactor consists is inserted of energy in the dissipation fault circuit, resistance and “ and” denotes limiting the inductance absence of [14,15,25,35]. resistance or × Thus,reactor. investigating First, the reactorthe influence was ignored, of the two and elements Figure 12 aon illustrates the fault thatcurrent the reddevelopment curve (“ag”) is important. provides an Theimproved related simulation performance was in performe limitingd fault under current. controlled Thus, conditions. the condition Figu withre 11a “a” displays was selected that limiting for the inductancefollowing can simulation. help slow Figure down 12 theb depictsaccelerating the performance speed of the offault various current reactor-based but increase FCLC the time scheme, spent in inwhich decaying thered the dashed–dotted freewheeling curvecurrent (“ad”) to its represents expected thelevel. lowest In Figure fault current 11b, the level. energy However, dissipation the “ad” resistancescheme wasfacilitates unsatisfactory the constraining for real projects,fault current where peak large value inductance and the accelera will aﬀectting the extinguishment dynamic response of thespeed freewheeling of the entire current. system The during adoption the normal of the state. reactor Therefore, and resistance the “af” scheme in the mostdischarging closely approachesperiod is suitable,the optimized considering FCLC that scheme, the maximum because fault the energy current dissipation will flow through resistance the consumesfreewheeling the diode energy while in the theAppl.fault IGBTs Sci. circuit. 2019 are, 9 This, xblocked phenomenon or the SM is due capacitors to the fault are being completely detected, discharged. and the FCL However, reactor being the insertedlimiting13 of 26 to inductancelimit the increasecan affect in the current dynamic speed, response but also speed being and removed prolong to the accelerate recovery the time. decaying Therefore, speed further of the The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. studyfreewheeling on the FCLC current design after is blocking required. the IGBT. Thus, investigating the influence of the two elements on the fault current development is important.

4 The related4 simulation was performed under controlledx 10conditions. Figure 11a displays that limiting x 10 7 7 inductance can help slow downNone the accelerating speed of the fault current but increaseNone the time spent 6 6 R=0.05ohm L=20mH in decaying the freewheeling current to its expected level. In Figure 11b, the energyR=0.05ohm dissipation L=20mH R=0.05ohm L=20mH 5 5 R=0.5ohm L=20mH R=0.05ohm L=100mH 4 x 10 resistance facilitates the constraining fault current peak value4 and the accelerating extinguishmentR=5ohm L=20mH of 4 R=0.05ohm L=200mH 4 3 the freewheeling3 current. The adoption of the reactor3 and resistance in the discharging period is 2 x 104 4 suitable, 2 considering that the maximum fault current will2 1 flow through the freewheeling diode while

DC Current(A) 0 the IGBTs1 are 2 blocked or the SM capacitors are completelyDC Current(A) 1 1.2 1.205 discharged. However, the limiting

0 0 0 inductance can 1.2affect 1.205the dynamic response speed and prolong the recovery time. Therefore, further Fault occurrence Fault occurrence

-1 -1 study1.1 on the1.2 FCLC1.3 design1.4 is1.5 required.1.6 1.7 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Time(s) Time(s)

4 4 x 10 x 10 7 7 (a) (b) None None 6 6 R=0.05ohm L=20mH R=0.05ohm L=20mH FigureFigure 11. 11. DCDC fault fault current current characteristics characteristicsR=0.05ohm L=20mH (a) ( awith) with variable variable5 limiting limiting inductance; inductance; (b ()b with) with variable variable 5 R=0.5ohm L=20mH R=0.05ohm L=100mH 4 energy dissipation resistance. x 10 energy dissipation resistance. 4 R=5ohm L=20mH 4 R=0.05ohm L=200mH 4 3 3 3 2 Tablex 104 2. Condition classiﬁcation for the fault current limiting circuit scheme. 4 2 2 1

DC Current(A) 0 DC Current(A) 1.2 1.205 20000 1 2 1 Time Point Label Fault Occurred5000 Fault Detected IGBT Blocked ad 0 ag 0 0 1.2 1.205 ae 15000 bgFault occurrence a 4000 XXFault occurrence -1 af 1.1 Resistance-related1.2 1.3 1.4 1.5 1.6 1.7 × -1 cg b 1 1.1 ag X1.2 1.3 1.4 1.5 1.6 1.7 1.8 condition Time(s) × 3000 ah × 10000 c Time(s) × × × 2000 5000 (a) d XX (b) × e 1000 XX DC Current(A) DC Figure0 Reactor-related11. DC fault current characteristics (a)× with variableCurrent(A) DC limiting inductance; (b) with variable Fault Fault f 0 X conditionoccurrence detected IGBT blocked × Fault Fault × energy dissipation resistance. occurrence detected IGBT blocked -5000 g 1.199 1.2 1.201 1.202 1.203 1.204 1.205×-1000 × × h XXX1.199 1.2 1.201 1.202 1.203 1.204 1.205 Time(s) Time(s)

20000 (a) (b) 5000 ad ag ae Figure15000 12. Comparison among different FCL schemes (a) different resistance conditions without bg 4000 af considering thecg reactor, (b) different reactor conditions with selected ag resistance schemes. 10000 3000 ah

2000 5000 Table 2. Condition classification for the fault current limiting circuit scheme. 1000 DC Current(A) DC 0 Fault Current(A) DC Fault IGBT Time PointFault Fault Label 0 occurrence detected IGBT blocked Fault Fault occurrence detected IGBT blocked -5000 Occurred Detected Blocked 1.199 1.2 1.201 1.202 1.203 1.204 1.205 -1000 1.199 1.2 1.201 1.202 1.203 1.204 1.205 Resistance- Time(s)a ×  Time(s)  related b ×  × (a) (b) condition c × × × FigureFigure 12. 12. ComparisonComparison amongd among different different FCL FCL schemes schemes ( (aa)) different different resistance resistance conditions conditions× without without consideringconsideringReactor- the the reactor, reactor, ( (be)) different different reactor × conditions with selected resistance schemes.schemes. related f ×  × conditionTable 2. Conditiong classification× for the fault current× limiting circuit scheme.× h Fault Fault IGBT Time Point Label Occurred Detected Blocked Resistance- a ×   related b ×  × condition c × × × d   × Reactor- e ×   related f ×  × condition g × × × h    Appl. Sci. 2019, 9, x 14 of 26

A series of simulations was conducted under controlled conditions to obtain the expected fault current limitation and rapid recovery. The simulation conditions are divided into resistance and reactor groups as follows: the former is labeled with “a”, “b”, “c”, and “d”, and the latter with “e”, “f”, “g”, and “h”. Specifically, the related explanations of the conditions are listed in Table 2. “” indicates that the resistance or reactor is inserted in the fault circuit, and “×” denotes the absence of resistanceAppl. Sci. 2019 or, 9reactor., 1661 First, the reactor was ignored, and Figure 12a illustrates that the red curve (“ag”)14 of 26 provides an improved performance in limiting fault current. Thus, the condition with “a” was selected3.2. Basic for Topology the following simulation. Figure 12b depicts the performance of various reactor-based FCLC scheme, in which the red dashed–dotted curve (“ad”) represents the lowest fault current level. However,The EFCLC the “ad” is scheme proposed was on unsatisfactory the basis of for analyzing real projects, the fault where current large inductance limitation characteristics will affect the T T dynamic(Figure 13 response). During speed the normal of the state, entire the system series-connected during the IGBTs, normal namely, state. Therefore,1 and 2, are the opened. “af” scheme When mosta fault closely is detected, approachesT1 and Tthe2 are op closedtimized by FCLC a switching-o scheme,ﬀ signal,because and the the energy energy dissipation dissipation resistance resistance consumesRFCL and FCLthe energy reactor inL theFCL faultare inserted circuit. This in the phen faultomenon circuit. is LdueFCL towill the be fault bypassed being detected, via bidirectional and the FCLparallel-connected reactor being inserted thyristors to Tlimit3 and theT 4increase. The surge in current arrestor speed, is equipped but also to being protect removed circuit to components accelerate thefrom decaying surge current speed andof the voltage. freewheeling In addition, current the after thyristors blocking can the function IGBT. as a voltage stabilizer due to the surge voltage across LFCL. Considering zero voltage switching and loss reduction, the IGBTs are 3.2.protected Basic Topology by a snubber circuit, which consists of snubber capacitor, snubber resistance, and diode [34].

D1 D2

T1 T2

LFCL

RFCL T3

MOA FigureFigure 13. 13. ProposedProposed enhanced enhanced fault fault current current limiting limiting circuit.

3.3. Fault Current Interruption with DC Circuit Breaker The EFCLC is proposed on the basis of analyzing the fault current limitation characteristics

(FigureConsidering 13). During that the fault normal relay state, involves the series-connected FCL behavior andIGBTs, DCCB namely, operation, 𝑇 and it 𝑇 is, necessaryare opened. to Wheninvestigate a fault the is detected, coordination 𝑇 and between 𝑇 are EFCLC closed behaviorby a switching-off and DCCB signal, operation and the in energy this paper. dissipation Hence, resistancethe fault interruption 𝑅 and FCL progress reactor could 𝐿 beare determined inserted in for the further fault circuit. parameter 𝐿 setting will be of bypassed EFCLC. Thevia bidirectionalDCCB topologies parallel-connected in articles and thyristors patents can 𝑇 be and classified 𝑇 . The into surge passive arrestor and activeis equipped resonance to protect DCCB, circuithybrid components DCCB (HCB), from and solid-statesurge current DCCB and (SCB) voltage. [39]. In The addition, resonance-based the thyris DCCBtors can spend function a relatively as a voltagelong time stabilizer in fault due current to the interruption surge voltage and across may lead 𝐿 to. Considering overcurrent. zero The HCBvoltage and switching SCB have and a rapid loss reduction,operation speed.the IGBTs Although are protected the detailed by a snubber topologies circ ofuit, the which HCB andconsists SCB of are sn diubberfferent capacitor, from the snubber nominal resistance,path, these and topologies diode [34]. can be equivalent to the ideal breaker in the nominal path and a metal oxide arrestor (MOA) when proactive switching control is applied [14,24]. A residential current breaker is 3.3used Fault to cut Current a residential Interruption current with in DC the Circuit MOA, whichBreaker is also modeled as an ideal breaker. The topologies of theConsidering DCCB and equivalentthat fault simulationrelay involves model FCL [14 ]behavi are exhibitedor and inDCCB Figure operation, 14a,b, correspondingly. it is necessary The to investigatemain breaker the demonstrated coordination between in Figure EFCLC 14b will behavior wait for and the DCCB operation operation delay in ultrafastthis paper. disconnector Hence, the faultswitch interruption (Figure 14a) progress operation, could and be the determined delay time isfor normally further parameter 2ms [33]. The setting fault of current EFCLC. with The a hybridDCCB topologiesDCCB operation in articles is exhibited and patents in Figure can be 15 .classified into passive and active resonance DCCB, hybrid DCCBFigure (HCB), 16 anddisplays solid-state the fault DCCB current (SCB) interruption [39]. The resonance-based sequence of the EFCLCDCCB spend with DCCB.a relativelyT1 and longT2 timeare opened in fault during current the interruption normal state, and whereas may leadT3, Tto4, andovercurrent. the DCCB The main HCB breaker and SCB are closed.have a Whenrapid operationa fault occurs, speed.T1 Althoughand T2 remain the detailed open beforetopologies a fault of the is detected, HCB and andSCB the are maindifferent breaker from of the the nominal DCCB path,remains these closed topologies (Figure can 16 a).be equivalent When a fault to the is detected, ideal breakerT1 and in Tthe2 are nominal switched path o ffandto a insert metal an oxide FCL arrestorbranch in(MOA) the fault when circuit proactive loop, switching and the DCCB control main is applied breaker [14,24]. remains A closedresidential due current to operation breaker time is useddelay to [33 cut] (Figure a residential 16b). Thus, current the faultin the current MOA, level which and is accelerating also modeled speed as arean ideal limited breaker. by the FCLThe branch, which releases the overcurrent pressure on the IGBTs and diodes in the converter and reduces the requirement of the DCCB in an interruption capacity. Once the converter is blocked under an overcurrent protection, T3 and T4 are switched on to bypass LFCL, and the DCCB main breaker is opened (Figure 16c). Consequently, RFCL shares the fault current with the MOA in the DCCB, and the fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the current Appl. Sci. 2019, 9, x 15 of 26 Appl. Sci. 2019, 9, x 15 of 26 topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a and Figure topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a and Figure Appl.14b, correspondingly. Sci. 2019, 9, 1661 The main breaker demonstrated in Figure 14b will wait for the operation15 delay of 26 14b, correspondingly. The main breaker demonstrated in Figure 14b will wait for the operation delay in ultrafast disconnector switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The in ultrafast disconnector switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The fault current with a hybrid DCCB operation is exhibited in Figure 15. faultlevel current slightly with decreases, a hybrid the DCCB fault current operation will is be exhibited cut via the in residential Figure 15. current breaker. In addition, T1,

T2, T 3, and T4 are switched to their normal states.

MOA MOA

(a) (b) (a) (b) Figure 14. (a) Direct current circuit breaker topology, (b) simplified simulation model. FigureFigure 14. 14. ((aa)) Direct Direct current current circuit circuit breaker breaker topology, topology, (b) simpliﬁedsimplified simulation model.

Imax Imax C I Fault current B_max C Fault current IB_max without DCCB without DCCB Fault current Faultwith currentDCCB with DCCB Fault current throughFault current arrestor through arrestor

A. Fault occurs A. Fault occurs B. Fault detected B B. Fault detected B C. Main breaker opens D C. Main breaker opens D D. Residential current breaker opens D. Residential current breaker opens A IdN A IdN

t ft tBop_ tmax t tBop_ tmax ft Appl. Sci. 2019, 9, x 16 of 26 Figure 15. Fault current with hybrid DCCB operation. Figure 15. Fault current with hybrid DCCB operation.

D D D1 D2 1 2 i fault i fault Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. 𝑇 and 𝑇 T T Figure 16 displaysT the faultT current interruption sequence of1 the EFCLC2 with DCCB. 𝑇 and 𝑇 are opened during the1 normal2 state, whereas 𝑇 , 𝑇 , and the DCCB main breaker are closed. When a LFCL are opened during the normal state, whereas 𝑇, 𝑇, and the DCCBT main breaker are closed. When a R T RFCL 3 LFCL fault occurs, 𝑇 and FCL𝑇 remain3 open beforeMOA a fault is detected, and the main breakerMOA of the DCCB fault occurs, 𝑇 and 𝑇 remain open before a fault is detected, and the main breaker of the DCCB T T 4 remains closed (Figure 16a).4 When a fault is detected, 𝑇 and 𝑇 are switched off to insert an FCL remains closed (Figure 16a). When a fault is detected, 𝑇 and 𝑇 are switched off to insert an FCL branch in the fault circuitMOA loop, and the DCCB main breaker remainsMOA closed due to operation time branch in the fault circuit loop, and the DCCB main breaker remains closed due to operation time delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL delay [33] (Figure 16b). Thus,(a )the fault current level and accelerating( bspeed) are limited by the FCL

D1 D2 D D branch, which releases the overcurrent pressurei on the IGBTs and1 2diodes in the i converter and branch, which releases the overcurrent pressurefault on the IGBTs and diodes in the fconverterault and T T T T reduces the requirement1 of the2 DCCB in an interruption capacity.1 Once the2 converter is blocked under reduces the requirement of the DCCB in an interruption capacity. Once the converter is blocked under LFCL LFCL an overcurrent protection,R T 𝑇 and 𝑇 are switched on to bypassR 𝐿T , and the DCCB main breaker an overcurrent protection,FCL 3 𝑇 and 𝑇 areMOA switched on to bypassFCL 𝐿3 , and the DCCBMOA main breaker 𝑅 is opened (Figure 16c). Consequently,T shares the fault current withT the MOA in the DCCB, and is opened (Figure 16c). Consequently,4 𝑅 shares the fault current with4 the MOA in the DCCB, and the fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the the fault circuit inductanceMOA is reduced to quickly extinguish the faultMOA current. Afterward, when the current level slightly decreases, the fault current will be cut via the residential current breaker. In current level slightly decreases,(c) the fault current will be cut via the (residentiald) current breaker. In addition,𝑇,𝑇,𝑇, and 𝑇 are switched to their normal states. addition,𝑇,𝑇,𝑇, and 𝑇 are switched to their normal states. Figure Figure 16.16. Sequence of fault interruption. ( a) After fault occurrence and before fault detection, ( b) T𝑇 1 andand T𝑇2are are switched switched oﬀ off,,(c )(c DCCB) DCCB operates, operates,T3 and𝑇 andT4 are 𝑇 turned are turned on, (d on,) RCB (d) opens,RCB opens, and T 3andand 𝑇T 4andare turned𝑇 are turned oﬀ. off.

4. Design of the Enhanced Fault Current Limiting Circuit

4.1. Design Objective The EFCLC aims to reduce the requirement for the interruption capacity and isolation speed in the DCCB. Several factors are considered to achieve the design objective.

1. The peak value of the DC line current 𝑖 must be limited under the maximum breaking current of the DCCB 𝐼_ when the main breaker opens. 2. The fault current rising speed (𝑑𝑖⁄𝑑𝑡) must be lower than the largest rate of the current change withstood by the DCCB ((𝑑𝑖⁄ 𝑑𝑡)_). 3. In accordance with the fault current through the converter arms displayed in Figure 10, the freewheeling diodes still withstand overcurrent after blocking IGBTs. Thus, the DCCB is required to operate before the fault current reaches its maximum value. That is, the main breaker must open before the IGBT is blocked, thereby benefiting the system recovery and restart. The

time period from fault occurrence to the DCCB operation (𝑡) must be shorter than the time consumed from fault occurrence to blocking IGBTs (𝑡 ). Specifically, 𝑡 involves the fault detection time (𝑡) and DCCB operation time (𝑡_) (Figure 15). In accordance with the aforementioned points, the following condition can be obtained: max(iI ) < dc B _max (38)

max(/)(/)di dt< di dt dc B _max (39)

tttt>=+ bl op fd B_ op (40)

4.2. Determination of Boundary Condition Reference [33] mentioned that the hybrid DCCB has been tested to interrupt the maximum fault current of 9 kA within 2 ms. Thus, 𝐼_ is set to 9 kA in this study. The DCCB operation time 𝑡_ is set to 2 ms. Therefore, (𝑑𝑖⁄ 𝑑𝑡)_ is set to 9 kA/2 ms = 4.5 kA/ms. The fault detection time under the DC fault in the HVDC system has been reduced to within 1ms via a wavelet-based algorithm without using communication [40]. Consequently, the fault detection time 𝑡 can only be set to 1ms, and the capacitor discharging time 𝑡 must be more than 1 ms+2 ms =3 ms. The worst fault scenario has been adopted in this part as the PPF at the end of the DC overhead line. Furthermore, the threshold value of the arm current (𝐼) is normally set to twice as that of the rated current (𝐼) to block the IGBT. Therefore, I =2×I = 2 × 1000A = 2000A with 𝐼 is set to 1000 A in this study. Appl. Sci. 2019, 9, 1661 16 of 26

4. Design of the Enhanced Fault Current Limiting Circuit

4.1. Design Objective The EFCLC aims to reduce the requirement for the interruption capacity and isolation speed in the DCCB. Several factors are considered to achieve the design objective.

1. The peak value of the DC line current idc must be limited under the maximum breaking current of the DCCB IB_max when the main breaker opens. 2. The fault current rising speed (didc/dt) must be lower than the largest rate of the current change withstood by the DCCB ((di/dt)B_max). 3. In accordance with the fault current through the converter arms displayed in Figure 10, the freewheeling diodes still withstand overcurrent after blocking IGBTs. Thus, the DCCB is required to operate before the fault current reaches its maximum value. That is, the main breaker must open before the IGBT is blocked, thereby beneﬁting the system recovery and restart. The time period from fault occurrence to the DCCB operation (top) must be shorter than the time consumed from fault occurrence to blocking IGBTs (t ). Speciﬁcally, top involves the fault detection time bl t f d and DCCB operation time tB_op (Figure 15). In accordance with the aforementioned points, the following condition can be obtained:

max(idc) < IB_max (38)

max(didc/dt) < (di/dt)B_max (39)

tbl > top = t f d + tB_op (40)

4.2. Determination of Boundary Condition Reference [33] mentioned that the hybrid DCCB has been tested to interrupt the maximum fault current of 9 kA within 2 ms. Thus, IB_max is set to 9 kA in this study. The DCCB operation time tB_op is set to 2 ms. Therefore, (di/dt)B_max is set to 9 kA/2 ms = 4.5 kA/ms. The fault detection time under the DC fault in the HVDC system has been reduced to within 1 ms via a wavelet-based algorithm without using communication [40]. Consequently, the fault detection time t f d can only be set to 1ms, and the capacitor discharging time tbl must be more than 1 ms + 2 ms = 3 ms. The worst fault scenario has been adopted in this part as the PPF at the end of the DC overhead line. Furthermore, the threshold value of the arm current (Ith) is normally set to twice as that of the rated current (IN) to block the IGBT. Therefore, I = 2 I = 2 1000 A = 2000 A with I is set to 1000 A in this study. th × N × N The capacitor discharging current is deﬁned in Equation (9) on the basis of the fault current analysis discussed in Section2. The contributions from the AC grid and distributed line capacitance are omitted here. According to Constraint (38), the time during fault detection and main breaker operation delay is 3 ms.

( ) = ( ) = max idc idis t t=3 ms < IB_max 9 kA (41) The change rate in the DC fault current can be obtained using Equation (42); the change rate must be less than 4.5 kA/ms. max(didc/dt) = max(idis(t)0) < 4.5kA/ms (42) In reference to Equations (35) and (36), Constraint (40) must be considered to decrease the arm current at 3 ms less than the threshold value of blocking the IGBT after fault occurrence.

( ) = iarm t t=3ms < Ith 2kA (43)

Equations (35)–(37) express that the equivalent capacitance and inductance determine the fault current development and capacitor discharging time. Moreover, the fault current curve must be Appl. Sci. 2019, 9, 1661 17 of 26 separated into two stages using the proposed EFCLC (Figure 12b). Specifically, the fault current rising speed is higher in the first 1 ms stage than in the rest time. Thus, the fault current change rate within the first 1 ms must be limited by Constraint (42). Furthermore, the fault current value at 3 ms after fault occurrence must be obtained by superposing the fault current calculation in two discharging stages. Therefore, varying the fault circuit parameters, which are similarly considered in determining the capacitor discharging time, must be addressed.

4.3. Parametric Design Before the EFCLC is inserted in the fault circuit loop, the fault current is only limited via the smoothing reactor, which decides the maximum increase in the fault current rate. The minimum smoothing reactor can be obtained using Equation (9) considering the limitations in the DCCB withstanding fault current change rate (4.5 kA). The theoretical minimum smoothing reactor is 41.2 mH. However, the simulation result provides 43 mH with 4.2% error. The reason may be attributed to the consideration of DC line current under the normal states. The smoothing reactor Ldc is set to 50 mH considering the margin. The EFCLC will be inserted to limit fault current rising speed and amplitude after detecting a fault. Thus, the fault current rising speed is less than the fault detection time; thus, Constraint (39) is satisﬁed by properly selecting a smoothing reactor. An initial test with the EFCLC has been performed. The energy dissipation resistance RFCL is set to 50 Ω, and the FCL reactor LFCL is set to 100 mH. The simulation conditions “af” and “ah,” as listed in Table2, are compared here. The red dashed line in Figure 17 indicates that a fault occurs at 1.2 s and takes 1 ms to detect fault [37]. Furthermore, the delay in the IGBT of the EFCLC is disregarded here. The fault current change rate during ∆t1 is approximately 4 kA/ms, which is expectedly limited under the maximum current change rate of the hybrid DCCB. The EFCLC is inserted in the fault current circuit at 1.201 s, and the fault current experiences a sharp decrease ∆I1 because a part of the electrical energy is stored in LFCL. The fault current rising speed is lower during ∆t2 than during ∆t1. Therefore, the fault current at 1.203 s (the main breaker opens) is limited to approximately 6.6 kA, which is far below the maximum breaking current of the DCCB. Moreover, LFCL is bypassed by the thyristor while the main breaker opens, and the fault current extinguishment can be accelerated. The initial simulation result suggests that Constraint (41) leads to the minimum value of LFCL and RFCL. Therefore, the controlled match of LFCL and RFCL must be investigated. The fault current at 1.201 s is consistently 4 kA given the unchanged fault circuit parameter. Therefore, Figure 17 presents that

4kA ∆I + ∆I < 9kA (44) − 1 2 In comparison with the blue dashed-dotted line illustrated in Figure 17, two current curves share nearly the same part during ∆t2. Thus, ∆I1 can be obtained with a diﬀerence between the current values of the two discharging conditions. In accordance with Equation (9), ∆I1 is expressed as Equation (45).

∆I1 = i (t) i (t) (45) dis_a f t=1ms − dis_ah t=1ms Moreover, Equations (44) and (38) can be simpliﬁed as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s.

i (t) kA dis_ah t=3ms < 9 (46)

The equivalent resistance Req_ah and equivalent inductance Leq_ah are acquired as Equations (47) and (48), respectively. Thus, on the basis of Equation (9), the fault current idis_ah at 1.203 s can be calculated. If RFCL = 20 Ω, then LFCL must be larger than 46.4 mH to limit the fault current at 1.203 s under 9 kA. The minimum LFCL matched with RFCL = 20 Ω has been veriﬁed via a controlled simulation (Figure 18). The simulation results of the EFCLC with controlled RFCL and diﬀerent LFCL are compared (Figure 18). The fault current with the EFCLC (calculated LFCL_min = 46.4 mH with RFCL_min = 20 Ω) Appl. Sci. 2019, 9, x 18 of 26

values of the two discharging conditions. In accordance with Equation (9), ∆𝐼 is expressed as Equation (45). Δ= − Ii1_dis af() t i dis _ ah () t (45) tms==11 tms Moreover, Equations (44) and (38) can be simplified as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s. < itdis_ ah () 9 kA (46) tms=3

The equivalent resistance 𝑅_ and equivalent inductance 𝐿_ are acquired as Equations (47) and (48), respectively. Thus, on the basis of Equation (9), the fault current 𝑖_ at 1.203 s can be calculated. If 𝑅 =20 𝛺, then 𝐿 must be larger than 46.4mH to limit the fault current at 1.203 s under 9 kA. The minimum 𝐿 matched with 𝑅 =20 𝛺 has been verified via a controlled simulation (Figure 18). The simulation results of the EFCLC with controlled 𝑅 and different 𝐿 are compared (Figure 18). The fault current with the EFCLC (calculated 𝐿_ = 46.4 𝑚𝐻 with Appl.𝑅_ Sci. 2019=20, 9, 1661 𝛺) reaches 9106 A at 1.203 s. Thus, the error rate of the theoretical calculation18 of 26 is approximately 1.2% within a reasonable range, and the minimum 𝐿 can be set to 47mH. Constraint (43) can be analyzed using the arm current Equations (24) and (25) in Section 2. Setting reaches𝑅 =20 9106 𝛺 A, the at 1.203 𝐿_ s. Thus, is calculated the error rate as of219mH the theoretical to satisfy calculation Constraint is approximately(43). The arm 1.2%currents within are acompared reasonable under range, andthe thecalculated minimum 𝐿_LFCL can and be 𝐿 set_ to 47mH. obtained Constraint via a (43)simulation can be analyzed (Table 3). using The = thecalculated arm current 𝐿_ Equations leads (24)to the and maximum (25) in Section arm current2. Setting (2023.5RFCL A), which20 Ω, thecan LcontributeFCL_min is calculatedto blocking asthe 219 IGBTs. mH to The satisfy error Constraint in the calculation (43). The method arm currents may be are attributed compared to underthe circulating the calculated currentLFCL among_min andarms.LFCL However,_min obtained the si viamulation a simulation method (Table provides3). The expected calculated resultLs;FCL that_min is,leads the currents to the maximum of the six armarms currentare all (2023.5limited A), under which 2 cankA contributeat 1.203 s. to Ther blockingefore, the in IGBTs.the overall The errorview in of the constrains, calculation 𝐿_ method is mayapproximately be attributed 225 to themH circulating when 𝑅 current is set amongto 20 Ω arms.. However, However, 𝐿_ the simulation is selected method as 250 providesmH with expected𝑅 =20 results; 𝛺 considering that is, the the currents margin of in the the six parameter arms are allsetting. limited under 2 kA at 1.203 s. Therefore, in the overall view of constrains, LFCL_min is approximately 225 mH when RFCL is set to 20 Ω. However, L is selected as 250 mH with R = 20 Ω considering the margin in the parameter setting. FCL_min FCLRRRR=++2 eq_ ah fault dc FCL (47) Req_ah = R f ault + 2Rdc + RFCL (47) 2 L =++LLL2 eq_0 ah2 dc FCL (48) L = L3 + 2L + L (48) eq_ah 3 0 dc FCL

7000 Main breaker opens

6000 af 5000 ah EFCLC is inserted ΔI 4000 2 ΔI 3000 1

2000 DC DC Current(A) DC Current/A 1000

Fault occur 0 Δ Δ t1 t2

1.199 1.2 1.201 1.202 1.203 1.204 Time(s)Time/s Appl. Sci. 2019, 9, x 19 of 26 FigureFigure 17. 17.Simulation Simulation results results of of the the DC DC line line current current with with the the EFCLC. EFCLC.

10000

8000 L=43.6mH 6000 L=44mH

L=45mH 9,106 4000 L=46mH

L=47mH 9,050 2000

DC current/A 9000 8991 DC Current(A) 0 8,950

1.2029 1.203 1.203 1.203

-2000 1.199 1.2 1.201 1.202 1.203 1.204 Time/sTime(s)

FigureFigure 18.18. Simulation resultsresults ofof thethe controlledcontrolled R𝑅FCL andand di differentﬀerent L FCL𝐿. .

Table 3. Arm currents under the calculated and simulated 𝐿_.

𝑳𝑭𝑪𝑳 = 𝟐𝟏𝟗 𝒎𝑯,𝑭𝑪𝑳 𝑹 = 𝟐𝟎 𝛀 𝑳𝑭𝑪𝑳 = 𝟐𝟐𝟓 𝒎𝑯,𝑭𝑪𝑳 𝑹 = 𝟐𝟎 𝛀 Phase-A upper arm current 1712.7 A Phase-A upper arm current 1668.3 A Phase-A lower arm current 2023.4 A Phase-A lower arm current 1999.2 A Phase-B upper arm current 2023.5 A Phase-B upper arm current 1999.1 A Phase-B lower arm current 1704.4 A Phase-B lower arm current 1680.2 A Phase-C upper arm current 1876.5 A Phase-C upper arm current 1834.3 A Phase-C lower arm current 1858.7 A Phase-C lower arm current 1852.3 A

5. Discussion Several existing FCL schemes were compared in terms of FCL ability, cost, power loss, and influence on recovery and restart operations. The energy dissipation resistance-based FCL method in Reference [14], the inductance-based FCL scheme [15,35], and the proposed EFCLC were simulated under controlled conditions in this section.

5.1. Fault Current-Limiting Ability Comparison To investigate the FCL ability, the bias voltage adopted in the scheme presented in Reference [15] is omitted for convenience, and the values of the FCL reactor and energy dissipation resistance are maintained in comparison with the FCL ability (𝑅 = 20 𝛺, 𝐿 = 250 𝑚𝐻). In accordance with the FCL method in Reference [21], the AC feeding current can be limited via a parallel-connected thyristor, and the FCL ability is compared on the basis of the capacitor discharging current in the present study. Therefore, the AC feeding current is eliminated by switching off the start connector in the simulation while the DCCB operates. The simulation results of the arm and DC line currents with different FCL schemes are compared, as exhibited in Figure 19. The arm current with the resistance- based method (R-method) is limited to approximately 6 kA (Figure 19a). The arm currents with inductance-based method (I-method) and proposed scheme are restricted under 2 kA (Figure 19c and Figure 19e, respectively). The proposed method can accelerate the fault current decay while the main breaker opens. Thus, the freewheeling diodes and IGBTs can be protected from overcurrent for a long time, and the fault current isolation speed is shortened. The R-method has the worst FCL performance, thereby limiting the DC line current to approximately 18 kA (Figure 19b). By contrast, the I-method and the proposed method can restrain the DC line current under 5.5 kA (Figure 19d and Figure 19f, correspondingly). However, the DC line current with the I-method remains at a high level after the main breaker opens. In summary, the proposed scheme has an improved performance in limiting the fault current through converter arms and DC line.

Appl. Sci. 2019, 9, 1661 19 of 26

Table 3. Arm currents under the calculated and simulated LFCL_min.

LFCL = 219 mH, RFCL = 20 Ω LFCL = 225 mH, RFCL = 20 Ω Phase-A upper arm current 1712.7 A Phase-A upper arm current 1668.3 A Phase-A lower arm current 2023.4 A Phase-A lower arm current 1999.2 A Phase-B upper arm current 2023.5 A Phase-B upper arm current 1999.1 A Phase-B lower arm current 1704.4 A Phase-B lower arm current 1680.2 A Phase-C upper arm current 1876.5 A Phase-C upper arm current 1834.3 A Phase-C lower arm current 1858.7 A Phase-C lower arm current 1852.3 A

5. Discussion Several existing FCL schemes were compared in terms of FCL ability, cost, power loss, and inﬂuence on recovery and restart operations. The energy dissipation resistance-based FCL method in Reference [14], the inductance-based FCL scheme [15,35], and the proposed EFCLC were simulated under controlled conditions in this section.

5.1. Fault Current-Limiting Ability Comparison To investigate the FCL ability, the bias voltage adopted in the scheme presented in Reference [15] is omitted for convenience, and the values of the FCL reactor and energy dissipation resistance are maintained in comparison with the FCL ability (RFCL = 20 Ω, LFCL = 250 mH). In accordance with the FCL method in Reference [21], the AC feeding current can be limited via a parallel-connected thyristor, and the FCL ability is compared on the basis of the capacitor discharging current in the present study. Therefore, the AC feeding current is eliminated by switching oﬀ the start connector in the simulation while the DCCB operates. The simulation results of the arm and DC line currents with diﬀerent FCL schemes are compared, as exhibited in Figure 19. The arm current with the resistance-based method (R-method) is limited to approximately 6 kA (Figure 19a). The arm currents with inductance-based method (I-method) and proposed scheme are restricted under 2 kA (Figure 19c,e, respectively). The proposed method can accelerate the fault current decay while the main breaker opens. Thus, the freewheeling diodes and IGBTs can be protected from overcurrent for a long time, and the fault current isolation speed is shortened. The R-method has the worst FCL performance, thereby limiting the DC line current to approximately 18 kA (Figure 19b). By contrast, the I-method and the proposed method can restrain the DC line current under 5.5 kA (Figure 19d,f, correspondingly). However, the DC line current with the I-method remains at a high level after the main breaker opens. In summary, the proposed scheme has an improved performance in limiting the fault current through converter arms and DC line.

5.2. Cost

The main cost of the proposed EFCLC lies in fault current-limiting inductance LFCL, energy dissipation resistance RFCL, semiconductor switches, and surge arrester. Similar to the main breaker in the hybrid DCCB, the number of IGBT depends on the voltage across the EFCLC. The amount and parameter selection of a surge arrester are also determined by protection requirement. The EFCLC can be regarded as an auxiliary circuit to share the energy absorption and electrical pressure by limiting the fault current under an acceptable level. Although IGBTs and surge arrester in EFCLC lead to extra cost, the HVDC system can ensure the fault interruption with a low risk on the DCCB failure. Moreover, according to the simulation result in Figure 19, the R-method adopted in References [14,41] has a higher fault current level than the proposed method during the fault interruption period, thereby indicating extra cost on interruption capacity, surge arrester, and the cooling system. Therefore, it might be economic to have EFCLC in protection operation, given its strength in FCL ability. Furthermore, lower peak fault current indicates less investment in DCCB interruption capability. The main expenditure of the I-method depends on the SFCL inductance technology because its unique characteristics can limit the fault current without aﬀecting the system’s dynamic response speed. However, the immaturity of Appl. Sci. 2019, 9, 1661 20 of 26 the SFCL device leads to an increased cost to satisfy the protection requirement in terms of the system recovery and restart. Furthermore, compared with the proposed approach, the I-method requires additional cost in the energy dissipation component to accelerate the fault current extinguishment. In summary,Appl. Sci. 2019 taking, 9, x comprehensive consideration of economic eﬃciency and FCL performance, EFCLC20 of 26 deserves consideration to be applied in real project.

7000 20000

6000 15000 5000

4000 10000 3000

2000 5000

Arm current(A) 1000

DC line current(A) DC line 0 0

-1000 -5000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (a) (b)

2000 6000

5000 1500 4000

1000 3000

2000 500

1000 Arm current(A) Arm

0 current(A) line DC 0

-500 -1000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (c) (d)

2000 6000

5000 1500 4000

1000 3000

500 2000

1000 Arm current(A) Arm 0 DC line current(A) 0

-500 -1000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (e) (f)

FigureFigure 19. 19.FCL FCL ability ability comparison comparison among among existing existing methods: methods: ( a(a)) Arm Arm current current in in the the resistance-based resistance-based method,method, ( b(b)) DC DC line line current current in in the the resistance-based, resistance-based, ( c()c) Arm Arm current current in in the the inductance-based inductance-based method, method, (d(d)) DC DC line line current current in in the the inductance-based inductance-based method, method, ( e()e) Arm Arm current current in in the the proposed proposed method, method, ( f()f) DC DC lineline current current in in the the proposed proposed method. method.

5.3.5.2. Power Cost Loss As explained in Section 4.3, the proposed scheme requires a smoothing reactor of 50 mH, thereby The main cost of the proposed EFCLC lies in fault current-limiting inductance 𝐿, energy leading to power loss during the normal state. Considering that the resistance value of a 2 mH reactor dissipation resistance 𝑅, semiconductor switches, and surge arrester. Similar to the main breaker equalsin the 18.9hybrid mΩ DCCB,[42], the the power number loss ofP IGBTL is expressed depends on as Equationthe voltage (49). across the EFCLC. The amount and

parameter selection of a surge arrester are also2 determined by protection requirement. The EFCLC 4IdNRLLr can be regarded as an auxiliary circuitPL =to share the energy100% absorption and electrical pressure (49) by limiting the fault current under an acceptablePcableN level. ×Although IGBTs and surge arrester in EFCLC lead to extra cost, the HVDC system can ensure the fault interruption with a low risk on the DCCB failure. Moreover, according to the simulation result in Figure 19, the R-method adopted in References [14,41] has a higher fault current level than the proposed method during the fault interruption period, thereby indicating extra cost on interruption capacity, surge arrester, and the cooling system. Therefore, it might be economic to have EFCLC in protection operation, given its strength in FCL ability. Furthermore, lower peak fault current indicates less investment in DCCB Appl. Sci. 2019, 9, x 21 of 26

interruption capability. The main expenditure of the I-method depends on the SFCL inductance technology because its unique characteristics can limit the fault current without affecting the system’s dynamic response speed. However, the immaturity of the SFCL device leads to an increased cost to satisfy the protection requirement in terms of the system recovery and restart. Furthermore, compared with the proposed approach, the I-method requires additional cost in the energy dissipation component to accelerate the fault current extinguishment. In summary, taking comprehensive consideration of economic efficiency and FCL performance, EFCLC deserves consideration to be applied in real project.

5.3. Power Loss As explained in Section 4.3, the proposed scheme requires a smoothing reactor of 50 mH, thereby leading to power loss during the normal state. Considering that the resistance value of a 2 mH reactor

equals 18.9 mΩ [42], the power loss 𝑃 is expressed as Equation (49). 4IRL2 =×dN L r Appl. Sci. 2019, 9, 1661 PL 100% 21 of(49) 26 P cableN where 𝐼 is the rated DC line current, 𝑅 = 0.00945 Ω/mH is based on Reference [43], 𝐿 is the where I is the rated DC line current, R = 0.00945 Ω/mH is based on Reference [43], L is the smoothingdN reactor, and 𝑃 is the ratedL DC line power. Thus, the smoothing reactorr in the smoothing reactor, and P is the rated DC line power. Thus, the smoothing reactor in the proposed proposed scheme causescablrN 0.135% power loss in comparison with the rated DC line power, thus scheme causes 0.135% power loss in comparison with the rated DC line power, thus denoting a denoting a promising economic efficiency. promising economic eﬃciency.

5.4.5.4. Inﬂuence Influence on on Fault Fault Current Current

Figure 20a,b presents the influence of 𝑅 and 𝐿 on the DC line current, respectively. When Figure 20a,b presents the influence of RFCL and LFCL on the DC line current, respectively. When 𝑅 increases but 𝐿 remains at 250 mH, the DCCB capability requirement is low, and the fault RFCL increases but LFCL remains at 250 mH, the DCCB capability requirement is low, and the fault current extinguishment is accelerated (Figure 20a). When 𝐿 increases but 𝑅 remains at 20 Ω, current extinguishment is accelerated (Figure 20a). When LFCL increases but RFCL remains at 20 Ω, thethe peak peak value value of of the the fault fault current current decreases decreases but but the the time time spent spent in in the the fault fault current current interruption interruption is is unaffected. Therefore, 𝐿 in the proposed scheme hardly influences the dynamic response or the unaffected. Therefore, LFCL in the proposed scheme hardly influences the dynamic response or the faultfault current current extinguishment. extinguishment.

12000 12000 without EFCLC without EFCLC L =200mH FCL 10000 R =10Ω 10000 FCL L =300mH FCL R =20Ω 8000 FCL L =400mH 8000 FCL R =50Ω FCL L =500mH FCL 6000 R =100Ω 6000 FCL

4000 4000

2000 2000 DC line current(A) line DC current(A) line DC

0 0

1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 Time(s) Time(s) (a) (b)

Figure 20. DC line current with variables (a) 𝑅 and (b) 𝐿 . Figure 20. DC line current with variables (a) RFCLand (b) LFCL.

5.5.5.5. Inﬂuence Influence on on Energy Energy Absorption Absorption Because of the isolation eﬀect of the thyristor on the AC feeding current, the fault current during fault interruption is mainly the freewheeling current, given the energy stored in the smoothing reactor, whose path is depicted in Figure 21. The energy stored in the smoothing reactor can be obtained using Equation (50). 2 EL = 1/2Ldci f ault(top) (50) where Ldc is the smoothing reactor; i f ault top is the fault current through the DC line while the DCCB operates, which can be obtained using Equation (9); and t0 is the time point of fault occurrences. s top t − 0 Ceq Idis0ω0 i f ault(top) = e− τ [Udc sin(ω1(top t0)) sin(ω1(top t0) θ)] (51) Leq − − ω1 − − Appl. Sci. 2019, 9, x 22 of 26

D1 D2 Ldc i fault

+ − T1 T2 U M L RCB LFCL R T M FCL 3 MOA + − + U − UR M T C 4 MOA

FigureFigure 21.21. FaultFault currentcurrent pathpath duringduring faultfault interruption.interruption.

Because of the isolation effect of the thyristor on the AC feeding current, the fault current during fault interruption is mainly the freewheeling current, given the energy stored in the smoothing reactor, whose path is depicted in Figure 21. The energy stored in the smoothing reactor can be obtained using Equation (50). E = 1/2Li2 ( t ) L dc fault op (50) where 𝐿 is the smoothing reactor; 𝑖(𝑡) is the fault current through the DC line while the

DCCB operates, which can be obtained using Equation (9); and 𝑡 is the time point of fault occurrences.

tt− − op 0 C I ω =−−−−τ eq ωωθdis00 itfault( op ) e [ U dc sin(10 ( tt op )) sin( 10 ( tt op ) )] (51) L ω eq 1

The energy absorbed by 𝑅 can be expressed as ==22 EURdtRiRdtR(/ R FCL ) (( FCL fault )/) FCL (52)  Then, the energy absorbed in the MOA of the DCCB can be expressed as E =−EE M LR (53)

Figure 20b displays that a large smoothing reactor will lead to a small 𝑖(𝑡). Thus, the energy stored in the smoothing reactor will decrease, thereby indicating a reduced energy consumed in the MOA and decreased time spent in the fault current interruption. Moreover, the fault detection time can influence the energy stored in the smoothing reactor in a positive relationship. Thus, determining the energy absorbed in 𝑅 must consider the effect of inductance and fault detection time to reduce stress on the MOA of the DCCB. The simulation result presented in Figure 22a shows that a large 𝑅 results in minimal energy absorption in the MOA of the DCCB given the low fault current level at the DCCB operation time point and shared energy absorption. Similarly, a large 𝐿 denotes a minimal energy absorbed in the MOA because an increase in 𝐿 leads to a low current and energy stored in 𝐿 when the main breaker opens. Overall, 𝑅 and 𝐿 can limit the fault current to a relatively low level to reduce the energy absorbed in the MOA of the DCCB. However, a balance between the DCCB and EFCLC is observed in terms of energy consumption during the fault current-limiting period and fault current extinguishment stage. Therefore, the tradeoff between FCL performance and additional cost on the snubber circuit and cooling system of the EFCLC must be considered. Appl. Sci. 2019, 9, 1661 22 of 26

The energy absorbed by RFCL can be expressed as Z Z 2 2 ER = (UR/RFCL)dt = ((RFCLi f ault) /RFCL)dt (52)

Then, the energy absorbed in the MOA of the DCCB can be expressed as

EM = EL ER (53) − Figure 20b displays that a large smoothing reactor will lead to a small i f ault top . Thus, the energy stored in the smoothing reactor will decrease, thereby indicating a reduced energy consumed in the MOA and decreased time spent in the fault current interruption. Moreover, the fault detection time can influence the energy stored in the smoothing reactor in a positive relationship. Thus, determining the energy absorbed in RFCL must consider the effect of inductance and fault detection time to reduce stress on the MOA of the DCCB. The simulation result presented in Figure 22a shows that a large RFCL results in minimal energy absorption in the MOA of the DCCB given the low fault current level at the DCCB operation time point and shared energy absorption. Similarly, a large LFCL denotes a minimal energy absorbed in the MOA because an increase in LFCL leads to a low current and energy stored in Ldc when the main breaker opens. Overall, RFCL and LFCL can limit the fault current to a relatively low level to reduce the energy absorbed in the MOA of the DCCB. However, a balance between the DCCB and EFCLC is observed in terms of energy consumption during the fault current-limiting period and faultAppl. current Sci. 2019 extinguishment, 9, x stage. Therefore, the tradeoff between FCL performance and additional23 of 26 cost on the snubber circuit and cooling system of the EFCLC must be considered.

x 107 4.5 22 4 20 L =500mH L =200mH 3.5 FCL 18 FCL L =400mH L =300mH FCL 16 FCL 3 L =300mH FCL L =400mH 14 FCL 2.5 L =200mH

(J) L =500mH FCL FCL (ms)

M 12 2 IN E t 10 1.5 8 1 6 0.5 4 0 20 40 60 80 100 20 40 60 80 100 R (Ω) R (Ω) FCL FCL (a) (b)

FigureFigure 22. 22.Characteristic Characteristic curves curves of absorbedof absorbed energy ener andgy and interruption interruption time time under under variables variables (a) RFCL (a)and 𝑅 (band) LFCL (b.) 𝐿.

5.6.5.6. Inﬂuence Influence on on Fault Fault Interruption Interruption Time Time L AlthoughAlthough FCL𝐿is involvedis involved in in the the EFCLC, EFCLC, it canit can still still be be bypassed bypassed by by the the thyristor thyristor after after the the main main breakerbreaker operates. operates. Thus,Thus, thethe faultfault currentcurrent extinguishment extinguishment speedspeed cannot cannot be be delayed delayed due due to to large large R inductance.inductance. AsAs mentionedmentioned in in Section Section 5.5, 5.5 ,the the fault fault current current level level is restricted is restricted by a by large a large 𝑅 andFCL and𝐿, LFCLand, andthe theinterruption interruption time time can can be bereduced reduced at at a alo loww fault fault current level atat thethe beginningbeginning of of fault fault extinguishment.extinguishment. According According to theto expressionthe expression of the attenuationof the attenuation coeﬃcient duringcoefficient the faultduring interruption the fault R expressedinterruption in Equation expressed (37), in theEquation large (37),FCL canthe acceleratelarge 𝑅 extinguishment can accelerate speed.extinguishment In summary, speed. the In R L interruptionsummary, the time interruption is reduced whentime is the reduced values when of FCL theand valuesFCL ofare 𝑅 high. and This 𝐿 result are agreeshigh. This with result the simulationagrees with result the demonstratedsimulation result inFigure demonstrated 22b. in Figure 22b.

5.7. Practicality and Necessity of Proposed Circuit According to the study in this section, the proposed FCL circuit has better performance in limiting fault current under DC pole-to-pole fault, compared with previous FCL method under same parameter setting. In the viewpoint of reality, the power loss during normal state is considered acceptable as analyzed in section 5.3. In order to cooperate with protection relaying, the proposed FCL circuit is installed at the ends of transmission line so that communication delay among DCCB, measure point and protection relay could be reduced. Moreover, big smoothing reactor (200 mH) in [42–44] would influence the dynamic response speed and proposed FCL circuit could help reduce value of smoothing reactor for better performance of dynamic response. However, it requires further investigation on economic efficiency of proposed method, considering previous FCL methods, such as superconductor based fault current limiter, FCL circuit and converter topology based approach. Another point should be noted that the proposed EFCLC would make more contribution to fault interruption and clearance, compared with traditional FCL behavior with DC terminal reactor. The basic advantage of EFCLC over DC terminal reactor could be summarized as following aspects. Firstly, EFCLC is only triggered as fault detected to limit fault current, thereby having no influence on normal state and system dynamic response. By contrast, to achieve the same level of FCL performance of EFCLC, larger DC terminal reactor is required even under normal state, which does affect system dynamic response. Seconded, compared with DC terminal reactor, EFCLC could accelerate fault clearing speed due to its energy dissipation resistor. The last but not the least, the FCL inductor in EFCLC would be bypassed after IGBT blocks. Hence, the fault isolation time would be reduced to some degree since remained inductor would delay the fault current clearance.

5.8. Effectiveness of the Proposed Circuit Appl. Sci. 2019, 9, 1661 23 of 26

5.7. Practicality and Necessity of Proposed Circuit According to the study in this section, the proposed FCL circuit has better performance in limiting fault current under DC pole-to-pole fault, compared with previous FCL method under same parameter setting. In the viewpoint of reality, the power loss during normal state is considered acceptable as analyzed in Section 5.3. In order to cooperate with protection relaying, the proposed FCL circuit is installed at the ends of transmission line so that communication delay among DCCB, measure point and protection relay could be reduced. Moreover, big smoothing reactor (200 mH) in [42–44] would influence the dynamic response speed and proposed FCL circuit could help reduce value of smoothing reactor for better performance of dynamic response. However, it requires further investigation on economic efficiency of proposed method, considering previous FCL methods, such as superconductor based fault current limiter, FCL circuit and converter topology based approach. Another point should be noted that the proposed EFCLC would make more contribution to fault interruption and clearance, compared with traditional FCL behavior with DC terminal reactor. The basic advantage of EFCLC over DC terminal reactor could be summarized as following aspects. Firstly, EFCLC is only triggered as fault detected to limit fault current, thereby having no influence on normal state and system dynamic response. By contrast, to achieve the same level of FCL performance of EFCLC, larger DC terminal reactor is required even under normal state, which does affect system dynamic response. Seconded, compared with DC terminal reactor, EFCLC could accelerate fault clearing speed due to its energy dissipation resistor. The last but not the least, the FCL inductor in EFCLC would be bypassed after IGBT blocks. Hence, the fault isolation time would be reduced to some degree since remained inductor would delay the fault current clearance.

5.8. Effectiveness of the Proposed Circuit With application of the proposed EFCLC in fault loop, the requirement of DCCB’s interruption ability is reduced, and fault current interruption speed is accelerated. A comparison is performed in Table4 between a fault situation with EFCLC and that without EFCLC, in terms of maximum fault current and fault interruption time. As mentioned in Section 4.3, LFCL_min and RFCL are set as 250 mH and 20 Ω in the test circuit. The test results shown in Table3 reflect that the peak fault current needed to interrupt at DCCB operation is reduced from 12.4 kA to 5.1 kA with the help of EFCLC. Meanwhile, the time taken for the whole fault interruption process decreases from 34.8 ms to 13.6 ms. In summary, the effectiveness of the proposed circuit is verified, and reduced peak fault current and accelerated fault interruption would contribute to lower cost in relay and fast fault clearance.

Table 4. Eﬀectiveness veriﬁcation of enhance fault current limiting circuit.

Term Requirement of Fault Current Interruption Fault Interruption Time Without EFCLC 12.4 kA 34.8 ms With EFCLC 5.1 kA 13.6 ms Improvement 41.1% 39.1%

6. Conclusions An EFCLC has been proposed and investigated in this study to reduce the DCCB requirement in terms of fault interruption capability and breaking speed. The EFCLC mainly consists of the energy dissipation resistor and FCL reactor. These devices are plugged into the fault loop after fault detection to limit the fault current rising speed and fault current level. Thus, while the DCCB operates, the fault current level is restrained, and the energy stored in the smoothing reactor is also reduced. Consequently, the fault current extinguishment stage can be accelerated given the increased energy dissipation resistor and decreased energy storage. Furthermore, the FCL reactor can be bypassed to accelerate the decaying of the freewheeling current. Moreover, the AC feeding current is eliminated via the bidirectional parallel-connected thyristor, whose feasibility and effectiveness have been verified in Appl. Sci. 2019, 9, 1661 24 of 26 existing works. Thus, this study focused on the methods for limiting fault current caused by capacitor discharging in the FCLC design. The proposed EFCLC has been verified to limit fault current under an expected level with a proper parameter setting on components. However, the performance tradeoff and additional cost of the EFCLC must be considered in terms of the cooling system, surge arrester, and overvoltage protection. The development of the EFCLC in the multi-terminal HVDC system, the related fault protection scheme, and the FRT strategy will be investigated in future research.

Author Contributions: All the authors have contributed to this paper in different aspects. Q.H. proposed the original concept and wrote the original draft. K.L. and L.Q. acted as supervisor and gave suggestions on paper improvement. S.Z., X.L. and Y.L. helped with software simulation and methodology improvement. Last but not least, H.D. contributed to paper editing and reviewing. Funding: This work was supported in part by the National Key Research and Development Project (Grant No. 2018YFB0904600). Conflicts of Interest: The authors declare no conflict of interest.

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