Views Out- Put of Each Phase to Make Sure That the Functional Safety Has Actually Been Achieved

TRADEOFFS BETWEEN PERFORMANCE AND

RELIABILITY IN INTEGRATED CIRCUITS

DANIEL J. WEYER

Submitted in partial fulﬁllment of the requirements

for the degree of Doctor of Philosophy

Department of Electrical Engineering and Computer Science

CASE WESTERN RESERVE UNIVERSITY

May 2019 CASE WESTERN RESERVE UNIVERSITY

SCHOOL OF GRADUATE STUDIES

We hereby approve the dissertation of Daniel J. Weyer

candidate for the degree of Doctor of Philosophy*.

Committee Chair Dr. Christos Papachristou

Committee Member Dr. Phillip Feng

Committee Member Dr. Soumyajit Mandal

Committee Member Dr. Francis Merat

Committee Member Dr. Daniel Saab

Date of Defense

April 9, 2019

*We also certify that written approval has been obtained

for any proprietary material contained therein. Contents

List of Tables v

List of Figures ix

Acknowledgments xx

Abstract xxii

1 Introduction 1 1.1 Problem Statement ...... 4 1.2 Outline ...... 6

2 Reliability of ICs/ASICs 8 2.1 Reliability analysis ...... 16 2.1.1 Time To Failure ...... 16 2.2 Continuous Distributions ...... 21 2.2.1 Exponential Distribution ...... 21 2.2.2 Normal (Gaussian) Distribution ...... 23 2.2.3 lognormal Distribution ...... 26 2.2.4 Weibull Distribution ...... 30 2.2.5 Gamma Distribution ...... 36 2.3 Discrete Distributions ...... 39

i CONTENTS

2.3.1 Poisson Distribution ...... 39 2.3.2 Chi-Square Disribution ...... 42

3 Aging Mechanism of CMOS Devices 49 3.0.1 xBTI = NBTI and PBTI ...... 50 3.0.2 Hot Carrier Injection (HCI) ...... 55 3.0.3 TDDB ...... 60 3.0.4 Electromigration (EM) ...... 66 3.0.5 Industry Standard Reliability Calculations ...... 70 3.0.6 Summary of IC/ASIC Aging/Degradation Models ...... 75

4 Interconnects 77 4.1 Metal and Dielectric Diﬀusion ...... 78 4.2 Electromigration Failure in Interconnects ...... 82 4.3 Reliability and Electromigration (EM) ...... 84 4.4 Interconnect Resistance ...... 89 4.4.1 Interconnect Scaling ...... 116 4.4.2 Dennard scaling relationship to Moore’s law ...... 132 4.4.3 ITRS scaling ...... 133 4.4.4 Interconnect Dielectric scaling ...... 153 4.4.5 Electromigration (EM) in interconnect wires ...... 158 4.5 ITRS Interconnect Scaling challenges ...... 164 4.5.1 Barrier Metal ...... 165 4.5.2 Inter-metal Dielectrics (ILD) ...... 166 4.5.3 Interconnect delay challanges ...... 166 4.5.4 Industry standards for EM ...... 170 4.5.5 EM percent lifetime equations ...... 176 4.6 Electromigration Copper Model parameters ...... 178

ii CONTENTS

4.7 Future of Interconnects ...... 193 4.7.1 Cobalt ...... 196 4.7.2 Ruthenium ...... 197

5 Trade offs for Lifetime versus Performance 199 5.1 Electromigration tradeoffs ...... 201 5.1.1 Current density (j) effects on gate delay ...... 210 5.2 Synopsys Process Development Kit ...... 211 5.2.1 Interconnect Resistivity ...... 212

5.2.2 Synopsys 28/32 PDK EM tradeoﬀs by Imax ...... 234

6 Lifetime Driven Design Methodology 238 6.1 OpenCore Amber 25 Microprocessor ...... 239 6.2 High Level Description of the Methodology ...... 241 6.3 Detailed Description of the Methodology ...... 245

7 Results 260 7.1 Layout ...... 260 7.2 Amber 25 Layout analysis ...... 266 7.3 EM analysis ...... 277

8 Summary 282

9 Discussion 284

10 Acronyms 287

11 Appendix 297 11.1 Tool Versions ...... 297 11.2 Amber 25 Testbench Source ...... 299 11.3 ICC TCL reporting ...... 306

iii CONTENTS

11.4 Python script to generate ALF ﬁle ...... 311 11.5 ITF (Interconnect Technology File) ...... 317 11.6 StarXtract ...... 323 11.7 Hspice Simulations ...... 328 11.7.1 Lifetime Comparisons ...... 328 11.7.2 Hspice Resistance Sweeps ...... 337 11.7.3 Clock Buﬀer hspice Simulations ...... 359 11.8 Semiconductor properties ...... 365 11.9 Nernst-Einstein relationship of drift velocity ...... 367 11.10Intel and Synopsys 90nm parameters ...... 370

12 Published Papers 374

iv List of Tables

4.1 Interconnection roadmap for scaling.[IRDS, 2016] ...... 86 4.2 Interconnect, etc. diﬃcult challenges.[IRDS, 2016] ...... 86 4.3 Resistivity and temperature coeﬃcient at 20 ◦C [GSU, 2017] . . . . . 94 4.4 Resistivity temperature variation for bulk pure metals ...... 101 4.5 Intel Resistivity Roadmap ...... 102 4.6 Intel 130nm process ...... 108 4.7 Dennard Scaling ...... 128 4.8 Intel Node Scaling ...... 129

4.9 Intel Jmax and ITRS Imax Scaling ...... 130 4.10 Intel and ITRS predicted Resistivity ...... 131

4.11 ITRS Jmax and Imax Scaling ...... 135

4.12 Intel Jmax and Imax Scaling ...... 136 4.13 Dennard Reliability effects ...... 151 4.14 Dennard Reliability effects on EM ...... 152 4.16 Interconnect’s Dielectric by Node ...... 153 4.15 Interconnect Dielectric ...... 157 4.17 EM Terms ...... 161 4.18 Projected electrical specifications of logic core device. [IRDS, 2016] . 167 4.19 Table: Projected power-performance-area (PPA) metrics of functional datapath. [IRDS, 2016] ...... 169

v LIST OF TABLES

4.20 IC/ASIC Aging Properties ...... 175 4.21 Black’s law Regression ...... 180

4.22 Black’s law Regression M2 ...... 182

4.23 M2 CDF...... 184 4.24 Black’s Law from Tan and Vairagar ...... 190

4.25 Black’s Law t50 for various Temperatures ...... 191

4.26 Jmax for various Temperatures and Failure rates ...... 192

5.1 trade oﬀ for n = 1 and α = 1 and n = 2 and Sakurai-Newton α = 1.2 205 5.2 Temperature verses Performance and Lifetime. Lowering the temperature has a more pronounced impact on the lifetime than the Perfor- mance increase...... 209 5.3 Synopsys PDK3D45:Metal Layers ...... 211 5.4 Comparison Synopsys 28/32nm to the Intel 32nm process ...... 214 5.5 BEOL for 28G and 28LP Products for Global Foundries Cu interconnects [Augur et al., 2012] ...... 218 5.6 ILD parameters for Synopsys 28/32 PDK ...... 220 5.7 Synopsys 28/32nm ILD parameters ...... 223

5.8 M1 dimensions for Synopsys 28/32 PDK ...... 224 5.9 Interconnect resistance parameters for Synopsys 28/32 PDK . . . . . 224 5.10 Via resistivity parameters for 25 ◦C [Lin et al., 2007] ...... 225 5.11 Via resistivity calculated for diﬀerent Temperatures [Lin et al., 2007] 225 5.12 Dielectric and Capacitance parameters for Synopsys 28/32nm PDK . 226 5.13 EM parameters for Synopsys 28/32nm PDK ...... 226

5.14 Synopsys 28/32nm Tsubstrate temperature rise based on Tambient and percent rise in temperature of the IC/ASIC ...... 228

5.15 Imax, Imaxw and Jmax for various Tuse temperatures ...... 235

5.16 Synopsys 28/32 nm PDK data for FEM EM temperature derating . . 235

vi LIST OF TABLES

6.1 Comparison of Lifetime calculations between ICC and hspice . . . . . 251

6.2 Synopsys 28/32 nm PDK data for the EM function FEM temperature derating ...... 252

6.3 Synopsys 28/32 nm PDK data for the EM function FEM temperature derating ...... 255

6.4 Synopsys 28/32 nm PDK data for the EM function FEM temperature derating ...... 256 6.5 Calculations for EM I and J for values for metal layers from Synopsys 28/32nm PDK ...... 256 6.6 Calculations for EM I and J values calculated for Vias ...... 257

7.1 Design Exploration (Max performance - meets timing) ...... 280 7.2 Design Exploration (Increment the clock period by 1 ns) ...... 280 7.3 Design Exploration (Iterate until 15 year target met) ...... 281 7.4 Design Exploration (Iterate until 15 year target met) ...... 281 7.5 Design Exploration (Power 15 year target met) ...... 281

10.1 Acronyms ...... 287

11.1 Tool Versions ...... 298 11.2 Percent change in tp for the 28/32nm inverter with ±40 change in interconnect resistance ...... 347 11.3 Delay change in tp for a typical 28/32nm inverter with ±40 change in interconnect resistance ...... 349

11.4 Iomax change for a typical 28/32nm inverter with ±40 change in interconnect resistance ...... 351 11.5 Percent change in tp for the 90nm inverter with ±40 change in interconnect resistance ...... 353

vii LIST OF TABLES

11.6 Delay change in tp for a typical 90nm inverter with ±40 change in interconnect resistance ...... 355

11.7 Iomax change for a typical 90nm inverter with ±40 change in interconnect resistance ...... 357

11.8 Capacitance load eﬀect on power, Jmax and Lifetime ...... 364 11.9 Semiconductor Properties ...... 366 11.10Boundry Conditions ...... 369 11.11Intel:Metal Layers ...... 370 11.12Synopsy 90nm PDK Metal Layers ...... 371 11.13Synopsy 90nm PDK simpliﬁed Metal Layers ...... 372 11.14Synopsy 90nm PDK capacitance for Metal Layers ...... 373

viii List of Figures

1.1 Perspective on sizes. [Bohr, 2014] ...... 3

2.1 The IC/ASIC Shrinking Bathtub ...... 9 2.2 Aging effects of a CMOS inverter [Bafleur and Perdu, 2016]...... 9 2.3 Typical FIT rates of electronic components and trend due to aging or degradation. [Hillman, 2009] ...... 10 2.4 Total guard banding of 15% is large. Blue shows the faults due to process variation. Red shows aging degradation [Alam et al., 2008]. . 11 2.5 Warranty Costs ...... 12 2.6 PDF f(t). f(t) represents the probability of finding a device failure between t and t+dt [McPherson, 2013] ...... 17 2.7 CDF F(t). F(t) represents the fraction of the population that failed [policeanalyst.com, 2012] ...... 17 2.8 Comparison of PDF, CDF and R [Andy, 2018] ...... 18 2.9 The Exponential PDF [Wikipedia, 2017b] ...... 22 2.10 The Exponential CDF [Wikipedia, 2017b] ...... 22 2.11 PDF f(t) for Normal Distribution [Kapur and Pecht, 2014] ...... 25 2.12 PDF f(t) of the Log normal Distribution for σ = 0.1 and σ = 0.5. [Kapur and Pecht, 2014] ...... 28 2.13 The Weibull PDF [Wikipedia, 2017d] ...... 31

ix LIST OF FIGURES

2.14 The Weibull distribution showing use in Reliability [Spinato et al., 2009] 32 2.15 The Weibull CDF [Wikipedia, 2017d] ...... 33 2.16 The Weibull distribution plot in terms of Weibits [McPherson, 2013] . 34 2.17 The Weibull distribution plot in terms of Weibits [McPherson, 2013] . 34 2.18 Comparison of the PDF, CDF and hazard functions for Exponential, Normal, lognormal and Weibull [Industrial-Electronics, 2017] . . . . . 35 2.19 The Gamma function for real values of α [Pishro-Nik, 2017] . . . . . 37 2.20 PDF for the Gamma Distribution for values α and λ [Pishro-Nik, 2017] 37 2.21 The Poisson PMF [Wikipedia, 2017c] ...... 41 2.22 The Poisson CDF [Wikipedia, 2017c] ...... 41 2.23 The Chi-Square PDF [Wikipedia, 2017a] ...... 43 2.24 The Chi-Square CDF [Wikipedia, 2017a] ...... 44 2.25 Chi Square Statistic [Berman, 2017] ...... 44

3.1 Threshold voltage shifts as a function of stress time under NBTI vs channel length [Yan-Rong et al., 2010] ...... 51 3.2 CMOS Inverter xBTI stress in a design [Shiyanovskii et al., 2009c] . 51 3.3 Silicon Lattice interface at Gate Oxide [Shiyanovskii et al., 2009c] . . 52 3.4 Illustrating the effects of PMOS NBTI effect on a CMOS inverter under stress [Shiyanovskii et al., 2009c] ...... 53 3.5 Measurement of NBTI at different temperatures ...... 54

3.6 HCI eﬀects: CHE(V d = V g), DAHC(V d = 2Vg), SGHE Vd >

Vg,SHE(|Vsub| >> 0 [Shiyanovskii et al., 2009c] ...... 56 3.7 A. Dielectric degradation occurs due to broken bonds/trap-creation in the dielectric material and at the SiO2/Si interface [McPherson, 2013] 60 3.8 Poly Short due to TDDB [McPherson, 2013] ...... 61 3.9 The four models best ﬁttings to the same set of accelerated TDDB data [McPherson, 2013]...... 65

x LIST OF FIGURES

4.1 Interconnection distribution.[Borkar, 1999] ...... 77 4.2 Diagram showing an ideal (sharp) interface of the metal and dielectric materials [Balasinski, 2016] ...... 78 4.3 Diagram showing a diﬀused metal-dielectric interface after the penetration of the metal into the dielectric [Balasinski, 2016] ...... 79 4.4 Diagram showing the metal dielectric interface with an energy diagram showing how metal atoms diﬀuse out of the metal matrix into the dielectric [Balasinski, 2016] ...... 79 4.5 Negative heat of oxide formation per oxygen atom in various metals [Balasinski, 2016] ...... 80

4.6 Cross section of the Al SiO2 interface [Balasinski, 2016] ...... 81 4.7 Failures in a damascene line. (a) Failure dominated by the void nucleation phase. (b) Failure dominated by void nucleation migration and growth [Orio, 2010]...... 83 4.8 EM lifetime variation as a function of the interconnect dimensions [Orio, 2010]...... 84 4.9 Active layers FEOL, MOL Local interconnect Li and BEOL Metal interconnect ...... 85 4.10 Experiment and model of lifetime scaling versus interconnect geometry

(∆Lcr).[IRDS, 2016] ...... 87

4.11 Evolution of Jmax (from device performance) and JEM (from targeted lifetime).[IRDS, 2016] ...... 88 4.12 Inter-connectection distribution...... 89 4.13 Comparison of the manufacturing process step diﬀerences between Al and Cu. [Khan and Kim, 2011] ...... 91 4.14 Copper dual-damascene fabrication process: Via patterning and Via and trench patterning [Orio, 2010]...... 92

xi LIST OF FIGURES

4.15 Copper dual-damascene: Barrier layer deposition and Cu seed deposition. Cu electroplating and excess removal by chemical mechanical polishing [Orio, 2010]...... 92 4.16 Copper dual-damascene: Capping layer deposition [Orio, 2010]. . . . 93 4.17 Interconnect dimensions...... 95 4.18 3 wire segments with different dimensions and branches...... 95 4.19 Illustrating different materials vias and interconnect wires...... 96 4.20 TCR (α) versus line width. [Guillaumond et al., 2003] ...... 100 4.21 TCR (α) versus line width. [Huang et al., 2008a] ...... 100 4.22 Copper grain boundries [Sun, 2009]...... 103 4.23 Grain boundry scattering [Cornelius and Toimil-Molares, 2010]. . . . 103 4.24 Surface scattering [Cornelius and Toimil-Molares, 2010]...... 103 4.25 Resitivity of Cu versus thickness; all surface scattering elastic, ρ = 1 [Yarimbiyik et al., 2006]...... 104 4.26 The effects on Cu resistivity of line width scaling due to scattering [Saraswat, 2003]...... 105 4.27 The resistivity of copper wire as a function of line width. The total resistivity is from scattering at the liner interface, grain boundary (GB) scattering and bulk resistivity (electron-phonon scattering) [Roberts et al., 2015]...... 105 4.28 Thickness dependence of the resistivity of evaporated copper films at 293 (◦K) Experimental data (—) calculated according to the statistical model [Finzel and Wimann, 1985]; (- - -) calculated on the basis of best fit [Schmiedl et al., 2008]...... 107 4.29 Bulk resistivity of various metals. [GSU, 2017] ...... 109 4.30 Sheet resistance as a function of layer pitch [Tyagi et al., 2000a] . . . 109 4.31 Sheet resistance as a function of layer pitch [Brain, 2016] ...... 110

xii LIST OF FIGURES

4.32 Cu line resistivity increases rapidly as line width decreases. The actual Van der Pauw pad thickness is label next to the data point. The resistivity of the largest pad with a 0.26 um thickness matches the measured data very well. [Jiang et al., 2001] ...... 111 4.33 van der Pauw Resistivity measurment technique. [Gadkari, 2005] . . . 112 4.34 Modeled Cu resistivity as a function of both inverse width and height. Model assumes no grain boundary scattering and ρ = 0, completely inelastic sidewalll scattering. [VanOlmen et al., 2007] ...... 113 4.35 Cu has excellent electromigration resistance. [Heidenreich et al., 1998] 114 4.36 Multiple interconnect stacks for cost, density and performance (from ITRS)...... 115 4.37 Technology for 90nm to 22nm nodes (from ITRS)...... 115 4.38 Parallel plate capacitance model of interconnect wire [Brain, 2016] . . 116 4.39 Capacitance vs Resistance change [Stork, 2005] ...... 117 4.40 Interconnect scaling [Brain, 2016] ...... 117

4.41 Ctotal for the line includes capacitance components from line-to-line and layer-to-layer [Brain, 2016] ...... 118 4.42 RC Delay Calculation Wire [Bohr, 1995] ...... 120 4.43 Interconnect scaling is limiting speed increases. [Bohr, 1995] . . . . . 120 4.44 Global line scaling. [Diebold, 2016] ...... 121 4.45 Delay versus Pitch. [Diebold, 2016] ...... 121 4.46 Novel materials innovations drive contact and BEOL RC improvement (reduction). [Besser, 2017a] ...... 122

4.47 Dennard scaling underestimates Intel and ITRS for M1 (y axis = Pitch in nm) ...... 138

4.48 Dennard scaling underestimates Intel for M1 (y axis = Pitch in nm) . 139

xiii LIST OF FIGURES

4.49 Dennard scaling underestimates Intel and ITRS for M1 (y axis = Pitch in nm log 10) ...... 140

4.50 Dennard scaling underestimates Intel for M1 (y axis = Pitch in nm log 10)...... 141 4.51 Dennard scaling underestimates Intel and ITRS for thickness (y axis = H in nm) ...... 142 4.52 Dennard scaling underestimates Intel for thickness (y axis = H in nm) 143 4.53 Dennard scaling underestimates Intel and ITRS for thickness (y axis = H in nm log 10) ...... 144 4.54 Dennard scaling underestimates Intel for thickness (y axis = H in nm log 10) ...... 145

4.55 Plot illustrating Intel and the ITRS are not scaling Imaxw according to Dennard scaling. The 2001 - 2011 are the ITRS predicted (y = mA/µm).146

4.56 Plot illustrating Intel and the ITRS are not scaling Imaxw according to Dennard scaling (y = mA/µm)...... 147

4.57 Intel and the ITRS are not scaling Imaxw according to Dennard scaling (y = mA/µm log 10) ...... 148

4.58 Intel and ITRS are not scaling Imaxw according to Dennard scaling (y = mA log 10) ...... 149

4.59 Intel is not scaling Imax according to Dennard scaling (y axis = mA) 150 4.60 Correlation of the thermal conductivity to the dielectric constant of various materials [Im et al., 2005b] ...... 158 4.61 Electron Wind [McPherson, 2013] ...... 159 4.62 A FIB cross section of the dual damascene copper line showing a slit failure under the Via. [He and Suo, 2004] ...... 162 4.63 A FIB cross section of the dual damascene copper line showing a trench failure in the interconnect line [He and Suo, 2004] ...... 163

xiv LIST OF FIGURES

4.64 Barrier layer needed to prevent Cu diﬀusion into dielectric ...... 165

4.65 Plot of ln t50 versus ln J to determine n ...... 173

4.66 Plot of ln t50 versus 1/T to determine the value of Ea ...... 173

4.67 Unipolar waveform illustrating Ipeak, Irms and Iavg [Liew et al., 1990] 178

4.68 How the current values Ipeak, Irms and Iavg used in interconnects . . . 179 4.69 Black’s Law Regression ...... 181

4.70 Black’s Law Regression for M2 ...... 183 4.71 Black’s Law Regression CDF ...... 185

4.72 tf50% Lifetimes using Black’s Law for M1 (y = years) ...... 186

4.73 log10(tf50%) Lifetimes using Black’s Law for M1 (y = years) . . . . . 186

4.74 tf50% Lifetimes using Black’s Law for M2 (y = years) ...... 187 4.75 Electromigration activation energies (left) and lifetimes for Cu/TaN/Ta liner/SiCN cap, Cu/TaN/Ta liner/Co cap, and Cu/TaN/Co liner/Co cap. [Edelstein, 2017] ...... 193 4.76 Via chamfer in the non-SAV direction (left). FAV scheme comparison for chamfer and CD control (right). [Briggs et al., 2017] ...... 194 4.77 Fully-Aligned Via (FAV) schematic, Cu/barrier recess TEM/EELS map, and implementation on W MOL. [Briggs et al., 2017] ...... 194 4.78 Through-Co Self-Forming Barrier concept and data. Mn from Cu(Mn) seed layer diﬀuses through ultrathin TaN/Co liner, reacts with residual O, and seals the composite barrier. Provides line-R reduction with preserved reliability. [Nogami et al., 2015] ...... 195 4.79 Through-Co Self-Forming Barrier concept and data. Mn from Cu(Mn) seed layer diﬀuses through ultrathin TaN/Co liner, reacts with residual O, and seals the composite barrier. Provides line-R reduction with preserved reliability. [Briggs et al., 2017] ...... 196

xv LIST OF FIGURES

4.80 Adhesion energy of CoWP compared to SiC, NSiC and SiN capping layers. [Gupta, 2010] ...... 197

5.1 DPA Model [Nagaraj et al., 1998] ...... 200 5.2 28nm EM example ...... 201

5.3 Performance verses Lifetime tradeoﬀ by % change in j with∆tlifetime

cuurent density exponent (j) of n = 1 and ∆fperformance current density exponent (j) of α =1...... 203

5.4 Performance verses Lifetime tradeoﬀ for ∆tlifetime current density ex-

ponent of n = 2, and Sakurai-Newton ∆fperformance current density exponent of α = 1.2...... 204 5.5 Performance verses Lifetime trade oﬀ for n = 1 and α = 1 ...... 206 5.6 Plot illustrating the tradeoﬀs of Current density j vs Temperature (T ) vs Lifetime (Z)...... 208 5.7 Metal stack for nominal process variation ...... 213 5.8 Capacitance, C, vs. inverse resistance, 1/R, at 112nm pitch (32nm: Metal-2; 22nm: Metal-4) [Ingerly et al., 2012b] ...... 216

5.9 Capping and Barrier layers for M2 ...... 218

5.10 Modulus of elasticity versus Dielectric constant, r [Besser, 2007] . . . 220 5.11 Interconnect capacitance model ...... 222

◦ ◦ 5.12 COMSOL simulation for Tsubstrate of 105 C and Tambient of 25 C .. 229

◦ ◦ 5.13 COMSOL simulation for Tsubstrate of 105 C and Tambient of 85 C .. 230

◦ 5.14 COMSOL simulation for COMSOL simulation for Tsubstrate of 105 C

◦ and Tambient of -40 C ...... 231

◦ ◦ 5.15 COMSOL simulation for Tsubstrate of 105 C and Tambient of 25 C .. 232

◦ ◦ 5.16 COMSOL simulation for Tsubstrate of 105 C and Tambient of 85 C .. 233

◦ ◦ 5.17 COMSOL simulation for Tsubstrate of 105 C and Tambient of -40 C .. 233

xvi LIST OF FIGURES

6.1 Amber 25 design block diagram ...... 240 6.2 High Level Design Exploration System ...... 241 6.3 Plot illustrating the tradeoffs of Current density j vs Temperature (T ) vs Lifetime (Z)...... 244 6.4 Tool flow for EM Methodology ...... 246 6.5 Library PVT (Process, Voltage and Temperature) diagram ...... 247 6.6 Tool flow for Spice to validate the EM Methodology using ICC . . . . 250 6.7 Synopsys 28/32nm PDK Acceleration Factor ...... 253 6.8 Synopsys 28/32nm PDK Acceleration Factor as used in ICC . . . . . 254

7.1 Amber25 design with ﬂoorplanning, gate placement and clock tree synthesized ...... 261 7.2 Clock tree highlighted in ICC ...... 262 7.3 Final ICC layout including the signals. Not all layers are shown. The x, y units are in µm ...... 263 7.4 Amber 25 layout showing the major blocks of the design ...... 264 7.5 Arm3 processor die for comparison to the Amber 25 design ...... 265 7.6 Amber 25 design wire count (Net Wire Length is in µm)...... 266 7.7 Amber 25 design average number of signals and clocks per metal layer (Net Wire Length is in µm)...... 267 7.8 Amber 25 design average number of Vias for the signals and clocks (Net Wire Length is in µm)...... 268 7.9 Amber 25 design ICC default toggle estimates (Net Wire Length is in µm)...... 269 7.10 Amber 25 design toggle rates with a cache size of 64 (Net Wire Length is in µm)...... 270 7.11 Amber 25 design toggle rates with a cache size of 128 (Net Wire Length is in µm)...... 271

xvii LIST OF FIGURES

7.12 Amber 25 design Power using the ICC default toggle rates (Net Wire Length is in µm)...... 272 7.13 Amber 25 design Power with a cache size of 128 (Net Wire Length is in µm)...... 273 7.14 Resistance for signal and clocks (Net Wire Length is in µm)..... 274 7.15 Capacitance for signal and clocks (Net Wire Length is in µm).... 275 7.16 Fanout of signal and clocks (Net Wire Length is in µm)...... 276 7.17 ICC layout showing the EM violations (yellow X’s) ...... 277

11.1 28/32nm LVT Inverter 0.5 Drive Schematic ...... 333 11.2 90nm LVT Inverter Schematic ...... 334 11.3 90nm LVT Inverter Schematic with Capicitors ...... 334 11.4 28/32nm LVT NAND2 Schematic ...... 335 11.5 90nm LVT NAND2 Schematic ...... 336 11.6 90nm LVT NOR Schematic ...... 336 11.7 Plot of the percent change in tp for a typical 28/32nm inverter . . . . 348 11.8 Plot of the delay change in tp for a typical 28/32nm inverter with ±40 change in interconnect resistance ...... 350

11.9 Plot of the Iomax change for a typical 28/32nm inverter with ±40 change in interconnect resistance ...... 352 11.10Plot of the percent change in tp for a typical 90nm inverter ...... 354 11.11Plot of the delay change in tp for a typical 90nm inverter with ±40 change in interconnect resistance ...... 356

11.12Plot of the Iomax change for a typical 90nm inverter with ±40 change in interconnect resistance ...... 358

11.13Interconnect delay calculation for Tperiod = 1RC ...... 359

11.14Interconnect delay calculation for Tperiod = 4RC ...... 360

11.15Interconnect delay calculation for Tperiod = 5RC ...... 360

xviii LIST OF FIGURES

11.16Interconnect delay calculation for Tperiod = 6RC ...... 361

11.17Interconnect delay calculation for Tperiod = 10RC ...... 361

11.18Clock simulation with Idd for time constant of 1 RC ...... 361

11.19Clock simulation with Idd for time constant of 4 RC ...... 362

11.20Clock simulation with Idd for time constant of 5 RC ...... 362

11.21Clock simulation with Idd for time constant of 6 RC ...... 362

11.22Clock simulation with Idd for time constant of 10 RC ...... 363 11.23Ratio of vacancy concentration at the blocking barrier C(0, t) to the

initial vacancy concentration C(x, 0) = C0) as a function of the nor-

malized to τ = α2 ×Dt for various conductor lengths for each boundary conditions of 11.6. Note that all solutions approximate the semi-inﬁnite case except near steady state. [Clement and Lloyd, 1992] ...... 368

xix Acknowledgments

Dedicated to my parents Richard and Hazel Weyer. I owe my deepest gratitude to my Committee Chair Dr. Christos Papachristou. His personal and professional guidance throughout my research has taught me more than I give him credit here. I also gratefully acknowledge my committee members for support and time for this work. I would like to express my sincere appreciation to my friend and mentor in research, Dr. Francis G. Wolﬀ. Without his enthusiasm, encouragement, knowledge and assistance throughout my educational journey, I would not have completed this dissertation. He inspired me to complete my research. Francis is the university’s Syn- opsy tool administrator, and the SolvNet ambassador. His help in getting through all the complexity of the tools and technology ﬁles was needed for this work. I am extremely grateful to my friend and co-worker Steve Clay. His knowledge and expertise in mathematics and reliability engineering, with his willingness and ability to teach me the principals of reliability has been instrumental in completing this dissertation. I need to thank Rockwell Automation for their support in my pursuit of my PhD. My manager and co-workers all supported me throughout my Master and PhD work. I would also like to thank Synopsys Incorporated for their support of the Case Computer Engineering Department by allowing the use of their ASIC tool suite, which made this work possible.

xx ACKNOWLEDGMENTS

And ﬁnally, I need to thank my family, and especially my wife Geri and children LeeAnn, Daniel and Darlene for their loving support in my education. Without their support this would not have been possible.

xxi Tradeoﬀs between Performance and Reliability in Integrated Circuits

Abstract by

DANIEL J. WEYER

The Reliability of the ICs or ASICs was assumed to always exceed the expected lifetime of the product. Reliability cannot be ignored as the IC/ASIC industry moves to nano-scale geometries. Integrated Circuit technology (IC) and ASIC in particular were always designed to tradeoﬀ between Performance, Cost (Area)Power. The Re- liability of the ICs or ASICs was assumed to always exceed the expected lifetime of the product. Reliability cannot be ignored as the IC industry moves to nano-scale geometries. This paper describes a design methodology to perform tradeoﬀs between Lifetime, Performance, Cost (Area) and Power. The main objective of this paper is to develop a design space exploration method and tools for IC/ASICs driven by lifetime concerns due to Electromigration. Our method applies to both safety based products that require longer lifetime, and also to higher performance products that are frequently replaced.

xxii Chapter 1

Introduction

In modern nanoscale IC and ASIC (IC/ASIC) designs, Lifetime and Reliability is now one of the design tradeoffs that needs to be considered. Traditionally, IC/ASIC design have been dominated by performance, cost (area) and power consumption especially in mobile wireless applications. There are different requirements for consumer, computer servers, automotive, medical, industrial, avionics and military IC/ASICs. Methods are needed to predict the useful life of an IC/ASIC for the lifetime of the product(s) it will be used in. Transistor degradation occurs due to the effects of Electromigration (EM),Negative Bias Temperature Instability (NBTI), Positive Bias Temperature (PBTI), Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB), which all can reduce the useful life of the ASIC. The useful IC/ASIC life due to these degredations was over100 years in 350 nano meter (nm) technology. The useful life is now targeted for10 years for150nm and below IC/ASIC technology.

Motivation

The IC/ASIC designer needs to consider Lifetime and Reliability as one of the trade- oﬀs along with Performance, Area and Power. If the end product needs the highest

1 CHAPTER 1. INTRODUCTION performance, and the lifetime of the product is 5 years, the design of the IC/ASIC can be maximized for performance and tradeoff the lifetime. If the lifetime of the product is greater than 10 years, performance can be traded off for longer lifetimes. With the growth of autonomous vehicles, reliability and lifetimes will be an very important design criteria going forward. Autonomous vehicles will require the latest IC/ASIC technologies and most likely be under power longer than the current average of 2 hours/per day. There are different lifetime expectations for consumer, automotive, medical, industrial and military. Methods are needed to predict the useful life of an IC/ASIC for the expected lifetime of the product(s) it will be used in. In smaller IC geometries, transistor degradation occurs due to the effects of Electromigration (EM), Negative Bias Temperature Instability (NBTI), Positive Bias Temperature (PBTI), Hot Car- rier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB). Each of these can reduce the useful life of the IC/ASIC. The useful IC/ASIC life due to these degradation’s was > 100 years in 350nm technology. The IC/ASIC process are now designed for a useful life of > 10 years from150nm and below process technologies. Each new IC/ASIC process has been following Moore’s law. Gordon Moore who at the time was the director of research at Fairchild Semiconductor in 1965 was asked to forecast what the IC/ASIC industry would do in the next 10 years. He published an editorial in Electronics Magazine where he speculated: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years” [Moore, 1965a] He revised his forecast in 1975 with an article presented at the IEEE International Electron Devices Meeting to

2 CHAPTER 1. INTRODUCTION

“Semiconductor complexity would continue to double annually until about 1980 after which it would decrease to a rate of doubling approximately every two years” [Moore, 1975] Moore’s law has been driving the IC/ASIC industry. This doubling has reduced the lifetime of an IC/ASIC. Figure 1.1 gives a perspective on the transistor sizes of the IC/ASICs technologies to meet “Moore’s Law”.

Figure 1.1: Perspective on sizes. [Bohr, 2014]

As the transistor shrank to meet Moore’s Law, the interconnect wires to connect the transistors also had to shrink. The interconnect wires are now the limiting factor in useful life of an IC/ASIC, due to electromigration in the interconnects wires. AMD predicted that “Electromigration: the time bomb in deep-submicron ICs” [Li and Young, 1996]. At IBM it was estimated that close to a billion 1966 dollars were spent in the eﬀort to understand and ﬁx the problem of electromigration failure. “This was when a billion dollars was a lot of money.” [Lloyd, 2002]. EM continues to be a major challenge in the designing of IC/ASIC today. In the late 1980’s Western Digital (WD) desktop hard drives had widespread failures in 12 to 18 months. The root cause was determined to be caused by an electromigation rule violation in a third party controller IC/ASIC. WD corrected the problem, but not before damage was done to their reputation [Balasinski, 2016].

3 CHAPTER 1. INTRODUCTION

Guard banding has been the technique used to predict an IC/ASICs useful life. Gaurd banding consist of a set design rules used when developing an IC/ASIC. These rules account for the process variations in the manufacturing of an IC/ASIC. Process variation occurs in the fabrication of an IC/ASIC, which causes variations in the at- tributes of transistors (length, widths, oxide thickness) and interconnect wires (length, width, thickness). Process variation causes measurable and predictable variance in the performance and reliability of the circuits in the IC/ASIC design. The amount of process variation becomes more pronounced at smaller process nodes [Wikipedia, 2018c]. The useful life is the expectation of the life of the product the IC/ASIC was designed into. The expectations for useful life of a cell phone is different than the expected life of automobile or a satellite. “Companies that have suffered from electromigration failures consequently, tend to set very conservative design rules, usually including wide power rails, which consume valuable routing space” “Unless the problem is eliminated by design, deep-submicron circuits will be failures waiting to occur” [Li and Young, 1996]. Guard banding makes the assumption that a component is operated under the absolute worst case conditions. To tradeoff between reliability and performance, a 10% degradation parameter does not imply 10 year component failure. IC/ASIC life may be greater or less than 10 years depending on the IC/ASIC circuit design and the environmental conditions that the IC/ASIC is operated under. We will propose a design methodology which will allow a designer to better predict an IC/ASICs useful life. The methodology allows a designer to consider Reliability in the Performance, Cost and Power design tradeoffs.

1.1 Problem Statement

The decision to create a new product involves detailed documentation of the design requirements. The requirements include, but not limited to:

4 CHAPTER 1. INTRODUCTION

• Cost of the product in the marketplace

• Design and manufacturing costs

• How many years can the product be sold

• Number of product sold

• How long must the product be in service

• Performance

• Power requirements

• Environment the product will used in

• Expected useful life of the product

• Size of the end product

From the product requirements, a product design team will make the decision to use a Commercial Off the Shelf (COTS) IC. FPGA or to design a custom ASIC. The COTS IC supplier will have to consider the design requirements for the IC with targeted markets, such as consumer, medical, industrial, aerospace military, etc. Product design teams have the knowledge to make the tradeoffs between Performance, Cost and Power. Reliability of the IC/ASICs was always greater than the other components in the product such as electrolytic capacitors in the power supplies. As the process nodes continue to shrink, this assumption no longer applies. The objective is to present an explanation of the physical aspects of transistor degradation, how the calculations for reliability are performed in the IC/ASIC industry, and propose a methodology in which product design teams can trade off between performance, power, cost and reliability. The focus will be on electromigration (EM) in the interconnect wires, as this is the limiting factor in useful life in process technologies below 150nm. The IC/ASIC

5 CHAPTER 1. INTRODUCTION industry made the tradeoff between performance and the reliability of the interconnect wires due and set the design goal of IC/ASIC to be a lifetime at least 10 years. The effects of EM will be discussed, and through layout rules and simulation show how the tradeoff between performance and reliability can be made. For a product design, the IC/ASIC designer needs to consider the degradation or aging mechanisms of an IC/ASIC to ensure the requirements for lifetimes are met. The focus of our research is the clock lines and a process to analyze trade offs in performance versus reliability in clock lines. Though power lines carry more current, thus have the potential for EM failures, but are routed on wider interconnect layers, have specialized tools for the design and analysis and are typically can be over designed in practice. For the discussion, aging is continuous phenomenon in the degradation of materials. Lifetime is a milestone in the age of IC/ASIC, which depends application domain. Our focus is Lifetime.

1.2 Outline

Chapter 2 will look at the Reliability of IC/ASICs and discusses the reasons reliability is important, reliability from the IC/ASIC industry perspective and how reliability is calculated for each of the aging mechanism as follows:

1. Importance of Reliability in IC/ASICs

2. Theory of transistor degradation or aging

(a) NBTI (Negative Bias Temperature Instability) and PBTI (Positive Bias Temperature Instability)

(b) HCI (Hot Carrier Injection)

(d) EM (Electromigration)

6 CHAPTER 1. INTRODUCTION

EM will be expanded to discuss our approach and how it needs to considered in the design of an IC/ASIC. Chapter 3 discusses the aging or degradation mechanism of CMOS devices used in IC/ASIC design. Chapter 4 investigates the interconnects and their effects on performance and reliability. Chapter 5 is the Trade offs for Lifetime versus Performance and the Library used in the work to show the design considerations for the EM aging or degradation. Chapter 6 is our Methodology. It use the theory and equations from Chapter 5 using a 28/32nm process node to show the affects of the aging in electromigration and our propose methodology. An Open Core 32-bit processor design used as an example with simulations and analysis of the clock trees to show our methodology of how an IC/ASIC can be designed to optimize for the tradeoffs of performance, cost, power and in reliability. Chapter 7 is the results of our research and discusses how the design space can be explored for performance, power, lifetime and cost in IC/ASIC design. Chapter 8 is a discussion of our work. Chapter 9 is is a summary of our contributions and future research. Chapter 10 is a list of Acronyms. Chapter 11 is the Appendix and details of the work performed to explore the IC/ASIC design space. Chapter 12 is my related research.

7 Chapter 2

Reliability of ICs/ASICs

IC/ASIC CMOS technology scaling has posed increasing part reliability concerns, which aﬀect the whole bathtub curve regions (Figure 2.1):

• Failure rate increases with scaling feature size

• Aging mechanism: Aging mechanism dominate

• Can be optimize for the end product

The Bathtub plots the Failure Rate verses time for IC/ASICs. There are three parts of the Bathtub cure:

• Infant Mortality

• Constant or Random failure

• Aging

Understanding the scaling impact on IC/ASICs reliability and the limitations of progressively scaled IC/ASIC CMOS technologies from a Point of Failure (PoF), standpoint will lead to improved reliability prediction, appropriate de-rating criteria, and help projects more eﬀectively mitigate risks. As fabrication processes progress

8 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.1: The IC/ASIC Shrinking Bathtub to smaller geometries, certain semiconductor effects become to dominate and limit the useful life of an IC/ASIC. The factors for transistor aging are EM, NBTI, PBTI, HCI and TDDB. These mechanisms affects the useful life. EM, NBTI, PBTI, HCI, and TDDB, which used to be second or even third-order effects, are now becoming a major failure mechanism if IC/ASIC design does not consider these effects as shown in Figure 2.2. These effect the performance of the CMOS transistors performance over time. The transistors trap charge in the case of NBTI, PBTI and HCI . The shrinking on the interconnects increases the resistance of the interconnects, which affects the speed at which a circuit will perform. To keep performance, a tradeoff must be made to the amount of current allowed in an interconnect wire. The more current the better the performance, but, the higher current causes degradation due to EM. TDDB is a catastrophic failure and must be accounted for in the design of the dielectric of the IC/ASIC technology process.

Figure 2.2: Aging eﬀects of a CMOS inverter [Baﬂeur and Perdu, 2016].

The early Infant Mortality is due to manufacturing defects. These are hopefully

9 CHAPTER 2. RELIABILITY OF ICS/ASICS found in the manufacturing testing of ICs/ASICs. The Random Failure are failures of the IC/ASIC during the lifetime. Aging failures predict the useful lifetime of the IC/ASIC. A group of industry experts formed The International Technology Roadmap for Semiconductors (ITRS). ITRS was created to asses the semiconductor or IC/ASIC technology and created roadmaps. In 2011 ITRS emphasized the concerns of these IC/ASIC failure mechanisms. For example, a telecom 90nm [Hillman, 2009], ASIC had a 10% failure within 4 years due to HCI. These reliability limitations are usually measured in units of FITs. For example, IC/ASIC CMOS process must not be worse than 50 FITs (Failure in Time) level in one billion device hours of operation (e.g. 1000 devices for 1 million hours or 1 million devices for 1000 hours). Figure 2.3 shows typical FIT rates for electronic components and products they are used in. The ﬁgure shows the trends of the semiconductor FIT rates are increasing. This is due to Moore’s Law, as more transistors are being placed in IC/ASICs.

Figure 2.3: Typical FIT rates of electronic components and trend due to aging or degradation. [Hillman, 2009]

There is no practical correlation of methods between transistor degradation and an IC/ASIC library of gates Flip Flops etc. or the design application. There are millions of gates and interconnect wires all with process variations in manufacturing. Guard banding has been the technique used to predict an IC/ASICs useful life. Guard banding does not predict the useful life. Guard banding makes the assumption

10 CHAPTER 2. RELIABILITY OF ICS/ASICS that a component is operated under the absolute worst case conditions. To tradeoff between reliability and performance, a 10% transistor degradation parameter rule does not imply 10 year component failure. ASIC life may be greater or less than 10 years depending on the IC/ASIC circuit design, and the environmental conditions that the ASIC is operated under. Figure 2.4 shows the design consideration due to aging. Clearly, guard-banding of 15% is large and understanding why this is necessary needs to be investigated to increase the performance of the IC/ASIC design. The cost of guaranteeing reliable operation of an IC/ASIC for the specified lifetime is increasing, and is paid for in terms of the chips performance.[Arasu et al., 2016]. Nano scale IC/ASICs have become more sensitive to various process parameters such as supply voltage and temperature. Designers follow the worst case design approach for guaranteeing IC/ASIC operation for all Process, Voltage and Temperature (PVT) variations of the IC/ASIC manufacturing process . However, rarely do the extreme corners occur in most fabricated IC/ASICs. Also, over time the IC/ASIC fabrication process is held to tighter tolerances. Excessive use of guard-banding limits the maximum performance. To continue the digital design success in nanometer CMOS, cost-effective variation tolerant design approaches are needed that guarantee circuit robustness in the presence of the variability influences, while avoiding over constrain- ing of the design [Meijer, 2011].

Figure 2.4: Total guard banding of 15% is large. Blue shows the faults due to process variation. Red shows aging degradation [Alam et al., 2008].

The reasons for guard-banding in ICs/ASICs is to ensure the reliability of the

11 CHAPTER 2. RELIABILITY OF ICS/ASICS

products designed with the IC/ASIC. The Figure 2.5 illustrates the cost of warranty to various industries. As can be seen from the ﬁgure the warranty cost are in billions of dollars.

Figure 2.5: Warranty Costs

Examples of recalls are: PC motherboards [Singer, 2005], medical pacemakers [LaPedus, 2006], thermal reliability such as graphic ICs [Yoshida, 2008], micropro- cessors causing system errors when running certain programs at a particular temperature [Merritt, 2004] [Fried, 2000], wire bonding and packaging reliability resulted in a graphic ICs [Clark, 2008] [LaPedus, 2008], and an FPGA vendor [McGrath, 2006]. These led to either a recall of the product or to the extension of the product warranties. CMOS technology scaling has posed increasing parts reliability concerns, which aﬀect the whole bath tub curve regions:

• Failure rate increases with scaling feature size

• Aging or Wear-out mechanism: Aging mechanism dominate

• Can be pushed out by design

Understanding the scaling impact on parts reliability and the limitations of progressively scaled CMOS technologies will lead to improved reliability prediction, appropriate derating criteria, and will help IC/ASIC designers more eﬀectively mitigate risks. Reliability is measured in FITs (Failures in Time). The number of units/ICs

12 CHAPTER 2. RELIABILITY OF ICS/ASICS failure is measured in PPM (Parts per Million). It is useful to note the deﬁnitions below:

1 FIT = 1 failure in 109 device-hours

1 PPM = 1 failure in 106 parts

Examples:

100 FIT = after 10 years operation 1% failure

10 FIT = after 10 years operation 0.1% failure

MTBF = Mean Time Between Failure - the arithmetic mean time between failures for a repairable system.

MTTF = Mean Time to Failure - the arithmetic mean time to failures for a non-repairable system. MTBF ≈ MTTF for non-repairable systems.

It is noteworthy, the MTBF and MTTF values are when 63% of the devices or products fail. Safety is also a concern especially for the Aerospace, Automotive, Industrial, Med- ical, and Military. There are standards such IEC 61508 (IEC - International Electro- technical Commission) for Industrial, ISO 26262 (ISO - International Organization for Standardization) for Automotive and various others such as the defense industry DOD 254. There are overlaps between the standards. For example the automotive standard ISO 26262 speciﬁes the use of IEC 61508. The IEC 61508 is a functional safety standard for Electric/ Electronic/Programmable Electronic (E/E/PE) Safety related systems - Proof of Safety [Foerster, 2010] It consist of documented body of evidence that provides a convincing and valid argument that a system is adequately safe for a given application in a given environment with justiﬁcation of engineering and management approaches to safety issues as follows:

13 CHAPTER 2. RELIABILITY OF ICS/ASICS

1. Safety System Project has various phases in its life cycle.

2. Functional Safety Assessment is a critical activity that checks and reviews output of each phase to make sure that the Functional Safety has actually been achieved.

3. Based on the Risk level SIL (Safety Integrity Level) an Independent person or an independent organization is required to carry out a Safety Assessment.

There are 4 SIL classes (ASIL for automotive) ratings for the compound or average certainty level of failure probability (probability of a failure per hour of operation that introduces danger) for a design. These are categorized as follows:

SIL4 (-): 1 failure in a minimum of 110,000 years

SIL3 (ASIL-D): 1 failure in a minimum of 11,000 years

SIL2 (ASIL-B/C): 1 failure in a minimum of 1,100 years

SIL1 (ASIL-A): 1 failure in a minimum of 380 years

For example a Nuclear Power Plant would be certiﬁed to SIL 4. Most industrial and automotive applications are SIL2 (ASIL B/C) or SIL3 (ASIL D). The aspect of aging must be accounted for in the IC/ASIC design to ensure the failures metrics are met for the product designs. When IC/ASICs are manufactured, and used under identical stress conditions, they will not fail in exactly the same way or at the same time. The reasons for this is that slight diﬀerences in the micro-structure and manufacturing processes exist in the micro-structures of the IC/ASIC. An IC/ASIC consists of the silicon die placed in package. Failure can occur in the silicon or the package the die is placed in and the failure mechanisms may not be identical. Statistical analysis can be performed on failures. Reliability of IC/ASICs can be summarized as follows [Wikipedia, 2018d]:

14 CHAPTER 2. RELIABILITY OF ICS/ASICS

1. Semiconductor devices are very sensitive to impurities and particles. There- fore, to manufacture these devices it is necessary to manage many processes while accurately controlling the level of impurities and particles. The ﬁnished product quality depends upon the many layered relationship of each interacting substance in the semiconductor, including metallization, IC/ASIC material (list of semiconductor materials) and package.

2. The problems of micro-processes, and thin ﬁlms and must be fully understood as they apply to metallization and wire bonding. It is also necessary to analyze surface phenomena from the aspect of thin ﬁlms.

3. Due to the rapid advances in technology, many new devices are developed using new materials and processes, and design calendar time is limited due to non- recurring engineering constraints, plus time to market concerns. Consequently, it is not possible to base new designs on the reliability of existing devices.

4. To achieve economy of scale, semiconductor products are manufactured in high volume. Furthermore, repair of ﬁnished semiconductor products is impracti- cal. Therefore, incorporation of reliability at the design stage and reduction of variation in the production stage have become essential.

5. Reliability of semiconductor devices may depend on assembly, use, and environmental conditions. Stress factors aﬀecting device reliability include gas, dust, contamination, voltage, current density, temperature, humidity, mechanical stress, vibration, shock, radiation, pressure, and intensity of magnetic and electrical ﬁelds.

15 CHAPTER 2. RELIABILITY OF ICS/ASICS

2.1 Reliability analysis

There are many time-dependent forms of degradation. The following three (3) forms are generally used as they tend to occur in nature. They are the Power-Law, Expo- nential and the Logarithmic models:

f(x) = ax±k is the Power Law function

f(x) = bx is the Exponential function

logb(x) = y is the Logarithmic function

The following sections give a brief overview on reliability and the statistical distributions used by the IC/ASIC Industry. A very good summary can be found in the book “Reliability Physics and Engineering” by J. W. McPherson and was used extensively [McPherson, 2013] in the following sections.

2.1.1 Time To Failure

For semiconductor industry three probability distribution functions historically have been used used for reliability analysis. They are the “normal”, ‘’lognormal” and ‘’Weibull”. The normal, lognormal and Weibull distributions are continuous distributions used for time to failure (TTF or tf ) analysis when failure in time data is available. The following are important statistical concepts, which are deﬁned mathematically in the next sections [Strong et al., 2009a]:

ft = f(t) = Probability Density Function (PDF) or Probability Distribution Function = Probability of observing a failure between t and t+dt

Ft = F (t) = Cumulative Distribution Function (CDF) or Cumulative failure probability

Rt = R(t) = Cumulative surviving distribution = R(t) = 1 − F (t)

16 CHAPTER 2. RELIABILITY OF ICS/ASICS

h(t) = Instantaneous Failure Rate (IFR) or Hazard function

H(t) = Cumulative hazard function

The PDF is a function that describes the ratio of devices or products that fail in a given period of time (t and t+dt) to the number of devices or products [Kapur and Pecht, 2014]. Figure 2.6 illustrates the PDF.

Figure 2.6: PDF f(t). f(t) represents the probability of ﬁnding a device failure between t and t+dt [McPherson, 2013]

The CDF is the fraction of the population that has failed. The CDF increases from zero to one. The CDF mathematically describes the probability of failure at a given time as is shown in Figure 2.7. The CDF equation is Equation 2.1.

Figure 2.7: CDF F(t). F(t) represents the fraction of the population that failed [policeanalyst.com, 2012]

17 CHAPTER 2. RELIABILITY OF ICS/ASICS

F (t) = P robability of failure = P robability[F ailed product ≤ t] = P [T ≤ t] (2.1) Z t = f(t)dt (2.2) 0

The reliability function R(t) is the cumulative distribution of the surviving population. It is obtained by subtracting the cumulative fails (CDF) from 1 (R(t) = 1 − F (t)). Just as the CDF must equal 1 after the last failure, the reliability function must equal 0 since there are by deﬁnition no survivors [Kapur and Pecht, 2014]. Figure 2.8 illustrate the PDF, CDF and Reliability.

Figure 2.8: Comparison of PDF, CDF and R [Andy, 2018]

The hazard rate is the rate at which failures occur over a given time interval. It does not depend on the original sample size. The hazard function or rate is deﬁned

18 CHAPTER 2. RELIABILITY OF ICS/ASICS

in Equation 2.3:

# of failures in a given time interval Hazard rate = # of survivors at the start of the interval × interval length (2.3) f(t) h(t) = (2.4) R(t)

The hazard rate or the instantaneous failure rate indicates the failure rate over the life of the population. The hazard rate is deﬁned in terms of the reliability R(t), and is described in Equation 2.5 [Kapur and Pecht, 2014]:

−1 dR(t) h(t) = (2.5) R(t) dt

dR(t) since f(t) = dt . The reliability function is shown in Equation 2.6:

Reliability function = R(t) = P robability [P roduct life > t] (2.6)

= P [T > t] (2.7)

= 1 − P [T ≤ t] (2.8)

= 1 − F (t) (2.9)

The importance of the cumulative hazard function H(t) is that it indicates the change in failure rate over the life of the population. Two designs may provide the same reliability at a speciﬁc time, but the hazard rates can diﬀer over time. The cumulative hazard in given by Equation 2.10 [Kapur and Pecht, 2014]:

Z t H(t) = h(τ)dτ (2.10) τ−1

R(t) and F (t) are related to h(t) and H(t) and the following relationships can be

19 CHAPTER 2. RELIABILITY OF ICS/ASICS

developed (Equation 2.11 [Kapur and Pecht, 2014].

f(t) 1 d h(t) = = − R(t) (2.11) R(t) R(t) dt d ln [R(t)] = (2.12) dt

or −d ln (R(t)) = h(t)dt (2.13)

Integrating both sides yeilds Equation 2.14

Z t − ln [R(t)] = h(τ)dτ (2.14) τ=0 = H(t) (2.15)

Since the four function f(t), F (t), R(t) and h(t) are related, if any one of the functions are known the three can be developed as shown in Equations 2.16, 2.17, 2.18 and 2.19: f(t) R(t) = (2.16) R(t

Z t R(t) = exp − h(u)du (2.17) 0

Z t f(t) = h(t) exp − h(u)du (2.18) 0

F (t) = 1 − R(t) (2.19)

It is useful to note the reliability function R(t) for systems is assumed to follow

20 CHAPTER 2. RELIABILITY OF ICS/ASICS

an exponential distribution as shown in Equation 2.20.

R(t) = expτ0t (2.20)

2.2 Continuous Distributions

Useful probability distribution for analysis of IC/ASIC are the Exponential, Normal (Gaussian) Distribution, lognormal, Weibull and Gamma distributions. These are continuous distributions, which is when a variable can take on value between two speciﬁed values.

2.2.1 Exponential Distribution

The exponential function is characterized as follows [Taboga, 2010], [Tsirelson, 2010]: Let X be an absolutely continuous random variable, then for the set of positive real numbers (Equation 2.21).

RX = [0, ∞] (2.21)

Let λ ∈ R+ the X has an exponential distribution with a rate parameter λ if its probability density function (PDF) is shown in Equation 2.22.

−λx λ exp if x ∈ RX fx(x) = (2.22) 0 if ∈/ RX

Figure 2.9 shows the plots for Exponential PDF: Then the Cumulative distribution function (CDF) or Cumulative failure rate is shown in Equation 2.23:

−λx 1 − exp if x ∈ RX Fx(x) = (2.23) 0 if ∈/ RX

21 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.9: The Exponential PDF [Wikipedia, 2017b]

Figure 2.10 shows the plots for Exponential CDF:

Figure 2.10: The Exponential CDF [Wikipedia, 2017b]

An important property of the exponential distribution is the memory-less property. This means that if a random variable X is exponentially distributed, its conditional probability obeys Equation 2.25 [Taboga, 2010].

P (X ≤ x + y|X > x) = P (X ≤ y) (2.24)

This property says that the probability that the event happens during a time interval of length y is independent of how much time has already elapsed x without the event happening. An example, if x = 30 seconds and y = 20 seconds shown in

22 CHAPTER 2. RELIABILITY OF ICS/ASICS

Equation 2.25: P (X > 30|X > 20) = P (X > 10) (2.25)

which says the event must wait more than another 10 seconds before the first arrival, given that the first arrival has not yet happened after 20 seconds, which is not different from the initial probability that is needed to wait more than 10 seconds for the first arrival. Reliability theory and reliability engineering make use of the exponential distribution. The memory-less property of exponential distribution, it is well-suited to model the constant Intrinsic failures portion of the bathtub curve in Figure 2.14. It is also very convenient because it is easy to add failure rates in a reliability model [Morris, 2014]. The mean or expected value E of an exponential distributed variable X with rate parameter λ is shown in Equation 2.26:

1 E[X] = (2.26) λ

The variance of X is shown in Equation 2.27:

1 V ar[X] = (2.27) λ2

2.2.2 Normal (Gaussian) Distribution

The normal distribution occurs when a random variable is aﬀected by random effects that no single factor dominates. By the central limit theorem which, states the sum of a large number of random variables is approximately normally distributed [Kapur and Pecht, 2014]. The central limit theorem (CLT) establishes that, in most situations, when independent random variables are added, their properly normalized sum tends toward a normal distribution (Gaussian) even if the variables are

23 CHAPTER 2. RELIABILITY OF ICS/ASICS

not normally distributed. The theorem is a key concept in probability theory because it implies that probabilistic and statistical methods that work for normal distributions can be applicable to many problems involving other types of distributions [Wikipedia, 2018a]. The CLT is used in the IC/ASIC reliability calculations that Normal distribution equations are used for the calculation of lognormal distributions. The PDF is deﬁned based on the Gaussian function is shown in Equation 2.28.

" # 1 1 t − µ2 f(t) = √ exp − , −∞ ≤ t ≤ ∞ (2.28) σ 2π 2 σ

where mu is the mean and sigma is the standard deviation. The normal distribution parameters follows:

Mean (arithmetic average) = µ

Variance = µ

Mode (highest value) = µ

Median = µ

Location parameter = µ

Shape parameter/standard diviation = µ

Figure 2.11 shows a plot of the Normal distribution PDF. The CDF or unreliability for the normal distribution is shown in Equation 2.29.

" # 1 Z t 1 x − µ2 F (t) = √ exp − dx (2.29) σ 2π −∞ 2 σ

There is no closed form of Equation 2.29. The values for the area under the Normal distribution are obtained from Normal distribution tables. This is performed

24 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.11: PDF f(t) for Normal Distribution [Kapur and Pecht, 2014] by converting the random value t to a random variable z as shown in Equation 2.30.

t − u z = (2.30) σ

A Normal random variable with the mean equal to zero and a variance of 1 is called a standard Normal variable (Z). The PDF is given by Equation 2.31.

2 1 − z φ(z) = √ exp 2 (2.31) 2π

(t−µ) where z ≡ σ . The properties of the standard Normal variables are tabulated in statistical tables. The CDF is deﬁned in Equation 2.32.

t − µ F (t) = Φ(z) = Φ (2.32) σ

The reliability function is shown in Equation 2.33. The hazard function is shown in Equation 2.34. t − µ R(t) = 1 − Φ (2.33) σ

25 CHAPTER 2. RELIABILITY OF ICS/ASICS

h φ(t−µ) i σ h(t) = (2.34) σR(t)

The Normal distribution has an increasing hazard function. When the normal distribution is used, the probabilities of a failure occurring before or after the mean µ time are equal because the mean is the same as the median. Comparisons given the mean value, the variability about the mean value is deﬁned through the standard deviation.

2.2.3 lognormal Distribution

For a continuous random variable, there may be a situation in which the random variable is a product of a series of random variables. The lognormal distribution is a positively skewed distribution. It can be used to model situations where large occurrences are concentrated at the tail (left) end of the range. The lognormal distribution is based on the normal distribution, but the failures in time are assumed to be distributed logarithmically rather than linearally. If X is a random variable with a normal distribution, then Equation 2.35 applies:

Y = expX (2.35)

If Y has a lognormal distribution the X = logY has a normal distribution. If Y is the product of n independent random variables shown in Equation 2.36:

Y = Y1Y2.....Yn (2.36)

Taking the natural logarithm of Equation 2.36:

ln Y = ln Y1 + ln Y2 + ..... + ln Yn (2.37)

26 CHAPTER 2. RELIABILITY OF ICS/ASICS

Then ln Y can be approximated by the normal distribution based on the central limit theorem [Kapur and Pecht, 2014]. The Lognormal distribution applies to many engineering functions. The use of the lognormal distribution is used to describe failures in time for an IC/ASIC, where aging mechanisms are general and complex in nature and not caused by one failure. An example is IC/ASIC industry committees have used the lognormal distributions for EM. The lognormal is also used for corrosion-induced and fatigue-induced failures. The lognormal distribution (PDF) is shown in Equation 2.38 [Kapur and Pecht, 2014].

" # 1 1 ln(t) − µ)2 f(t) = √ exp − (2.38) σt 2π 2 σ " # 1 ln(t) − µ)2 = √ exp √ (2.39) σt 2π σ 2

where σ is the standard deviation of the logarithms of the times to failure and µ is the mean of all the logarithms of all the times to failure. If a random variable X follows a lognormal distribution then ln X follows a normal distribution. The median (which equals the mean and mode) can also can be expressed as

ln(t50), which allows the lognormal PDF to be expressed as in Equation 2.40 [McPherson, 2013].

" # 1 ln(t) − ln(t )2 f(t) = √ exp − √ 50 (2.40) σt 2π σ 2

σ is approximated by Equation 2.41:

t50 σ = ln(t50) − ln(t15.87) ≈ ln (2.41) t16

where t16 is the time to failure for 16% of the devices. Equation 2.41 is use to approximate σ [McPherson, 2013]. Figure 2.12 shows a plot of the lognormal distribution PDF.

27 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.12: PDF f(t) of the Log normal Distribution for σ = 0.1 and σ = 0.5. [Kapur and Pecht, 2014]

28 CHAPTER 2. RELIABILITY OF ICS/ASICS

The cumulative failure probability F for the lognormal distribution is given by the Equations 2.42:

" # 1 Z t 1 ln x − µ2 F (t) = √ exp − dx (2.42) σ 2π −∞ 2 σ lnt − µ F (t) = Φ (2.43) σ 1 ln(t50 − ln(t) F (t) = erfc √ for t ≤ t50 (2.44) 2 σ 2 1 ln(t50 − ln(t) F (t) = 1 − erfc √ for t ≥ t50 (2.45) 2 σ 2

An alternative method to determine and plot cumulative fraction failed F is to use the number of logarithmic standard deviations represented by the “Z-values”. The Z-value is the number of standard deviations associated with a cumulative failure F. The values to go from F to Z-value and Z-vaule to F can be found in tables or using Microsoft’s EXCEL program. EXCEL provides function Z = NORMSINV (F ) and

F = NORMDIST (Z). In general once the t50 and σ values have been found any cumulative fraction F can be found with Equation 2.46 [McPherson, 2013].

tF % = t50 exp (ZF × σ) (2.46)

The following relationships Equations 2.47 are often used:

t t t t = 50% ; t = 50% ; t = 50% (2.47) 16% exp (1σ) 1% exp (2.33σ) 0.13% exp (3σ)

The hazard function for the lognormal is described in Equation 2.48.

φ ln t−u h(t) = σ (2.48) tσR(t)

If a population follows a lognormal distribution, then the MTTF can be found

29 CHAPTER 2. RELIABILITY OF ICS/ASICS with Equation 2.49. σ2 MTTF = exp µ + (2.49) 2

The lognormal distribution parameters follow:

Mean (arithmetic average) = exp (µ + 0.5σ2)

Variance = (exp σ2 − 1) exp 2µ + σ2

Median (50% failures) = exp µ

Mode (highest value of f(t)) t = exp (µ − σ2)

Location parameter = exp µ

Shape parameter/standard diviation = σ

Estimate of σ = ln t50 t16

[McPherson, 2013].

2.2.4 Weibull Distribution

The Weibull distribution is used to provide the distribution of lifetimes of objects. It was originally proposed to quantify fatigue data, but it is also used in analysis of systems involving a “weakest link” [Weisstein, 2017]. The weakest link means that the failure of a system is dominated by the weakest element in the system. Thus the Weibull is used in the reliability of systems. The Weibull distribution is useful in calculating and plotting IC/ASIC failure mechanisms. An example is Time Dependent Dielectric Breakdown (TDDB), which the entire capacitor fails when a localized region of the capacitor fails. The Weibull distribution is useful in modeling semiconductor failure rates when failure in time data is available.

30 CHAPTER 2. RELIABILITY OF ICS/ASICS

The general form of Weibull probability density function (PDF) is deﬁned as Equation 2.50: " # β t − γ β−1 t − γ β f(t) = exp − (2.50) α α α

where:

β is the shape function

α is the scale parameter

γ is the location parameter and is not usually used and can be set to 0

In most cases of IC/ASIC reliability analysis, the location parameter γ is not required. The Weibull can then be represented by Equation 2.51:

" # β t β−1 t β f(t) = exp − (2.51) α α α

Figure 2.13 shows the plots for Weibull PDF.

Figure 2.13: The Weibull PDF [Wikipedia, 2017d]

Figure 2.14 illustrates how the shape parameter aﬀects the shape of the Weibull distribution and how it can be used in reliability analysis. β < 1 is the infant mortality

31 CHAPTER 2. RELIABILITY OF ICS/ASICS

or early failures of IC/ASIC. β = 1 is the intrinsic or normal life failures and β > 1 is the deterioration or aging failures. The Failure rate is the frequency a IC/ASIC fails and is expressed in failures per unit of time. The Greek letter lambda λ is used in reliability engineering. The MTBF is deﬁned as:

1 MTBF = λ

λ is only valid in the normal life or the ﬂat region in the bathtub curve. The IC/ASIC lifetimes are typically much less than the MTBF due to early failures and aging failures.

Figure 2.14: The Weibull distribution showing use in Reliability [Spinato et al., 2009]

The cumulative failure probability can be found by Equation 2.52.

" # Z t t β F (t) = f(t)dt = 1 − exp − (2.52) 0 α

Figure 2.15 shows the plots for Weibull CDF. Rearranging Equation 2.52 and taking the logarithms of both side shown in Equa- tion 2.53. t ln [− ln (1 − F )] = β ln (2.53) α

When F is 0.63212 in Equation 2.53 the left side of the equation approaches 0, therefore when discussing distributions following the Weibull distribution the 63.2

32 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.15: The Weibull CDF [Wikipedia, 2017d] percentile is the ﬁgure of merit for fallout [Strong et al., 2009b]. Generally this is simpliﬁed and t63 is substituted for α as shown in Equation 2.54.

t ln [− ln (1 − F )] = β ln (2.54) t63

The slope β can be found by rearranging Equation 2.54, which results in Equation 2.55. ln [− ln (1 − F )] β = h i (2.55) ln t t63

When ﬁtting data it is useful to plot the data using ‘’Weibits’ [McPherson, 2013]’. A Weibit is deﬁned as in Equation 2.56.

W eibit = ln [− ln (1 − F )] (2.56)

To plot the collected data using Weibits as the y axis and t (time) as the y axis is shown in Figure 2.16. From the graph of the data, the Weibit = 0, corresponds to

t63 and the slope would be β.

33 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.16: The Weibull distribution plot in terms of Weibits [McPherson, 2013]

Conversions from F (t) to Weibits can be found in tables. An example table is in Figure 2.17.

Figure 2.17: The Weibull distribution plot in terms of Weibits [McPherson, 2013]

Knowing t63 and β any F can be found by using Equation 2.57.

1 t = t exp ln [− ln (1 − F )] (2.57) F % 63% β

34 CHAPTER 2. RELIABILITY OF ICS/ASICS

The following relationship Equations 2.58 are often used [McPherson, 2013].

t63% t63% t63% t10% = ; t1% = ; t0.1% = (2.58) 2.25 4.60 6.91 exp β exp β exp β

A comparison of the PDF, CDF and hazard functions for the Exponential, Normal, lognormal and Weibull is shown in Figure 2.18.

Figure 2.18: Comparison of the PDF, CDF and hazard functions for Exponential, Normal, lognormal and Weibull [Industrial-Electronics, 2017]

35 CHAPTER 2. RELIABILITY OF ICS/ASICS

2.2.5 Gamma Distribution

The gamma distribution is a two-parameter family of continuous probability distributions. The gamma distribution is used in reliability analysis for cases where partial failures can exist. A given number of partial failures must occur before an item fails (i.e redundant systems), or is the time to the second failure when the time to failure is exponentially distributed. The failure density function or PDF is Equation 2.59.

λ f(t) = (λt)α−1 exp−λt (2.59) Γ(α)

for t > 0 and where:

α mean = µ = λ

1 α 2 standard deviation = σ = λ

α is the number of partial failures or events to generate a failure

λ is the complete failure rate

The Γ(α) is the gamma function (Equation 2.60).

Z ∞ Γ(α) = x(α−1) expx dx (2.60) 0

Figure 2.19 illustrates the Gamma function for positive real values: which can be evaluated with standard tables. When (α − 1) is a positive integer, Γ(α) = (α − 1)!, which is usually the case for most reliability analysis, i.e. a partial failure situation. The failure density distribution is Equation 2.61.

λ f(t) = (λt)(α−1) exp−λt (2.61) (α − 1)

For the case α = 1 then the Gamma function becomes the Exponential density

36 CHAPTER 2. RELIABILITY OF ICS/ASICS

Figure 2.19: The Gamma function for real values of α [Pishro-Nik, 2017] function. Figure 2.20 illustrates the PDF for the Gamma distribution for example values of α.

Figure 2.20: PDF for the Gamma Distribution for values α and λ [Pishro-Nik, 2017]

The cumulative failure rate or CDF is shown in Equation 2.62.

λα Z ∞ R(t) = 1 − F (t) = t(α−1) expt dt (2.62) Γ(α) 0

It can be shown when α is an integer (Equation 2.63):

α−1 X λtk exp−λt R(t) = 1 − F (t) = (2.63) k! k=0

which is the Poisson distribution [Math, 2011].

37 CHAPTER 2. RELIABILITY OF ICS/ASICS

An example [Math, 2011]: An anti-aircraft missile system has demonstrated a gamma failure distribution with α = 3 and λ = 0.05. What is the reliability for a 24 hour mission time and the hazard rate at the end of 24 hours, since α is an integer (Equation 2.64).

α−1 X λtk exp−λt R(t) =F (t) = (2.64) k! k=0 3−1 X 0.05(24)k exp−0.05t R(24) = (2.65) k! k=0 R(24) = 0.301 + 0.362 + 0.216 = 0.88 (2.66)

The hazard function for the gamma is Equation 2.67.

f(t) h(t) = (2.67) R(t)

The PDF is shown in Equation 2.68.

λ f(t) = (λt)(α−1) exp−λt (2.68) (α − 1) 0.05 f(t) = (0.05(24))(3−1) exp−.0.05(24) (2.69) (3 − 1) f(t) = 0.011 (2.70)

and the hazard calculation is Equation 2.71.

0.011) h(24) = (2.71) R(0.88) h(24) = 0.012 failures/hour (2.72)

38 CHAPTER 2. RELIABILITY OF ICS/ASICS

2.3 Discrete Distributions

Other useful probability distribution are the Poisson, Bi-nomial and Chi-Square distribution. These distributions are discrete distributions used in physics, engineering and manufacturing. They describe the probability of occurrence for discrete random events or processes controlled by chance. They are related and express the probability of a given number of events occurring in a fixed interval of time and/or space, if these events occur with a known average rate and independently of the time since the last event [Franken, 1970]. If you sample a population in order to determine defects, discrete values are obtained such as the part is good or the part is defective. These distributions are use to describe the probability of occurrence for discrete random (controlled by chance) events/processes. Examples are the number of defects observed on a silicon wafer or the number of manufacturing defects observed to come off the assembly line in given time intervals, and to calculate FIT rates for a IC/ASIC device. These distributions are used to estimate lifetimes when part failure data in time is not available. The following sections give the definitions and a small example of how they can be used in IC/ASIC fabrication.

2.3.1 Poisson Distribution

The Poisson distribution is a discrete distribution and used to describe the probability of occurrence of a random variable or processes. The Poisson random variable must satisfy the following conditions [Bourne, 2018], [Wikipedia, 2017c]:

1. The number of successes in two disjoint time intervals is independent

2. The probability of a success during a small time interval is proportional to the entire length of the time interval

3. The occurrence of one event does not aﬀect the probability that a second event will occur. They occur independently

39 CHAPTER 2. RELIABILITY OF ICS/ASICS

4. The rate at which events occur is constant. The rate cannot be higher in some intervals and lower in other intervals

5. Two events cannot occur at exactly the same instant; instead, at each very small sub-interval exactly one event either occurs or does not occur

6. The probability of an event in a small sub-interval is proportional to the length of the sub-interval

If these conditions are met, then k is a Poisson random variable and the distribution of k is a Poisson distribution. Many times a certain event occurs in a speciﬁc time interval or in a speciﬁc length or area. Examples are:

1. defects per silicon wafer

2. Number of late shipments per 1,000 shipments

3. Number of bugs per byte of code

4. Number of pieces scrapped per 1,000,000 pieces produced

5. Survival rate analysis

6. Birth defects and genetic mutations

7. The number of phone calls received at an exchange or call center in an hour

Equation 2.73 is the Poisson distribution.

λk P (X = k) = f(k) = exp−λ (2.73) k!

where:

k = 0, 1, 2,...

40 CHAPTER 2. RELIABILITY OF ICS/ASICS

λ is the mean number of successes in the given time interval or region of space

If λ is the average number of successes E(X) occurring in a given time interval or region for the Poisson distribution, then the mean λ and the variance V(X) of the Poisson distribution are both equal to λ (Equation 2.74).

E(X) = λ; V (X) = σ2 = λ (2.74)

The Probability Mass Function (PMF) gives the probability that a discrete random variable is exactly equal to a value. Figure 2.21 shows plots for the Poisson PMF for various values of k. Figure 2.22 shows the plots for Poisson CDF.

Figure 2.21: The Poisson PMF [Wikipedia, 2017c]

Figure 2.22: The Poisson CDF [Wikipedia, 2017c]

Example [Wiley, 2017]: Assume that the number of particles of contamination

41 CHAPTER 2. RELIABILITY OF ICS/ASICS on a wafer follow a Poisson distribution with 1.5 particles per square inch. The speciﬁcations for a 6-inch diameter wafer state that there must be 24 or fewer particles in each of the sectors of the wafer. The objective of this type of speciﬁcation is to limit the number and the clustering of particles. What yield is expected from the current process?

1. For six-inch diameter wafer, the area is 32 = 28.27 square inches.

2. For each sector, the area is 28.27/6 = 4.71 square inches.

3. Consequently, the mean number of particles per sector is 4.71 in2 x 1.5 particles/in2 = 7.06 particles.

Let X have a Poisson distribution with = 7.06, the probability that there are 12 or fewer particles in a sector is Equation 2.75.

λk exp12 7.0612 P (X ≤ 12) = exp−λ = = 0.9714 = 97.14% (2.75) k! k!

2.3.2 Chi-Square Disribution

Another useful probability distribution is the Chi-Square (pronounced Kai-Square) distribution. This distribution is used to estimate lifetimes when part failure data in time is not available. The Chi-Squared distribution is used for reliability demonstration test design when the failure rate behavior of the product follows an exponential distribution. It is well known in reliability engineering for testing the “goodness of ﬁt”. The devices/processes are treated as good or defective with discrete values where means there are 2 degrees of freedom. The Chi-Square distribution is used in estimating the lifetimes of an IC/ASIC in the High Temperature Operating Lifetime Test (HTOL). HTOL is a reliability test applied to IC/ASICs to determine their intrinsic reliability. The HTOL test stresses the IC/ASICs at elevated temperatures, elevated

42 CHAPTER 2. RELIABILITY OF ICS/ASICS

voltage and dynamic operation for a predeﬁned period of time. The IC/ASIC is monitored under stress and tested at intermediate intervals. HTOL test is sometimes referred to as a ”lifetime test”. The value χ2 can be computed by performing k trials and note the observed value Oi versus the expected value Ei then this sampling distribution will follow a Chi-Square distribution as shown in Equation 2.76 [McPherson, 2013].

k X (Oi − Ei) χ2 = (2.76) E i=1 i The Chi-Square distribution has the following properties [Berman, 2017]:

The mean is equal to the number of degrees of freedom: = v = k.

The variance is equal to two times the number of degrees of freedom: σ2 = 2×v

When the degrees of freedom are ≥ 2, the maximum value for PDF occurs when χ2 = v − 2. As the degrees of freedom increase, the Chi-Square curve approaches a normal distribution.

Figure 2.23 shows the plots for Chi-Square PDF.

Figure 2.23: The Chi-Square PDF [Wikipedia, 2017a]

The Chi-Square Distribution is constructed so that the total area under the curve is equal to 1. The area under the curve between 0 and a particular Chi-Square value,

43 CHAPTER 2. RELIABILITY OF ICS/ASICS has a cumulative probability associated with that Chi-Square value. Figure 2.24 shows the plots for Chi-Square CDF.

Figure 2.24: The Chi-Square CDF [Wikipedia, 2017a]

For example, in the Figure 2.25 below, the shaded area represents a cumulative probability associated with a Chi-Square statistic equal to A or the probability that the value of a Chi-Square statistic will fall between 0 and A [Berman, 2017] [weibull.com, 2017].

Figure 2.25: Chi Square Statistic [Berman, 2017]

χ2 (1 − P, v) is the upper end of the range and χ2 (P, v) is the lower end of the speciﬁed range. To ﬁnd a defective fraction F , for a single Sample Size (SS) from a large population of the IC/ASICs, it is expected the number of defects is SS ×F . But

x it is observes the number of defects is SS × Fs from the sampling. Let Fs = SS where

44 CHAPTER 2. RELIABILITY OF ICS/ASICS

x is the number of defective IC/ASIC devices, which can be described by Equation 2.77 [McPherson, 2013].

χ2 (1 − P, v) χ2 (P, v) ≤ SS ≤ (2.77) x 2 x 2 [( SS )−F ] [( SS )−F ] F F Since the IC/ASIC is defective or non-defective, then the number of degrees of freedom is equal to v = k − 1 = 2 − 1 = 1. The upper end (left side of Equation 2.77) and the SS is randomly drawn from the population for a P conﬁdence level. The upper end of the range in Equation 2.77 can be used to determine the sample size SS that should be drawn from the population to be at a P conﬁdence that the fraction defective in the population is ≤ F we have Equation 2.78 [McPherson, 2013].

χ2 (P, v = 1) SS = (2.78) x 2 [( SS )−F ] F Conﬁdence intervals for the Chi Square distribution can be deﬁned as in Equation 2.79. χ2 (1 − P, v) ≤ χ2 ≤ χ2 (P, v) (2.79)

The Confidence interval has a Confidence Level (CL), which in general terms quan- tifies the level of confidence that the parameter lies in the interval.

Using Chi square in Reliability

The Chi square distribution is one of the most widely used probability distributions in inferential statistics. Examples of where Chi square is used follows:

1. Goodness of ﬁt tests

2. In hypothesis testing

3. Estimating variances

45 CHAPTER 2. RELIABILITY OF ICS/ASICS

4. Independence of two criteria of classiﬁcation of qualitative data

5. Friedmans analysis of variance by ranks

6. Estimating the slope of a regression line Via its role in Students t-distribution

7. Analysis of variance problems Via its role in the F-distribution [Morteza and Ahmadabadi, 2010]

The Chi square can be used when the failure distribution is exponential such as IC/ASIC aging where the failure in time distribution is exponential. The exponential distribution PDF is shown in Equation 2.80 [weibull.com, 2017] [McPherson, 2013].

f(t) = λ exp−λt (2.80)

where λ is the failure rate. For the exponential distribution, the Mean Time To Failure (MTTF) is the inverse of the failure rate which is equal to the mean of the exponential distribution shown in Equation 2.81.

R(t) = λ exp−λt (2.81)

The reliability function (R(t)) for an exponential distribution is Equation 2.82.

1 MTTF = (2.82) λ

There is a one-to-one relationship between the failure rate MTTF and reliability R. If T is the accumulated test time (T ) then Equation 2.83 is used to calculate T .

χ2 1 CL,2(r+1) = (2.83) 2T MTTF

where r is the number of the failures and CL is the conﬁdence level.

46 CHAPTER 2. RELIABILITY OF ICS/ASICS

Why can the Chi-Squared distribution be used for design of reliability demonstration test [weibull.com, 2017]. Equation 2.84 can be used when the failures times follow an exponential distribution. Then the number of failures in the time interval T follows a Poisson distribution with the associate parameter λT .

(λT )i exp−(λT ) P [N(T ) = i] = (2.84) i!

where N(T ) is the number of events during time T. The upper bound of the failure rate λ can be found by Equation 2.85.

r X (λT )i exp−(λT ) 1 − CL = (2.85) i! i=0 where:

r is the total number of failures

CL is the conﬁdence level

λ is the failure rate at the conﬁndence level of CL

From Equation 2.85 the relationship from the Poisson distribution to the Chi square distribution can be shown. Letting x = λT , then Equation 2.85 becomes Equation 2.86. r X xi exp−x 1 − CL = (2.86) i! i=0 For a given conﬁdence level CL, the corresponding upper bound of a random variable X can be solved by Equation 2.87.

r X xi exp−x Pr(X < x) = CL = 1 − (2.87) i! i=0

It can be shown that Equation 2.87 can be related to the Gamma distribution

47 CHAPTER 2. RELIABILITY OF ICS/ASICS

Y ∼ Gamma(k, λ). The CDF for the Gamma distribution is Equation 2.88.

k−1 X (λy)i exp−λy Pr(Y < y) = F (y, k, λ) = 1 − (2.88) i! i=0

Comparing Equation 2.87 with Equation 2.88 it can be shown that the Gamma distribution X ∼ Gamma(r + 1, 1). Based on the properties of a Gamma random

2 variable, 2X ∼ Gamma(r + 1, 2), it can be shown χ2(r+1) is a special case of the Gamma distribution if the random variable follows Gamma(r + 1, 2). Therefore,

2 2X ≈ χ2(r+1). Since x = λT , the upper bound of the failure rate is Equation 2.89.

χ2 1 λ = CL,2(r+1) = (2.89) 2T MTTF

48 Chapter 3

Aging Mechanism of CMOS Devices

In this section the following mechanisms of the aging process for a CMOS device will be brieﬂy discussed for completeness: Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), and Hot Carrier Injection (HCI). These mechanisms result in creating charged centers in the gate oxide layer over time when the IC/ASIC is operating. These charged centers eﬀect the potential distribution within the transistor and degrade transistor performance by increasing

the transistor threshold voltage (Vth) and decrease in saturation drive current (IDsat ) and transconductance (gm). The exponential character of the model equations for both NBTI and HCI reveals extreme sensitivity of the device lifetime to the variation of the device parameters that are controlled by manufacturing process. The CMOS technology scaling and rising complexity of manufacturing process, create variations of device parameters that are critical for device lifetime [Shiyanovskii et al., 2010]. Time Dependent Dielectric Breakdown (TDDB) is a catastrophic failure, not a degradation or aging mechanism. TDDB must be accounted for in the design and manufacture of the dielectrics in the IC/ASIC.

49 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

This section will also discuss failure mechanism Electromigration (EM) and Time Dependent Dielectric Breakdown (TDDB). EM aﬀects the resistance of the interconnect wires, vias and transistor contacts over time. This increase in resistance will cause an increase in the delay of a circuit, and eventual a timing failure will occur. TDDB is a catastrophic failure, not a degradation or aging mechanism, and must be accounted for in the design and manufacture of the dielectrics in the IC/ASIC.

3.0.1 xBTI = NBTI and PBTI

NBTI and PBTI effects have been known since the very early developments of MOS- FET devices. In nano-scale IC/ASIC technologies they are a major degradation mechanisms. NBTI has effects on the p-channel MOSFETs and PBTI has effects on the n-channel MOSFETs. NBTI causes a significant threshold voltage shift (50 - 100mV ) and decrease in drain current mostly in p-channel MOSFETs under a negative gate bias and at elevated temperatures (100 − 150◦C). PBTI effects mostly in p-channel MOSFETs under a position gate bias and at elevated temperatures 3.1 [Shiyanovskii et al., 2009b]. For the discussion, NBTI and PBTI will be combined as xBTI. There are many models proposed to explain the xBTI effects. These include oxide hole injection, electron tunneling and the diffusion-reaction models. The most accepted model is the diffusion-reaction (or electrochemical) model concept that re-

lates the activation energy Ea to the diﬀusion of hydrogen, which dissociate at the interface with the multiple hydrogen-terminated Si bonds (Si − H). the deposition processes for current MOSFETs employ oxynitride, SiON layer as a gate dielectric material deposited by plasma enhanced CVD or rapid thermal oxidation in presence

of NO or NO2 gases [Shiyanovskii et al., 2009b]. The transistors of an inverter are under stress in a design as shown in Figure 3.2 that illustrates when the conditions for xBTI occur in an IC/ASIC design.

50 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

Figure 3.1: Threshold voltage shifts as a function of stress time under NBTI vs channel length [Yan-Rong et al., 2010]

Figure 3.2: CMOS Inverter xBTI stress in a design [Shiyanovskii et al., 2009c]

51 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

The xBTI eﬀect is by the breaking of Si − H bonds in the Si − SiO2 interface in the diﬀusion-reaction model [Liu et al., 2002], [Alam, 2003], [Schroder and Babcock, 2003]. The transistor channel consists of a silicon lattice (Si),

which interfaces with a gate oxide layer consisting of silicon dioxide (SiO2), shown in

Figure 3.3. Due to a crystal mismatch at the Si − SiO2 interface, there are dangling Si bonds, called interface traps, which are present at the interface. Hydrogen (H) is usually used to passivate most of the interface traps [Shiyanovskii et al., 2010].

Figure 3.3: Silicon Lattice interface at Gate Oxide [Shiyanovskii et al., 2009c]

The breaking of the Si − H occurs when the MOSFET transistors are under stress. This results in a dangling silicon interface trap, increase in Vth and the released

hydrogen forming into H2 within the gate oxide as shown in Figure 3.4. The change P in the number of interface traps can be described as ∆Nit ∝ (broken SiH bonds).

The change in Vth, IDsat and transistor delay τd are also proportionally related with

the change in Nit as shown in equation 3.1:

X ∆τd ∝ ∆Vth ∝ ∆IDsat ∝ ∆Nit ∝ (broken Si − H bonds) (3.1)

The aging mechanism as a function of time can be described as follows using the

static NBTI neutral H2 diﬀusion model [Vattikonda, 2006] shown in Equation 3.2.

2 1 Nit = K 3 × t 6 + Nit0 (3.2)

52 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

The value K is calculated by Equation 3.3.

s ε V gs−V th −Ea ox T E K ∝ (Vgs − Vth) × e ox 0 × e kT (3.3) Tox

Figure 3.4: Illustrating the eﬀects of PMOS NBTI eﬀect on a CMOS inverter under stress [Shiyanovskii et al., 2009c]

where Nit0 is the initial number of interface traps of Nit, t is stress time, Tox is the

gate oxide thickness, Vgs is the gate to source voltage, Vth is the threshold voltage, k

is the Boltzmann constant, T is the temperature, E0 and Ea are ﬁtted coeﬃcients of 1.92.0MV/cm and 0.12eV , respectively. Equation 3.4 describes how NBTI causes a shift in a transistors performance.

Ea βVgs k T n ∆p = A0e e B t (3.4)

where ∆p is a shift in a device parameter such as ∆Vth or ∆IDsat , A0 is derived from the CMOS gate oxide and process technology, β is the measured gate sensitivity,

Vth is the threshold voltage, Ea is the apparent activation energy, t is stress time, n is measured stress time exponent, k is the Boltzmann constant, and T is the temperature. The equations 3.3 and 3.5 demonstrate that NBTI eﬀect increases with elevated temperature. The eﬀect is due to the creation of interface traps and to buildup of positive

53 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

oxide charge over periods of time (from several months to years depending on the device operation conditions). Trapped holes can be thermally activated and can

cause dissociation of oxide defects. The threshold voltage shift ∆Vth is expressed as shown in Equation 3.5.

( −Ea ) ∆Vth = A0(Vg; t) exp kT (3.5)

where Ea is the NBTI activation energy and A(Vg; t) is a function of gate voltage and time,[Bernstein et al., 2006], [Gielen et al., 2008], [Stathis and Zafar, 2006], [Shiyanovskii et al., 2010]. NBTI temperature dependence is shown in Figure 3.5.

Figure 3.5: Measurement of NBTI at diﬀerent temperatures

54 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

3.0.2 Hot Carrier Injection (HCI)

The term hot carrier injection describes electrons (holes) that have accumulated suf- ﬁcient kinetic energy to overcome potential barrier and be injected into the gate oxide. Such accumulation occurs in high electric ﬁeld for electrons that have avoided subsequent scatterings with the lattice atoms. The operational conditions and the toggling frequency of the CMOS transistor are direct contributors to the HCI rate

[Schroder and Babcock, 2003]. The carriers must overcome the SiSiO2 energy barrier of about 3.7eV for electrons and 4.6eV for holes. For NMOS, hot electrons are produced and for PMOS holes are produced. The average free path of hot electrons decreases with the rise in temperature. The HCI eﬀect is enhanced at low temperature operation. Injection of hot carriers can result from generation of new traps at

or near the SiSiO2 interface or generation of new traps in the oxide itself. The traps located at SiSiO2 interface aﬀect the transconductance, gm, and leakage current of the device. The traps that are located in the gate oxide increase the threshold voltage,

Vth. The carriers can also increase the substrate current, Isub. Thus, the HCI degradation can be monitored through shifts in the threshold voltage or transconductance and drain current. There are four known mechanism for HCI, and they describe the conditions for

carriers to enter the gate oxide as listed below when the voltage on the gate (Vg)

approximately equal to the voltage on drain (Vd):

CHE: Channel hot-electron

DAHC: Drain Avalanche hot-carrier

SGHE: Secondary generated hot-electron

SHE: Substrate hot-electron

The conditions necessary for the hot carrier mechanisms are listed below:

55 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

CHE: Vg ≈ Vd

DAHC: Vg << Vd

SGHE: Vd > Vg

SHE: |Vsub| >> 0

Figure 3.6 illustrates the injection mechanisms for CHE, DAHC, SGHE and SHE. The effects of HCI are more prominent in NMOS devices compared to the PMOS devices. It requires 3.3eV for electrons to overcome the surface energy barrier at the Si − SiO2 interface and get injected into the oxide, compared to 4.6eV for holes [Schroder and Babcock, 2003]. Hot carrier effects are created about or aggravated by reductions in device dimensions without corresponding reductions in operating voltages, resulting in higher electric fields internal to the device.

Figure 3.6: HCI eﬀects: CHE(V d = V g), DAHC(V d = 2Vg), SGHE Vd > Vg,SHE(|Vsub| >> 0 [Shiyanovskii et al., 2009c]

CHE injection is at a maximum with Vg ≈ Vd. Channel carriers that travel from the source to the drain are sometimes driven towards the gate oxide and can

be trapped in the SiO2 region. DAHC injection occurs under the stress condition

Vg << Vd. This occurs as hot electrons and hot holes are injected into the dielectric. The carriers gain their energy from the high electric ﬁeld in the drain region. SGHE

is a photon generation process. SGHE stress condition is Vd > Vg. Photons are

56 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

generated in the high ﬁeld region near the drain and induce electron-hole pairs. The second eﬀect is the avalanche condition near the drain region leading to the injection of both, electrons and holes into the gate dielectric. SHE injection is a result of a

high positive or negative bias at the substrate (|Vsub| >> 0) Vg ≈ Vd. Figure 3.6 shows the operating region where HCI conditions CHE and DAHC occur during IC/ASIC operation. The most physically destructive HCI mechanism is DAHC injection [Takeda et al., 1983]. This type of carrier injection occurs when the

drain voltage, Vd, is much greater then the gate voltage, Vg (worse case Vd = 2Vg). Such conditions create a very high electric ﬁeld near the drain region. This high electric ﬁeld accelerates the carriers into the drain depletion region. The high rate of acceleration propels the carriers to collide with Si lattice atoms and through impact ionization, create displaced electron-hole pairs, shown by the yellow region in Figure 3.6. The majority of the generated holes are usually absorbed by the substrate and thus increases the substrate current, Isub Some of the generated electrons proceed to the drain and result in increased drain current, Id. However, some of the electron - hole pairs gain enough energy to breach the Si − SiO2 interface energy barrier, 3.7eV for electrons and 4:6eV for holes. Once, the carriers have passed the energy barrier of the Si − SiO2, they can either be trapped at the Si − SiO2 interface, within the oxide itself or become gate current,

Ig. After the bulk silicon has been cleaved, and the exposed silicon bonds have been passivated during the manufacturing process, Si − H bonds are formed as shown in Figure 3.3. Carriers with enough energy, 0.3eV , can break these weak Si − H bonds and get trapped thus forming a space charge. Over time, as more and more carriers are trapped, there is an increase in threshold voltage, Vt, and a change in conveyed conductance, gm for NMOS transistors. These changes in device characteristics result in decrease performance and eventual device failure [Shiyanovskii et al., 2009c]. There have been several models describing the eﬀect of HCI on device lifetime.

57 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

The ﬁrst model, shown in 3.6, expresses generated interface traps through set of

experimentally measured characteristics such as: the substrate current (Isub), drain current (ID), the degradation parameters extracted from wafer measurements (n, m and H), the time duration per transition (TS), and the total number of transistor switching (NS) [Jiang et al., 1998].

Z T s 1 1−m m n ∆Nit ∝ NS × Id (t) × Isub(t)dt) (3.6) WH 0

The second model characterizes HCI eﬀect through the mean free path of hot - electron, λe shown in Equation 3.7 [Li et al., 2008].

h ( −φit,e )in ∆Nit = C1 Ids/W × exp qλeEm × tn (3.7)

where W is the width of the CMOS device, Em is the electric ﬁeld at the drain,

Ids is the drain to source current, φit,e is the critical energy of an electron to generate interface traps ∆Nit , q is the charge of an electron, t is the stress time, the value of n ranges between 0.5 and 1 and C1 is a process constant [Jiang et al., 1998].

The third model expresses device the lifetime through the substrate current, Isub (Equation 3.8 [Li et al., 2008].

n Isub EaHCI tf = AHCI exp (3.8) W kBT

where tf is the time to failure, Isub is the substrate current, EaHCI is the apparent activation energy (0.1 to 0.2eV ), kB is the Boltzmanns constant, T is the temperature in Kelvin, n is a process dependent constant, and AHCI is a model pre-factor. The exponential character of model equations for HCI (and NBTI) reveal extreme sensitivity of the device lifetime to the variation of the device parameters that are controlled by the manufacturing process [Shiyanovskii et al., 2010], [Shiyanovskii et al., 2009c],

58 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

[Shiyanovskii et al., 2009b].

59 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

3.0.3 TDDB

Time Dependent Dielectric Breakdown (TDDB) is not an aging mechanism. TDDB is due to very high electrical fields in the gate dielectric of the MOSFET devices in an IC/ASIC. After a period of degradation due to bond breakage and/or trap creation the dielectric eventually undergoes a breakdown as illustrated in Figure 3.7. The breakdown is caused by a thermal runaway condition due to high current flow. This localized current density and associated severe heating can result in a conductive filament forming in the dielectric shorting the gate to the substrate in the MOSFET device (see Figure 3.8). A failure due to TDDB is a catastrophic failure.

Figure 3.7: A. Dielectric degradation occurs due to broken bonds/trap-creation in the dielectric material and at the SiO2/Si interface [McPherson, 2013]

Figure 3.8 shows the trapping of the holes initially and then followed by electron trapping continues up to the point of catastrophic breakdown whereby the localized Joule heating produces a melt-ﬁlament shorting the poly-gate and silicon substrate. In very thin dielectrics (10 nm), the pre-breakdown leakage may show a stress-induced leakage current increase prior to breakdown of the dielectric. Also, hyper-thin dielectrics (4 nm) can show soft breakdown characteristics [McPherson, 2013]. Historically there are two models used to describe TDDB. The E-Model that is ﬁeld driven and 1/E model, which is current driven.

60 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

Figure 3.8: Poly Short due to TDDB [McPherson, 2013]

61 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

TDDB: Exponential E-Model

In the E-Model low fields and high temperature results in TDDB due to field enhanced thermal bond breakage. The field stretches the molecular bonds thus making them

weaker and more susceptible to breakage by Boltzmann’s thermal processes. The tf Equation 3.9 is the inverse of the degradation rate and decrease exponentially with the ﬁeld [McPherson, 2013].

Q tf = A0 exp (−γEox) exp (3.9) KBT

where:

γ is the ﬁeld acceleration parameter,

Eox is the electric ﬁeld in the oxide and is given by the voltage dropped Vox

across the dielectric divided by the oxide thickness tox,

Q is the activation energy (enthalpy of activation), and

A0 is a process/material-dependent coeﬃcient that varies for each node and

causes the tf to actually become a times-to-failure distribution, usually model as Weibull distribution.

62 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

TDDB: Exponential 1/E-Model

The 1/E Model for TDDB damage is assumed to be due to current ﬂow through the dielectric due to FowlerNordheim (FN) conduction. Electrons are injected by F-N conduction band of the dielectric from the cathode to the anode. As the electron are accelerated through the dielectric because of the impact ionization the dielectric. Hot holes can also be produced, which could tunnel back causing dielectric damage.

Since the degradation of the dielectric are the result of F-N conduction the tf is an

1 exponential dependence on the reciprocal of the electric ﬁeld i.e. E shown in Equation 3.10 [McPherson, 2013]:

G(T ) tf = τ0(T ) exp (3.10) Eox

where:

τ0(T ) a temperature-dependent prefactor

G(T ) is a temperature-dependent ﬁeld acceleration parameter for the 1/E- Model.

63 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

TDDB: Power-Law Voltage V-Model

˙ For thin SiO2 dielectrics (40A), a power-law voltage model has been proposed for TDDB in the form of Equation 3.11:

−n tf = B0 (T )[V ] (3.11)

This model assumes for ballistic transport there is no scattering of the engery or energy loss in the ultra thin dielectric ﬁlms. The amount of energy delivered to the anode is e × V . For ultra thin oxides the exponent observed is in the range of n = 40-48 [McPherson, 2013].

√ TDDB: Exponential E-Model

For poor quality SiO2 or low k dielectrics the mechanism has been proposed to be due to Poole-Frenkel eﬀect (a means by which an insulator can conduct electricity) or Schottky conduction. The current induced degradation the tf model is shown in 3.12 [McPherson, 2013]: h √ i tf = C0(T ) exp −α E (3.12)

where the root-ﬁeld acceleration parameter α a is given by Equation 3.13:

∂ ln(TF ) α = − √ (3.13) ∂ E T

The physics for each of the TDDB models are different. There is no consensus in the industry on which model to use. McPherson has ranked the result as shown in Fig- ure 3.9. Shown are the four models best fittings to the same set of accelerated TDDB data. All the models tend to give a very good fitting to the four accelerated TDDB data points. But, their extrapolated results to lower electric fields are quite different. The E-Model gives the shortest time-to-failure when the results are extrapolated to

64 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES lower electric ﬁelds. The 1/E-Model gives the longest time-to-failure at lower electric ﬁelds. From this the E-Model is the most conservative and the 1/E-Model is the most optimistic in their projections of tf [McPherson, 2013]. The E-Model model is the √ most conservative, next is E-Model, then the V-Model, and lastly the 1/E-Model [McPherson, 2013].

Figure 3.9: The four models best ﬁttings to the same set of accelerated TDDB data [McPherson, 2013].

65 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

3.0.4 Electromigration (EM)

Electromigration was discovered more than 100 years ago. The ﬁrst observation was reported by the french physicist M. Gerardin in 1841. This emerged as an important area of studies since the late 1960s when electromigration damage was found to have caused failure of inductor lines in integrated circuits [Ho and Kwok, 1989]. Although EM exists whenever current ﬂows through a metal wire, the conditions necessary for EM to be a problem simply did not exist back then. It became a concern only when the relatively severe conditions necessary for the operation of an IC/ASICs, as the geometries of IC/ASIC interconnect wires keep shrinking [Lloyd, 2002]. James R Black of Motorola Inc. in 1967 studied the EM in semiconductors. He carried out experimental work that led to development of Black’s Law. The original Blacks Law model is shown in Equation 3.14 [Black, 1967].

Ea −2 k T tf50% = A0 × j × e B (3.14) where:

tf is the median time to failure in hours for 50% of the interconnect wires to fail

A0 is a constant including the failure condition in hours/A/cm2

j is the current density in the interconnect wire

Ea is the activation energy in electron volts ranging from 0.2eV to 1.33eV for Aluminum

2 is current density exponent, n = 2 nucleation

kB is Boltzmans constant

T is the temperature in Kelvin

66 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

There are many more proposed equations for EM. The General Blacks Law model shown in Equation 3.15 was generalized by Blair [Blair et al., 1971] as current density of j−2 in Black’s Law (Equation 3.14) did not ﬁt measured data as the process nodes shrank. It was found that n ranged from 1 to 2. The industry had to switch from Aluminum to Copper as the interconnect wires shrank. The reasons are described

in Chapter 4. For Aluminum n = 2, and had an activation energy (Ea) of 0.2eV to

1.33eV. Copper was found to have a n = 1 and Ea of 0.4eV to 2.07eV.

Ea −n k T tf = A0 × j × e B (3.15)

The Duty cycle model (Equation 3.16) takes into account the duty cycle of the AC waveform (d) in the interconnect wire[English et al., 1972], [Hummel and Hoang, 1989], [Tao et al., 1994].

A0 Ea t = e kB T (3.16) f dmjn

The Blech Length model in Equation 3.17 was proposed when it was observed a critical current density was needed before EM occurred [Arzt and Nix, 1991], [Blech, 1976].

Ea −n k T tf = A0 (j − jc) e B (3.17)

The Width model in Equation 3.18 added the width of the interconnect W [Black, 1978], [Merchant, 1982], [Young and Christou, 1994], [Yan et al., 2005].

Ea −2 k T tf = A0W t × j × e B (3.18)

The Contact model was proposed to account for the contact of the metal-semiconductor of the CMOS transistors (Equation 3.19). W is the contact width, L the contact length and the constant α which relates grain size and distribution [Prokop and Joseph, 1972],

[Veshinfsky, 1995]. B0 is a process constant. It is diﬀerentiated from A0 in Black’s

67 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

Law as it may be diﬀerent for contacts as opposed to vias.

B0W α + Ea t = e L kB T (3.19) f j

The Self-heating (Joule) model shown in Equation 3.20, considered the eﬀects of the self heating due to the current ﬂow in the interconnect [Black, 1982].

Ea −2 kB (Tself +Tmetal) tf = A0 × j e (3.20)

Researchers created an Analytical model considering diﬀusion concurrently with EM (Equation 3.21), which resulted in the original Black’s Law current exponent of 2 e.g. j2 [Shatzkes and Lloyd, 1986].

2 E Cf kT −2 a kB T tf = ∗ × j e (3.21) D0 Z qρ

The Recovery model has a recovery factor for AC current ﬂow (r). Since current is ﬂowing in both direction for an AC signal, metal ions move in both directions, which causes recover from EM in the interconnect. (Equation 3.22) [Ting et al., 1993].

A Ea 0 k T tf = n e B (3.22) (javg+ − r|javg+|)

The Multilayered model considers when barriers are used in the interconnect [Tao et al., 1996]. W is the width and H is the height of the interconnect wire.

E 2 2 20 − 3π 3 1 a t = W − H + H e kB T (3.23) f 10W j

The Nucleation-Growth model consider the relative contributions of nucleation and growth. A0 and B0 are constants that contain geometric information, such as the size of the void required for failure. Given values for A0 (nucleation) and B0 (growth),

68 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

Equation 3.24 shows that the relative contributions of nucleation and growth vary as a function of the current density [Lloyd, 2007].

B0T A0kT Ea t = t + t = + e kB T (3.24) f nuc growth j2 j

Multi-Via model an empirical model (Equation 3.25) for Cu dual-damascene technology (Section 4.4) considers with a quantitative relation capable of predicting the lifetime expectancy of multi-Via structures [Marras et al., 2007].

Ea 1 −n k T γ 1− N tf = A0j e B e vias (3.25)

Current density j, is not clearly deﬁned in many published papers. Symbolically,

j could refer to javg, jpeak, jmax, jrms or jdc. The original usage is the average cur-

rent density (javg) [Black, 1969], but later these ambiguities were refined to consider pulse waveform [English et al., 1972] or electromigration recovery [Ting et al., 1993]. The current density exponent n, was originally 2 [Black, 1969], and was assumed a property of aluminum, but later fabrication techniques using barriers, liners, refractory, joule heating and shunts, revealed different values could be better modeled as nucleation and void growth [Lloyd, 2007] In Black’s Law, the failure rate is defined as when 50% of the interconnects have failures. It is not a degradation model. No implication are made for the reliability calculations e.g. the 0.1% failure distributions used by reliability engineers. The temperature T is also ambiguous in Black’s Law, because it is not clear if T is the substrate temperature or the temperature rise due to joule heating from the current in the interconnect.

69 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

3.0.5 Industry Standard Reliability Calculations

The IC/ASIC industry created a council called the Joint Electronics Devices and Engineering Council (JEDEC). JEDEC is the global leader in developing standards for the IC/ASIC industry. JEDEC collaborative eﬀorts are to ensure product inter- operability by decreasing time-to-market, reduce product development costs, which beneﬁts the industry and the consumer. JEDEC has created standards for predicting, testing and measuring failures that are used for IC/ASIC industry to predict lifetimes. The standards can be found online at www.jedec.org. These standards are elaborated in the next Sections. “JESD” is a JEDEC Standard Document and “JEP” is a JEDEC Procedure. EM is the dominate aging/degradation mechanism at today’s process node, and needs to be considered when designing an IC/ASIC. EM is discussed in detail in Chapter 4.

Industry Standards for calculating xBTI

JEDEC has multiple standards that can be used for estimating aging/degradation eﬀects due to xBTI. They are:

Standard JEP 122H [JEP122H, 2016] “Failure Mechanisms and Models for Semiconductor Devices”

Standard JESD 90 [JESD90, 2004] “A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress”

Standard JESD 241 [JESD241, 2015] “Procedure for Wafer-Level DC Charac- terization of Bias Temperature Instabilities”

JEP 122H calculations for xBTI recognizes that the current state of the xBTI models are limited by the knowledge of the physics for the mechanism, in contrast

70 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

to EM where the physics are better understood and observable with electron micro- scopes.

For a given gate oxide thickness (tox), either Equations 3.26 or 3.27 are used for phenomenological models for xBTI degradation.

E ∆p = A (V )α exp a tn (3.26) 0 G kT

E ∆p = A exp(βV ) exp a tn (3.27) 0 G kT

where:

∆p = shift in device parameter of interest (Vt, %gm, %Idsat, etc.)

A0 = pre-factor dependent on the gate oxide process and CMOS technology

Ea = apparent activation engery (experimental measured values range from -0.01 to +0.15 eV)

k = Bolztmann’s constant (8.617332478x10−5eV/◦K)

T = channel temperature in kelvins ◦K

α = measured gate voltage exponent (measured values range between 3 to 4)

β = measured gate voltage sensitivity, units are reciprocal of Voltage

t = stress time

n = measured time exponent (measured values range between 0.15 to 0.25)

The xBTI lifetime equation for Equation 3.26 is shown in Equation 3.28.

1 " # n ∆p tf50% = (3.28) α Ea A0(VG) exp kT

71 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

The xBTI lifetime equation for Equation 3.27 is shown in Equation 3.29.

1 " # n ∆p t = (3.29) f50% Ea A0 exp(βVG) exp kT

HCI

There are multiple JEDEC Standards used for HCI:

JESD 122 [JEP122H, 2016] “Failure Mechanisms and Models for Semiconductor Devices”

JESD 28-1 [JESD28-1, 2001] “N-Channel MOSFET Hot Carrier Data Analysis”

JESD 28A [JESD28A, 2001]“Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress”

JESD 60A [JESD60A, 2004] “A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress”

JESD 122 states that for sub-0.25 µm p-channel, the drive current tends to decrease like NMOS after hot carrier stress. For sub-0.25 µm p-channel, worst-case

lifetime occurs at maximum substrate current stress. The time-to-failure (tf ) model is the same as n-channel. The drive currents for the n-channel transistors tend to decrease after HCI stressing; the p-channel drive current may increase or decrease depending on channel length and stress conditions. The JESD 122 model for degradation induced by HCI is shown in Equation 3.30.

n ∆p = A0 × t (3.30) where:

∆p = shift in device parameter of interest (Vt, %gm, %Idsat, etc.)

72 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

A0 = material dependent material parameter

t = stress time

n = empirically determined exponent, a function of stress voltage, temperature and eﬀective channel length)

The N-channel transistors uses an Eyring model. The Eyring model makes the practical assumption of mathematically separable, independent variables. Equation 3.31 shows the model for an N-channel device.

E t = B(I )−N exp a (3.31) f50% sub kT

where:

B = arbitrary scale factor (strong function of proprietary factors such as doping proﬁles, sidewall spacing dimensions, etc.)

Isub = peak substrate current during stressing

N = 2 to 4

Ea = apparent activation engery (experimental measured values range from -0.2 to +0.4 eV)

k = Bolztmann’s constant (8.617332478x10−5eV/◦K)

T = channel temperature in kelvins ◦K

The P-channel transistor (< 25µm )model is shown in Equation 3.32.

E t = B(I )−N exp a (3.32) f50% sub kT

where:

73 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

B = arbitrary scale factor (strong function of proprietary factors such as doping proﬁles, sidewall spacing dimensions, etc.)

Isub = peak substrate current during stressing

N = 2 to 4

Ea = apparent activation engery (experimental measured values range from +0.1 to +0.2 eV)

k = Bolztmann’s constant (8.617332478x10−5eV/◦K)

T = channel temperature in kelvins ◦K

Industry Standards for TDDB

JEDEC has created standard procedures for testing an IC/ASIC process for TDDB:

JEP001 [JEP001A, 2014] “foundry Process Qualiﬁcation Guidelines - Backend of Life (Wafer Fabrication Manufacturing Sites)”

JEP122 [JEP122H, 2016] “Failure Mechanisms and Models for Semiconductor Devices”

JEP159 [JEP159A, 2015] “Procedure for the Evaluation of Low-k Metal Inter / Intra-Level Dielectric Integrity”

These standards specify tests and procedures for TDDB, and recommend using the model that best ﬁts the data collect when a process node is being created.

Industry Standards for EM

The JEDEC standard, JESD63 [JESD63, 1998], used by the semiconductor industry only considers the electromigration stress of direct current (DC), jdc or javg and does

74 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES not consider recovery or the joule heating in the interconnects, which are discussed in later Chapter 4.

3.0.6 Summary of IC/ASIC Aging/Degradation Models

This Section summarizes the aging/degradation time to failure (tf ) models. tf is defined when the process node is being develop. xBTI, HCI and EM are typically defined as a 10% change in a parameter. These parameters affect the timing, and are guard banded to allow for a 10% change over the defined lifetime of the IC/ASIC. The defined lifetime of an IC/ASIC is defined as the time when 0.1% of the devices fail in sub 180nm processes. The IC/ASIC manufacture process lifetime goal is typically greater 10 years. We want to use these parameters and guard bands, to create a process to make the tradeoffs between performance, cost, power and reliability of an IC/ASIC design. NBTI is a degradation of the PMOS transistor as previously described. NBTI is a charge trapping phenomenon. NBTI tf is typically less that PBTI. Equation 3.33 is used for NBTI [McPherson, 2013], [Yan et al., 2009], [Bernstein et al., 2006], [Salemi, 2008], [Schroder, 2007], [Pompl and Rhner, 2005].

Ea γNBTI Eox k T tf = A0e e B (3.33)

where:

tf failure condition (i.e. 10% Vt shift)

A0 is a process constant

γNBTI eﬀective metal charge

Eox is the electic ﬁeld across the gate and channel

Ea is 0.019eV to 0.24eV

75 CHAPTER 3. AGING MECHANISM OF CMOS DEVICES

kB is Boltzmans constant

T is the temperature in Kelvin

Equation 3.34 is the equation for HCI.

Isub Ea t = A e kB T (3.34) f 0 W

[McPherson, 2013] where:

tf failure condition (i.e. 10% Vt shift)

A0 is a process constant

Isub is the substrate current

W is the width of the transistor

Ea is 0.019eV to 0.24eV

kB is Boltzmans constant

T is the temperature in Kelvin

EM tf is usually deﬁned as a 10% change in resistance of the interconnect wire, not a failure of the wire. The EM TTF is shown in Equation 3.35.

Ea −n k T tf = A0 × j × e B (3.35)

76 Chapter 4

Interconnects

Advanced IC/ASICs have ≈ 30 miles of interconnect wires if they were laid end-to-end [Miyasato, 2018]. The Figure 4.1 illustrates the amount of interconnect wires and wire length within a IC/ASIC. With the IC/ASIC industry trying to follow Moore’s law the number of interconnect wires will continue to grow. This chapter introduces the

Figure 4.1: Interconnection distribution.[Borkar, 1999] concepts of interconnect delays, which are dependent on interconnect wire resistance, wire capacitance, wire geometrical dimensions of length, width, thickness, pitch, Vias and layers. Topics also discussed are future trends (Dennard scaling), current density and electromigration.

77 CHAPTER 4. INTERCONNECTS

4.1 Metal and Dielectric Diﬀusion

In the IC/ASIC process metal is placed over a dielectric. An issue is that the metal can migrate into the dielectric. There are two mechanisms by which metals can migrate into dielectrics. One is diffusion of the metal atoms by elevated temperature. The other is drift of metal ions from an external electric field. Ideally there would be a very sharp interface between the metal and dielectric, as the schematic diagram Figure 4.2 illustrates. But, under sufficiently high temperature, metal atoms can be activated and they will diffuse into the dielectric. There is a higher concentration of the metal atoms in the deposited metal film in a metal interconnect than the dielectric. The movement produces a net flow of metal atoms across the interface into the dielectric. The consequence is the boundary between the metal is not clearly defined as shown in Figure 4.3 [Balasinski, 2016].

Figure 4.2: Diagram showing an ideal (sharp) interface of the metal and dielectric materials [Balasinski, 2016]

There is also field enhanced ion drift that can occur if a strong electric field is applied to the dielectric and there are metal ions in the dielectric. The electric field will provide an additional driving force for ion migration inside the dielectric. Figure 4.4 shows the metal dielectric interface with an energy diagram, illustrating that the metal ions must overcome two barriers to diffuse into the dielectric film. The process by which the metal atoms or ions are initially released is complex. For metal atoms to thermally diffuse into the dielectric, the atoms need to overcome the

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Figure 4.3: Diagram showing a diﬀused metal-dielectric interface after the penetration of the metal into the dielectric [Balasinski, 2016]

Figure 4.4: Diagram showing the metal dielectric interface with an energy diagram showing how metal atoms diﬀuse out of the metal matrix into the dielectric [Balasinski, 2016]

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metallic bonding Em as was shown in Figure 4.4. A good indication of the metallic bonding Em is given by the melting point of the material. The origin of metal-ions depends on the chemistry of the interface layer. Most dielectric materials used in IC/ASICs contain oxygen. The oxidation of the metal at the dielectric surface is an important reaction that takes place in the metal dielectric interface. The Metal Oxygen (M − O) bonding strength is related to the heat of metal oxide formation. The less negative heat of oxide formation implies a lower oxidation tendency and weaker MO bonds. These bonds may not be sustained when under severe electrical and thermal stress. Figure 4.5 shows the negative heat of oxide formation per oxygen atom for a selective group of elements.

Figure 4.5: Negative heat of oxide formation per oxygen atom in various metals [Balasinski, 2016]

Al has a low melting temperature, which indicates a weaker Em barrier. How- ever, the formation of Al2O3 is very high. When an Al interconnect is deposited on a SiO2 surface, the Al reduces the SiO2 dielectric to form a thin layer of Al2O3.

The Al2O3 serves as a barrier. The Al2O3 is so dense that it can prevent Al atoms and oxygen from diﬀusing, which prevents further oxidation acting as a self-limited oxide as shown in Figure 4.6. The dense Al oxide which, has very strong AlO bonds, which prevents bond breakage in the oxide eliminating the ion generation

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[Fisher and Eizenberg, 2008], [He et al., 2011], [Mallikarjunan et al., 2002].

This strong Al − SiO2 is a very stable interface and has served the IC/ASIC industry for a long time [Balasinski, 2016].

Figure 4.6: Cross section of the Al SiO2 interface [Balasinski, 2016]

As the interconnect wires became smaller, the resistance of Al was a limiting factor. Cu replaced Al, due to it’s lower resistivity, but does not have a stable interface

to the dielectric. Most literature on Cu ion drift in SiO2 results from the oxidation of Cu at the interface. This is caused by the contamination of oxygen-containing species on the surface or from oxidation ambient due to the environment, instead

of through the reduction at the SiO2 surface. In general, if there is a Cu oxide at

the Cu − SiO2 interface, Cu ions can be generated and released into SiO2 under thermal or electrical stress. Cu has a relatively low melting temperature (1085◦C), which means its metallic bonding within Cu metal matrix is weak. Without a stable and dense interface, Cu atoms can diﬀuse thermally into low-k dielectrics at an elevated temperature or during the PVD (Physical Vapor Deposition) deposition of Cu [Balasinski, 2016]. Once Cu is ionized it diﬀuses through the dielectric due to a concentration gradient, reaching the interface with the Si where the transistors are formed [Fisher and Eizenberg, 2008]. This is why a barrier is needed for Cu (Section 4.4) .

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4.2 Electromigration Failure in Interconnects

When an electric current passes in a conductor, ions and atoms are driven towards the anode due to the momentum transfer from the electrons to the ions/atoms [Huntington and Grone, 1961]. Due to the confinement boundary imposed by the barrier layer in Cu dual-damascene interconnects, there is an accumulation of ions/atoms at the anode side and a depletion of ions/atoms at the cathode end. The dual- damascene process is how Cu interconnects are created and will be described in Sec- tion 4.4. The ion/atom accumulation at the anode leads to a compressive stress, while the depletion of atom at the cathode causes a tensile stress. These stress developments can results in two distinct failures. If the compressive stress is sufficiently high and the surrounding dielectrics are weak, metal extrusion or hillocks can form, causing short circuit [Wei et al., 2008]. Conversely a sufficiently high tensile stress can lead to void formation, which can grow and span the line or via, causing the line resistance to significantly increase, and the interconnect fails [Gignac et al., 2003]. Usually, the critical stress for extrusion formation is larger than that for void formation, and the latter is the dominant failure mechanism [De Orio, 1981]. Electromigration induced failures occur in two (2) distinctive phases; nucleation and growth. In the first phase of nucleation, no EM generated voids can be observed in the interconnect, and there is not a significant resistance change of the line detected [Marieb et al., 1995]. This phase lasts until a void is nucleated and is observed in scanning electron microscopy (SEM) pictures. After the second phase starts (growth), the void can evolve in several different ways, until the void finally grows to a critical size causing a significant resistance increase. The void may grow, and completely sever the interconnect line [Choi et al., 2008], [Besser et al., 1992]. The total EM lifetime is the sum of the time for a void to nucleate plus the time for the void to develop [De Orio, 1981]. Figure 4.7 shows the two typical failures in a copper dual-damascene line

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[Gambino et al., 2009]. In the ﬁrst case (a) the void nucleates right under the via, and tends to occur soon after nucleation. The time to failure of the interconnect is dominated by the nucleation period. If the void nucleates away from the Via (b), the void has ﬁrst to migrate towards the via, where it then grows to cause the failure. The lifetime of the interconnect is dominated by the void growth or evolution phase [Gambino et al., 2009], [De Orio, 1981].

Figure 4.7: Failures in a damascene line. (a) Failure dominated by the void nucleation phase. (b) Failure dominated by void nucleation migration and growth [Orio, 2010].

Figure 4.8 shows the EM lifetime, normalized to the expected lifetime for the 1µm technology node, as a function of the interconnect cross sectional area [Hu et al., 2006], [Hu et al., 2004]. As the dimensions of the interconnects decrease, the electromigration lifetime also decreases, due to the reduction of Via and line dimensions required for a smaller critical void to cause the failure [Hu et al., 2006]. Moreover, as the line width is reduced beyond 100nm, the growth of Cu grains during the line fabrication is also reduced, leading to smaller grain sizes [Dubreuil et al., 2008], [Yao et al., 2008], [Schwartz and Srikrishnan, 2007]. This causes the interconnect to change from a bamboo-like to polycrystalline structure, where the grain boundary diﬀusion provides an additional path for mass transport [Hu et al., 2007] of the Cu ions. Another contribution for shorter electromigration lifetimes comes from the intro-

83 CHAPTER 4. INTERCONNECTS duction of low-κ interlevel dielectrics [Noguchi et al., 2009], [Gambino et al., 2009], [De Orio, 1981], [Orio, 2010].

Figure 4.8: EM lifetime variation as a function of the interconnect dimensions [Orio, 2010].

4.3 Reliability and Electromigration (EM)

Interconnect wires are formed in the Back End of Line (BEOL) in the IC/ASIC process (Metal 1 and above). The active transistors are formed in the Front End of Line (FEOL). The Middle of the Line (MOL) (sometimes referred to Middle End of Line (MEOL)) for interconnects, first introduced for mainstream production at 20nm, can help reduce congestion for short local routes. The MOL local interconnect (Li) layers offers a way to achieve very dense local routing below the first metal layer (BEOL). There may be several of these layers available in a given process, and most do not use contacts or vias. Instead, they connect by shape overlap without any need for a cut layer. Not needing contacts makes the interconnect routing denser because contacts are larger than nets, and cannot be placed too close to nets [Carlson, 2013]. The MOL is below the first metal layer, and can be considered an extension to polysilicon local interconnect. Although MOL routing requires multiple masks, it is

84 CHAPTER 4. INTERCONNECTS less expensive to implement than traditional metal layers because it does not employ vias. These interconnect lines connect the upper and lower layers and on to the polysilicon contacts using shape overlap [Carlson, 2013]. Figure 4.9 [Beckley, 2012] illustrates the FEOL, MOL and BEOL layers in an IC/ASIC.

Figure 4.9: Active layers FEOL, MOL Local interconnect Li and BEOL Metal interconnect

The resistance of the interconnect wires is a limiting factor in the performance of an IC/ASIC. In a perfect lattice, there is no resistance. Electrons move in a periodic potential with no other interaction with the metal atoms. But a perfect lattice cannot exist above absolute zero due to atomic vibrations, vacancies, and chemical impurities. Grain boundaries and dislocations are also present. Perhaps even more important, at any temperature above 0 ◦K, the atomic vibrations are larger. The vibrations of a metal move the atoms out of their thermal equilibrium position, dis- turbing the periodic potential of the lattice, causing electron scattering by the atoms. The force due to collisions of electrons to metal atoms is called the momentum exchange. This results in EM. EM is defined as motion of ions/atoms of a thin film interconnect due to the high current densities passing through the interconnect. The motion on the ion/atoms can lead to the formation of ”voids or holes (Figure 4.7 above) and hillocks in the thin film, which can grow to a size where the interconnect resistance will increase, and unable to pass current or causes a shorting to other interconnects. Copper is known to be more resistive to electromigration than aluminum

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[Gadkari, 2005]. The industry roadmap for scaling of the wires is shown in Table 4.3.

Table 4.1: Interconnection roadmap for scaling.[IRDS, 2016]

The challenges and issues for the scaling of the interconnect wires on performance are shown in Table 4.3 list.

Table 4.2: Interconnect, etc. diﬃcult challenges.[IRDS, 2016]

An eﬀective scaling model has been established, which assumes the void is located at the cathode end of the interconnect wire containing a single Via with a drift velocity (ion/atom movement) dominated by interfacial diﬀusion as shown in Figure

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h 4.10. This model predicts that life time scales with w × J , where w is the linewidth (or the Via diameter), h the interconnect thickness, and J is the current density. The geometrical model predicts that the lifetime of the interconnect decreases by half for each new generation, it can also be aﬀected by small process variations of the interconnect dimensions.

Figure 4.10: Experiment and model of lifetime scaling versus interconnect geometry (∆Lcr).[IRDS, 2016]

The maximum equivalent dc current density (Jmax) and the maximum current

density (JEM ) is limited by the interconnect geometry scaling is shown in Figure

4.11. Jmax increases with scaling due to reduction in the interconnect cross-sectional area and the increase in the maximum operating frequencies of IC/ASICs. Practical solutions to overcome the lifetime decrease in the narrow linewidths are being pursued. Recent studies show an increasingly important role of grain structure in contributing to the drift velocity and thus the EM reliability beyond the 45nm node. Process options with Cu alloys seed layer (e.g., Al or Mn) have been shown to be an optimum approach to increase the lifetime. Other approaches are the insertion of a thin metal layer (e.g CoWP or CVD-Co) between the Cu trench and the dielectric SiCN barrier and the usage of the short length effect. The short length effect has effectively been

87 CHAPTER 4. INTERCONNECTS used to extend the current carrying capability of conductor lines and has dominated the current density design rule for interconnects[IRDS, 2016].

Figure 4.11: Evolution of Jmax (from device performance) and JEM (from targeted lifetime).[IRDS, 2016]

The issue with interconnect wires is the delay increases by the square of the length (L2). To minimize the delay of the wire requires more current drive from the gate to compensate for the increased resistance, and thus timing closure. This increase in current leads to progressively worse EM aging issues. Long wires called global interconnects are used to route VDD and voltage signal across the IC/ASIC. The wire resistance dominates the resistance of the driving gate i.e. Rwire Rdr →

2 RwireCwire ∝ L . The length of the longest wire on a IC/ASIC has increased by ≈ 20% with each new process technology. The cross sectional area of global interconnects has not scaled with each process technology. The width (w) and the (h) are not scaled down in newer process technology. In order to minimize the increase in global interconnect delay, global interconnect are placed in separate planes or layers of the IC/ASIC interconnect wiring. The use of repeaters can be used to reduce the maximum capacitance of the interconnect wiring, which will reduce the driving gate current as shown in Figure 4.12 [Magen et al., 2004]. In general the Delay = n(R × C), where n is the number

88 CHAPTER 4. INTERCONNECTS of wires a gate has to drive. Buﬀers can be added to reduce the delay Delay = 3 × RC + 2 × GateDelay.

best line

Figure 4.12: Inter-connectection distribution.

4.4 Interconnect Resistance

The IC/ASIC industry has moved from aluminum to copper for interconnect wires to decrease the resistance to increase performance. IBM introduced copper on its PowerPC microprocessor in 1998, which was revolutionary at the time. Aluminum interconnects was the standard in 1998. The rest of the industry followed more slowly. Advanced Micro Devices in 2000 produced a 180-nanometer Athlon processor, and in 2002, Intel produced a 130-nm copper Pentium 4. Fabrication cost and yield were the fundamental reasons for the slow adoption. The move was made for 3 reasons; performance, scaling and reliability. The lower resistivity of copper results in higher performance as wire delay is decreased. Also as noted in the previous section the length of the longest wire in an IC/ASIC increases by ≈ 20% with each new process, which results in increase wire resistance. The lower resistivity of copper leads to lower joule heating of the wire. This allows higher current densities for the smaller wire sizes. Reliability is also improved due to copper’s lower activation energy, making it more resistive to EM failures. Morever,

89 CHAPTER 4. INTERCONNECTS copper’s higher thermal conductivity provides more efficient heat conduction paths [Khan and Kim, 2011], [Quirk and Serda, 2001b], [Keyes and Scansen, 2006], [Matsumoto and Wade, 1999]. There are challenges with copper. Copper is difficult to pattern using the con- ventional techniques used for aluminum. Chlorine gas used to etch metals in plasma, forms chloride that does not readily evaporate. Copper quickly diffuses (hillocks) into silicon and oxides (copper poisoning). This causes spikes of copper that can be long enough to penetrate through the transistor junctions. Copper also has poor oxidation and corrosion resistance. Copper quickly oxidizes in air and does not protect the underlying copper (Section 4.1) from further oxidation [Khan and Kim, 2011]. Copper interconnects require a manufacturing process significantly different from that of aluminum-based IC/ASIC. Around 1995, IBM collaborated with equipment manufacture Novellus Systems (now part of Lam) on an electrochemical deposition (ECD) or metal plating process for copper. IBM contributed the ECD solution, which enabled copper to be plated from the bottom up without voids in high aspect ratio features. Novellus led a Damascus Alliance to address key integration issues to aid in the process adoption. Then in June of 1998, the Damascus production-ready damascene process was announced. Shortly thereafter, IC/ASIC manufactures began replacing aluminum with copper for the interconnect layers as the Age of Damascene began [Miyasato, 2018]. In 1997 IBM and Motorola introduced the process called the Dual Damascene to form copper interconnects. The name originates from Damascus the capital of Syria. The Damascene process is similar to a metal inlay process from the middle ages used in the Middle East. The Damascene process is an additive process. Figure 4.13 illustrates the differences in the process steps between Al and Cu [Khan and Kim, 2011].

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Figure 4.13: Comparison of the manufacturing process step diﬀerences between Al and Cu. [Khan and Kim, 2011]

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For the Damascene process the dielectric is deposited (shown in Yellow), and patterned using standard lithography and etching techniques to form the Via and trench as shown Figure 4.14. This is followed by the deposition of a diffusion barrier, which is typically a Ta-based layer shown in Blue in Figure 4.15. The diffusion barrier layer has two major functions. It prevents Cu atoms migrating into the interlevel dielectric (ILD), and provides good adhesion to Cu . A copper seed is then deposited by physical vapor deposition (PVD), followed by chemical electroplating of the copper to fill the Via and trench shown in Figure 4.16 (Green). The excess Cu is removed by a chemical mechanical polishing process (CMP), and an etch stop layer (also called capping layer shown in Tan), typically SiN based, is deposited. The complete interconnect structure is produced by repeating these process steps for each level of metallization completing the interconnect structure of an IC/ASIC [Justison, 2003],[De Orio, 1981], [Orio, 2010].

Figure 4.14: Copper dual-damascene fabrication process: Via patterning and Via and trench patterning [Orio, 2010].

Figure 4.15: Copper dual-damascene: Barrier layer deposition and Cu seed deposition. Cu electroplating and excess removal by chemical mechanical polishing [Orio, 2010].

The beneﬁts of introducing copper is the reduction of resistivity to 1.678 µΩ − cm

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Figure 4.16: Copper dual-damascene: Capping layer deposition [Orio, 2010]. versus 3.2 µΩ − cm for Al-0.5%Cu, which results a reduction in power consumption, tighter packing density and superior resistance to EM [Quirk and Serda, 2001a]. Ta- ble 4.4 compares the resistivity of various materials.

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Table 4.3: Resistivity and temperature coeﬃcient at 20 ◦C [GSU, 2017]

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Interconnect wires within a metal layer are describe by length (l), width(w), thickness/height (h) and pitch (P ). Pitch is the wire width and the spacing between the wires (W + S). Pitch generally refers to the minimum width (W ) and spacing (S) of a particular metal layer as shown in Figure 4.17.

Figure 4.17: Interconnect dimensions.

Interconnect wires are routed with diﬀerent widths and length within a single metal layer as shown in Figure 4.18. Vias are used to connect interconnect wires between one or more layers.

Figure 4.18: 3 wire segments with diﬀerent dimensions and branches.

The Via metal is not required to be the same metal material as the interconnect wire. Metal materials at diﬀerent layers may also be diﬀerent, for example in past

95 CHAPTER 4. INTERCONNECTS

nodes M1 may be aluminum (future nodes Co or Ru) and M2 may be Cu as shown in Figure 4.19.

Figure 4.19: Illustrating diﬀerent materials vias and interconnect wires.

Interconnect resistance is described in several ways as follows:

1. resistivity Rho

2. ρ (Greek letter Rho)

3. sheet ρ

4. sheet resistance Rs

5. wire resistance Rw

Fabrication suppliers highly guard the resistivity of their process, and generally

will use Rs or Rw. If the supplier considers the minimum width of process a competitive advantage they specify Rw. Even pitch is given in order not to reveal the width of the interconnects to the competition. Useful equation for wire resistance are shown in Equations 4.1.

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ρ(T, h, g) l R = × = ohm (4.1) t w ρ R = = Ω/m (4.2) s t ρ R = = ohm/m (4.3) w t × W P = l × W (4.4) P W ≈ × (4.5) 2 t AR = = aspect ratio = (4.6) w ρ l ρ × l ρ l 2l R = × = 2 × = = R × = R × l ohm (4.7) h w h × P h w s P w P ρ = R × h = R × h × w = R × h = R × h × (4.8) s w w w 2 P 2 = R × AR × ohm − m (4.9) W 4 (4.10)

The symbol ρ represents resistivity in units of Ohms-m (ohms-meter). ρ is dependent on Temperature (T ), thickness/height (h) and grain size (g). For example, the

−8 ◦ bulk DC resistivity of pure copper, ρ0 is 1.72×10 ohm-m at temperature 20 C (1.72 µΩ−cm or 17.2 nohm-m). Resistivity is affected by temperature, and by the thickness and grain size. Large grain sizes and small thickness can lead to a resistivity of copper as high as 7.0 × 10−8 ohms-m. For Al(0.5% Cu), ρ = 2.8µΩ − cm, which is sometimes used in process as small as 45nm. As mentioned earlier, in metals, increasing temperature increases ion vibration amplitudes, which increases collisions and reduces the current flow. This produces a positive temperature coefficient. For semiconductors, increasing temperature “shakes loose” more electrons which increases the mobility and increases current flow. This produces a negative temperature coefficient. The Equation 4.11 is the first order linear resistivity equation as a function of

temperature. The nominal temperature, Tnom, is the resistivity measured for ρnom,w

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of the wire. w is the width of the wire. The temperature coeﬃcient, α is the linear rate at which the wire changes.

ρw = ρnom,w (1 + αnom,w (T − Tnom)) (4.11)

Equation 4.12 shows how the spice simulator models the resistor. The TC2 where TC is temperature coeﬃcient is rarely reported in the literature.

2 R = R (Tnom) 1 + TC1 (T − Tnom) + TC2 (TC2( T − Tnom) (4.12)

ρ20◦ l = × (1 + α ◦ (T − T ◦ )) ohms (4.13) t w 20 20

Equation 4.14 shows the DC bulk electrical resistivity for pure aluminum. Note that a 10% change in temperature results in 4.3% change in resistivity [Rumble, 2017] [Desai et al., 1984].

ρAl = ρnom,al (1 + αnom,al (T − Tnom)) (4.14)

= 2.650 (1 + 0.004312 (T − 20◦)) µΩ − cm (4.15)

Equation 4.16 shows the DC bulk electrical resistivity for pure Cu (not annealed) [Matula, 1979b]. Pure Cu has a resistivity of 1.678 microhm-cm at 20◦C whereas annealed Cu has a higher resistivity 1.7243793 mohms-cm [Matula, 1979a], [Martienssen and Warlimont, 2005]. Any mechanical stress, thermal stress or metal impurity such as oxygen will change the resistivity. Note that a 10% change in temperature results in 4.0% change in resistivity.

ρcu = ρnom,cu (1 + αnom,cu (T − Tnom)) (4.16)

= 1.678 (1 + 0.004033 (T − 20◦)) µΩ − cm (4.17)

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For a copper interconnect “nanowire”, where the width is 44nm and the thickness

is 230nm, Equation 4.18 shows the resistivity with a Tnom at zero degrees Celsius. The resistivity increases, but the temperature coeﬃcient decreases as the copper wire becomes thinner [Schindler et al., 2003b], [Huang et al., 2008b].

ρCu,nano = ρ0◦ (1 + α0◦ (T − T0◦ )) (4.18)

= 4.25 (1 + 0.00250 (T − 0◦)) µΩ − cm (4.19)

The TC and TCR (α) of metal decreases with reductions in feature sizes, resulting in a lower α for Cu ﬁlm in IC/ASICs compared to bulk Cu. This means that the nanowires have a narrower process temperature variation than bulk copper. Equations 4.20 and 4.24 are useful linear transforms to compare diﬀerent α’s at the same nominal temperature T nom [Firiti et al., 2003], [Schindler et al., 2003a], [Guillaumond et al., 2003].

ρnew = ρold (1 + αold (Tnew − Told)) (4.20)

= 4.25 (1 + 0.00250 (20◦ − 0◦)) µΩ − cm (4.21)

ρold αnew = αold × (4.22) ρnew 4.25 = 0.00250 × = 0.002381 (4.23) 4.4625

ρcu,nano = ρ20◦ (1 + α20◦ (T − T20◦ )) (4.24)

= 4.25 (1 + 0.00250 (T − 20)) µΩ − cm (4.25)

Figure 4.20 demonstrates the temperature coeﬃcient varies with temperature (TCR or α). The thinner ﬁlms exhibit less temperature dependence when compared to the α of bulk Cu as shown in Figure 4.21 [Gadkari, 2005], [Huang et al., 2008a].

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Figure 4.20: TCR (α) versus line width. [Guillaumond et al., 2003]

Figure 4.21: TCR (α) versus line width. [Huang et al., 2008a]

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Table 4.4 shows the resistivity variations for pure Al and Cu [Roberts et al., 2015].

Table 4.4: Resistivity temperature variation for bulk pure metals

TCR Operating Min Typ Max condition (α)

Thick- - ◦ ◦ ◦ ◦ ◦ ◦ Melting Temp ◦ 0 C 20 C 25 C 70 C 85 C 125 C α20◦C ness 40 C Point - T% 260% -11% -2% 0% 180% 240% 400%

Aluminum ◦ (Al) Bulk 1.965 2.417 2.650 2.709 3.222 3.393 3.850 0.004330 660 C µΩ − cm

-27% -11% -2% 0% 19% 25% 42%

Copper ◦ (Cu) Bulk 1.272 1.543 1.678 1.712 2.017 2.119 2.389 0.004033 1083 C µΩ − cm

-26% -11% -2% 0% 18% 24% 40% Copper (Cu) Nano 3.825 4.250 4.463 4.516 4.994 5.153 5.578 0.002381 µΩ − cm

-15% -6% -1% 0% 11% 14% 24%

Table 4.4 shows actual Intel reported values for diﬀerent process nodes. Resistivity is reported in various forms such as sheet resistance, wire resistance or resistivity [Bohr et al., 1994a], [Bohr et al., 1994b], [Yang et al., 1998], [Tyagi et al., 2000b], [Jan et al., 2003], [Bai et al., 2004], [Mistry et al., 2007], [Natarajan et al., 2008a], [Jan et al., 2012], [Natarajan et al., 2014], [Kim et al., 2014], [Bohr et al., 1994a], [Mistry, 2017], [Chen et al., 2012]. In general, thin ﬁlm metal resistivity can be modeled as shown in Equation 4.26.

ρ = ρ(T, h, g) = ρ0 + ρs + ρg + ρp (4.26)

ρ0 is DC bulk resistivity

ρs is due to surface scattering

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Table 4.5: Intel Resistivity Roadmap

Dielectric M Thick- Reported Rho, # RC, Node, Node 1 M Con- Pitch, 1 ness, AR Cw Resis- uohm- lay- Vdd ps/ References nm Shrink Shrink stant, nm nm tance cm ers mm2 k

350 880 600 Al PTEOS 4 2.5 Intel ‘94

250 0.71 640 0.73 480 1.5 Al 4.1 5 1.8 Intel ‘96

Rs=85 Intel ‘98, 180 0.72 500 0.78 480 1.9 Al 4.1 3.55 6 123 mohms/sq eetimes

230 Rs=68 100, 130 0.72 350 0.70 280 1.6 Cu 1.9 3.6 6 Intel ‘00 fF/mm mohms/sq 70

Rho = 2.5 85, 90 0.69 220 0.63 150 1.4 Cu 2.5 2.9 7 1.0 Intel ‘04 uohm- 120 cm

65 0.72 210 0.95 170 1.6 Cu 2.9 8 1.0 120 Intel ‘04

0.20 Rw=3.3 Intel’07, 45 0.69 160 0.76 144 1.8 3.8 9 fF/um ohm/um ‘08

0.2 Rw=8 32 0.71 112.5 0.70 95 1.7 Cu 4.3 9 Intel ‘08 fF/um ohm/um

Intel ‘12 ULK 22 0.69 90 0.80 4.48* 9 0.75 *IEEE CDO ‘16

Rw=13 LK Intel ‘14 14 0.64 56 0.62 5.63* 13 ohm/um CDO *IEEE’16

Rw=13 Intel’17 10 36 6.61* ohm/um *IEEE’16

ρg is due to grain boundry scattering

ρs is due to phonon scattering

Figure 4.22 is a sample of SiO2/Cu/SiO2, which illustrate the Cu grain boundries [Sun, 2009]. Figure 4.23 illustrates the scattering at the grain boundries Figure 4.24 illustrates surface scattering [Cornelius and Toimil-Molares, 2010]. Figure 4.25 shows a plot of copper resistivity as a function of thickness and grain

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Figure 4.22: Copper grain boundries [Sun, 2009].

Figure 4.23: Grain boundry scattering [Cornelius and Toimil-Molares, 2010].

Figure 4.24: Surface scattering [Cornelius and Toimil-Molares, 2010].

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size [Yarimbiyik et al., 2006].

Figure 4.25: Resitivity of Cu versus thickness; all surface scattering elastic, ρ = 1 [Yarimbiyik et al., 2006].

Resistivity increases as the grain size decreases due to the increase in density of the grain boundary, which act as carrier scattering sites. The resistivity also increases as conductor size decreases due to the increase in surface scattering. Figure 4.26 shows the eﬀects of line width scaling due to scattering [Saraswat, 2003]. Furthermore, thin ﬁlm metal copper resistivity is a function of width below 10nm as shown in Figure 4.27 [Roberts et al., 2015].

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Figure 4.26: The eﬀects on Cu resistivity of line width scaling due to scattering [Saraswat, 2003].

Figure 4.27: The resistivity of copper wire as a function of line width. The total resistivity is from scattering at the liner interface, grain boundary (GB) scattering and bulk resistivity (electron-phonon scattering) [Roberts et al., 2015].

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Thin ﬁlm metals ﬁrst order approximation resistivity can be modeled as Equation 4.27, where the scattering constant C is 20nm:

C ρ = ρ 1 + (4.27) 0 d where:

ρ the electrical resistivity

ρ0 is DC bulk resistivity

d is thickness of the ﬁlm

C is the scattering constant

Below 10nm thickness, copper resistivity grows exponentially as shown in Figure 4.28 [Schmiedl et al., 2008]. For interconnect wires there are 4 parameters that aﬀect delay in a circuit. They are length, width, height and pitch. Long wires have more resistance; Thin wires also have more resistance. The closer the wire spacing (pitch) the higher the capacitance. The increase in resistance and capacitance causes an increase in delay. Contact Vias also add resistance (2 - 20 ohms), which slow down the interconnect wire. This can be overcome with multiple Vias. Refer to Figure 4.17. A simple ﬁrst order model can be used to estimate interconnect RC delay illustrating the increases have on the wire delay. Assuming that the minimum metal pitch (P ) equals twice the metal line width (w), assuming that the dielectric thickness (t) above and below a metal line equals the thickness of the metal line, and using l to denote the line length and ρ is the resistivity of the metal, Equation 4.28 can be used to estimate the line resistance (R), line capacitance (C) and RC delay.

ρl R = (4.28) t(P/2)

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Figure 4.28: Thickness dependence of the resistivity of evaporated copper ﬁlms at 293 (◦K) Experimental data (—) calculated according to the statistical model [Finzel and Wimann, 1985]; (- - -) calculated on the basis of best ﬁt [Schmiedl et al., 2008].

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Table 4.6 illustrates the metal layers (M1 - M6) for Intel’s 130 nm process

[Tyagi et al., 2000a]. The table shows how the resistance increases from M1 at the transistor level, to metal layer M6 used for power and ground.

Table 4.6: Intel 130nm process

AR Sheet Dielec- Thick- Resis- 130nm Pitch as- Resistance Cw tric RC ness tivity Intel’00 nm pect Rsq fF/mm Constant ps/mm2 nm rho ratio mOhms/sq k

M1 350 280 1.6 68 1.90 230 3.6 100

M2 448 360 1.6 55 1.98 230 3.6 58

M3 448 360 1.6 55 1.98 230 3.6 58

M4 756 570 1.5 32 1.82 230 3.6 20

M5 1120 900 1.6 20 1.80 230 3.6 8

M6 1204 1200 1.6 16 1.92 230 3.6 6

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Copper is an attractive substitute for standard aluminum interconnects due to its lower resistivity and improved electromigration resistance. The resistivity of pure Cu is 1.68 mohms-cm compared to 3.2 µΩ − cm for Al-0.5%Cu alloys used. [Timalsina and Boruchowitz, 2015] [Lacy, 2011]. Figure 4.29 list the bulk resistance for various metals [GSU, 2017].

Figure 4.29: Bulk resistivity of various metals. [GSU, 2017]

Figure 4.30 shows that the sheet resistance increases quadratically with scaling.

Figure 4.30: Sheet resistance as a function of layer pitch [Tyagi et al., 2000a]

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Figure 4.31 shows the metal pitch scaling with a 70% scaling trend (0.7x or √1 ). 2

Figure 4.31: Sheet resistance as a function of layer pitch [Brain, 2016]

Contemporary processes use copper, but copper atoms diﬀuse readily into Sili- con and damage the FETs. The copper interconnects must be encapsulated by a diﬀusion barrier as shown earlier in the description of the damascene process. Fig- ure 4.32 illustrates how the resistance increases with the decreasing in line width [Jiang et al., 2001].

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Figure 4.32: Cu line resistivity increases rapidly as line width decreases. The actual Van der Pauw pad thickness is label next to the data point. The resistivity of the largest pad with a 0.26 um thickness matches the measured data very well. [Jiang et al., 2001]

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The common method to measure the resistance of a IC/ASIC interconnect is to use the van der Pauw technique. Van der Pauw showed Equation 4.29.

d d exp −πR × exp −πR = 1 (4.29) 12,34 ρ 23,41 ρ

where:

d is the thickness of the sample

ρ = is the resistivity

R12,34 = is the resistance determined by dividing the potential diﬀerence V4V3 by the current going from 1 to 2

R23,41 = is the resistance determined by dividing the potential diﬀerence V1V2 by the current going from 4 to 3

Figure 4.33 shows how the van der Pauw are performed. After the measurements of the thickness of the sample and the two resistance values, the resistivity ρ can be calculated [qdusa, 2007], [Kasl and Hoch, 2005] and [Van der Pauw, 1958].

Figure 4.33: van der Pauw Resistivity measurment technique. [Gadkari, 2005]

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Figure 4.34: Modeled Cu resistivity as a function of both inverse width and height. Model assumes no grain boundary scattering and ρ = 0, completely inelastic sidewalll scattering. [VanOlmen et al., 2007]

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Copper (Cu) has excellent reliability. The T50 for Cu is > 100 times better than AlCu as shown in Figure 4.35.

Figure 4.35: Cu has excellent electromigration resistance. [Heidenreich et al., 1998]

The number of metal layers stack add cost, but for are needed for performance. Figure 4.36 illustrates how IC/ASIC manufactures oﬀer various metal stacks based on needs for cost versus performance. Figure 4.37 from the ITRS roadmap show the interconnect wires parameters from 90nm to 22nm. The interconnect wire resistance increases as the technology is shrinking.

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Figure 4.36: Multiple interconnect stacks for cost, density and performance (from ITRS).

Figure 4.37: Technology for 90nm to 22nm nodes (from ITRS).

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4.4.1 Interconnect Scaling

The dielectric constant for SiO2 is shown in Equation 4.30.

ε = kε0 (4.30)

−14 ε0 = 8.85 × 10 F/cm (4.31)

k = 3.9 for SiO2 (4.32)

εdi Cint = WL (4.33) tdi

Figure 4.38 show the capacitance model [Brain, 2016]. Typical wires have ≈ 0.2 fF/µm compared to 2 fF/µm for the gate capacitance. The capacitance is decreasing linearly due to the dielectrics becoming thinner.

Figure 4.38: Parallel plate capacitance model of interconnect wire [Brain, 2016]

The resistance is increasing on a steep exponential as the pitch of the lines is decreasing due to scattering aﬀects. The increase in resistance for ﬁxed pitch wires is much greater than the decrease in capacitance.Figure 4.39 illustrates how R is changing 1000X compared to the capacitance. Capacitance continues to decrease linearly as shown in Figure 4.40.

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Figure 4.39: Capacitance vs Resistance change [Stork, 2005]

Figure 4.40: Interconnect scaling [Brain, 2016]

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The total capacitance for an internal interconnect (M2 in Figure 4.41), is the line- to-line capacitance, and the layer-to-layer for the interconnect. Equation 4.34 show the total capacitance for the inner layer.

Figure 4.41: Ctotal for the line includes capacitance components from line-to-line and layer-to-layer [Brain, 2016]

Ctotal = 2Cline−line + 2Clayer−layer (4.34)

Interconnect pitch scaling is required to support the dense routing needs. Scaling improves layout density, but degrades interconnect RC delay despite the line length scaling. If we assume that the metal width (w) = space (s) = half pitch (P ) and an aspect ratio (AR) such that the metal height (h) = ARw, and Via height or thickness (t) = w, then a wire with length (L) has the following resistance and capacitance per length as shown in 4.35.

R ρ 4ρ = = , and (4.35) L wh AR × P 2 (4.36) C 2 (C + C ) h w total = L v = 2ε + = 2ε (AR + 1) (4.37) L L s t

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where ε is the dielectric constant of the Inter-Layer Dielectric (ILD) as shown in 4.41. For a ﬁxed apect ratio system with pitch scaling 0.7x described by these equations, and resulting wire length scaling of 0.7x at each technology node, the line resistance per length will increase by 1.43x at each technology node while capacitance per length will remain constant at 1x. Increasing metal aspect ration (AR) improves

1 RC delay, but diminishing returns are achieved as RC will scale as 1 + AR . The scaling diﬀerence between transistor and interconnect delay with pitch results in a more than 10X increase in the relative interconnect to transistor delay (Figure 4.41) [Brain, 2016].

2Lt LP C = 2 (C + C ) = 2εε + (4.38) t v 0 P 2t 4L2 L2 RC = 2ρεε + (4.39) 0 P 2 t2

Capacitance per micron is remaining constant at about 0.2fF/um. This is roughly 1/10 the gate capacitance. Local wires are getting faster, but not quite tracking the transistor improvement and not a major problem. Global wires are getting slower and it is no longer possible to cross a chip in one cycle. For typical wire dimensions, inductance can be ignored. Realistic wiring systems have inductance Lind = 0.2-0.5nH/mm. For wires > 2mm for 180nm when driver impedance > line impedance for Rt > 2Z0. Inductance can be ignored for long wires

(> 2mm for 180nm) when the attenuation factor > 1 : 0.5 × Rwire > Z0 Inductance needs to be considered for clocks and power grids, but not signal [Ho, 2005]. The lumped model lumps the wire resistance into single R and a total into a single C. This is good for short wires, but pessimistic and inaccurate for long wires. The R and C are proportional to length (L) as is the RC delay is proportional to the square

119 CHAPTER 4. INTERCONNECTS of the length L2:

• R and C are proportional to L

• RC delay proportional L2

Figure 4.42: RC Delay Calculation Wire [Bohr, 1995]

• c = 46ARF/um2,C = 46 × e−18(a = 1 × e−18)

The RC delay can be estimated by Equation 4.40 as shown in Figure 4.43 [Bohr, 1995]:

Figure 4.43: Interconnect scaling is limiting speed increases. [Bohr, 1995]

L L × 0.5P L × T τ = RC delay = ρ 2ε ε + (4.40) 0.5P × T r 0 T 0.5P 1 4 = 2ρε ε l2 + (4.41) r 0 T 2 P 2

Global conductor lines are getting smaller in cross sectional area, but not in length. This is causing RC signal delays to grow exponentially. From Equation 4.42, which approximates the RC delay, the length (L) stays the same but the width (w) is decreasing as shown in Figure 4.44 [Diebold, 2016].

L2 RC delay = ρε (4.42) w2

Figure 4.45 illustrates the exponential rise in interconnect delays.

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Figure 4.44: Global line scaling. [Diebold, 2016]

Figure 4.45: Delay versus Pitch. [Diebold, 2016]

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Innovations in interconnect wiring materials are being developed to decrease RC as shown in Figure 4.46 [Besser, 2017a].

Figure 4.46: Novel materials innovations drive contact and BEOL RC improvement (reduction). [Besser, 2017a]

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Dennard’s Scaling

Dennard’s scaling is a law based on a paper from 1974 co-authored be Robert Den- nard. Dennard observed as transistors get smaller the power density stays constant; therefore the power is in proportion with area, as voltage and current scale with the length [Wikipedia, 2018b]. Dennard scaling eﬀects of Moores law are shown in Ta- ble 4.7 [Hoeneisen and Mead, 1972], [Dennard et al., 1974], [Takahashi et al., 2000], [Dennard et al., 2007]. The parameters that are aﬀected by scaling are:

s scaling factor

L length

W width

H thickness

Tox oxide thickness

Eox electrical ﬁeld of oxide

j current density

φ resistivity

Jmax maximum current density

Idsat saturation current

Idsatw saturation current per cm

Imax Maxium current allowed in an interconnect

Constant scaling is denoted by the value of one. For the constant electric ﬁeld column, as the process node scales, the electric ﬁeld over the gate and channel is held constant. It requires the supply voltage as well as threshold voltage to shrink for each node

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[White and Chen, 2008]. In the constant supply voltage column the Vdd is not scaled as the process shrinks. In the lateral field column, the supply voltage and channel width is not scaled in an attempt to maintain a constant electric field. The generalized scaling column allows for different rates of scaling for supply voltage and geometric parameters. Table 4.7 illustrate how the parameters scale. The constant electrical field strength scaling is when field scaling is kept constant between the transistor gate and the channel due to Dennard scaling. This is shown as follows [Dennard et al., 1974]:

Vgs Vgs s Eox ≈ = = 1 = (MV/cm, constant field scaling) (4.43) T Tox ox s The Node scaling has not been tracking with the Dennard scaling (where Dennard √ 1 Vdd Shrink = 1 − s = 1 − 2 = 29% ) as shown in Table 4.8. s scaling stopped in 1999

Tox and s scaling stopped in 2003. The electric ﬁeld of the oxide saturated in 1999.

The Eox ration shows the Vdd scale divided by the Tox scale, and this is expected to be constant of one from year to year. Note the effective High-K+ metal gate oxide thickness, not actual. In comparison, Intel 90nm process for 1.2nm Tox at 10 year lifetime states an Eox of 7.5 MV/cm [Thompson et al., 2002]. If the supply voltage, Vdd, cannot scale anymore, then this is referred to as constant voltage scaling. This affects the electric field as shown in Equation 4.44.

Vgs Vgs Eox ≈ = = s = (MV/cm, constant voltage scaling) (4.44) T Tox ox s

Constant voltage scaling places undo stress on the gate oxide, leading to shorter lifetimes due to wear out mechanisms such as NBTI, PBTI and HCI. The transistor saturation current is model by Equation 4.45.

W ox 2 W ox 2 Idsat = (Vgs − Vt) ≈ Vdd (mA) (4.45) L Tox L Tox

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Equation 4.46 is for constant ﬁeld scaling [Dennard et al., 1974].

W 2 s ox Vdd Idsat = (4.46) L Tox s s s 1 = (4.47) s

For constant voltage scaling this becomes Equation 4.48 [White and Chen, 2008].

W I = s ox (V )2 (4.48) dsat L Tox dd s s = s (4.49)

Idsat is also expressed by industry in another form in units of milliamps per width micron, which allows comparisons across processes which is denoted by Equation 4.50.

J HW I Idsat I = dsat = dsat = s (4.50) dsat W W W s = 1 = constant (mA/um, constant field) (4.51)

For constant voltage scaling this becomes Equation 4.52.

I sI I = dsat = dsat (4.52) dsat W W s = s2 = quadratic (mA/um, constant voltage) (4.53)

The wire current density, Jmax for constant ﬁeld scaling needed to support the transistors maximum driving current, becomes Equation 4.54.

I J H I Idsat J = dsatw = dsat = dsat = s (4.54) max H H HW H W s s 2 = sJmax = linear (mA/cm , constant voltage) (4.55)

125 CHAPTER 4. INTERCONNECTS

Current scaling, which increases linearly will place stress on interconnect wires which will result in shorter lifetimes due to electromigration. For constant voltage scaling, the current density scaling becomes much worse, s3Jmax as shown in Equation 4.56:

I I sI J = dsatw = dsat = dsat (4.56) max H HW H W s s 3 2 = s Jmax = cubic (mA/cm , constant voltage scaling) (4.57)

Current scaling, which increases cubic-ally will place undo stress on interconnect wires which results in even shorter lifetimes due to electromigration illustrated by Equation 4.58:

Imax = Jmax × Area = Jmax × H × W (4.58)

Table 4.9 shows the derived equations from the published literature from Intel.

The ITRS Imax is computed from the ITRS reported Jmax and metal area over various years. The Intel Jmax was approximated from the transistor current driving strength. Table 4.10 shows the interconnect wire resistivity as reported in the literature.

The reporting of resistance has changed over the years from sheet resistance ( Rs, mohms per square) to resistivity (ρ, µΩ) ohms centimeter) and to line resistance

(Rw, ohms per micrometer). The starred (*) denotes the reported resistance value and a non-star entry is calculated from the starred value. The bulk resistivity of aluminum is 2.82µΩ − cm and bulk copper is 1.68µΩ − cm. The resistivity increases due to the manufacturing quality of the interconnect due to the grain size and electron reﬂectivity of the shrinking wire shown in Equation 4.59.

ρ ρ R = = = s2R (4.59) w HW H W w s s

Using the Fuchs-Sondheimer (FS) plus the Mayadas-Shatzkes (MS) model to cal-

126 CHAPTER 4. INTERCONNECTS culate ρ is shown in Equation 4.60 [Pyzyna et al., 2017].

3 1 1 3 1 ρ = ρ λ C (1 − p) + + ρ 1 − α + 3α2 − 3α2 ln 1 + (4.60) s b 8 e H W b 2 α

where: R λ α = g (4.61) 1 − Rg G

√ G = g HW (4.62)

The Dennard constant ﬁeld scaling for metal resistivity ρ becomes Equation 4.63.

Rg λe α = q = s α (4.63) 1 − Rg H W g s s

! 3 1 1 3 1 ρ = ρ λ C (1 − p) + + ρ 1 − (sα) + 3(sα)2 − 3(sα)2 ln 1 + s b 8 e H W b 2 (sα) s s (4.64) Equation 4.64 can be simpliﬁed to Equation 4.65, which grows quadratic-ally as the wire dimensions decrease.

s ρ = ρ + ρ (1 − s + s2) = s2ρ = quadratic(µΩ − cm) (4.65) s 2 b b s

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Table 4.7: Dennard Scaling Generalized Constant Constant Generalized Parameter Units Lateral selective Field Voltage scaling scaling

L nm 1/s 1/s 1/s 1/s 1/sL

W nm 1/s 1 1/s

H nm 1/s 1 1/s

Tox nm 1/s 1/s 1

Vdd Volts 1/s 1 1 /s

Eox MV/cm 1 s

Idsat mA 1/s s s /s /sw

Idsatw mA/µm 1 s2 j MA/cm2 s s3 s2

ρ µohm-cm s/2 s/2 s/2

Jmax MA/cm2 s s3 s2

Imaxw mA/µm 1 s2

Imax mA 1/s s

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Table 4.8: Intel Node Scaling

Intel E , Year V Shrink T , nm Shrink ox E Ratio Node dd ox MV/cm ox

1991 800 nm 5.0 20 2.50

1993 500 nm 3.3 34 % 10 50 % 3.30 1.32

1995 350 nm 2.5 40 % 6.0 40 % 4.17 1.26

1997 250 nm 1.8 28 % 4.08 32 % 4.41 1.06

1999 180 nm 1.5 17 % 2.0 51 % 7.50 1.70

2001 130 nm 1.3 13 % 1.5 25 % 8.67 1.16

2003 90 nm 1.2 8 % 1.2 20 % 10.00 1.15

2005 65 nm 1.1 8 % 1.1 8 % 10.00 1.00

2007 45 nm 1.0 9 % 1.0 9 % 10.00 1.00

2009 32 nm 1.0 0 % 0.9* 10 % 11.11 1.11

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Table 4.9: Intel Jmax and ITRS Imax Scaling

I , ITRS Intel H dsatw J I Year NMOS max max I Node nm Shrink Scale mA/µm Scale mA Shrink max mA/µm mA

350 1995 600 0.675 0.1125 0.3194 nm

250 1997 480 20% 0.755 1.12 0.1573 1.40 0.2416 24% nm

180 1999 475 1% 0.94 1.25 0.1979 1.26 0.2350 3% nm

130 2001 280 41% 1.03 1.10 0.3679 1.86 0.1803 23% 0.470 nm

90 2003 154 45% 1.00 0.97 0.6494 1.77 0.1100 39% 0.085 nm

65 2005 168 -9% 1.20 1.20 0.7143 1.10 0.1260 -15% 0.123 nm

45 2007 144 14% 1.36 1.13 0.9444 1.32 0.1088 14% 0.078 nm

32 2009 95.6 34% 1.62 1.19 1.6941 1.79 0.0911 16% 0.067 nm

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Table 4.10: Intel and ITRS predicted Resistivity

ITRS Intel R ρ ITRS H P s R ρ Year Node Shrink Metal mΩ / w µΩ- R nm Shrink nm Ω/µm µΩ- w nm cm Ω/µm cm

1997 250 480 20% 640 27% Al 110* 0.344 5.28 3.3

1999 180 475 1% 500 22% Al 85* 0.340 4.04 2.2

2001 130 280 41% 350 30% Cu 68* 0.389 1.90 2.2

2003 90 154 45% 220 37% Cu 1.358 2.5* 2.2

2005 65 168 -9% 210 5% Cu 2.2

2007 45 144 14% 160 24% Cu 3.3* 3.8 3.43 4.36

2009 32 95.6 34% 112.5 30% Cu 8* 4.3 3.80 7.81

2011 22 90 Cu 4.30 14.93

2014 14 56 Cu 13* 5.20 34.91

2017 10 36 Cu/Co 13* 6.33 79.13

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4.4.2 Dennard scaling relationship to Moore’s law

Moore’s law as commonly curve ﬁt is shown in Equation 4.67:

Y ear−1971 N = 2300 × 2 2 (4.66) or √ Y Y 0.5Y N = N0 × 2 2 = N0 × 2 = N0 × 2 (4.67)

which is every two years, Y/2, the number of transistors (N) double independently of the die size. The 2300 is the number of transistors of the Intel 4004 in the year 1971 [Moore, 1965b]. It is interesting to note that the square root of 2 can be used instead, but it is only an observation. Dennard scaling can be used periodically as one of many techniques to double the number of transistors. One Dennard method is to double the number of transistors per area.

1 The Dennard scaling constant, s, is when the Area = 2 and assuming Moore’s law halves the area for every new node using Dennard scaling illustrated by Equation 4.68.

A = HW (4.68) 2 H W = (4.69) s s HW = (4.70) s2

√ s2 = 2 therefore s = 2 ≈ 1.4, which has been noted in the literature as approximately 1.5x. The maximum current density constant ﬁeld scaling becomes Equation 4.71 [Bohr, 2004]:

√ 2 Jmax = sJmax = 2Jmax ≈ 1.4Jmax (mA/cm ) (4.71)

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which has been noted in the literature as approximately 1.5x.

Jmax is commonly expressed in to other common forms, Imaxw and Imax. Imaxw is the maximum current allowed DC current in an interconnect wire for a speciﬁc process

2 node in mA/cm . Imax is the current in mA. The design kits for process nodes specify the Imaxw for each metal layers and Vias. The Imaxw is constant relative to constant ﬁeld scaling which serves as an easy benchmark (Equations 4.72 and 4.73).

H I = J H = sJ = 1 = (mA/µm = 10 × (mA/cm2)/(nm ∗ 0.001) (4.72) maxw max max s

H W I = J HW = sJ = s = linear (mA) (4.73) max max max s s

4.4.3 ITRS scaling

This section discusses the International Technology Roadmap for Semiconductors

(ITRS) trends due to interconnect scaling, and assessing the values of Jmax, Imaxw and Imax. Comparisons are made with predictive Dennard scaling and Intel process values as published in the literature. The 28nm process node values are of interest, since they will be later used in simulations, and these values are of importance in the comparison to industry production values.

Geometrical Scaling of interconnect wire Height, Pitch and Area

Tables 4.11 show the ITRS geometrical scaling over the years 1997 through 2011. Table 4.12 shows Intel process values of interest. The Node column represents the wafer start year [Bohr, 2004] [Bohr, 2012] [Bohr, 2014] for the process in nanometers.

The MMP and M1 columns represents the minimum metal pitch (MMP) and metal layer one for that node in nm. The metal width is approximated as pitch divided by two. The Metal column is the metal material type for M1. Column AR is the aspect

133 CHAPTER 4. INTERCONNECTS

ratio for M1. Column H is the Height or thickness of the wire calculated from the aspect ratio in nanometers, i.e. AR times pitch/2. The Idsatw column is the drain saturation current in milliamps per micron (mA/um) and this is assumed to have

the same value as Imaxw. The Jmax column is calculated from Idsatw divided by the thickness (H). in units of mega amperes per centimeter squared (MA/cm2). This is a reasonable approximate assumption, since Intel does not publish this number, but allows comparison with the ITRS published values. The scale column is the scale

ratio of Jmax from the previous year. The Dennard column is Jmax scaling based on Moores law with a scaling factor (s) of square root of 2. This scaling is based on the year of 1997 using the 0.1573MA/cm2 as the initial value. This column is calculated as shown in Equation 4.74:

year −1997 year − 1997 √ 2 0.25(year−1997) Jmax = Jmax0S 2 = Jmax0 × 2 = Jmax0 × 2 (4.74)

The column Imax is the current drive of the smallest transistor in units of milliamps (mA). To keep pace with the performance, ITRS predicted Imax would keep increasing until the 32nm node. As the interconnects kept shrinking Imax could not keep increasing due to the EM aﬀects on lifetimes of the IC/ASIC. Table 4.12 shows the interconnect parameters from the 2007 ITRS roadmap and Intel published data [Allan, 2007]. The table shows that Dennard’s scaling could no longer be applied after Intel’s 22nm node.

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Table 4.11: ITRS Jmax and Imax Scaling

Idsatw Jmax Jmax Year Node MMP M1 Metal AR H Jmax Imax Imaxw Scale Dennard

1997 250 640 640 Al 1.5 480 0.755 0.1573 0.1573 0.242

1999 180 500 500 Al 1.9 475 0.940 0.1979 1.26 0.2224 0.235

2001 130 350 350 Cu 1.6 280 1.03 0.3679 1.86 0.3146 0.180

2003 90 220 220 Cu 1.4 154 1 0.6494 1.77 0.4449 0.110

2005 65 210 210 Cu 1.6 168 1.2 0.7143 1.10 0.6292 0.126

2007 45 160 160 Cu 1.8 144 1.36 0.94 1.32 0.8898 0.109

2009 32 112.5 112.5 Cu 1.7 95.6 1.62 1.69 1.79 1.2583 0.091

2011 22 80 90 Cu 1.08 1.7796

2014 14 52 70 Cu 1.04 2.9928

2017 10 36 36 Cu/Co 5.0333

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Table 4.12: Intel Jmax and Imax Scaling

Node MMP M Scale, J J Year 1 AR H I J max max I Intel Intel ITRS 2Y maxw max Scale Dennard max

2007 45 160 136 1.7 115.6 1.15 1.00 0.8898 0.0782

2008 118 1.8 106.2 1.27 1.20 0.0752

2009 32 112.5 104 0.76 1.8 93.6 1.28 1.37 1.38 1.2583 0.0667

2010 90 0.76 1.8 81.0 1.39 1.72 1.43 0.0627

2011 22 80 80 0.77 1.8 72.0 1.38 1.91 1.39 1.7796 0.0550

2012 72 0.80 1.8 64.8 1.20 1.85 1.08 0.0432

2013 64 0.80 1.9 60.8 1.37 2.25 1.18 0.0438

2014 14 52 56 0.78 1.9 53.2 1.37 2.57 1.39 2.9928 0.0383

2015 50 0.78 1.9 47.5 1.22 2.57 1.14 0.0305

2016 44 0.79 2.0 44.0 1.35 3.06 1.19 0.0296

2017 10 36 40 0.80 2.0 40.0 1.19 2.97 1.16 5.0333 0.0238

2018 36 0.82 2.0 36.0 1.16 3.23 1.06 0.0209

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Equations 4.75, 4.76, 4.77 and 4.78 show the comparison trends for M1, H, Area,

Jmax,Imaxw respectively. The Dennard scaling is based on the year 1997 as the initial value.

640 nm Dennard M1 = year−1997 (4.75) S 2

480 nm Dennard H = year−1997 (4.76) S 2

2 year−1997 Dennard Jmax = 0.1573ma/cm × S 2 (4.77)

Dennard Imaxw = 0.755ma/µm (4.78)

Figure 4.47 is a plot of the Dennard’s scaling, Intel published (MMP) and ITRS predictions for M1 pitch (y axis) in nm. The plot shows that the Dennard scaling underestimates the ITRS and Intel’s M1 pitch. The ITRS in 1997 was overestimated as they were assuming aluminum but Intel switched to copper.

137 CHAPTER 4. INTERCONNECTS

Figure 4.47: Dennard scaling underestimates Intel and ITRS for M1 (y axis = Pitch in nm)

138 CHAPTER 4. INTERCONNECTS

Figure 4.48 is Dennard scaling and Intel published and ITRS predictions M1 pitch simpliﬁed to show the trend (y axis) in nm. Again the plot shows Dennard scaling underestimates the actual M1 pitch.

Figure 4.48: Dennard scaling underestimates Intel for M1 (y axis = Pitch in nm)

139 CHAPTER 4. INTERCONNECTS

Figure 4.49 is Dennard’s scaling, Intel published and ITRS predictions for M1 pitch (y axis) in log 10 scale.

Figure 4.49: Dennard scaling underestimates Intel and ITRS for M1 (y axis = Pitch in nm log 10)

140 CHAPTER 4. INTERCONNECTS

Figure 4.50 show the metal M1 pitch trends for Dennard scaling and Intel with pitch (y axis) in log 10 scale.

Figure 4.50: Dennard scaling underestimates Intel for M1 (y axis = Pitch in nm log 10)

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Figure 4.51 is a plot of the Dennard’s scaling, Intel published and ITRS predictions

for M1 thickness (H) in nm (y axis). The plot shows that the Dennard scaling underestimates the Intel’s and ITRS M1 thickness. The ITRS in 1997 was overestimated as they were assuming aluminum but Intel switched to copper.

Figure 4.51: Dennard scaling underestimates Intel and ITRS for thickness (y axis = H in nm)

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Figure 4.52 is a simpliﬁed plot of Dennard scaling, Intel’s published and ITRS predictions for M1 thickness (H) in nm. Again Dennard scaling underestimated the pitch of M1.

Figure 4.52: Dennard scaling underestimates Intel for thickness (y axis = H in nm)

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Figure 4.53 is a plot of Dennard scaling, Intel’s published and ITRS predictions for M1 thickness (H) in nm log 10.

Figure 4.53: Dennard scaling underestimates Intel and ITRS for thickness (y axis = H in nm log 10)

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Figure 4.54 is a simpliﬁed plot to show the thickness (H) trends for Dennard, Intel and ITRS in nm log 10.

Figure 4.54: Dennard scaling underestimates Intel for thickness (y axis = H in nm log 10)

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Figures 4.55, 4.56, 4.57 and 4.58 show the maximum current density trends for Dennard, Intel and the ITRS. Intel and ITRS are not scaling at the same rate as

Dennard scaling would predict. This is explained by Idsat not scaling.

Figure 4.55 show the maximum current trends for Imaxw in mA/µm per Dennard, Intel and the ITRS predictions. The ﬁgure shows Intel is not scaling at the same rate as Dennard scaling, since Idsat is not scaling.

Figure 4.55: Plot illustrating Intel and the ITRS are not scaling Imaxw according to Dennard scaling. The 2001 - 2011 are the ITRS predicted (y = mA/µm).

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Figure 4.56 is a simpliﬁed plot of Figure 4.55 showing years 2001 - 2011 Imaxw to better show how Dennard scaling is not being followed (y = mA/µm).

Figure 4.56: Plot illustrating Intel and the ITRS are not scaling Imaxw according to Dennard scaling (y = mA/µm)

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Figure 4.57 is a plot of Imaxw in log 10 per Dennard, Intel and the ITRS predictions to further show how Dennard scaling is not being followed (y = mA/µm log 10).

Figure 4.57: Intel and the ITRS are not scaling Imaxw according to Dennard scaling (y = mA/µm log 10)

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Figure 4.58 is a simpliﬁed plot of 4.57 Imaxw in log 10 for years 2001 - 2011 to amplify how Dennard scaling is not being followed (y = mA/µm log 10).

Figure 4.58: Intel and ITRS are not scaling Imaxw according to Dennard scaling (y = mA log 10)

Figure 4.59 show the maximum current Imax trends for Dennard, Intel and the ITRS. Intel and ITRS are not scaling at the same rate as Dennard scaling would predict, because Idsat is not scaling.

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Figure 4.59: Intel is not scaling Imax according to Dennard scaling (y axis = mA)

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Dennard Aging scaling

Table 4.13 shows the Dennard scaling reliability effects. Under the constant field scaling that xBTI and TDDB remains unchanged. Electromigration lifetime decreases by Dennard scaling factor squared (sn), and worse when resistivity is considered. Elec- tromigration becomes the dominant failure mechanism under constant field whereas xBTI and TDDB dominate under constant voltage scaling. Since voltage scaling ended around 2005 as illustrated in the plot above, electromigration is now the dominate aging mechanism.

Table 4.13: Dennard Reliability eﬀects

Aging/Wearout Constant Constant Model Field Voltage

E A a tf tf EM 0 kB T tf = jn e sn s3n

E A a tf tf 0 kB T tf = ρnjn e s2n s4n

E I a HCI sub kB T tf stf tf = A0( w )e

E a tf xBTI −γnbti ·Eox kB T tf tf = A0e e es

E a tf TDDB −γox ·Eox kB T tf tf = A0e e es

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Table 4.14 shows the comparison of copper and aluminum for Dennard scaling. Clearly, Copper is a major improvement over aluminum.

Table 4.14: Dennard Reliability eﬀects on EM Copper Aluminum EM model (n=1, growth) (n=2, nucleation)

E A a tf tf 0 kB T tf = jn e s s2

E A a tf tf 0 kB T tf = ρnjn e s3 s6

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4.4.4 Interconnect Dielectric scaling

The Dielectric constant within metal layers is critical to Moores law. As metal pitches decrease according to Dennard scaling, the crosstalk signal increases and this is com- pensated by decreasing the dielectric constant. A second effect is as the dielectric constant decreases so does the thermal conductivity, thereby increasing the temperature within the die and package. Table 4.15 shows the dielectric (k) materials used and the corresponding technology nodes. Table 4.16 is organized by the technology nodes. Low-K (LK) dielectrics are classified in the range of 3.5 and 2.4. Ultralow K (ULK) dielectrics are classified below 2.4 [Beaudoin et al., 2005]. Extra Low-k Di- electric (ELK) range around 2.5 to 2.2 [Su et al., 2005]. Below 2.5, dielectrics become difficult to apply due to mechanical structural weaknesses and in the long term, may limit k to around 2.5 [Inoue, 2013].

Table 4.16: Interconnect’s Dielectric by Node

Interconnect’s Dielectric by Node

Process Metal k Dielectric Material References

250nm IBM M1 - M6 4.3 SiO2 [Gambino, 2010b]

[Gambino, 2010b], 180nm IBM M1 - M7 3.75 F-SiO2, FSG/USG [Barth et al., 2000]

ﬂuorine-doped silicate glass UMC 3.6 [Clendenin, 2001] (FSG)

Fluorine-doped oxide 130nm Intel M2 - M4 3.7 [Tyagi et al., 2000b] (SiOF/FSG)

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Interconnect’s Dielectric by Node

Black Diamond, App. Mate- AMD LK [Gupta, 2010] rials

Black Diamond, App. Mate- [Clendenin, 2001], TSMC 2.9 rials [Clendenin, 2002]

SiLK, Spin-on Dielectric, [Clendenin, 2001], IBM 2.65 Dow Chem. [Clendenin, 2002]

SiLK, Spin-on Dielectric, [Clendenin, 2001], UMC 2.65 Dow Chem. [Clendenin, 2002]

90nm TSMC 2.5 Novellus CDO PEVCD [EETimes, 2004]

Intel M2 - M6 <3.0 CDO, Carbon doped oxide [Jan et al., 2003]

Intel M1, M7 SiO2/SiN [Jan et al., 2003]

[Grill and Neumayer, 2003], IBM 3.0 SiCOH [Edelstein, 2009]

UMC 2.7 Upper layers FSG [EETimes, 2004]

[Grill and Neumayer, 2003], 65nm IBM 3.0 SiCOH [Edelstein, 2009]

Intel M1 - M8 2.9 LK CDO [Natarajan et al., 2008a]

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Interconnect’s Dielectric by Node

[Natarajan et al., 2008a],

45nm Intel M1 - M7 2.5 ULK CDO [Moon et al., 2008], [Gambino, 2007]

Intel M8 SiO2 [Moon et al., 2008]

M1 - M6, TSMC 2.55 [Chern, 2007] Mx

M7 -M8, TSMC 2.9 [Chern, 2007] My

TSMC M9 - M10 USG [Chern, 2007]

IBM M4 - M8 3.0 PECVD SiCOH [Sankaran et al., 2006]

[Sankaran et al., 2006], IBM M1 - M3 2.4 PECVD ULK porous SiCOH [Grill and Neumayer, 2003]

32nm IBM 2.4 ULK pSiCOH [Edelstein, 2009]

Intel 2.5 ULK CDO [Gambino, 2010a]

22nm IBM 2.2 pSiCOH [Edelstein, 2009]

[Jan et al., 2012], Intel M1 - M6 ULK CDO [Ingerly et al., 2012a]

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Interconnect’s Dielectric by Node

[Jan et al., 2012], Intel M7, M8 LK CDO [Ingerly et al., 2012a]

14nm Intel M11 3.9 SiO2 [Fischer et al., 2015a]

M0, M9, Intel LK CDO [Fischer et al., 2015a] M10

M1, M2,

Intel M3, M5, ULK CDO [Fischer et al., 2015a]

M7, M8

Intel M4, M6 1 Interlaced Air Gap, AG [Fischer et al., 2015a]

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Table 4.15: Interconnect Dielectric

Dielectric Published k Similar names Process

SiO2 3.9 glass 250nm

USG Undoped Silicate Glass

3.9 undoped ﬂuorosilicate glass, ﬂuorine con- 180nm IBM FSG 3.7 doped taining SiO2, F-SiO2, SiOF 130nm Intel

LK CDO LK Carbon Doped Oxide 90nm Intel

SiCOH 3.0 Carbon doped oxide, SiOCH 90nm IBM

Black Diamond 2.9 BD, Lk, Applied Materials 130nm TSMC

ATP, Aromatic thermosetting low- SiLK 2.65 130nm UMC K polymer, AMD10

Black Diamond II 2.5 Applied Materials pSiCOH 2.4 Porous SiCOH 45nm IBM

ULK CDO ULK Carbon Doped Oxide 45nm Intel

Air 1 Air Gap, limited to few layers 14nm Intel

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In spite of demand of low-k material over the technology generations, practical k-value stay around 2.5, due to diﬃculty in integration [Inoue, 2013]. Low-k dielectric materials for ILD have much lower thermal conductivities compared to SiO2 [Im et al., 2005b]. Figure 4.60 illustrates how the various low-k materials eﬀect thermal conductivity.

Figure 4.60: Correlation of the thermal conductivity to the dielectric constant of various materials [Im et al., 2005b]

4.4.5 Electromigration (EM) in interconnect wires

EM is a reliability concern for both Aluminum-based and Copper-based metallizations. Figure 4.61 shows that due to the momentum exchange between the current carrying electrons and the metal lattice, metal ions can drift under the inﬂuence of the electron wind [McPherson, 2013]. The concept of the “electron wind” driving force was ﬁrst formulated by Fiks (1959) and Huntington and Grone (1961). Independently, the authors employed a semi-classical ballistic approach to treat the collision of the moving atom by the

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Figure 4.61: Electron Wind [McPherson, 2013] charge carriers. Huntington and Grone showed that not only do the initial and ﬁnal states of the charge carriers need to be considered in the collision process, but the spatial variation of the force experienced by the moving atom had to be accounted for. These ideas yielded a driving force depending on the type of defect and the atomic conﬁguration of the jumping path. The formulation of the driving force was a major contribution to the study of electromigration. It demonstrated the possibility of using electromigration to investigate directly the interaction of mobile defects and charge carriers. This stimulated considerable interest during the 1960s in experimental studies on electromigration in metals as defects in interconnect were observed [Ho and Kwok, 1989]. The force F exerted on a metal ion due to the electron wind is directly proportional to the electron current density as shown in Equation 4.79.

∗ n F = ρ0Z eJ (4.79) where:

ρ0 resistivity of the metal

Z∗e eﬀective metal-ion charge

J n electron current density

Electromigration is due to the momentum exchange between the current carrying electrons and the metal lattice structure. Metal ions can drift under the inﬂuence

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of the electron wind caused by the current of electrons. The force (F) exerted on a metal ion due to the electron wind is directly proportional to the electron current density J e:

~ ~ F = Fwind + Fdirectforce (4.80)

Let N = ne/Z where N = atomic density

ηeρd ηe ρd ρd N Fwind = = Z = Z (4.81) ηdρ Z ηaρ ηd ρ

∗ ~ Fdirectforce = Fd = Zd qE (4.82)

∗ where Zd is valance of the metal atom

~ Fem =Fd + Fwind (4.83) ∗ ~ ρd N ~ = Zd qE − Z qE (4.84) ηd ρ ∗ ~ ρd N ~ = Zd qE − Z qE (4.85) ηd ρ = Z∗qE~ (4.86)

= Z∗qρj (4.87)

where Z∗ = Z∗ − Z ρd N is the eﬀective charge number, which is the measure d ηd ρ of ion-electron interaction. The lower the value implies lesser momentum exchange from electron to ion.

−0.9 −8 ρcu = 1.86x10 e # of grain boundries [Wen et al., 2003]

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Table 4.17: EM Terms

EM Terms

Term Description q 1.6 × 10−19 coulombs (c)

Ea 0.9eV (Ea(g) = 2.1eV ; Ea grain boundry = Ea(gb) = 0.8eV )

28 Atoms N 1.53 × 10 um3 T 573oK = 300◦C + 273.15◦C

ma 6 A 20 A j 2 cm2 = 2 × 10 cm2 = 2 × 10 m2

N kg σcu 40uP a = 4.1P a; P a = m2 = s2 Z∗ Cu = 1; Al = 4.3; eﬃciency number

β Cu = 28gP a(109P a); Al = 50gP a = Bulk Modulus

−29 −3 ΩCu 1.182 × 10 m = Atomic V olume

−29 −3 ΩAl 1.66 × 10 m = Atomic V olume 4.2 Ωcm(gb); 1.95 uΩ cm(bulk); 1.8 × 10−8Ω m; 5.66 × ρCu(T ) 10−6 Ω cm(350◦C) = Resistivity

−6 ◦ ρAl(T ) 2.67 uΩcm(gb); 4.15 × 10 Ωcm(350 C) = Resistivity

Lν Cu = 0.2um; Al = 0.2um = V oid Length n growth = 1; nucleation = 2; voids that move = −1to − 2.5

−23 J −5 eV 0 kB 1.381 × 10 ◦K ; 8.617 × 10 ◦K = Boltzman s constant Q∗ 1.387 × 10−19 ◦C = heat transport e 1.602 × 10−20

Links # of V ia links

B 5 × 107P a = Back flow stress modulus w 4um

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EM Terms

w 0.25um

Ω 1.182 × 10−23 cm3 = vacancy volume

−23 3 Dν 10 cm = vacancy volume

Figure 4.62 shows a FIB cross section of an EM failure under the Via. This is referred to as a slit failure. This is the most common form of failure in an interconnect wire and will cause an early failure. The liner underneath the Via blocks the atomic diﬀusion between the copper lines at the two levels. Figure 4.63 shows a FIB cross section of an EM failure in the interconnect wire. This is referred to a trench failure, and will fail later due to an increase in resistance of the wire by the trench. The electric current drives atoms to drift away from the Via in the lower level line [He and Suo, 2004].

Figure 4.62: A FIB cross section of the dual damascene copper line showing a slit failure under the Via. [He and Suo, 2004]

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Figure 4.63: A FIB cross section of the dual damascene copper line showing a trench failure in the interconnect line [He and Suo, 2004]

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4.5 ITRS Interconnect Scaling challenges

The most difficult challenge for interconnects is the introduction of new materials that meet the interconnect wires conductivity requirements and reduce dielectric permittivity (κ). The conductivity impact of shrinking size effects on interconnect structures must be mitigated. Future effective κ requirements preclude the use of a trench etch stop for dual damascene structures. Dimensional control is a key challenge for present and future interconnect technology generations and the resulting difficult challenges for etch is to form precise trench and Via structures in low-κ dielectric material to reduce variability in RC delay. The dominant architecture, damascene, requires tight control of pattern, etch and planarization. To extract maximum IC/ASIC performance, interconnect structures cannot tolerate variability in their profiles without producing undesirable RC timing degradation. New meteorology techniques are needed for in-line monitoring of adhesion and defects. Larger wafers and the need to limit test wafers will drive the adoption of more in situ process control techniques. From Section 4.3, Table 4.3 highlights and differentiates the top key challenges, while Table 4.3 showed the interconnect scaling roadmap. Copper (Cu) is the pre- ferred solution, but due to limits of electromigration the local interconnect (MOL),

M1, and Mx levels will embed non-Cu solutions such as Cobalt (Co) and possibly Ruthenium (Ru) [Zhang et al., 2016a], particularly for vias, due to their better ability to fill the narrow trenches on top of the improved EM performance. For non-Cu materials, two directions are proposed. One is the usage of the metals with less size effect e.g. silicides and the other is the introduction of materials that have different conductance mechanism e.g. carbon and collective excitation’s such as phonons which are analogous to photons [Oxford, 2009]. These materials are still in R&D phase to implement in an IC/ASIC. Although a resistivity increase due to electron scattering in Cu or higher bulk resistivity in non-Cu solutions (e.g. Co, Ru), a hierarchical interconnect approach such as scaling of line length along with that of the width still

164 CHAPTER 4. INTERCONNECTS can overcome the problem [Graef, 2011], [IRDS, 2016].

4.5.1 Barrier Metal

Copper Cu interconnect barrier materials prevent Cu diﬀusion into the adjacent dielectric as shown in Figure 4.64. They must also form a suitable, high quality interface with Cu to limit vacancy diﬀusion and achieve acceptable EM lifetimes. TaN is a well- known industry solution. Although the scaling of TaN deposited by PVD is limited, other nitrides such as MnN which can be deposited by CVD or Atomic Layer Depo- sition (ALD) have recently attracted attention. As for the emerging materials, SAM (Self-Assembled Monolayers) are researched as the candidates for future generation [IRDS, 2016].

Figure 4.64: Barrier layer needed to prevent Cu diﬀusion into dielectric

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4.5.2 Inter-metal Dielectrics (ILD)

Reduction of the ILD κ value is slowing down because of problems with manufacturability. The poor mechanical strength and adhesion properties of low-κ materials are obstructing their incorporation. Delamination and damage during Chemical Me- chanical Polishing (CMP) are problems at early stages of IC/ASIC manufacturing and the hardness and adhesion properties needed to deal with the stress imposed during assembly and packaging. Issues associated with the integration of highly porous ultra-low-κ (κ ≤ 2) materials are becoming clearer. Air-gap technologies oﬀer an alternative path to lower the inter-layer capacitance. There emerging materials, MOF (Metal Organic Framework) and COF (Carbon Organic Framework) are being explored [IRDS, 2016].

4.5.3 Interconnect delay challanges

The ITRS paper on “More Moore White Paper” projects the delay in interconnects. An important performance (speed) metric for the transistor is the intrinsic speed I/CV where C includes the gate capacitance plus the gate fringing capacitances. These fringing capacitances have been found to be larger than the intrinsic capacitance over the channel region of the MOS device. To calculate the speed requires a modeling of parasitic components in the device [Bardon et al., 2016]. From Table 4.18, the ratio of the total fringing capacitance’s to the gate capacitance over the channel is increasing with scaling. In order to capture the behavior of a wireloaded datapath to connect the device parameters to IC/ASIC, a ring-oscillator is used where each stage is implemented with an inverter with a drive strength of 4x (D4) driving a star wireload with its branches driving three D4 inverters. The wireload model is in a π2 conﬁguration to account for the distributed RC eﬀect. Details of this modeling and how the interconnect is coupled with the device in reference to a standard-cell context is explained in

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Table 4.18: Projected electrical speciﬁcations of logic core device. [IRDS, 2016]

[Badaroglu and Xu, 2016]. For circuit-level transient simulations there is a need for compact-model based software such as BSIM CMG or open source models such as Virtual Source Model (VSM) from MIT [Khakifirooz and Antoniadis, 2006]. We used VSM models to capture the circuit-level parameters such as delay and power per stage from a ring oscillator. Its inputs were transparently validated in TCAD with support from the NanoHub Team of Purdue University [Klimeck et al., 2008]. There are also analytical modeling tools such as MASTAR (Model for Assessment of CMOS Technologies And Roadmaps) from the ITRS, which is an analytical modeling tool to capture the major device characteristics such as Ion, Ieff, and Ioff. MASTAR was used in the editions of ITRS before 2013. In this datapath model the delay of each stage is approximated by the Elmore expression given in Equation 4.88 [Badaroglu and Xu, 2016]:

Tdel = 0.69 × Rdr × Cint + (0.69 × Rdr + 0.38 × Rw) × Cw + 0.69 × (Rdr + Rwire) × Cout (4.88)

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where:

Rdr = resistance of driver

Cint = the capacitance seen at the output of drive

Rw = wire resistance

Cw = wire capacitance

Cout = the load capacitance due to the gates connected to the load

WL = wire length

There are other methods for calculating delays besides Elmore (Arnoldi and AWE). These are beyond the scope of this work. For logic technologies beyond 2017 the dominant term from Equation 4.88 is typ-

ically found to be Rw × Cout [Badaroglu and Xu, 2016]. This implies that increasing the driver strength does not increase performance if there is no improvement in the parasitic resistance of interconnect and/or a reduction in the parasitic loading of the standard cell device [IRDS, 2016]. Table 4.19 shows the performance scaling across 7 nodes from 2015 to 2030 is 22% node-to-node improvement for datapaths without wireload and while it becomes 9% node-to-node improvement for datapaths loaded with tight pitch metal routing. If wireload routing is done with intermediate metal (at 80nm pitch), the node-to-node performance improvement becomes 16%. This scheme requires an eﬀective reduction of the vertical resistance, which is the cumulative sum of Via resistances. To gain performance the routing of critical paths needs to be done in intermediate metallization layers. The energy per switching reduction is on track for around a 36% reduction on node-to-node basis (on average). This is achieved due to the Fin depopulation of the Fin FET transistors, which also enables the cell height reduction. Raw gate density also improves by approximately 2X in a node-to-node basis until 2024. After

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2024 it is expected that 3D scaling by sequential/stacked integration would maintain the scaling of the number of functions per unit cube. The current roadmap edition assumes that the raw gate density is a metric to represent the scaling of the number of functions [IRDS, 2016].

Table 4.19: Table: Projected power-performance-area (PPA) metrics of functional datapath. [IRDS, 2016]

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4.5.4 Industry standards for EM

There are many standards used by the IC/ASIC industry. A list of the JEDEC standards for EM follows:

JESD33 - “Standard method for Measuring and Using the Temperature Co- eﬃcient of Resistance to Determine the Temperature of a Metallization Line” [JESD33B, 2004]

JESD37 - “Lognormal Analysis of Uncensored Data and of Singly Right-Censored Data utilizing the Persson and Rootzen Method” [JESD37A, 2017]

JESD61 - “Isothermal Electromigration Test Procedure” [JESD61A, 2007]

JESD63 - “Standard Method for Calculating the Electromigration Model Pa- rameters for Current Density and Temperature” [JESD63, 1998]

JESD87 - “Standard Test Structures for Reliability Assessment of AlCu Metal- izations with Barrier Materials” [JESD87, 2001]

JEP122 - “Failure Mechanisms and Models for Semiconductor Devices” [JEP122H, 2016]

JEP139 - “Characterize Aluminum Interconnect Metallization for Stress-Induced Voiding” [JEP139, 2012]

JESD202 - “Failure mechanisms and models for semiconductor devices” [JESD202, 2006]

The American Society for Testing and Materials (ASTM) also has a standard for EM that the IC/ASIC industry uses, called ASTM1260 - “Standard Test Method for Estimating Electromigration Median Time-to-Failure and Sigma of Integrated

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Circuit Metallizations [Metric]” [ASTM-standardF1260, 2003]. Table 4.20 contains the information needed to support these standards. This data may be considered proprietary by the Fab’s and diﬃcult to obtain.

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The model for EM in the JESD202 is Black’s equation 4.89, which is discussed in later sections.

E t = A J −n exp a (4.89) 50 0 kT where:

t50 is the time to failure for 50% of the interconnects

A is a constant

n is a constant

J is the mean current density of the test line stressed

Ea is the activation energy

k = Bolztmann’s constant (8.617332478x10−5eV/◦K)

T is the mean stress temperature of the lines stressed

The standard notes that the determination of A and n can be obtained by JEDEC Standard JESD63 [JESD63, 1998]. The JESD63 shows experimental methods to determine t50 for constant temperature with varying current density and for constant constant current with varying of the temperature. The standard shows how to collect the sample estimates and their conﬁdence intervals for (t50) and time to fail (tf ) from EM stress test with diﬀerent stress conditions. The data is recommended to be obtained by following the procedure of the standard EM test method in [Black, 1982] and using standard method for determining the joule heating in a test line in JESD33.

The EM test method includes procedures for calculating sample estimates of both t50 and σ from the failure times of the test parts. The sample estimates for t50 and σ are obtained from the average and the standard deviation of the natural logarithm of the individual failure times. In performing such EM tests, the stress temperature

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of the structures being stressed is the sum of the local ambient stress temperature and of the temperature increase of the test line due to power dissipation in the test structure and elsewhere on the wafer or parts. Figure 4.65 is an example of plotting

the test data. A plot of ln t50 versus ln J illustrates how −n can be found by the best line ﬁt of the data.

Figure 4.65: Plot of ln t50 versus ln J to determine n

Finding Ea can be found plotting ln t50 versus 1/T and ﬁnding the slope of the best ﬁt line of the test data.

Figure 4.66: Plot of ln t50 versus 1/T to determine the value of Ea

Once −n and Ea are found the process material constant A can be found using Black’s Equation 4.89. The JESD63 shows methods to obtain sample estimates and conﬁdence levels of the model parameters for t50 or a set of tf data for constant temperature with varying current density, and varying temperature for a constant

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current. The standard has procedures for EM test methods that are used for deter-

mining the joule heating in a test line. The sample estimates for t50 and standard deviation (σ) for the time failure. The method is for j runs from 1 to N, where N is the sample size and the impact of sample size on the conﬁdence intervals for the estimates. In performing the EM tests using the methods in the standard, the stress temperature of the line structures is the sum of the local ambient stress temperature, and the temperature increase of the test line due to the power dissipation in the structure and elsewhere on the IC/ASIC. The JEDEC 122 Standard has a model for median time to failure as shown in Equation 4.90. −n Ea tf50% = A0(J − Jcrit) exp (4.90) kBT

where:

t50% is the time to failure for 50% of the interconnects

A0 arbitrary scale factor

J applied current density

Jcrit the current density below which no electromigration takes place in the speciﬁc structure being tested (Blech Length)

Ea is the activation energy

−5 eV k is Boltzmann’s constant 8.62 × 10 ◦K

T is the mean stress temperature of the lines stressed

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Table 4.20: IC/ASIC Aging Properties

Variable Description

2 A0,metal Metal Worst Case, (hours/A/cm )

Ea,metal Metal Activation Energy (eV )

Nmetal Metal Grain Size parameter

2 Js,metal Stress Current Density (A/cm )

◦ Ts,metal Stress Temperature ( C)

σmetal Sigma, lognormal standard deviation t50%,metal or t50% or t0.1% stress, assuming a 2-parameter lognormal distribution t0.1%s,metal

◦ Tu,via Use temperature ( C)

2 Ju,via Use current density (A/cm )

2 Ju max,via Maximum use current density allowed for the design (A/cm )

W , metal To convert current I into current density J; Metal strip and Via Via width (um2) Wvia A , p,metal To convert current I into current density J; Metal strip and Via Via width (um2) Ap,V iaΨ)

∆R The percent change in Resistance to t0.1%

B(T ),Ak The percent change in Resistance to t0.1%

JEDEC Test standard and version utilized Standard

Conﬁdence Percent conﬁdence level for t50% and t0.1%

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Calculating and testing for a Time To Failure (tf ) for EM

Any tf value can be calculated using Equation 4.91.

tf% NORMSINV 100 σ tf = tf50%e (4.91)

where:

tf% Target cumulative IC/ASIC Failure percent

tf50% Time to Failure for 50% of the IC/ASIC

σ standard deviation

NORMSINV Inverse function of the standard normal distribution; NORMSINV = Inverse function of normal distribution in Microsoft’s Excel

The NORMSINV function can be used for the exponential distribution of EM, due to the Central Limit Theorem (CLT). The industry considers an EM failure when the resistance of the interconnect changes by 10%. Since the timing is aﬀected by the change in resistance, the design rules for a given process account for the 10% change. Conversion of current density (J) to current (I) (Equation 4.92). Ψ is the resistance of the wire. Ψ accounts for change in the wire resistance due to temperature. This is used in the testing of EM Vias and interconnects as current is easily measured.

ma A I um J 2 = (4.92) cm (ApΨ)

4.5.5 EM percent lifetime equations

t50s/u t0.1% = (4.93) s/u eZpσ

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F where Zp = NORMSINV 100 in Microsoft’s Excel

AkT B(T ) Ea t = t + t = + exp kB T (4.94) 50% n growth J j2

NORMSIM

h Ea i −n k Ts tfs = A0Js e B (4.95)

As stated in the introduction, since the 150nm node the goal for reliability of the interconnects is > 10 years. To validate the process, testing is performed at elevated temperatures and an Acceleration Factor (AF) is used to estimate the lifetimes of Vias and interconnect wires. Equation 4.96 is the equation used for AF.

" # −n Ea tfu Js k 1 − 1 AF = = exp B ( Tu Ts ) (4.96) T F s Ju

where:

tfu = tf for use being targeted

tfs = tf for stress test

Ju = current density for use

Js = current density for stress test

n = current density exponent

Tu = Temperature for use

Ts = Temperature for stress test

177 CHAPTER 4. INTERCONNECTS

4.6 Electromigration Copper Model parameters

This section describes the parameters required for copper electromigration lifetime calculation based on experiment test data from [Vairagar et al., 2004a] and [Tan et al., 2005]. The following calculations are described as follows: activation energy (Ea), current density exponent (n), process, (A0) material constant, lognormal sigma (σ), maximum current (Imax), lifetime versus temperature plots, and guard banding to map this with the 28nm Synopsys library. The reliability engineers for a given fabrication node typically provide the maximum allowable values for three interconnect current densities [Banerjee et al., 1999].

These are the average javg, the RMS, jrms, and the peak, jpeak as illustrated in Figure 4.67.

Figure 4.67: Unipolar waveform illustrating Ipeak, Irms and Iavg [Liew et al., 1990]

Figure 4.68 illustrates the current magnitudes and use. The peak current density is simply the current density corresponding to the peak current of the waveform described in Equation 4.97.

I I j = peak = peak (4.97) peak A WH

where:

A is the cross sectional area the interconnect

178 CHAPTER 4. INTERCONNECTS

Figure 4.68: How the current values Ipeak, Irms and Iavg used in interconnects

W is the width of the interconnect

H is the height of the interconnect

The average current density is shown in Equation 4.98.

1 Z TP javg = j(t)dt (4.98) Tp 0

where Tp is the time period of the current waveform. The RMS current density is shown in Equation 4.99.

s Z TP 1 2 jrms = j (t)dt (4.99) Tp 0

For a ﬁxed temperature, EM lifetime of interconnects is determined by javg

[Liew et al., 1990]. Self-heating is determined by jrms. High performance interconnect designs are based on the specified limits for the maximum values of the average, RMS, and peak current densities [Nagaraj et al., 1998]. Interconnects can be classified into signal and power interconnects. They differ in that currents in signal lines are bipolar (bi-directional [Liew et al., 1990], while those in power lines are usually unipolar (uni-directional). For unipolar current waveforms javg and jrms can be calculated using jpeak shown by Equations 4.100 and 4.101. These interconnect limits

179 CHAPTER 4. INTERCONNECTS do not account for self-heating. The self heating is accounted for in the maximum currents allowed in an interconnect wire.

j j = avg (4.100) peak r

j j = √avg (4.101) rms r

where r is the duty cycle and shown in Figure 4.67. Table 4.21 shows experiment test data from [Vairagar et al., 2004a] and [Tan et al., 2005]. A test structure of interconnects was created and tested for failure to t50%.

Table 4.21: Black’s law Regression

Metal J , 1/k T , H W stress t , hours T ln(t ) B Layer MA/cm2 50 stress 50 ◦K

◦ M2 350 nm 700 nm 0.8 510.7 300 C 6.24 20.25

M2 350 nm 700 nm 0.8 271.1 325 ◦ C 5.60 19.40

M2 350 nm 700 nm 0.8 120.5 350 ◦ C 4.79 18.62

180 CHAPTER 4. INTERCONNECTS

The wide metal layer M2 of the test structure activation energy AE is computed

1 by using a linear regression exponential law ﬁt of (ln(t50)) versus while keeping kB T the current density stress constant. The exponential equation component of Blacks

Ea law is (tf50% = AE exp( ) where kB is Boltzmanns constant, and Tstress is the kB Tstress stress temperature in Kelvin. The regression equation becomes Equation 4.102.

1 ln(tf50%) = ln (AE) + Ea × (4.102) kBT

The regression computations are shown in Equations 4.103 and 4.104

1 Ea = slope ln(t50), = 0.8869eV (4.103) kBT

1 ln(AE) = intercept ln(t50, = −11.6832 (4.104) kBT

Figure 4.69 is a plot of the test data to illustrate how Ea was calculated.

Figure 4.69: Black’s Law Regression

181 CHAPTER 4. INTERCONNECTS

The material constant then results in Equation 4.105

ln(AE) −11.6832 A50 = exp n = exp 1.256 = 199.6863 (4.105) (Jstress) (8x105A/cm2)

The metal layer M2 current density exponent n is computed by using a linear

regression power law ﬁt of ln(t50) versus ln(Jstress) while keeping the temperature

An constant. The power law equation component of Blacks law is t = n . The f50% (Jstress)

regression equation then becomes, ln(tf50%) = ln(An) + n × ln(Jstress). Table 4.22 summarized the result.

Table 4.22: Black’s law Regression M2

Metal H W T t , hours J ln(t ) ln(J ) Layer stress 50 stress 50 stress

0.8 M 350 nm 700 nm 350 ◦C 120.5 4.79 13.59 2 MA/cm2

1.2 M 350 nm 700 nm 350 ◦C 73.33 4.29 14.00 2 MA/cm2

1.5 M 350 nm 700 nm 350 ◦C 54.56 4.00 14.22 2 MA/cm2

The regression computations for M2 are shown in Equations 4.106, 4.107 and 4.108.

n = slope (ln(tF 50%), ln(Jstress)) = −1.256 (4.106)

ln(An) = intercept (ln(tF 50%), ln(Jstress)) = 21.869 (4.107)

182 CHAPTER 4. INTERCONNECTS

Figure 4.70: Black’s Law Regression for M2

The material constant then results in Equation 4.108.

exp (ln(An)) A50 = (4.108) exp Ea kB Tstress exp (21.869) = = 199.683 (4.109) 0.8869 exp ◦ kB ×350C

The lognormal sigma (σ) can be computed as a linear regression ﬁt of the normal inverse function (NORMSINV), or a simple approximate slope equation of one

t−mu standard lognormal deviation. The F (t) = Φ σ becomes the regression form of −1 1 ZF = Φ F (t) = A + σ × ln(t). Table 4.23 shows the values for CDF for ln(t).

Figure 4.71 plots ln(t) verses ZF .

183 CHAPTER 4. INTERCONNECTS

Table 4.23: M2 CDF

Metal Z H W T CDF F(t) t, hours F ln(t) Layer stress Φ-1(F(t))

◦ M2 350 nm 280 nm 350 C 0.1% 0.001 50 -3.09 3.91

◦ M2 350 nm 280 nm 350 C 3% 0.03 70 -1.88 4.25

◦ M2 350 nm 280 nm 350 C 16% 0.16 90 (t16) -0.99 4.55

◦ M2 350 nm 280 nm 350 C 50% 0.5 120.5 (t50) 0.00 4.91

◦ M2 350 nm 280 nm 350 C 96% 0.96 200 1.75 5.30

◦ M2 350 nm 280 nm 350 C 99.9% 0.999 300 3.09 5.70

The regression computations are shown in Equation 4.110.

1 = slope Φ−1(F (t)), ln(t ) = 3.447 (4.110) σ 50 1 = 3.447 (4.111) σ σ =0.290 (4.112)

The value of σ can be compared to an alternate equation σ = ln t50 = 0.2918, t16 which approaches the shape of a normal distribution . The literature has reported various sigmas averaging around 0.5 [Lloyd, 1979]. The slope intercept is shown in Equation 4.113.

−µ = intercept Φ−1(F (t)), ln(t ) = 3.447 (4.113) σ 50

Table 4.24 shows the summary of Blacks law extracted parameters as computed from [Vairagar et al., 2004a] and [Tan et al., 2005]. The star (*) denotes M1 data copied from M2 for the exponential n value. The last column shows the tf50% at

184 CHAPTER 4. INTERCONNECTS

Figure 4.71: Black’s Law Regression CDF

◦ 0.8MA 105 C in years for a current density of cm2 . Sensitivity analysis was done to show

that a 10% in current density causes a larger increase in the tf50% when compared to a 10% increase in the n exponent. Using a n exponent value of 1 is commonly used in copper by Fab suppliers, which oﬀers the greatest improvement to tf50%. The lognormal sigma values approach a normal distribution by the CLT (i.e. 0.18) as the stress temperature increases. The parameters from Table 4.24, can now be applied to the Black’s Law electromigration equation (Equation 4.114) for the median time to fail (i.e. 50% of the population fail).

Ea n k T tf50% = Af50%j e b (4.114)

Table 4.25 shows the tf50% calculation for the various temperatures from Table 4.24 in order to compare the experimental hours with the least regression curve ﬁt denoted by a slash [Choi et al., 2004].

Figures 4.72 and 4.73 show the tf50% and log10(tf50%) plots for metal layer M1

0.8MA using a current density (j) of cm2 in years using Black’s Law from the test data. ◦ The lifetime at 105 C for M1 700 nm is 16.78 years and 280 nm is 7.84 years.

The lengths for both M1 and M2 lines are 50 µm, 100 µm,and 800 µm. The thick-

185 CHAPTER 4. INTERCONNECTS

nesses for M1 and M2 line are 0.36m and 0.24m, respectively. The width of all lines is 0.28 µm and the cylindrical shaped Vias have diameters of 0.26 µm [Choi et al., 2004].

Figure 4.72: tf50% Lifetimes using Black’s Law for M1 (y = years)

Figure 4.73: log10(tf50%) Lifetimes using Black’s Law for M1 (y = years)

0.8MA Figure 4.72 shows the plot of tf50% for metal layer M2 using cm2 in years. The ◦ lifetime at 105 C for M2 700nm is 578.96 years and 280nm is 388.18 years. In order to determine lifetime aging/wearout, a suitable failure rate must be considered. A common industry practice is to use a 0.1% failure rate assuming a lognor-

186 CHAPTER 4. INTERCONNECTS

Figure 4.74: tf50% Lifetimes using Black’s Law for M2 (y = years)

mal distribution with µ and σ of tf50%,σ. The electromigration is modiﬁed as shown in Equation 4.115.

−1 µ+ZF σ µ σZF σZF σΦ (CDF ) tCDF = F (ZF ) = e = e e = tf50%e = tf50%e (4.115) where:

tCDF Target cumulative distribution of the IC/ASIC Failure percent

ZF Time to Failure for 50% of the IC/ASIC

σ standard deviation

NORMSINV Inverse function of the standard normal distribution; NORMSINV = Inverse function of normal distribution in Microsoft’s Excel

−1(50%) In the cases of 50% failure rate, ZF = Φ has the value of 0, tf%CDF and for

−1(0.1%) the 0.1% failure rate, ZF = Φ has the value of -3.09. Equation 4.116 is the

tf50%CDF .

σΦ−1(50%) 0 tf50%CDF = tf50%e = tf50%e = tf50% (4.116)

187 CHAPTER 4. INTERCONNECTS

The t0.1%CDF becomes Equation 4.117.

σΦ−1(0.1%) −3.09σ t0.1%CDF = tf50%e = tf50%e (4.117)

Finally, the electromigration equation for a given failure rate becomes Equation 4.118.

−1(CDF ) E σΦ E E Af50% a σΦ−1(CDF ) Af50%e a ACDF a t = e kB T e = e kB T = e kB T (4.118) 0.1%CDF jn jn jn

Equation 4.119 shows the t0.1%.

−3.09σ Af50%e Ea A0.1% Ea t = e kB T = e kB T (4.119) f0.1% jn jn

To ﬁnd the lifetimes of interconnect, accelerated tests are performed. Equation 4.120 show how to calculate the Acceleration Factor (AF).

A 0 Ea A0 Ea n exp t j kB Tuse n e AF = f50%,use = use = juse × kB Tuse (4.120) A0 Ea tf50%,stress A0 Ea n e n exp juse kB Tuse jstress kB Tstress

Equation 4.120 can be reduce as shown in Equation 4.121. Note that A0 is can- celed.

n n tf50%,use jstress Ea − Ea jstress Ea 1 − 1 AF = = e kB Tuse kB Tstress = e kB Tuse Tstress tF 50%,stress juse juse (4.121)

= AFj × AFT (4.122)

Using Equation 4.121 to ﬁnd t50,use is shown in Equation 4.123.

tf50%,use = tf50%,stress × AFj × AFT (4.123)

188 CHAPTER 4. INTERCONNECTS

In order to ﬁnd the lifetime for electromigration the maximum current density jmax for the desired lifetime and temperature needs to be calculated as shown in Equations 4.124, 4.125, 4.126, 4.127 4.129 [Li et al., 2011a], [Tan et al., 2005], [Vairagar et al., 2004b], [Yan et al., 2005], [Arnaud et al., 1998], [Lloyd, 1979], [Zhu, 2013], [Synopsys, 2011], [Synopsys, 2012], [Pyzyna et al., 2017], [Natarajan et al., 2008b], [Packan et al., 2009a], [Packan et al., 2009b], [Li et al., 2011b].

n tf50%,use jstress Ea 1 − 1 = e kB Tuse Tstress (4.124) tf50%,stress juse

j50%,use Tf50%,stress Ea 1 − 1 = e kB Tstress Tuse (4.125) jf50%,stress Tf50%,use

1 ! T Ea 1 1 n f50%,stress k T − T jmax,50% = juse = jstress e B stress use (4.126) Tf50%,use

jmax = jlifetime,Z% (4.127)

1 ! T n Ea 1 1 50%,stress Zσ − nk T − T 2 = jstress e e B stress use (MA/cm ) (4.128) T50%,lifetime

jmax = jlifetime,0.1% (4.129)

1 ! T n Ea 1 1 50%,stress −3.09σ − nk T − T 2 = jstress e e B stress use (MA/cm ) (4.130) T50%,lifetime

Table 4.26 shows jmax for diﬀerent temperatures and failure rates.

189 CHAPTER 4. INTERCONNECTS

Table 4.24: Black’s Law from Tan and Vairagar

Metal Layer M1 M1 M2 M2

H, nm 350 350 350 350

W, nm 280 700 280 700

Ea, eV 0.4889 0.5953 0.8408 0.8869 n -1.249 (*) -1.256 (*) -1.249 -1.256

◦ 2 t50 at 350 C at 0.8 MA/cm 189.4 hours 119.7 hours 136.2 hours 120.5 hours

2 A50 Hours/A/cm 494329.4 44471.9 500.11 199.69

◦ 2 t50 at 105 C a Ct 0.8 MA/cm 7.84 years 16.78 years 388.18 years 578.96 years

5123.99 8818.87 t (E +10%) 35.13 years 104.29 years 50 a years years

1361.80 t (n -10%) 18.31 years 39.41 years 907.16 years 50 years

11452.61 18818.77 t (n = -1) 231.16 years 544.54 years 50 years years

σ 300 ◦C 0.33 0.78 0.28

σ 325 ◦C 0.60 0.61 0.25

σ 350 ◦C 0.33 0.29 0.29

2 A0.1% Hours/A/cm 178292.5 18150.4 204.11

2 t0.1% at 105 ◦C at 0.8MA/cm 2.83 6.85 158.44

t0.1% at σ = 0.5 1.67 3.58 82.79

190 CHAPTER 4. INTERCONNECTS

Table 4.25: Black’s Law t50 for various Temperatures

Metal H, W, j, 300 ◦C 325 ◦C 350 ◦C 350 ◦C 2 Layer nm nm MA/cm t50, hours t50, hours t50, hours Error

M2 350 700 0.8 510.7 / 483.84 271.1 / 228.43 120.5 / 114.54 -4.95%

1.2 73.33 / 68.83 -6.13%

1.5 62.56 / 52.01 -16.87%

M2 350 280 0.8 532.9 / 524.04 246.1 / 257.25 136.2 / 133.71 -1.83%

1.2 79.33 / 80.58 1.57%

1.5 62.56 / 60.98 -2.53%

M1 350 700 0.8 315.4 / 294.00 203.3 / 177.65 119.7 / 111.78 -6.62%

M1 350 280 0.8 418.8 / 416.88 270.2 / 275.64 189.4 / 188.40 -0.53%

191 CHAPTER 4. INTERCONNECTS

Table 4.26: Jmax for various Temperatures and Failure rates

Metal Layer M1 M1 M2 M2

H, nm 350 350 350 350

W, nm 280 700 280 700

Ea, eV 0.4889 0.5953 0.8408 0.8869 n -1.249 (*) -1.256 (*) -1.249 -1.256

σ 350 ◦C 0.33 0.29 0.29

◦ 2 t50 at 350 C at 0.8 MA/cm 189.4 hours 119.7 hours 136.2 hours 120.5 hours

◦ 2 t50 at 105 C at 0.8 MA/cm 7.84 years 16.78 years 388.18 years 578.96 years

◦ Jmax50 at 105 C for 11.4 years 1.5837 0.5571 0.0468 0.0337

◦ 2 t0.1% at 105 C C at 0.8MA/cm 2.83 6.85 158.44

◦ jmax0.1% at 105 C for 11.4 years 0.000317 0.000093 0.000040

◦ Jmax0.1% at 105 C for 11.4 years 0.5713 0.2274 0.0191

192 CHAPTER 4. INTERCONNECTS

4.7 Future of Interconnects

A metal cap can be placed on Cu damascene interconnects with proper barrier interfaces [Hu et al., 2002]. This cap can essentially eliminate EM completely, by raising the EM activation energy in the interconnect to bulk Cu values. A further enhancement is the insitu integration of an ultra-thin metal cap with a hermetic dielectric barrier cap, which will prevent O2 penetration and E-M degradation [Edelstein, 2017]. Another enhancement is the wrap-around integration of Co liner and cap shown in Figure 4.75.

Figure 4.75: Electromigration activation energies (left) and lifetimes for Cu/TaN/Ta liner/SiCN cap, Cu/TaN/Ta liner/Co cap, and Cu/TaN/Co liner/Co cap. [Edelstein, 2017]

This allows seamless top corners, and improved Cu gapfill that eliminates sidewall voids, which would cancel the metal caps effectiveness. A 1000x increase in EM lifetimes and 1.7 eV activation energy in 10nm node has been measured. This extends Cu EM reliability with no interconnect resistance penalty. The Cu/low-k dielectric TDDB is also affected by scaling, and needs to be mitigated for reliability. A benefi- cial integration breakthrough was the development of a self-aligned Via (SAV) scheme [Brain et al., 2009]. The SAV eliminates Via top flaring and via-line space constric- tion outside the Via trench, which will preserve TDDB reliability at finer pitches. SAV has served well for several generations, but it becomes necessary to limit Via chamfering below as shown in 4.76 [Briggs et al., 2017].

193 CHAPTER 4. INTERCONNECTS

Figure 4.76: Via chamfer in the non-SAV direction (left). FAV scheme comparison for chamfer and CD control (right). [Briggs et al., 2017]

A novel fully-aligned Via (FAV) scheme shown in Figure 4.78 [Briggs et al., 2017] is being developed for future nodes BEOL and MOL vias.

Figure 4.77: Fully-Aligned Via (FAV) schematic, Cu/barrier recess TEM/EELS map, and implementation on W MOL. [Briggs et al., 2017]

It is essential to mitigate Cu resistance scaling impacts for interconnects and vias, from size-effects and from the end of Cu barrier scaling in the approximately 1-3 nm node range. Alternate conducting materials, with various ultrathin barriers, and several barrier-less metal are candidates to replace Cu. These candidate metals have higher bulk resistivities, but less size-effects, and no need for nm-scale barriers. They may have higher interconnect resistivity than Cu with a finite diffusion bar-

194 CHAPTER 4. INTERCONNECTS rier, therefore may have a lower resistance interconnects than Cu. These barrier-less candidates must not decrease reliability, and must have manufacturable deposition and patterning processes. Leading candidates are Cobalt (Co) [Kelly et al., 2016], Ruthenium (Ru) [Zhang et al., 2016b], [Wen et al., 2016][28, 29], and other Pt-group metals [Wen et al., 2016], [Gall, 2016]. For Cu/barrier interconnects, a through-Co self-forming barrier shown in Figure 4.78 [Nogami et al., 2015] is the leading candidate. The ﬁgure shows that it oﬀers the lowest interconnect resistivity and with the promise for good reliability.

Figure 4.78: Through-Co Self-Forming Barrier concept and data. Mn from Cu(Mn) seed layer diﬀuses through ultrathin TaN/Co liner, reacts with residual O, and seals the composite barrier. Provides line-R reduction with preserved reliability. [Nogami et al., 2015]

Co and Ru wires with minimal liners are being evaluated, but Through-Cobalt Self Forming Barrier (tCoSFB) [Edelstein, 2017] is competitive verses Co or Ru beyond the 7nm node as shown in Figure 4.79. Cobalt and Ruthenium are rare in nature and costly.

195 CHAPTER 4. INTERCONNECTS

Figure 4.79: Through-Co Self-Forming Barrier concept and data. Mn from Cu(Mn) seed layer diﬀuses through ultrathin TaN/Co liner, reacts with residual O, and seals the composite barrier. Provides line-R reduction with preserved reliability. [Briggs et al., 2017]

4.7.1 Cobalt

From [Gupta, 2010], Cobalt (Co) is a hard, bluish white metal, which melts at 1493 ◦C and is found in nature in association with nickel and arsenic. At the 10nm/7nm node cobalt will begin to be used for ﬁlled contacts and local interconnect. Co has a resitivity of 1.72 µΩ − cm. It dissolves in mineral acids, and does not combine directly with hydrogen or nitrogen to form hydrides or nitrides of the metal, which is important in IC/ASIC fabrication. At elevated temperatures, Co reacts with atmo- spheric oxygen. In a moist atmosphere it forms oxides of the metal (CoO and Co3O4).

There is no evidence of the existence of a Co2O3 compound. Co has been used in the Cu-damascene process as an adhesion promoter [Li et al., 2005]. The thin epitaxial barrier layer of CoSi2 has shown promise because of its morphological integrity above 550 ◦C [Broadbent, 1987]. Ultra-thin (10 A)˚ cobalt ﬁlm deposited by e-beam evapora- tion and rapid thermal processing shows low resistivity (14 µΩ − cm) and the surface roughness of the ﬁlm remains unchanged above 500 ◦C [Kleinschmit et al., 1999], [S. Kal, 1999]. Low-resistivity Co has also been used as a contact metal in IC/ASIC, which greatly enhances EM.

196 CHAPTER 4. INTERCONNECTS

Recently Cobalt Tungsten Phosﬁde (CoW P) deposited by the electroless method [Petrov et al., 2002] has been used as cap material in Cu interconnects. Capping the copper in the Cu-damascene process with CoWP has improved device reliability [Kohn et al., 2001]], [Gupta, 2010] The superior adhesion energy of CoWP compared to SiC, NSiC and SiN capping layers is shown in Figure 4.80.

Figure 4.80: Adhesion energy of CoWP compared to SiC, NSiC and SiN capping layers. [Gupta, 2010]

4.7.2 Ruthenium

Ruthenium (Ru) is a shiny, silvery metal in the Platinum-group, which melts at 2334 ◦C and an estimated bulk self diﬀusion activation energy of 4 eV. These are both much higher than Cu [Zhang et al., 2016a]. Ru has eight oxidation states the most common are RuO2, RuO3 and RuO4 [Cabot, 2010]. RuO4 is known to be toxic. Ru has a resitivity of 7.4 µΩ − cm. Research is being performed for depositing Ru in

197 CHAPTER 4. INTERCONNECTS

IC/ASIC fabrication. A variety of deposition tools and techniques to yield films of ruthenium Via atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD) are being tried. Each of these deposition methods has advantages and disadvantages that must be considered in developing a process for depositing Ru. Ruthenium is a hard metal with little chemical reactivity. Because of the hardness, planarization by CMP results in limited removal. Early work on Ru CMP has been limited. Proper control of the mechanical slurries chemistry must be controlled that do not cause toxic oxide byproducts to form [Cabot, 2010]. Ru is an option to replace Cu at the 5nm node [Besser, 2017b]. Ru is alternative materials that require less or no barrier/adhesion layer. Though new materials are higher resistivity by eliminating the barrier layer/adhesion layers a lower cross- sectional resistance may result. Around the 5nm node we may begin to see ruthenium interconnects with no barrier/adhesion layer and despite ruthenium’s high resistivity because it can outperform copper with a 2nm barrier at small dimensions[Jones, 2017]. EM performance of Ru interconnects is expected to be excellent based on Ru’s material properties. Initial EM testing performed on the 24nm wide Ru filled dual damascene structures at 395 ◦C and with a current density 65 mA/µm2 has been created, and no failure has been observed after a significant amount of time. This is significantly longer than the life time of a comparable copper with a structure with a Co cap [Zhang et al., 2016a].

198 Chapter 5

Trade oﬀs for Lifetime versus Performance

The Driving Point Admittance model approximates the driving point characteristics of an interconnect’s resistance (R) and capacitances (C) as shown in Figure 5.1. It is sufficiently accurate to model the average, RMS and peak current densities [Nagaraj et al., 1998], which we will exploit for the tradeoffs of performance, cost, power and reliability/lifetimes. The delay of a digital logic circuit is affected by the resistance and capacitance of the interconnect, which were discussed in Sections 4.4 and 4.4.1. At advanced nodes, EM becomes a new component that needs to be optimized with performance, cost, and power. At 28nm, only a few of the interconnects pose EM violations. At 16nm this might rise to 500 or 1,000 nets. Up-front prevention needs to be performed or this may rise to 10,000 if EM is not considered part of the design [Goering, 2014]. Fortunately, there are ways to reduce current density and mitigate electromigration. Unfortunately, there are area or performance tradeoffs. They are:

• Widen the wire to reduce current density

199 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

Figure 5.1: DPA Model [Nagaraj et al., 1998]

• Reduce the frequency

• Lower the supply voltage

• Keep the wire length short

• Reduce buﬀer size in clock lines

To control EM, foundries define current limits for each wire. Many parameters are used in the calculation of the limits including wire width, layer, activity, frequency, and temperature. The width and length of the wires then becomes part of the design rule set. It is not a simple matter of just following the rules. If the width is increased the spacing changes. Not only the width, but also the spacing of neighboring wires must be considered [Goering, 2014]. Changing the width of the wires also violates the design rule set, and will affect the yields. Thus the R and C are not changed from the design rules set by the foundry. Our methodology changes the current in the wires, which affects electromigration, but allows for trading off between performance and lifetimes (reliability). Figure 5.2 shows currents in different metal layers.

200 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

Figure 5.2: 28nm EM example

5.1 Electromigration tradeoﬀs

The lifetime of an interconnect wire based on Blacks law for electromigration is determined primarily by current density and temperature. The higher the current density going through an interconnect wire for a ﬁxed height, H and width W, the shorter the lifetime. Conversely the lower the current density going through an interconnect wire for a ﬁxed height, H and width W, the longer the lifetime. This relates to the delay in a logic gate by the higher the current, the faster the gate performs (i.e. smaller

gate delay, td). Conversely, lowering the current results in a slower gate delay. Figure 5.3 shows the trade oﬀ between Performance and Lifetimes in relative percentage.

Electromigration tradeoﬀ by Current Density (j)

Equation 5.1 shows the general equation for a 0.1% percent failure over 100,000 hours or 11.4 years [Xiu, 2007], which is the targeted lifetime for a process.

−3.09σ Af,50%e Ea Af,0.1% Ea t = e kB Tm = e kB Tm (5.1) f,0.1% jn jn

To ﬁnd how a change in j aﬀects EM lifetimes (∆tf ), let the temperature Tnew =

201 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

Tbase, which implies A0.1%new = A0.1%base shown in Equation 5.2.

Ea Ea −n k T −n k T tf,base = A0.1%base × j × e B base and tf,new = A0.1%new × j × e B new (5.2)

tF new The Equations in 5.2 can then be used to ﬁnd ∆tlifetime. The ∆tf = when tF base expanded is shown in Equation 5.3.

Ea −n k T −n tf,new A0.1%new × j × e B base j0.1%base ∆tf = = Ea = (5.3) tf,base −n k T j0.1%new A0.1%base × j × e B base

Equations 5.4 and 5.5 are a summary of the trade oﬀ equations between lifetime and performance.

E −n a Aem ∆t ≈ A × (∆j) e kB Tm ≈ (relative years, fixed temperature) lifetime f,0.1% (∆j)n (5.4)

α (∆j) α ∆fperformance ≈ ≈ (∆j) (relative Gigahertz, fixed temperature) (5.5) Adelay

Figure 5.3 shows the trade oﬀ for ∆tlifetime cuurent density exponent (j) of n = 1

and ∆fperformance current density exponent (j) of α = 1.

Figure 5.4 shows the trade oﬀ for ∆tlifetime current density exponent of n = 2,

and the Sakurai-Newton ∆fperformance current density exponent of α = 1.2 [Sakurai and Newton, 1990]. Each ﬁgure shows that when the x-axis current density j is one, then the y-axis is 10, which represents 10 year lifetime, and represents the maximum frequency of relative performance of one. Observe, that for the same percentage current density drop, lifetime increases much more rapidly than gate de-

1 lay (performance). This due to the j in the current density lifetime equation versus the linear growth in gate delay. For example, for n = 1 and α = 1, a 10% drop in

202 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

Figure 5.3: Performance verses Lifetime tradeoﬀ by % change in j with∆tlifetime cuurent density exponent (j) of n = 1 and ∆fperformance current density exponent (j) of α = 1

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current density results in 11.11 years and 10% drop in frequency performance. A 10% increase in j results in 9 year lifetime and a 10% increase in frequency performance.

Figure 5.4: Performance verses Lifetime tradeoﬀ for ∆tlifetime current density exponent of n = 2, and Sakurai-Newton ∆fperformance current density exponent of α = 1.2

Table 5.1 show the tradeoﬀs in Performance verses lifetimes for diﬀerent values of n and α.

204 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

Table 5.1: trade oﬀ for n = 1 and α = 1 and n = 2 and Sakurai-Newton α = 1.2

%trade %trade %Lifetime, %Performance, %Lifetime, %Performance, %j oﬀ, n=1, oﬀ, n=2, n=1 α=1 n=2 α=1.2 α=1 α=1.2

0.4 25.00 4 29.00 62.50 3.33 65.83

0.5 20.00 5 25.00 40.00 4.35 44.35

0.6 16.67 6 22.67 27.78 5.42 33.20

0.7 14.29 7 21.29 20.41 6.52 26.93

0.8 12.50 8 20.50 15.63 7.65 23.28

0.9 11.11 9 20.11 12.35 8.81 21.16

1 10.00 10 20.00 10.00 10.00 20.00

1.1 9.09 11 20.09 8.26 11.21 19.48

1.2 8.33 12 20.33 6.94 12.45 19.39

1.3 7.69 13 20.69 5.92 13.70 19.62

1.4 7.14 14 21.14 5.10 14.97 20.08

1.5 6.67 15 21.67 4.44 16.27 20.71

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Electromigration tradeoﬀ by Temperature

For the typical lifetime of an IC/ASIC of ≈ 10 years, the relative temperature ∆T can be deﬁned with a relative ∆tf of 1 for the lifetime of 10 years. With these assumptions, Equation 5.6 illustrates how lifetimes are aﬀected by temperature.

1 ∆T e m 1 −1 ∆t ≈ = e ∆Tm (relative lifetime %) (5.6) F e1

Figure 5.5 shows the trade oﬀ and the y-axis will be scaled by 10 in order to represent 10 years when the relative x-axis temperature is 1.

Figure 5.5: Performance verses Lifetime trade oﬀ for n = 1 and α = 1

Table 5.2 highlights that lowering the temperature has a more pronounced impact on the lifetime than the increase in performance. Increasing the allowable temperature of the IC/ASIC increases the gate performance, but at a much slower rate. The gate delay decreases as more current is driving the gate, which increases the power consumption of the gate (Watts). This results in an increase in temperature of the IC/ASIC. The Equation 5.7 begins by using the the steady state thermal

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convection equation.

kA Q = (T − T )(W atts) (5.7) L mos ambient

The relative change in temperture can then be described in Equation 5.8.

kA Q = ∆T = A ∆ (5.8) L mos

The power of a gate is described by the drive current of the gate (Igate) times the gate resistance (Rgate) as in Equation 5.9.

2 Pgate = IgateRgate = Q = Amos∆T (5.9)

Allowing an increase in operating temperature of the IC/ASIC will allow an increase in gate current, which will improve the gate performance. Equation 5.9 then implies Equation 5.10.

√ 1 Igate ∝ ∆T = T 2 (5.10)

Using Equation 5.15, td,performance can be calculated as in Equation 5.11.

CloadVdd CloadVdd − 1 td,performance = ∝ √ ∝ T 2 (5.11) Iavg T

For relative performance ( 1 ), Equation 5.12 is used. td,performance

1 ∆fperformance ∝ ∆T 2 (5.12)

Given a ﬁxed gate current Iavg, as the temperature rises the gate slows down due 3 − 2 to the mobility of the MOSFET, where µmos(T ) ∝ Tmos [Chain et al., 1997], resulting

3 − 3 in tdelay(T ) ∝ T 2 or fdelay(T ) ∝ T 2 .

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Combining Electromigration tradeoﬀ by Current Density and Tempera- ture

Both the current density and temperature tradeoﬀs can be combined to meet the requirements of the IC/ASIC. Equations 5.13 and 5.14 show the calculations for Lifetime and Performance respectively.

n 1 −1 ∆tlifetime ≈ (∆j) e ∆Tm (5.13)

α 1 ∆fperformance ≈ (∆j) ∆T 2 (5.14)

Figure 5.6 shows the design exploration tradeoﬀs based on electromigration parameters, current density, j, and temperature, T . The pink plot shows the result of increasing the current density and temperature leads to high IC performance. The blue plot shows the result of lifetime due to current density and temperature. The combine plot shows the tradeoﬀ design between lifetime and performance.

Figure 5.6: Plot illustrating the tradeoﬀs of Current density j vs Temperature (T ) vs Lifetime (Z)

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Table 5.2: Temperature verses Performance and Lifetime. Lowering the temperature has a more pronounced impact on the lifetime than the Performance increase.

%T % Lifetime % Performance % Trade oﬀ

0.3 103.12 5.48 108.60

0.4 44.82 6.32 51.14

0.5 27.18 7.07 34.25

0.6 19.48 7.75 27.22

0.7 15.35 8.37 23.72

0.8 12.84 8.94 21.78

0.9 11.18 9.49 20.66

1 10.00 10.00 20.00

1.1 9.13 10.49 19.62

1.2 8.46 10.95 19.42

1.3 7.94 11.40 19.34

1.4 7.51 11.83 19.35

1.5 7.17 12.25 19.41

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5.1.1 Current density (j) eﬀects on gate delay

The delay of a digital logic circuit is aﬀected by the amount of current (I) in the

interconnect wires. The following section derives the gate delay (td) as a relative percentage change in current density j. The current density in an interconnect is current times the height and width. Equation 5.15 is the equation for td based on current.

Vdd CloadVdd td = RmosCload = Cload = (picoseconds) (5.15) Iavg javg × H × W

Therefore the relative eﬀects of current density j on the gate delay td is shown in Equation 5.16. C V ∆t = load dd (relative percent) (5.16) d ∆j × H × W

CloadVdd Adelay 1 If we allow Adelay = then ∆td = . Since frequency is , the relative ×H×W ∆j td frequency of a digital circuit is shown in Equation 5.17.

∆j × H × W ∆j ∆fd = = (relative percent) (5.17) CloadVdd Adelay

A detailed model of gate delay is given by Sakurai-Newton [Sakurai and Newton, 1990] as shown in Equation 5.18.

CloadVdd td = α (5.18) kmos (Vdd − Vth)

where k = W µ C = 1 , and can be shown to be similar to relative mos L mos ox Rmos frequency Equation 5.17 as in Equation 5.19.

α α ∆Vdd (∆j) ∆fd ≈ ≈ (relative percent) (5.19) RmosH × W Adelay

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5.2 Synopsys Process Development Kit

Synopsys Incorporated provides a 28/32 nm IC/ASIC Process Development Kit (PDK), which was used in this work. The PDK provides the complete technology ﬁles to simulate. synthesize, place and route and perform electromigration analysis of an

IC/ASIC design. The supply voltage, Vdd, is 1.05 volts. This section describes the important parameters, compares them to the Intel processes and applies the parameters to modeling of electromigration in the interconnect wires. The Synopsys PDK is compared to Intel to ensure Synopsys PDK contains realistic values and add the parameters missing from the PDK. The resistivity of the metals in the Synopsys PDK was found to be unrealistic. EM information was not in the PDK. Table 5.3 shows Metal layers for the FreePDK3D45 [NCSU, 2011].

Table 5.3: Synopsys PDK3D45:Metal Layers

Synopsys PDK3D45:Metal Layers

Pitch Via di- Via Thickness Resistivity Name (Width/Space) Permittivity mension resistance (nm) (1) (ohm/sq) (nm) (nm) (ohm) (2)

Top Metal 1600 (800/800) 1000 (4) 0.060 (4) 2.5

TM Cap Ox- 1000 2.5 800 0.25 ide

ILD 9 2000 2.5 800 0.5

Global(9-10) 1600 (800/800) 2000 0.030 (3) 2.5

ILD 7-8 820 2.5 400 1

ThinGlobal 800 (400/400) 800 0.075 (3) 2.5 (7-8)

ILD 4-6 290 2.5 140 3

Semi-global 280 (140/140) 280 0.21 2.5

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Synopsys PDK3D45:Metal Layers

ILD 2-3 120 2.5 70 5

Intermediate 140 (70/70) 140 0.25 2.5 (2-3)

ILD 1 120 2.5 65 6

Metal 1 130 (65/65) 130 0.38 2.5

Poly- 85 2.5 65 8 Dielectric

Poly 125 (50/75) 85 7.8 2.5

Gate Oxide 200 2.5 6000 (5) 0.2 (5)

Substrate 40000 2.5 6000 (5) 0.2 (5)

BM Cap Ox- 200 2.5 6000 (5) 0.2 (5) ide

Back Metal 1600 (800/800) 1000 (4) 0.060 (4) 2.5

5.2.1 Interconnect Resistivity

Table 5.4 shows the interconnect wire parameters in comparison to the Intel 32nm process [Natarajan et al., 2008b], [Packan et al., 2009a], [Packan et al., 2009b]. Col- umn one is the metal layer. All layers are copper based. The Rs column is the sheet resistance as described in [Synopsys, 2012] and [Synopsys, 2011]. The H columns are the thickness or height of the interconnect wires for Synopsys and Intel. The Intel thickness is calculated as follows, H = AR × (P itch/2). The Pitch columns are the interconnect wires representing metal width plus metal space, i. e. S + W . The min-

imum M1 width is assumed to be pitch P/2 or 50nm or 0.050µm. The AR columns represent interconnect aspect ratio of height or thickness over width as shown in Fig- ure 5.7. The Synopsys PDK aspect ratio is calculated as follows, AR = H/(P itch/2).

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Figure 5.7: Metal stack for nominal process variation

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Table 5.4: Comparison Synopsys 28/32nm to the Intel 32nm process

Metal ρ, R , R , D, H, H, Pitch, Pitch AR, ρ, R , w 28nm s AR µΩ- w Ω/µm Ω/ nm nm Intel nm Intel Intel Intel Ω/µm nominal cm Intel

M1 0.45 200 95 95 100 112.5 1.9 1.7 4.275 4.3 9.00 8.0

M2 0.45 600 95 95 112 112.5 1.7 1.7 4.275 4.3 8.04 8.0

M3 0.45 600 95 95 112 112.5 1.7 1.7 4.275 4.3 8.04 8.0

M4 0.45 600 95 151 112 168.8 1.7 1.8 4.275 4.3 8.04 5.33

M5 0.45 600 95 204 112 225.0 1.7 1.8 4.275 4.3 8.04 4.0

M6 0.45 600 95 303 112 337.6 1.7 1.8 4.275 4.3 8.04 2.67

M7 0.45 600 95 388 112 450.1 1.7 1.7 4.275 4.3 8.04 2

M8 0.45 600 95 504 112 566.5 1.7 1.8 4.275 4.3 8.04 1.59

M9 0.11 600 190 8000 340 19400 1.2 1.5 2.09 4.3 0.69 0.464

MRDL 0.074 3000 280 4000 0.14 2.07 0.04

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The rho, ρ, columns in Table 5.4 represent the metal layer resistivity in µ-Ω cm

(micro-ohms cm). The 28/32 nm Synopsys M1 resistivity ρ, was calculated as in Equation 5.20. This ρ of 0.95 0.95µΩ − cm is below the value of bulk copper of 1.68 µΩ − cm. The Ω/µm columns are the interconnect wire resistance. The Intel resistivity is four times higher than listed for the Synopsys PDK.

Rs × HM1 =0.1Ω/ × 95nm (5.20)

−9 = 0.1Ω/95 × 10 m (5.21) = 0.95µΩ − cm (5.22)

The metal resistivity manufacturing quality is aﬀected by the metal grain size and grain boundary reﬂections. These values are not published for these processes and can only be speculated. The Synopsys and Intel copper resistivity can be compared to the Fuchs-Sondheimer (FS) and the Mayadas-Shatzkes (MS) model [Pyzyna et al., 2017] as shown in Equation 5.23.

3 1 1 3 1 ρ = ρ λ C(1 − p) + + ρ 1 − α + 3α2 − 3α2ln 1 + (5.23) s b 8 e H W b 2 α

where α is shown in Equation 5.24 and G is shown in Equation 5.25.

R λ α = g × e (5.24) 1 − Rg G

√ G = g H × W (5.25)

The assumptions will be a bulk copper resistivity ρb of 1.68µΩ-cm, electron mean

free path λe of 39 nm, rectangle cross section C constant of 1.2, interface specularity, ρ

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of 0.49, grain boundary reﬂection Rg of 0.693, lower bound g of 1.25, a mean grain size of 86.15 nm, Area of 4750 nm2, H is 95 nm, W is 50nm and α of 0.1490. The FS model component of the resistivity is 0.4590 µΩ − cm and the MS is 4.0442 µΩ − cm. The MS model dominates the resistivity. Adding the FS and MS components results in an

analytical ρs value 4.5032 µΩ-cm. The ρs calculation results approximately matches

Intels 32nm resistivity of 4.2560 µΩ-cm, sheet resistance of 0.4480 Ω/ and wire line resistance of 8 Ω/µm and capacitance of 0.2 fF/µm [Natarajan et al., 2008b]. Intel also reports for 0.2fF/µm, a value of 0.1275 µm/Ω or 7.84 Ω/µm shown in Figure 5.8 [Ingerly et al., 2012b].

Figure 5.8: Capacitance, C, vs. inverse resistance, 1/R, at 112nm pitch (32nm: Metal-2; 22nm: Metal-4) [Ingerly et al., 2012b]

The Intel M2 resistivity was calculated. Intel only reports line resistance (Rw, 8Ω/µm), line resistance length (L = 1µm), pitch (P, 112.5nm) thickness (H, 95nm), and aspect ratio (AR, 1.7) [Natarajan et al., 2008b]. In order to approximate the resis-

(R×H×W ) tivity, ρ = L , the metal width was determined by Intel’s aspect ratio AR was calculated as follows, W = H/AR = 95nm/1.7 = 56nm. Alternately, the W

216 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE can be calcualted by the pitch W = 0.5 × P = 0.5 × 112.5 = 56.25nm. There- fore, ρ = R × H × W/L = 8Ω × 0.095µm × 0.056µ/1µm = 0.042560Ω = µm =

4.2560µΩ − cm = 0.042560Ω − µm. The sheet resistance, Rs, becomes ρ/H =

0.042560Ω − µm/0.095µm = 0.448Ω/ ≈ 0.45Ω/. By reducing Rg to 0.66845

(from 0.693), then the FS/MS resistivity analytical value ρs is 4.2560 µΩ − cm and matches to the Intel value. Other published works mention that for a 28nm analog process the sheet resistance is 0.45 Ω/ [Pipino, 2017]. The analytical analysis and the published Intel resistivities are much higher than the values in the Synopsys educational PDK. The Synopsys PDK resistivity is 0.95

µΩ − cm and a sheet resistance of 0.1 Ω/ and an interconnect wire line resistance of 2 Ω/µm. A value of 0.95 µΩ − cm cannot be less than the bulk resistivity of copper, which is 1.68 µΩ−cm. Therefore, the interconnect technology ﬁle (.itf) sheet resistance values (RSPQ) for metal layers M1 to M8 where modiﬁed from 0.1 to 0.45. In addition, the resistivity decreases on the higher and thicker metal layers approach- ing the resistivity of bulk copper, resulting in M9 and MRDL (Metal Redistribution

Layer) having sheet resistances of 0.11 and 0.074 Ω/ respectfully, which gives a resistivity of 2.09 and 2.07 µΩ − cm. For comparison, Table 5.5 illustrates the Rs for Global Foundries 28nm process [Augur et al., 2012]. As shown previously, the Intel

Rs is 7.84 ohms/µm. The capping layer (top), diﬀusion barrier (side) and liner thicknesses were not given by the 28/32nm Synopsys or the32nm Intel process. The barrier helps limit the copper from diﬀusing into the surrounding dielectric, minimizes electromigration and can provide the additional purpose of being a resistive shunt when voids form within the copper. Figure 5.9 shows the capping and barrier of a interconnect on metal 2

(M2). The sheet resistance including the resistivity of the liner thickness is shown in Equation 5.26.

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Table 5.5: BEOL for 28G and 28LP Products for Global Foundries Cu interconnects [Augur et al., 2012]

Figure 5.9: Capping and Barrier layers for M2

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L R = ρ = ρL(H − t − t − t )(W − t ) + R (Ω/µm) S HW dish capping barrier barrier barrier (5.26) Unless all the capping and barrier details are known, it is diﬃcult to make accurate inferences of the actual resistivity of the metal in the interconnect wire. Table 5.6 shows the interconnect layer dielectric (ILD) for the 28/32 nm Synopsys PDK and compares it with the Intel 22nm published data [Ingerly et al., 2012b]. The BEOL metal stack begins on top of the transistor gate: D1, M1, D2, M2 and so forth.

Interconnect capacitance is maximum, Cmax when the dielectric distance is the smallest. The top layer is encapsulated using a polymer, which provides additional properties that are necessary such as humidity resistance [Wyant and Schuckert, 2000], [Im et al., 2005a] and [pol, 2017]. The Synopsys 28/32 nm process has thermal conductivity and capacitance permittivity, r, which matches much older processes above 90nm but this is not in line with the current industry process such as Intel 32m. The tradeoﬀ of lower dielectric constants result in weaker mechanical structures. The modulus of elasticity is 71.4 GPa for SiO2 (K-value or r 3.9) whereas Low-K are around 2.5 resulting in 6 GPa. This means stress reliability becomes critical in the silicon die shown in Figure 5.10. The thermal conductivity is low for Intel, which implies the IC/ASIC will run hotter compared to older processes [Besser, 2007].

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Table 5.6: ILD parameters for Synopsys 28/32 PDK

28nm Cmax Cnominal Cmin ILD Metal Metal Thermal Intel, 22nm ILD Thermal

Dielectic Dmin, Dnom, Dmax, W, K, K, εr H, nm Material εr layer nm nm nm nm W/mK W/mK

D1 120 200 300 3.9 50 95 1.43 ULK CDO 2.5 0.4

D2 500 600 720 3.9 56 95 1.43 ULK CDO 2.5 0.4

D3 500 600 720 3.9 56 95 1.43 ULK CDO 2.5 0.4

D4 500 600 720 3.9 56 95 1.43 ULK CDO 2.5 0.4

D5 500 600 720 3.9 56 95 1.43 ULK CDO 2.5 0.4

D6 500 600 720 3.9 56 95 1.43 ULK CDO 2.5 0.4

D7 500 600 720 3.9 56 95 1.43 LK CDO 3.0 0.3

D8 500 600 720 3.9 56 95 1.43 LK CDO 3.0 0.3

D9 500 600 720 3.9 160 190 1.43 LK CDO 3.0 0.3

DMRDL 3000 3000 3000 3.9 2000 280 0.12 Polymer 3.4 0.12

Figure 5.10: Modulus of elasticity versus Dielectric constant, r [Besser, 2007]

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Interconnect Capacitance

Equation 5.27 shows how to calculate the fringe capacitance [Barke, 1988], [Yuan and Trick, 1982], [Sakurai and Tamaru, 1983], [Karsilayan et al., 2014].

   H 2π   max  cfringe,max = r0 − + r (5.27)  2Dmin   ln 1 + 2Dmin 2Hmax 2Hmax + 2  Hmax Dmin Dmin

The parallel plate capacitance model (non-fringe) is shown in equation 5.28. The relative permittivity is denoted as r and will be 3.9 for Silicon Dioxide (FSG) for the 28/32nm Synopsys process. The absolute permittivity, 0 in a vacuum is 8.85 × 10−12F/m. The distance between the plates is denoted by D and the area of the plates is denoted by Area.

Area Cpp = (F arads) (5.28) r 0 D

Figure 5.11 shows the geometry for the interconnect computational model shown in Equation 5.29. Equation 5.29 is the interconnect capacitance computational model, which assumes a wire length of one micron.

CppM1,total = CppM1,Substrate + 2CppM1,M1 + CppM1,M2 (F arads) (5.29)

Equations 5.30, 5.31 and 5.32 are the equations for CppM1,Substrate, CppM1,M1 and

CppM1,M2 used in Equation 5.29.

15 WM1 × LM1 10 fF/F WM1 CppM1,Substrate = r0 = r0 6 × (fF/µm) DM1 − Hpoly 10 µm/m DM1 − Hpoly (5.30)

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Figure 5.11: Interconnect capacitance model

15 HM1 × LM1 10 fF/F HM1 CppM1,M1 = r0 = r0 6 × (fF/µm) (5.31) SM1 10 µm/m DM1

15 WM1 × LM1 10 fF/F DM2 CppM1,M2 = r0 = r0 6 × (fF/µm) (5.32) DM1 − HM1 10 µm/m DM2 − HM1

Table5.7 shows the Synopsys PDK 28/32 nm (nominal) process for the interconnect dielectric and metal values. Columns denote the PDK 28/32nm process information reported by the Synopsys IC Compiler (ICC) Place and Route SW tool. The Cpp (Calc) column is the result of the analytical calculations from Equation 5.29.

These values can be compared to the Cnominal (ICC) column and are approximately equal to the calculated values. Rnominal values are in the range of the Intel 32nm process as discussed in the previous section.

Intel reports for a 32nm M2 interconnect, a line capacitance of 0.2 fF/µm

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Table 5.7: Synopsys 28/32nm ILD parameters

ILD ILD Metal Metal IMD RPSQ R C Cpp RC 28nm nominal nominal (itf) (itf) (itf) (itf) (itf) (itf) (ICC) (ICC) (Calc) delay

Dielectic Dnom, H, W, S, Rs, 2 εr Ω/µm fF/um fF/um ps/mm layer nm nm nm nm Ω/ D1 /M1 200 3.9 95 50 50 0.45 9.0 0.150 0.148 1350

D2 /M2 600 3.9 95 56 56 0.45 8.0 0.160 0.125 1286

D3 /M3 600 3.9 95 56 56 0.45 8.0 0.100 0.125 804

D4 /M4 600 3.9 95 56 56 0.45 8.0 0.100 0.125 804

D5 /M5 600 3.9 95 56 56 0.45 8.0 0.087 0.125 699

D6 /M6 600 3.9 95 56 56 0.45 8.0 0.087 0.125 699

D7 /M7 600 3.9 95 56 56 0.45 8.0 0.085 0.125 683

D8 /M8 600 3.9 95 56 56 0.45 8.0 0.085 0.132 683

D9 /M9 600 3.9 190 160 160 0.11 1.8 0.097 0.117 667 DMRDL 3000 3.9 280 2000 2000 0.074 1.8 0.110 0.034

[Natarajan et al., 2008b] [Fischer et al., 2015b]. Also reported by Intel are values in the range of 0.17 fF/µm to 0.22 fF/µm interpreted from Figure 5.8 [Ingerly et al., 2012b]. For 22nm, Intel reports a range of 0.15 fF/µm to 0.185 fF/µm [Ingerly et al., 2012b].

The 28/32 nm Synopsys M1 reports 0.15 fF/µm, which lies within the low range for the Intel 32nm and 22nm processes.

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28nm Synopsys nominal Process Interconnect M1 Summary

Table 5.8 summarizes the dimensions for the Synopsys 28/32nm PDK.

Table 5.8: M1 dimensions for Synopsys 28/32 PDK

Metal Cu Copper

H 95 nm M1 thickness

W 50 nm M1 width

AR 1.9 M1 aspect ratio, H/W

S 50 nm M1 metal spacing

P 100 nm M1 pitch, S+W

The previous section showed that ρ was not correct in the Synopsys 28/32nm PDK.

Table 5.9 shows the modiﬁed value used for ρM1 and summarizes the parameters used for the wire interconnects in the calculations and layout [Lin et al., 2007].

Table 5.9: Interconnect resistance parameters for Synopsys 28/32 PDK

ρbulk 1.68 µΩ-cm bulk copper resistivity -8 ρM1 4.2750 µΩ-cm M1 resistivity, 4.2750 x 10 Ω-m ◦ βM1 25 C 0.003 Temperature coeﬃcient for copper (TC1 Spice, CRT1 .itf)

λe 39 nm electron mean free path C 1.2 rectangle cross section p 0.49 interface specularity g 1.25 lower bound grain factore

Rg 0.66845 grain boundary reﬂection RPSQ, Rs 0.45 Ω / sheet resistance (rounded up from 0.448) Rnominal,Rw 9.0 Ω / µm line resistance M1

Rw,RM2 8.0 Ω / µm line resistance M2

The resistivity for Vias was provided by the Synopsys 28/32nm PDK at 25 ◦C as shown in Table 5.10. The resistivity was calculated for diﬀerent temperatures as shown in Table 5.11, which follow the values published by Lin [Lin et al., 2007].

Table 5.12 summarizes the M1 dielectric and capacitance parameters for the Syn- opsys 28/32nm PDK. Table 5.13 summarizes the EM parameters for the Synopsys

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Table 5.10: Via resistivity parameters for 25 ◦C [Lin et al., 2007]

α, TCR 0.003 ◦ To 25 C

ρ(To) 4.275 µΩ − cm Thickness 95nm

Width, M2 56nm V ia 1.0 Ω

V iax 0.5 Ω

V ia8 0.1 Ω

V iaRDL 0.05 Ω

Table 5.11: Via resistivity calculated for diﬀerent Temperatures [Lin et al., 2007]

T -40 ◦C 0 ◦C 20 ◦C 25 ◦C 70 ◦C 85 ◦C 105 ◦C 110 ◦C 125 ◦C ρ, µΩ − cm 3.441 3.954 4.211 4.275 4.852 5.045 5.301 5.365 5.558 RP SQ, Ω/ 0.3623 0.4163 0.4433 0.4500 0.5108 0.5310 0.5580 0.5648 0.5850 Rw, Ω/µm 6.4688 7.4330 7.9152 8.0357 9.1205 9.4821 9.9643 10.0848 10.4464

V ia1, Ω 0.8050 0.9250 0.9850 1.0000 1.1350 1.1800 1.2400 1.2550 1.3000 V iax, Ω 0.4025 0.4625 0.4925 0.5000 0.5675 0.5900 0.6200 0.6275 0.6500 V ia8 0.0805 0.0925 0.0985 0.1000 0.1135 0.1180 0.1240 0.1255 0.1300

V iaMRDL 0.0403 0.0463 0.0493 0.0500 0.0568 0.0595 0.0620 0.0628 0.0650

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28/32nm PDK.

Table 5.12: Dielectric and Capacitance parameters for Synopsys 28/32nm PDK

D1 200 nm Dielectic thickness, below M1

D2 600 nm Dielectic thickness, above M1

εr 3.9 Capacitance relative permittivity, IMD, ILD, SiO2

Em 71.4 GPa Modulus of elasticity

◦ Dielectric thermal conductivity, SiO2 κox (Tox ) = κox 1.43 W / m C −4 −6 2 1.43 + 3.86 × 10 · Tox + 2 × 10 × Tox Cnominal 0.15 fF / µm Line capacitance, M1 between Substrate and M2 RC 1350 ps/mm2 RC wire delay for a wire length of 1 mm

Table 5.13: EM parameters for Synopsys 28/32nm PDK

Ea 0.8 eV EM activation energy n 1 EM current density exponent σ 0.4 EM lognormal sigma

t0.1% 100,000 hours EM 0.1% lifetime failure, 11.4 years R 0 EM recovery T 105 ◦C 378.15 ◦K, temperature of metal Jmax, 105 ◦C 1.194 MA/cm2 EM Maximum current density 2 A50% 8.95 hours/A/cm EM constant

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Temperature and EM

The interconnect wire’s electromigration is eﬀected by the wire temperature, Tm. This is related to the physical layout of the metal stack of an IC/ASIC. The interconnect wires for each metal layer will rise in temperature within the metal/dielectric (oxide) stack. The IC/ASIC die is usually encapsulated in a 2000 to 3000 micron thick polymer with a thermal conductivity of 0.12 watts/meter-kelvin. This polymer surrounds the sides and the top of the die and has a temperature of Tambient. Each of the metal layers are modeled such that resistivity is temperature dependent on the temperature of the oxide layer as shown in Equation 5.33. The dielectric oxide thermal conductivity model is temperature dependent as shown in Equation 5.34 [Black, 1982].

−4 −6 2 κ(Tox) = 1.43 + 3.86 × 10 × Tox + 2 × 10 × Tox (watts/meter − Kelvin) (5.33)

ρm(Tm) = ρM1 × (1 + βM1 (Tm − Tref )) (5.34)

The bottom of the die is the substrate, which has a temperature of Tsubstrate. The metal stack material parameters were described in Tables 5.6 and 5.7 in the previous section. Table 5.14 summaries Tmax for various substrate temperatures and external operating temperatures. The temperature peaks near the MRDL layer, which is the highest metal layer. As the external temperature rises above 25 ◦C, the internal temperature of the IC/ASIC begins to rise proportionally. This illustrates that for each metal layer the temperature, (Tm) is dependent on the ambient temperature

(Tambient). To see the temperature effects for EM, thermal simulations were performed using COMSOL a multi-physic modeling SW tool derived from the Synopsys 28/32nm PDK technology file (.itf). This file contains sheet resistance, layer thickness, minimum

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Table 5.14: Synopsys 28/32nm Tsubstrate temperature rise based on Tambient and percent rise in temperature of the IC/ASIC

◦ Tsubstrate Tambient 85 C Tmax - -40 ◦C 25 ◦C 85 ◦C Percent Tsub◦C 95 ◦C 95 ◦C 100.916 ◦C 118.63o ◦C 23.63 ◦C 25% 105 ◦C 105 ◦C 108.744 ◦C 126.396 ◦C 21.40 ◦C 20% 110 ◦C 110 ◦C 112.663 ◦C 130.284 ◦C 20.28 ◦C 18% 125 ◦C 125 ◦C 125.892 ◦C 141.966 ◦C 16.97 ◦C 14%

metal widths, and dielectric constants. These parameters were applied to COMSOL multi-physics using thermal and electrical physics to model the worst case current density parameters. The substrate temperature, T, is the temperature representing the transistor layer. The dielectric layers act as an insulator, which can add heat as each metal layer also heats up due to the current density of each metal layer. The metal self-heating eﬀects the current density of the metal layer, and must be derated for the EM tables for a given substrate temperature and ambient temperature outside the die. Each metal wire is minimum width for the Synopsys 28/32 nm nominal

process dimensions. Each interconnect wire, from M1 to MRDL, is at Jmax using a value of 1.164 MA/cm2.

◦ ◦ Figure 5.12 shows the thermal plots for Tsubstrate of 105 C and Tambient of 25 C, which rises to a maximum 111 ◦C at the top metal layer.

◦ ◦ Figure 5.13 shows Tsubstrate of 105 C and Tambient of 85 C, which rises to a maximum 127 ◦C. Figure 5.14 shows Tsubstrate of 105 ◦C and Tambient of -40 ◦C.

◦ ◦ Figure 5.15 shows Slice plots for Tsubstrate of 105 C and Tambient of 25 C, which rises to a maximum 111 ◦C at the top metal layer. This illustrate the temperature

proﬁle from M1 to the MRDL layer.

◦ ◦ Figure 5.16 shows Slice plots for Tsubstrate of 105 C and Tambient of 85 C, which

228 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

◦ ◦ Figure 5.12: COMSOL simulation for Tsubstrate of 105 C and Tambient of 25 C

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◦ ◦ Figure 5.13: COMSOL simulation for Tsubstrate of 105 C and Tambient of 85 C

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◦ Figure 5.14: COMSOL simulation for COMSOL simulation for Tsubstrate of 105 C ◦ and Tambient of -40 C

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◦ ◦ Figure 5.15: COMSOL simulation for Tsubstrate of 105 C and Tambient of 25 C rises to a maximum 111◦C at the top metal layer.

◦ ◦ Figure 5.17 shows Slice plots for Tsubstrate of 105 C and Tambient of -40 C, which rises to a maximum 111 ◦C at the top metal layer.

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◦ ◦ Figure 5.16: COMSOL simulation for Tsubstrate of 105 C and Tambient of 85 C

◦ ◦ Figure 5.17: COMSOL simulation for Tsubstrate of 105 C and Tambient of -40 C

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5.2.2 Synopsys 28/32 PDK EM tradeoﬀs by Imax

The maximum allowable DC current, Imax for metal layers M1 to M9 given in the

28/32nm Synopsys PDK library is shown in Equation 5.35. From the Imax equation,

Jmax and Imaxw values can be calculated by using the thickness, H and width W of the metal layer. The equations are used by the Synopsys layout tools (ICC - IC Compiler) to calculate currents in the interconnects, which is used in our methodology described in Chapter 6.

Imax = FEM (Tm) × (0.9W − 0.002) ≈ Imaxw × W (mA) (5.35)

[Synopsys, 2012] where W is the interconnect in micrometers (µm), FEM is an electromigration factor, W is the width of the interconnect.

An example is shown in Equation 5.36 for metal layer M1. For the temperature

◦ of the metal Tm = 110 C, the electromigration factor FEM = 1. The width of the

interconnect is WM1 = 50nm with a height HM1 = 95nm.

Imax = 0.81W − 0.0018 = 0.81(0.050µm) − 0.0018 = 0.0387mA (5.36)

[Synopsys, 2012]

From Equation 5.36, Jmax can be found as shown in Equation 5.37.

I 0.0387mA J = max = = 0.853MA/µ2 (5.37) max H × W 0.095 µm × 0.050 µm

The Imaxw calculation is shown in Equation 5.38.

2 Imaxw = Jmax × H = 0.853 MA/cm × 0.095 µm = 0.81035 mA/µm (5.38)

Table 5.15 shows the allowable current densities for the Via and metal layer at

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various operating temperatures (Tuse), for an EM lifetime of 11.4 year (100,000 hours).

The Imax, Via column shows that the minimum Via is equal or greater than the capacity of the minimum Imax of the interconnects. The 2007 ITRS column is for a metal pitch of 104nm at 105 ◦C (W = pitch P/2), and is used as a comparison with the 28/32nm Synopsys PDK to ensure the PDK contains realistic data. The 32nm Intel column is used as a comparison but, Intel did not specify the temperature. Intel speciﬁed the Idsat of the NMOS transistor. The Dennard scaling was used as previously derived for a constant Imax. In comparison, an older 180 nm TSMC process using an aluminum metal layer was deﬁned as 1 mA/µm for electromigration [Zhu, 2013], which closely matches the 28/32nm Synopsys copper metal process.

Jmax increases as the operating temperature decreases in proportion to the Arrhenius equation.

Table 5.15: Imax, Imaxw and Jmax for various Tuse temperatures 100 105 110 115 120 125 T 95 ◦C Intel ITRS use ◦C ◦C ◦C ◦C ◦C ◦C Imax,via mA 0.0620 0.0569 0.0560 0.0400 0.0300 0.0220 0.0160 Imax, W=0.050 mA 0.0600 0.0569 0.0911 0.0667 0.0542 0.0387 0.0290 0.0213 0.0155 µm Imaxw mA/µm 1.256 1.191 1.620 1.282 1.134 0.810 0.608 0.446 0.324 2 Jmax MA/cm 1.322 1.253 1.694 1.370 1.194 0.853 0.639 0.469 0.341

Table 5.16 shows the Synopsys 28/32nm PDK values of FEM electromigration

temperature derating factor for metal layers M1 to M9. It is assumed that the Syn- opsys FEM derates the Jmax in order to maintain the 11.4 year lifetime for a 0.1% failure rate.

Table 5.16: Synopsys 28/32 nm PDK data for FEM EM temperature derating ◦ ◦ ◦ ◦ ◦ ◦ ◦ Tuse 95 C 100 C 105 C 110 C 115 C 120 C 125 C 368.2 373.2 378.2 383.2 388.2 393.2 398.15 T use ◦K ◦K ◦K ◦K ◦K ◦K ◦K

FEM(T) 1.55 1.47 1.4 1 0.75 0.55 0.4

Fjmax(T) 2.68 1.91 1.38 1 0.73 0.54 0.40

In order to understand the relationship of FEM to reliability theory and the Ar-

235 CHAPTER 5. TRADE OFFS FOR LIFETIME VERSUS PERFORMANCE

rhenius equation, a derivation of FEM (T) is as follows. The acceleration factor (AF) is the ratio of the use to the stress temperatures for t50% as shown in Equation 5.39.

Ea n k Tuse t50,use A0jusee B AFj = = Ea (5.39) t50,stress n k T A0jstresse B stress n Ea j e kB Tuse = use (5.40) j Ea stress e kB Tstress Ea 1 1 n k T − T = (Fjmax(T )) e B use stress (5.41)

For Cu interconnects the following parameters can be used: n = −1, Ea = 0.8,

◦ Tstress = 110 C, and no acceleration factor i.e. AF = 1, Equation 5.39 becomes Equation 5.42

Ea 1 − 1 k T T ◦ Fjmax(Tuse) = e B use 110 (5.42)

2 The Synopsys PDK 28/32nm library deﬁnes Jmax = 1.194MA/cm and a σ =

0.4. To ﬁnd the time to failure (t0.1), knowing Black’s Law EM follows a lognormal

distribution, and from previous sections, Equation 5.43 can be used to ﬁnd (t0.1) [McPherson, 2013].

Ea −n k Tuse NORMSINV (0.1%)×σ t0.1% = A50jmaxe B e (5.43)

Using σ = 0.4, Equation 5.43 becomes Equation 5.44.

Ea −n k Tuse −3.09×σ t0.1% = A50jmaxe B e (5.44)

A50 is not speciﬁed in the Synopsys PDK 28/32nm library. A50 can be found using Equation 5.44, which becomes Equation 5.45.

− Ea n k Tuse 3.09×σ A50 = t0.1%jmaxe B e (5.45)

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Equation 5.46 calculates A50 for t0.1% = 100, 000 hours, with:

◦ ◦ Tuse = 105 = 378 K n = 1

Ea = 0.8

−6 ◦ kB = 8.61733 × 10 eV/ K, Boltzmann’s constant σ = 0.4

0.8 3.09×0.4 6 2 − k (378◦K) e A50 = 100, 000hours 1.194 × 10 A/cm e B (5.46)

= 8.95hours/A/cm2 (5.47)

= 8.95−6hours/ MA/cm2 (5.48)

= 1.02 × 10−3years/ A/cm2 (5.49)

If the standard deviation σ is increased to 0.5, A50 is decreased as shown in Equation 5.50.

2 A50 = 6.59hours/A/cm (5.50)

= 6.59−6hours/ MA/cm2 (5.51)

= 7.52 × 10−4years/ A/cm2 (5.52)

237 Chapter 6

Lifetime Driven Design Methodology

This chapter will describe a lifetime driven methodology to explore the tradeoffs between Reliability, Performance, Cost (Area) and Power. The Reliability or degradation effects of electromigration affect the lifetime of the IC/ASIC and the product it is used in. Examples are a mission profile of the IC/ASIC can be explored and optimized depending if the product requires maximum performance and can tolerate a 5 year lifetime. A mission profile is the desired goals of a product and the environmental conditions the product will operate under. A mission profile is

– Environmental or Ambient temperature

– Lifetime

– Performance

– Power

– Cost (area)

Note there are two design scenarios that can use the proposal procedure.

238 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

a. Increase lifetime with safe circuit operation for longer times with possible loss of some performance within an acceptable threshold of about 10%. This scenario may apply to safety oriented designs in automobile industry, avionics, health care, military and many more.

b. Decrease life time resulting to increase performance with higher performing circuit operation at shorter lifetimes. This scenario applies to wireless devices such as smart phones and other IoT type of devices as these devices are frequently replaceable.

The proposal methodology allows for design space exploration for IC/ASICs driven by EM lifetime concerns. In our experiments, we employed a microprocessor design as a representative IC/ASIC design using commercial simulation, synthesis and layout tools from Synopsys. We developed procedures and custom scripts for driving the tools to perform our design exploration methodology.

6.1 OpenCore Amber 25 Microprocessor

An Amber 25 processor core from OpenCores [OpenCores, 2017] was used to validate our methodogy’s approach. OpenCore’s is an online community for the development of IP (Intellectual Properties) Cores. The Amber 25 processor is an ARM-compatible 32-bit RISC processor. The Amber core is an ARM3 hardware architecture that is compatible with the ARM R v2a instruction set architecture (ISA), and is supported by the GNU SW toolset. The Amber 25 has a 5-stage pipeline, separate 2-way data and 2-way instruction caches with a width of 128 bits and a 128-bit Wishbone bus interface with a single synchronous clock. The Amber 25 contained a UART, timer and Ethernet MAC, but they were not needed for the experiments, therefore not implemented. The Amber 25 was designed and targeted for a Xinlinx Virtex FPGA. Modiﬁcations were made so it could be implemented as an ASIC. Since the Amber

239 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

25 was optimized for FPGA synthesis, there was no reset logic for the registers. Modifications were made so all flip-flops could be reset with an input pin. Figure 6.1 shows the block diagram of the Amber 25, with the testbench used in simulation.

Figure 6.1: Amber 25 design block diagram

The testbench was designed to implement the RAM and the control signals needed for the Amber 25 microprocessor. A binary sort routine was written in assembly to exercise the Amber 25 and Wishbone bus. Having representative test vectors to exercise the design is an important to our methodology to predict the power, which causes self heating of the interconnects and aﬀects the lifetime.

240 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.2: High Level Design Exploration System 6.2 High Level Description of the Methodology

This section explores the design tradeoffs in the design of an ASIC. A high level diagram of the tool flow is shown in Figure 6.2. To begin the tool flow, a Mission Profile for the product IC/ASIC based on the following elements needs to be determined.

– Environmental or Ambient temperature

– Lifetime

– Performance

– Power

– Cost (area)

Next is the exploration of the tradeoﬀs. The Standard Cell library for a process node used for a digital ASIC design is typically characterized for a 10 year lifetime at 110 ◦C. The deﬁnition of a failure in an IC/ASIC design is when a interconnect wire resistance changes by 10%. The timing closure for the design will allow for a 10%

241 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY change in resistance and still meet timing for the circuit. This would be the baseline for the Mission Proﬁle (10 year lifetime for IC/ASIC at 110 ◦C. The IC/ASIC design would be synthesized, placed and routed, and the EM analysis performed exploring the lifetime versus performance space. – Exploration Procedure

• Synthesize the design with Design Compiler

• Simulate the gate netlist to generate a switching activity ﬁle for power and EM calculations

• Perform thermal simulations with COMSOL (Section 5.2.1) for the Mission Proﬁle to determine the substrate. The temperature is needed for Black’s Law calculations.

• Place and Route the design using ICC

• Perform EM analysis for a baseline IC/ASIC design for a 10 year lifetime (10% interconnect wire resistance change).

• Fix all EM violations that may occur.

• For Increase in lifetime

– Increase lifetime progressively to 10+Years in 1 year increments up to 20 years.

– Identify violations at 10+Years

– Fix violations for circuit to be operational at 10+Years

– May need to reduce performance constraint within a given threshold e.g. 10% decrease in performance for acceptable operation at 10+Years.

– End procedure at 20 years

242 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

• For a decrease in lifetime

– Decrease lifetime progressively to 10–Years down to 4 years.

– Identify violations at 10–Years

– Fix violations for circuit to be operational at 10–Years

– Manage increase performance within a given threshold e.g. 10% increase in performance for acceptable operation at 10-Years.

– End procedure at 4 years

The goal of our methodology is to explore the design space between performance, operating temperature and lifetimes. Cost would also be a consideration if the die size became too large to meet the Mission Profile goals. Figure 6.3 shows the design exploration tradeoffs based on electromigration parameters of current density (j), and temperature, T. The pink plot shows the result of increasing the current density and temperature leads to a higher IC performance. The blue plot shows the result of lifetime due to current density and temperature. The combined plot shows the tradeoff design between lifetime and performance.

243 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.3: Plot illustrating the tradeoﬀs of Current density j vs Temperature (T ) vs Lifetime (Z)

244 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

6.3 Detailed Description of the Methodology

The tools used for the methodology follow. The version of the tools are listed in the Appendix in Section 11.1. A detailed diagram of the tool ﬂow for the methodology is shown in Figure 6.4.

1. Library - Synopsys 28/32nm PDK

2. RTL and Gate simulations - Synospsy VCS

3. Synthesize RTL to Gate Level netlist - Synopsys Design Compiler (DC)

4. Place and Route and analysis - Synopsys IC Compiler (ICC)

5. Power, timing, EM analysis - Synopsys ICC

6. Parasitic interconnect extraction - Synopsys StarXtract

7. Tcl and Python scripting languages

8. Thermal simulation - COMSOL

9. Analog simulation - Synopsys hspice

10. Amber 25 assembler for the test bench - VASM

The Synopsys 28/32nm PDK contains the library information needed for simulation, synthesis and place and route for the PVT (Power, Voltage, Temperature) corners needed for an IC/ASIC design. The library PVT diagram is shown in Figure 6.5. The libraries are characterized for the PVT corners for the variations in manufacturing process. The Target Library consist of multi-threshold voltage logical gates.

There are three (3) gate input voltage thresholds (Vt). These are used to trade oﬀ between gate speed (performance) and power. The lvt (low voltage threshold) are the fastest gates with highest power. The hvt (high voltage threshold) are the slowest

245 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.4: Tool ﬂow for EM Methodology

246 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.5: Library PVT (Process, Voltage and Temperature) diagram

gates with lowest power. The rvt (regular voltage threshold) would be between the lvt and hvt libraries for speed and power. The Process Corner or Scaling Libraries contain the timing information for the variations in the manufacturing process. There are five (5) Process corners for each of the Vt gate libraries. They are ss (slow-slow), tt (typical-typical), ff (fast-fast), sf (slow-fast) and ff (fast-fast). These are for the process variation between the PMOS and NMOS transistors of the gates. An example is the sf Process corner is for a slow PMOS gate and a fast NMOS due to process variation in the manufacturing process. There are four (4) corners for the supply Voltage (V). The voltages are 0.85V, 0.95V, 1.0V and 1.05V. For each V there are three (3) tempertures characterized, -40 ◦C, 25 ◦C and 125 ◦C. Some additional details about these librearues follow. The place and route libraries also contain three (3) Vt libraries. These are the Physical Reference Li- braries in Figure 6.5. The Interconnect Library contains the interconnect technology file (.itf ), which contains the interconnect wire information. The source is the saed32nm 1p9m nominal.itf, and the program grdgenxo is used to convert this file to

247 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY the saed32nm 1p9m nominal.tlplus file used by ICC. The Electromigration Library (saed32nm 1p9m nominal.alf) includes the information needed by ICC to perform electromigration analysis of the design. This is the file that was modified to perform the tradeoffs between performance and lifetime. The Mission Profile is chosen for the ambient temperature the IC/ASIC will operate, the lifetime, performance and cost expectation of the product. The Mission Profile starts with the goal of the maximum temperature of the IC/ASIC substrate temperature of 110 ◦C, a lifetime for 0.1% failure of the devices of 11.4 years (100,000 hours) and performance of a 1 GHz clock. The RTL Verilog description of the Amber 25 design (Section 6.1) was simulated to verify the design. A test bench was generated that performs a sort using an assembly program based on the assembler VASM. The test bench also was used to create a switching activity file (saif). The VCS simulator uses the saif Gate Library provided in the 28/32nm PDK. This is used by the place and route tool ICC for power and EM analysis. After simulation, the Design Compiler (DC) from Synopsys was used to synthesize a gate level netlist from the RTL design. DC uses the Target Libraries, which contain the 3 multi-threshold Vt libraries (saed32hvt tt1p0v125c.db, saed32rvt tt1p0v125c.db, saed32hvt tt1p0v125c.db). DC also inputs the Scaling Library groups for Process, Voltage and Temperatures corner calculations. From the DC gate level netlist, ICC is used for floor planning, gate placement, clock tree synthesis and timing aware routing of the design. ICC also performs timing, power and EM analysis. EM analysis starts by performing a thermal simulation to obtain the substrate and metal layers temperatures. The interconnect metal stack and inter-dielectric information was used to find the substrate temperature based on the ambient temperature from the Mission Profile. This was then used as input along with the PDK 28/32nm, σ value, Lifetime target, Metal Vias and package thermal

248 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

deratings to modify the Black’s Law equation. A python script then modified the EM input file to ICC (saed32nm 1p9m nominal.alf) for EM analysis of the design to explore the performance versus lifetime design space. ICC performs the calculations for EM for each interconnect wire in the design. Multiple iteration were performed with ICC investigating the best way to fix the violation as follows.

– Redesign the RTL module around the wire(s) violation

– Reroute the violator wire(s)

– Add buﬀers intersecting the violator wire(s)

– Reduce or increase supply voltage (Vdd)

– Reduce temperature by cooling circuit (such as heat sinks) or change Mission Proﬁle operating environment

– If possible, widen violator wire

– Reduce the lifetime depending on Mission Proﬁle

– Reduce the performance depending on Mission Proﬁle

hspice simulations were performed to validate the analysis of EM in ICC by creating a ring oscillator (11 inverters). Figure 6.6 shows the tool flow. A command file called starrc commands.cmd was created to extract the interconnect wires resistance and capacitance (RC) using StarXtract. An example of the hspice file created by StarXtract is shown in the Appendix Section 11.6. The Technology Foundry files from the 28/32 PDK supply the information needed to extract the RC information from the design. The output of StarXract is a spice file. hspice was used to verify the currents of the interconnects and gate delays for nets identified by ICC as EM.

249 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.6: Tool ﬂow for Spice to validate the EM Methodology using ICC

Table 6.3 shows the comparisons between hspice and ICC for different clock frequencies (performance), power, current densities (J) for lifetimes for the ring oscillator. The table shows that our methodology of modifying the EM library of ICC is valid for exploring the performance and lifetime tradeoffs. The hspice file used in the table is in the Appendix Section 11.7.1.

250 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Table 6.1: Comparison of Lifetime calculations between ICC and hspice

Clock ICC Power hspice ICC J ICC Life hspice Freq hspice J Period uW Power Ma/cm2 yr Life yr

1 ns 1 GHz 10.756 10.750 0.195 0.195 27.142 27.158

0.5 ns 2 GHz 21.512 21.51 0.3904 0.390 13.571 13.579

0.25 ns 4 GHz 43.024 43.00 0.7808 0.7804 6.7857 6.7894

0.25 ns 4 GHz 29.5676 29.573 0.5366 0.5367 9.8739 9.8721

0.25 ns 4 GHz 26.8764 26.9131 0.4878 0.4884 10.8626 10.8477

251 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Modiﬁed Black’s Law for Methodology

A function to derate Jmax is needed to guide ICC for the methodology. The Synopsys 28/32nm PDK provides a table of values and an equation for the acceleration factor

(AF) to derate Imax in order to maintain the 11.4 year lifetime for a 0.1% failure rate at 110 ◦C. The AF values are shown in Table 6.2.

The PDK shows how Imax is calculated using the table based on an AF function

(FPDK ) and the operating temperature (T ) as shown in Equation 6.2.

◦ Imax(Top) = FPDK (Top) × Imax(110 C) (6.1)

◦ An example of how to calculate Imax for 125 C is shown in Equation 6.2

◦ ◦ ◦ Imax(125 C) = FPDK (125 C) × Imax(110 C) (6.2)

Table 6.2: Synopsys 28/32 nm PDK data for the EM function FEM temperature derating

◦ ◦ ◦ ◦ ◦ ◦ ◦ Top 95 C 100 C 105 C 110 C 115 C 120 C 125 C

368.15 373.15 378.15 383.15 388.15 393.15 398.15 ◦K ◦K ◦K ◦K ◦K ◦K ◦K

I , max 1.55 1.47 1.4 1 0.75 0.55 0.4 FPDK(T)

Figure 6.7 is a plot of the Synopsys 28/32nm PDK acceleration factor (AF) func-

tion based on temperature. The FPDK (T ) plot shows there is an exponential and a linear component for the table values. The Synopsys 28/32nm PDK also provides the copper interconnect process vari-

◦ ◦ ◦ ables for Ea = 0.8eV , Tfab = 110 C(383.15 K) and T lin = 105 C (Table 5.13). The

252 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.7: Synopsys 28/32nm PDK Acceleration Factor

exponential acceleration factor function for the operating temperature (Top) of the

IC/ASIC can be deﬁned as Fexp(Top), and is shown by the yellow line in Figure 6.8.

The cross over temperature from exponential to linear is shown as Tfab in the ﬁgure.

The linear acceleration function can be described as Flin(Top), and is shown by the red line in Figure 6.8. The linear functionFlin(Top) is a curve ﬁt for the temperature

◦ values from 105 C and below from the PDK Imax values.

Equation 6.3 describes the exponential acceleration function for Fexp(Top).

Ea 1 1 k T − 110◦C ◦ Fexp(Top) = e B op where Top > 105 C (6.3)

Equation 6.4 describes the linear curve ﬁt acceleration factor function.

◦ ◦ Flin(Top) = 5.495583 − 0.015(Top − 105 C) where Top < 105 C (6.4)

Combining Equations 6.3 and 6.4 gives the function for the acceleration factor

253 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Figure 6.8: Synopsys 28/32nm PDK Acceleration Factor as used in ICC

(Fjop(Top)) for a given operating temperature (Top) as deﬁned in Equation 6.5.

Fjop(Top) = Fexp(Top) + Flin(Top) (6.5)

Table 6.3 summarizes the acceleration factors used in the methodology. The

Fjamx(T ) in the table are the values if only the the exponential AF (Equation 6.3) was used, and shown by the yellow line in the plot in Figure 6.8. This would result in derating factors at lower temperatures that are too optimistic and not aligned with the AF given in the PDK. The Fjop(T ) row in the table uses Equation 6.5 for the AF function values. These match the AF function values in the PDK validating the equation, and is used the “Modiﬁed Black’s Law” in the methodology (Figure 6.2).

Generating the Synopsys 28nm EM ALF ﬁle

ICC analyizes EM and uses the ALF ﬁle as the input for the analysis. The calculations for the ALF ﬁle are based on the equations given in the Synopsys 28/32 PDK. Table

254 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Table 6.3: Synopsys 28/32 nm PDK data for the EM function FEM temperature derating

◦ ◦ ◦ ◦ ◦ ◦ ◦ Top 95 C 100 C 105 C 110 C 115 C 120 C 125 C

368.15 373.15 378.15 383.15 388.15 393.15 398.15 ◦K ◦K ◦K ◦K ◦K ◦K ◦K

I , max 1.55 1.47 1.4 1 0.75 0.55 0.4 FPDK(T)

Fjmax(T) 2.684 1.914 1.378 1 0.732 0.540 0.401

Flin(T) 1.548 1.473 1.398 1.323 1.248 1.173 1.098

Fjop(T) 1.548 1.473 1.398 1 0.732 0.540 0.401

6.4 shows the metal and Via equations for the calculation of Iavg, Imax, Irms, Ipeak at for 110 ◦C.

◦ Table 6.5 shows the Synopsys 28nm PDK metal and Via data for 110 CIavg, Imax,

Irms, Ipeak computed from the EM PDK equations. Table 6.6 shows the Synopsys

◦ 28nm PDK metal and Via data for 110 CIavg, Imax, Irms, Ipeak computed from the EM PDK equations for comparison. The current densities are computed from the current by dividing the thickness and width. The last two columns are the

Javg,P DK unipolar current densities computed from the base Javg where Jpulse,rms = √ . (duty cycle)

Javg,pdk Jpulse,peak = (duty cycle) . By setting the duty cycle assumption, the unipolar model can be made to ﬁt or act as a worst case ﬁt for (duty cycle) = r = 0.02 for the Jrms, and

(duty cycle) = r = 0.05 for Jpeak (Section 4.6). The Synopsys 28nm PDK does not supply the Via RMS or PEAK information. This was created using the standard pulse equations from Section 4.6 and shown below.

255 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Table 6.4: Synopsys 28/32 nm PDK data for the EM function FEM temperature derating

Iavg , mA IRMS , mA Ipeak , mA

q 18×0 .9 (0.9W − M1 0.9(0.9W − 0.002) 2 0.9W +0.197 = 13∆T (0.9W − 0.003) 0.9W −0.003 0.002)

M2 to q 9×0 .9 (0.9W − 2 × 0.9(0.9W − 0.002) = 2∆T (0.9W − 0.003)2 0.9W +0.197 M8 0.9W −0.003 0.002)

q 20×0 .9 (0.9W − M9 2 × 0.9(0.9W − 0.002) 2 0.9W +0.197 = 13∆T (0.9W − 0.003) 0.9W −0.003 0.002)

q 5×0 .9 (0.9W − MRDL 5 × 0.9(0.9W − 0.002) 2 0.9W +0.197 = 5∆T (0.9W − 0.003) 0.9W −0.003 0.002)

ViaX 0.04

ViaRDL 0.08

Table 6.5: Calculations for EM I and J for values for metal layers from Synopsys 28/32nm PDK

256 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Table 6.6: Calculations for EM I and J values calculated for Vias

The current density for the applications mission profile operating conditions, jop, is derived based on the IC/ASIC fabs (Synopsys PDK) current density jfab(Tfab,Ffab,Lfab), where Tfab, Ffab, Lfab and Dfab are the temperature, failure lifetimes and temperature derating for each metal layer in the metal stack and the thermal package data. Python scripts were used to modify the .alf and .itf files needed by ICC for the EM analysis. The .alf file contains the current densities allowed in each metal layer and Vias. The python script creates the tables in the .alf file for javg, jrms and jpeak. How these values are used in the EM analysis were described in Section

5.2.2. Equation 6.6 shows the derivation to find jop from jfab for the mission profile and .alf file modification. The .itf file contains the interconnect resistance data. The interconnect tables in the .itf file are modified based on temperature data from the thermal COMSOL simulations of the mission profile. Three different .itf files were needed to execute the methodology with ICC. The files have the interconnect parameters based on temperature for -40 ◦C, 25 ◦C and 125 ◦C, and are listed in the Appendix Section 11.5. The Synopsys program grdgenxo converts the .itf file to the .tluplus file used by ICC.

257 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

Ea −n kBTfab NORMSINV (Ffab)σ Lfab A50jfabe e = Ea (6.6) Lop −n kBTop NORMSINV (Fop)σ A50jop e e Ea n kBTfab NORMSINV (Ffab)σ jope e = Ea (6.7) n kBTop NORMSINV (Fop)σ jfabe e Ea kBTop NORMSINV (Fop)σ n Lfab e e n jop = Ea × jfab (6.8) L kBT op e fab eNORMSINV (Ffab)σ Ea 1 1 Lfab ( − ) n kB Top Tfab (NORMSINV (Fop)−NORMSINV (Ffab))σ = jfab × e e (6.9) Lop 1 L Ea ( 1 − 1 ) n fab kB Top T (NORMSINV (Fop)−NORMSINV (Ffab))σ jop = jfab × e fab e (6.10) Lop

The algorithm to generate the Electromigration Library (.alf ﬁle in Figure 6.2) for the electromigration tables follows:

Application input: Top, Fop, Lop, Lop for each metal layer M and Via V for each temperature table, T for each metal width W

jop(Top,Fop,Lop,Dop) = 1 " # n Ea 1 1 L − j fab e kB Top−Dop Tfab eσ(NORMSINV (Fop)−NORMSINV (Ffab)) fab Lop

EM Table (M, T, W) = javg = jop

j √avg EM Table (M, T, W) = jrms = r

javg EM Table (M, T, W) = jpeak = r A small portion of the generated .alf ﬁle tables is shown below. The python script created to generate the ﬁle is in the Appendix Section 11.4.

LIBRARY saed32nm_em_1p9m { LAYER M1 { PURPOSE = routing; LIMIT { CURRENT average_limit { MEASUREMENT = average;

258 CHAPTER 6. LIFETIME DRIVEN DESIGN METHODOLOGY

MAX { HEADER { TEMPERATURE { TABLE { -40 25 105 110 125 } } WIDTH { TABLE { 0.05 0.1 0.15 } } } TABLE { 0.1412 0.1035 0.0570 0.0387 0.0155 0.2824 0.2069 0.1140 0.0774 0.0311 0.4236 0.3104 0.1711 0.1161 0.0466 } } }

The design space is explored by using the modiﬁed EM library ﬁles with ICC. The designer of the IC/ASIC can then use the ICC commands to explore the design space as listed below.

– Reroute the violating interconnect wire(s)

– If possible, widen violator wire(s)

– Add buﬀers intersecting the violator wire(s)

– Explore reducing or increasing the supply voltage (Vdd)

– Explore reducing or increasing operating environment temperature

– Explore reducing or increasing (depending on Mission Proﬁle)

– Explore reducing or increasing performance (depending on Mission Proﬁle)

The designer would iterate through the ICC tool until the mission mode requirements are met, with no EM violations.

259 Chapter 7

Results

The results show how our methodology could be used for a microprocessor IC/ASIC design. We iterated through the methodology to explore the design space for tradeoﬀs in performance, lifetimes, and/or operating temperatures.

7.1 Layout

The Amber 25 RTL design was simulated by writing assembly code to ensure the design was correct. The assembly code is listed the Appendix in Section 11.2. Refer to Figure 6.2 for the following discussion. The design synthesized to produce a hierarchical gate level netlist using DC. The ﬁrst steps performed in ICC to layout the design are:

– Floorplan the design, placing the hierarchical blocks.

– Place the gates of the deign

– Insert the clock tree using clocktree synthesis.

Figure 7.1 shows the results of performing these steps. The ﬁgure shows the placement of blocks, instantiation of the gates and the clock tree routing. Figure 7.2 is a close up of the clock tree design in the ICC tool.

260 CHAPTER 7. RESULTS

Figure 7.1: Amber25 design with ﬂoorplanning, gate placement and clock tree synthesized

261 CHAPTER 7. RESULTS

Figure 7.2: Clock tree highlighted in ICC

262 CHAPTER 7. RESULTS

Detailed routing was then performed with ICC. Figure 7.3 shows the layout of the Amber 25 after the detailed routing.

Figure 7.3: Final ICC layout including the signals. Not all layers are shown. The x, y units are in µm

263 CHAPTER 7. RESULTS

Figure 7.4 shows the layout annotated with the major blocks of the Amber 25.

Figure 7.4: Amber 25 layout showing the major blocks of the design

264 CHAPTER 7. RESULTS

Figure 7.5 is the die for an Arm3 processor (22 mm x 23 mm), which was the basis for the Amber 25 (9 mm x 9 mm), and is included for the comparison to the Amber 25 design.

Figure 7.5: Arm3 processor die for comparison to the Amber 25 design

265 CHAPTER 7. RESULTS

7.2 Amber 25 Layout analysis

There are 14,296 combinational gates, 14,319 sequential or Flip Flops (FF) in the Amber 25 design (Total 65,287). Simulations were performed with the ICC and gate level netlist to create the switching activity ﬁles (saif) for the power calculations. ICC has rich TCL (Tool Command Language) commands for reporting details of the design. An example script is shown in the Appendix Section 11.3, which was used to generate the statistics used in Figure 7.6. Figure 7.6 shows the wire count of the Amber 25 design. Note there are no clock wires longer than ≈ 800 µm. This is due to the clocktree topology and the buﬀering performed in clocktree synthesis for timing closure.

Figure 7.6: Amber 25 design wire count (Net Wire Length is in µm)

266 CHAPTER 7. RESULTS

Figure 7.7 shows the average number of signals and clocks per metal layer of the Amber 25 design. The total length of a Net consists of all the wire segments on the diﬀerent layouts for all of the fanout ﬁgures.

Figure 7.7: Amber 25 design average number of signals and clocks per metal layer (Net Wire Length is in µm)

267 CHAPTER 7. RESULTS

Figure 7.8 shows the average number of Vias for the signals and clocks of the Amber 25 design.

Figure 7.8: Amber 25 design average number of Vias for the signals and clocks (Net Wire Length is in µm)

268 CHAPTER 7. RESULTS

Figure 7.9 shows the ICC default toggle estimates, which is used in the power calculation. The toggle rate is based on the number of transition in a 1 ns period. The NetAvg is the signal and clocks toggles combined.

Figure 7.9: Amber 25 design ICC default toggle estimates (Net Wire Length is in µm)

269 CHAPTER 7. RESULTS

Figure 7.10 shows the toggle rate using the saif (switching activity interface file) simulations with the cache sized at 64. These toggle estimates were used in the power calculation. Note the toggle rate from the simulations is 200 times less the ICC default toggle rate in Figure 7.9. The ICC default toggle rate gives a very high (pessimistic) power calculation, which will demonstrated in the figures below. This illustrates the importance of performing simulations to estimate power, and the use of the saif in the methodology for calculating the temperature for performance versus lifetime tradeoffs. Again, the toggle rate is based on the number of transition in a 1 ns period, and the NetAvg is the signal and clocks toggles combined.

Figure 7.10: Amber 25 design toggle rates with a cache size of 64 (Net Wire Length is in µm)

270 CHAPTER 7. RESULTS

Figure 7.11 shows the toggle rate using the saif (switching activity interface file) simulations with the cache sized at 128. Note that the toggle rates are similar to the cache size of 64. This is included to show that doubling the size of the cache in this design does not have a significant effect on the number of signals switching, therefore will have minimal impact on the power calculations.

Figure 7.11: Amber 25 design toggle rates with a cache size of 128 (Net Wire Length is in µm)

271 CHAPTER 7. RESULTS

Figure 7.12 shows the power in the Amber 25 design using the default ICC toggle rates for the calculations. The AvgPwr is the average power of signals and clocks.

Figure 7.12: Amber 25 design Power using the ICC default toggle rates (Net Wire Length is in µm)

272 CHAPTER 7. RESULTS

Figure 7.13 shows the power with the cache sized at 128. This figure shows that using the default ICC toggle rates will result in a very pessimistic power calculation, which affects the temperature. This will result in a pessimistic performance versus lifetime tradeoff. The AvgPwr is the average power of signal and clocks.

Figure 7.13: Amber 25 design Power with a cache size of 128 (Net Wire Length is in µm)

273 CHAPTER 7. RESULTS

Figure 7.14 shows the maximum resistance for the signals and clocks in the design. The MaxRes is the average of the clock and signal resistance. The ﬁgure shows that the resistance increases as expected.

Figure 7.14: Resistance for signal and clocks (Net Wire Length is in µm)

274 CHAPTER 7. RESULTS

Figure 7.15 shows the maximum capacitance for the signals and clocks in the design. The MaxCap is the average of the clock and signal capacitance.

Figure 7.15: Capacitance for signal and clocks (Net Wire Length is in µm)

275 CHAPTER 7. RESULTS

Figure 7.16 shows the maximum fanout of the signals and clocks in the design.

Figure 7.16: Fanout of signal and clocks (Net Wire Length is in µm)

276 CHAPTER 7. RESULTS

7.3 EM analysis

After the detailed routing was completed, EM analysis was performed in ICC. Figure 7.17 shows how the net segments violations are highlighted with a yellow X in ICC.

Figure 7.17: ICC layout showing the EM violations (yellow X’s)

277 CHAPTER 7. RESULTS

The lifetime is calculated as discussed in Section 6.3. The equation to calculate lifetime is shown in Equation 7.1.

n J Ea 1 − 1 fab kB Top Tfab σ(NORMSINV (fop)−NORMSINV (ffab)) Lop = Lfab × n × e × e (7.1) Jop J n fab σ(NORMSINV (fop)−NORMSINV (ffab)) = Lfab n × F (Top) × e (7.2) Jop

= F (Jop) × F (Top) × F (fop) (7.3)

where Lfab is the lifetime of the speciﬁed by the Fab’s EM speciﬁcation, Lop is the operational lifetime, Jfab is the Fab lifetime current density, Jop is the current density

◦ in operation, Tfab is the Fab’s lifetime temperature (110 C), Top is the operation temperature, ffab is the Fab failure rate (0.1%) and fop is the operation acceptable failure rate. F (jop) is the acceleration factor for current density, F (Top) is the acceleration for temperature and F (fop) is operational failure rate function. For the Fab (28/32nm PDK), operating conditions of a for a 10 year failure rate of 0.1 %, the lifetime metal layer current density of J in library and lifetime temperature

◦ of 110 C, Equation 7.1 would be 1 (F (Jop) = 1, F(Top) = 1 and F (fop) = 1. In Section 6.3 it was shown that from -40 ◦C to 25 ◦C is in the linear function of the acceleration factors, and from above 25 ◦C is an exponential function of the acceleration factors. Our methodology modified the libraries for ICC and the following steps can be performed for the tradeoff analysis. The mission profile was a performance target of 1 GHZ (1 GHZ clock - 1ns period) and the layout is fixed. The steps used in ICC to perform the performance tradeoff:

– Perform EM analysis to ﬁnd the nets that have EM violations

– Report the switching power

– Change the clock frequency to ﬁx EM violation

278 CHAPTER 7. RESULTS

– Report the switching power

– Compute lifetime. Iterate until target is met

The steps used in ICC to perform the current density tradeoﬀ (F (J)) by decreasing

or increasing Vdd:

– Perform EM analysis to ﬁnd the nets that have EM violations

– Report the switching power

– Iterate runs of ICC with Vdd over the Vdd operation range, report switching power

– Compute lifetime. Iterate until target is met

The steps used in ICC to perform the tradeoﬀ by temperature (F (T )):

– Perform EM analysis to ﬁnd the nets that have EM violations

– Report the switching power

– Iterate runs of ICC for the temperatures ranges, reporting the switch power

– Compute lifetime. Iterate until target is met

The steps used in ICC to perform the tradeoﬀ of the acceptable failure rate

(F(fop)):

– Perform EM analysis to ﬁnd the nets that have EM violations

– Report the switching power

– Iterate runs of ICC with tf for the acceptable failure rate, report switching power

– Compute lifetime. Iterate until target is metj

279 CHAPTER 7. RESULTS

Table 7.1 shows the maximum performance obtained for the design. The table

◦ shows the performance. Cost and Lifetime for three diﬀerent Vdd for 25 C. For

example for a Vdd or 1.05 V, the max clock period was 2.90ns or 345 MHz, the cost was for 0.1% failures, which resulted in Lifetime of 5 years.

Table 7.1: Design Exploration (Max performance - meets timing)

Table 7.2 is the second iteration, where we increase the clock period by 1 ns. For

Vdd of 1.05 V, the performance was reduced to 256 MHz, and the Lifetime was only increased by 0.8 years (5.8 years).

Table 7.2: Design Exploration (Increment the clock period by 1 ns)

Table 7.3 is the result of the iterations to achieve the goal of a 15 year Lifetime.

From the table the performance reached was 38 MHz (clock period of 26ns) for Vdd of

1.05 V. For a Vdd 0.85 V and 0.78 V the performance would be increased to 71 MHz and 95 MHz respectively. Table 7.4 show the tradeoﬀ in Cost if we allow for a 1.0% failure rate. The Lifetime is increased to 22 years.

280 CHAPTER 7. RESULTS

Table 7.3: Design Exploration (Iterate until 15 year target met)

Table 7.4: Design Exploration (Iterate until 15 year target met)

Table 7.5 is the summary for a target Lifetime of 15 years with 0.1% failure for the three Vdd voltages. The performance is 26 MHz, 14 MHz and 10.5 MHz. The Cell power is the power due to the IC/ASIC standard cells. The net power is the power due to the RC of the interconnect wires. The leakage power is the leakage of the standard cells. As can be seen from the table the leakage power dominates. This is due to the Synopsys 28/32nm PDK. The table also shows the tradeoﬀs for Lifetime if the product the IC/ASIC will be used in can tolerate a 1% failure rate.

Table 7.5: Design Exploration (Power 15 year target met)

281 Chapter 8

Summary

The reliability engineering principals and the challenges the IC/ASIC fabrication industry face when creating a new process node were reviewed. The five wearout mechanisms (NBTI, PBTI, HCI, TDDB and Electromigration) were shown to determine the lifetime of the IC/ASIC. As the transistors shrink in each successive process node, the interconnect wires also had to shrink. The limiting factor for lifetime was shown to be the interconnect wires due to Electromigration. At the 150nm process node the IC/ASIC industry set the design goal for the lifetime of the interconnect wires to be 10 years at 110 ◦C. Intel processor design goal is 10 years at 100 ◦C. The Electromigration tradeoffs for the design of the interconnect wires are size, the maximum current allowed in the interconnect and the operating temperature. The wire size wants to be as small as possible to follow Moore’s Law (double the transistor density every 18 months). The current in the interconnects determines the performance of the IC/ASIC. The more current in the wire the better the performance of the IC/ASIC. But this causes an increase in power being dissipated, which affects the operating temperature. The purpose of this research was to develop a design space exploration method and tools for IC/ASICs driven by performance, cost and lifetime based on a mission profile.

282 CHAPTER 8. SUMMARY

The typical mission profile for a consumer product (cell phone) is different than a server or a safety design (avionics, automotive). A cell phone operating temperature environment is approximately 0 to 40 ◦C, a server approximately 0 to 50 ◦C and a safety design -40 to 70 ◦C. These environmental profiles affect the temperatures in the IC/ASICs. Since the lifetime of the IC/ASIC is due to the wearout mechanism of Electromi- gration, the proposed approach applies to two scenarios in practice. First, increasing the lifetime of ASIC while keeping performance reduction within a threshold. The second is reducing the lifetime, which incurs increased performance. The first scenario applies to safety products (avionics, automotive), while the second to higher performance that are frequently replaced (cell phones). The exploration method is based on solid reliability background analysis that allows the designer to make the tradeoffs between performance, power, lifetimes and costs in the design of an IC/ASIC to meet the product objectives. The methodology developed used industry IC/ASIC design tools form Synop- sys Incorporated. Extensive research was done looking at the the parameters in the libraries used by the major IC/ASIC fabricators for Electromigration, to ensure realistic results were obtained. The methodology was verified using a representative design from OpenCores [OpenCores, 2017]. hspice simulations were performed and compared to the results from the layout tools to ensure correlations with the methodology. The tradeoffs were performed by using thermal simulations based on the mission profile, and feed to scripts that modified the input files used by the layout tools to design, analyze and explore the design space. Plots were created from the results of the methodology to show to tradeoffs for performance versus lifetimes for the representative design.

283 Chapter 9

Discussion

The contributions of this research are:

– Developed a design space exploration tool suite, which trades oﬀ cost, performance, power and lifetime

– Improves the IC Lifetime at the expense of Performance for critical applications

– Increases the Performance at expense of Lifetime for commercial applications

– In depth study of the reliability issues of IC/ASICs which included:

– Comprehensive review of the industry standards for the reliability of IC/ASICs

– Analysis of the state of the art for Electromigration

– Electromigration analysis based on Black’s Law

– Developed a coordination tool suite (Black’s Law modiﬁcation) along with commercial tools, which coordinates the design ﬂow

– Tool suite consists of our own development analysis and tradeoﬀ platform

– Design space of the tradeoﬀs for performance, power, lifetime and cost

284 CHAPTER 9. DISCUSSION

– Built a library model based on a 28/32nm PDK for the methodology

– Validated the library model using hspice

– Developed an IC/ASIC design from public domain RTL microprocessor FPGA design

– Lifetime as a design consideration

– Applied the methodology to a representative microprocessor design and obtained the design tradeoﬀ results

– Methodology to explore the design space of the tradeoﬀs for performance, power lifetime and cost.

– Built a library model based on a 28/32nm PDK for the methodology.

– Validated the library model using hspice.

– Applied the model to a representative microprocessor design.

The design goals of products and their mission profile and design goals (performance, power, reliability, cost, operating environment) are different for consumer, servers, automotive, medical, industrial, avionics, and military. The Design Space Exploration Methodology allows a designer to explore the options available to meet the design goals of the product design that the IC/ASIC is used in. The methodology can also be used to verify the reliability of an IC/ASIC for safety certifications. Future research would be to apply our methodology to a Fin FET based process (14nm or 7nm). Our methodology can be extended, to add the capability for ICC to reroute specific nets for the EM tradeoffs. The analysis of the new materials that are needed to replace Cu below the 5 or 7nm process nodes due to EM is required. AI/Machine learning techniques to design exploration

285 CHAPTER 9. DISCUSSION

Co and Ru have been proposed to replace Cu below 5nm processes ([Kelly et al., 2016],

[Zhang et al., 2016a]). Intel has moved to Co in M1 and M2 in their 10nm process [Jones, 2018]. How these new materials eﬀect the reliability and lifetimes of IC/ASICs needs to be studied. The roadmap for the shrinking of the IC/ASICs designs with Si is predicted by the ITRS to end in 2030 [IRDS, 2016]. Following the closure of the ITRS activities in 2015, the Heterogeneous Integration Roadmap (HIR) committee was created. This committee is sponsored by the IEEE Electronics Packaging Society (EPS), SEMI, IEEE Electron Devices Society (EDS), IEEE Photonics Society and the ASME EPPD Division. Multiple die from multiple process nodes will be placed in the same package [IRDS, 2016], [Roy et al., 2016]. EM analysis will need to perform on the individual die, with the considerations of the thermal self heating of the other die in the package.

286 Chapter 10

Acronyms

Table 10.1: Acronyms

Acronyms

AFM Atomic Force Microscopy

ALD Atomic Layer Deposition

ALF Advanced Library Format

AF Acceleration Factor

α Inter Metal Dielectric used interchangeably with TC and TCR

287 CHAPTER 10. ACRONYMS

Acronyms

ASIC Application Speciﬁc Integrated Circuit

ASIL Automotive Safety Integration Level

astm ASTM American Society for Testing and Materials

BEOL Back End of Line

CDF Cumulative Density Function

CDP Copper Damascene Process

CLT Central Limit Theorem

CMOS Complementary Metal-Oxide Semiconductor

CMP Chemical Mechanical Polishing

CNT Carbon Nano Tube

288 CHAPTER 10. ACRONYMS

Acronyms

Co Cobalt

COD Carbon Doped Oxide

COTS Commercial Oﬀ The Shelf

COF Covalent Organic Framework

COTS Chemical Vapor Deposition

CoWP Cobalt Tungsten Phosphide

DIBL Drain Induce Barrier Lowering

DoF Depth of Focus

DPT Double Patterning Techniques

ECD Electrochemical deposition

289 CHAPTER 10. ACRONYMS

Acronyms

EM Electromigration

EOT Electrical Oxide Thickness

Fab Fabrication

FAV Fully Aligned Via

FEP Front end Process

FEOL Front End of Line

FIT 1 FIT = 1 failure in 109 device-hours

F-N Fowler-Nordheim

f(t) Probability Density Function

F(t) Culumative Distribution Function or Cumulative failure probability

290 CHAPTER 10. ACRONYMS

Acronyms

GCD Greatest Common Divisor

HCI Hot Carrier Injection

HIR Heterogeneous Integration Roadmap

HRTEM High Resolution Transmission Electron Microscopy

HTOL High Temperature Operating Life

IC Integrated Circuit

ICC Integrated Circuit Compiler

IEC International Electrotechnical Commission

IEEE Institute of Electrical and Electronics Engineers

ILD Inter Layer Dielectric

291 CHAPTER 10. ACRONYMS

Acronyms

IMD Inter Metal Dielectric

ISO International Organization for Standardization

itf interconnect technology ﬁle

ITRS International Technology Roadmap for Semiconductors

j or J Current Density

JEDEC Joint Electron Devices and Engineering Council

LER Line Edge Roughness

MASTAR ITRS Model for Assessment of CMOS Technologies And Roadmaps

MDP Multiple Double Patterning

MEOL Middle End Of Line

292 CHAPTER 10. ACRONYMS

Acronyms

MRDL Metal Redistribution Layer

MOL Middle Of Line

MTTF Mean Time To Failure

MOCVD Metal Organic Vapor Deposition

MOF Metal Organic Framework

M-O Metal Oxygen

NBTI Negative Bias Temperature Instability

OPC Optical Proximity Correction

PDF Probability Density Function or Probability Distribution Function

PDK Process Design Kit

293 CHAPTER 10. ACRONYMS

Acronyms

PEM Photoelectron Microscopy

PECVD Plasma Enhanced Chemical Vapor Deposition

PBTI Positive Bias Temperature Instability

PPM Parts Per Million - 1 failure in 106 parts

PVD Physical (Plasma) Vapor Deposition

PVT Process, Voltage, Temperature

QCA Quatum Cellular Automa

RDR Restrictive Design Rules

R(t) Reliability Function

Ru Ruthenium

294 CHAPTER 10. ACRONYMS

Acronyms

SADP Self Aligned Double Patterning

SAQP Self Aligned Quad Patterning

saif switching activity interface ﬁle

SAV Self aligned Via

SEM Scanning Electron Microscopy

SIL Safety Integration Level

SOI Silicon on Insulator

SPC Statistical Process Control

SS Sub-threshold Swing

SW Software

295 CHAPTER 10. ACRONYMS

Acronyms

TC Temperature Coeﬃcient used interchangeably with TCR and α

TCR Inter Metal Dielectric used interchangeably with TC and α

TCL Tool Command Language

TDDB Time Dependent Dielectric Breakdown

TEM Transmission Electron Microscope

TTF Time To Failure

tf Time To Failure

tCoSFB Through-Cobalt Self Forming Barrier

XPR Cross Polarization Ratio

296 Chapter 11

Appendix

11.1 Tool Versions

Below are the tool versions used for the methodology. Again, I would like to thank Synopsys Incorporated for their support of the Case Computer Engineering Depart- ment by allowing the use of their ASIC tool suite, which made this work possible.

297 CHAPTER 11. APPENDIX

Table 11.1: Tool Versions

Tool Version

Simulation - VCS I-2014.03

Synthesis - DC F 2011.09-SP3 for Linux – Jan 26, 2012

Layout - ICC F-2011.09-ICC-SP3 for Linux – Jan 23, 2012

Scripting - Python 2.7 for Linux

Parasitic Extraction - StarXtract F-2011.12-SP2

Spice - hspice L-2016.06-SP2-1 linux64 (build id: 4344973)

Thermal - COMSOL Multiphysics 3.5a - 3.5.0.603

IC Library - SAED32 EDK Rev 1.0.2 2012

Design - Amber 25 OpenCores v2.1 March 2015

Assembler - VASM Retargetable Assembler 2018

298 CHAPTER 11. APPENDIX

11.2 Amber 25 Testbench Source

Below is the testbench used to exercise the Amber 25 microprocessor in the design methodology. module tb #( parameter MEM_DATA_SIZE =8192, // = 2048, parameter SORT_SIZE =2, //=128, // =64 (129702 clocks, 28263 clocks cache on) //=16 (11514 clocks, 2834 clocks cache on), parameter MAX_CLOCKS =1903300, parameter CACHE_ON =1 ) // =1 ( );

// SORT_SIZE = 2 ( 1070 clocks, 493 clocks cache on) // SORT_SIZE = 4 ( 1184 clocks, 684 clocks cache on) // SORT_SIZE = 8 ( 4118 clocks, 1197 clocks cache on) // SORT_SIZE = 16 ( 11514 clocks, 2834 clocks cache on) // SORT_SIZE = 32 ( 35768 clocks, 8143 clocks cache on) // SORT_SIZE = 64 (129702 clocks, 28263 clocks cache on) // SORT SIZE =128 ( clocks, 103598 clocks cache on, // Sim Time: 20719850000 ps, Run Time: 6.42 hours)

reg tb_clk; reg tb_reset; wire tb_rdy; reg tb_done;

// Wishbone Master I/F wire [31:0] o_wb_adr; wire [15:0] o_wb_sel; wire o_wb_we; wire [127:0] o_wb_dat; wire o_wb_cyc; wire o_wb_stb;

reg testfail; reg [31:0] clk_count = ’d0; reg [31:0] i; reg [31:0] i_data;

reg mem_ack; reg mem_err; reg[1:0] mem_state; reg[127:0] mem_read; reg[31:0] mem_addr;

/* stack top, ldr sp,stack; see below "stack: .long 8192" */ reg[31:0] mem_data[0:MEM_DATA_SIZE-1]; integer wordindx;

initial begin testfail = 1’d0; end

299 CHAPTER 11. APPENDIX

// 200 MHz clock #2500 // 400 MHz clock #938 // 25 MHz clock #20000 initial begin // Warning, only prints if anything changes! // it is not a sequential time stepper //$monitor($time," %t clk=%b inst=%032h r1=%032h r2=%032h r3=%032h r4=%032h // windx=%032h we=%01b stb=%01b ack=%01b // wbaddr=%08h i_wb_dat=%032h o_wb_dat=%032h",

//tb.u_a25_core.execute_iaddress tb.u_a25_core.execute_daddress

if (1’b0) begin // shows all glitches $monitor(" %04d clk=%b stall=%01b f=%01b e=%01b m=%01b c=%01b expc=%032h inst=%032h reg=%032h we=%01b stb=%01b ack=%01b wb@=%08h i_wb_dat=%032h o_wb_dat=%032h", i, tb_clk, tb.u_a25_core.u_decode.i_core_stall, tb.u_a25_core.u_fetch.o_fetch_stall, tb.u_a25_core.u_execute.o_exec_stall, tb.u_a25_core.u_mem.o_mem_stall, tb.u_a25_core.u_fetch.cache_stall, tb.u_a25_core.u_execute.u_register_bank.o_pc, tb.u_a25_core.fetch_instruction, tb.u_a25_core.u_execute.u_register_bank.i_reg, o_wb_we, o_wb_stb, mem_ack, o_wb_adr, mem_read, o_wb_dat);

end // If you do not use the $read_lib_saif command, the simulator registers // all internal nets for monitoring by default. // $set_gate_level_monitoring("on"); same as no // $read_lib_saif("../saed32hvt_tt1p05v25c.saif"); // icc_shell> lib2saif -out saed32hvt_tt1p05v25c.saif // /space/solvnet_32nm/SAED32_HVT_EDK/lib/stdcell_hvt/db_nldm/saed32hvt_tt1p05v25c.db $read_lib_saif("../saed32hvt_tt1p05v25c.saif"); // forward saif files $read_lib_saif("../saed32lvt_tt1p05v25c.saif"); $read_lib_saif("../saed32rvt_tt1p05v25c.saif"); $set_gate_level_monitoring("on"); $set_toggle_region(tb.u_a25_core); $toggle_start();

tb_done = 1’b0; tb_clk = 1’b0; #50 /* n=2 no cache = 758 */ /* n=4 no cache = 1364 */ /* n=8 no cache = 3023 */ /* n=16 no cache = 8493 */ /* n=32 no cache = 26416 */ /* i<= 191318 for 64 word sort */ /* i<= 711798 for 128 word sort */

300 CHAPTER 11. APPENDIX

/* i<=2766082 for 256 word sort */ for (i=0; i

//hide glitches $display(" %04d clk=%b stall=%01b f=%01b e=%01b m=%01b expc=%032h ce=%01b c=%01b inst=%032h cout=%032h reg=%032h we=%01b stb=%01b ack=%01b wb@=%08h i_wb_dat=%032h o_wb_dat=%032h", i, tb_clk, tb.u_a25_core.u_decode.i_core_stall, tb.u_a25_core.u_fetch.o_fetch_stall, tb.u_a25_core.u_execute.o_exec_stall, tb.u_a25_core.u_mem.o_mem_stall, tb.u_a25_core.u_execute.u_register_bank.o_pc, tb.u_a25_core.u_fetch.i_cache_enable, tb.u_a25_core.u_fetch.cache_stall, tb.u_a25_core.fetch_instruction, tb.u_a25_core.u_fetch.cache_read_data128, tb.u_a25_core.u_execute.u_register_bank.i_reg, o_wb_we, o_wb_stb, mem_ack, o_wb_adr, mem_read, o_wb_dat); tb_clk = 1’b1; #100; tb_clk = 1’b0; if (i == 20) tb_reset = 1’d0; // start clock during reset mode #100; end $toggle_stop(); // backward saif file $toggle_report("./a25_tb_icc_vcs.saif", 1.0e-9, "tb.u_a25_core");

for (i=0; i<2048; i=i+1) begin if ((mem_data[i] !== 32’hxxxxxxxx)) begin $display("mem[%09d %032hh]=%032h", i*4, i*4, mem_data[i]); end end $display(" mem_data size=%0d", MEM_DATA_SIZE); end initial begin /* 0x00 main: */ mem_data[ 0] = 32’hea000006; /* 0x00 b test ; interrupt vector - reset*/ mem_data[ 1] = 32’heafffffc; /* 0x04 b ain-4 ; interrupt vector - undefined instructions*/ mem_data[ 2] = 32’heafffffa; /* 0x08 b main-8 ; interrupt vector - SWI*/ mem_data[ 3] = 32’heafffff8; /* 0x0c b main-12 ; interrupt vector - prefetch abort */ mem_data[ 4] = 32’heafffff6; /* 0x10 b main-16 ; interrupt vector - data abort */ mem_data[ 5] = 32’heafffff4; /* 0x14 b main-20 ; interrupt vector - address acception */ mem_data[ 6] = 32’heafffff2; /* 0x18 b main-24 ; interrupt vector - IRQ */ mem_data[ 7] = 32’heafffff0; /* 0x1c b main-28 ; interrupt vector - FIRQ */

/* test: */ mem_data[ 8] = 32’he3a04044; /* 0x20 mov r4,#0x44 ; test for stack restore*/ mem_data[ 9] = 32’he3a05055; /* 0x24 mov r5,#0x55 */ mem_data[10] = 32’he3a06066; /* 0x28 mov r6,#0x66 */ mem_data[11] = 32’he3a07077; /* 0x2c mov r7,#0x77 */ mem_data[12] = 32’he3a08088; /* 0x30 mov r8,#0x88 */ mem_data[13] = 32’hEB000056; /* 0x34 bl cache ; enable/disable cache */

301 CHAPTER 11. APPENDIX

mem_data[14] = 32’he59f003c; /* 0x38 ldr r0,array ; p = &array[0] */ mem_data[15] = 32’he59f103c; /* 0x3c ldr r1,asize ; N = 16*/ mem_data[16] = 32’he59f203c; /* 0x40 ldr r2,rseed ; rseed = 1; */ mem_data[17] = 32’hEB00000F; /* 0x44 bl rand ; randarray(p, N, rseed); generate random sort values */ mem_data[18] = 32’he1a04000; /* 0x48 mov r4,r0 ; parity checksum */ mem_data[19] = 32’he1a05001; /* 0x4c mov r5,r1 ; lower arithmetic checksum*/ mem_data[20] = 32’he1a06002; /* 0x50 mov r6,r2 ; upper arithmetic checksum*/ mem_data[21] = 32’he59f0020; /* 0x54 ldr r0,array ; p = &array[0] */ mem_data[22] = 32’he59f1020; /* 0x58 ldr r1,asize ; N = 16*/ mem_data[23] = 32’heb00001e; /* 0x5c bl bsort ; bsort(); sort array */ mem_data[24] = 32’hE59F0014; /* 0x60 ldr r0,array ; p = &array[0]*/ mem_data[25] = 32’he59f1014; /* 0x64 ldr r1,asize ; N = 16 */ mem_data[26] = 32’he1a02004; /* 0x68 mov r2,r4 ; parity checksum */ mem_data[27] = 32’he1a03005; /* 0x6c mov r3,r5 ; lower arithmetic checksum */ mem_data[28] = 32’he1a04006; /* 0x70 mov r4,r6 ; upper arithmetic checksum */ mem_data[29] = 32’heb00002c; /* 0x74 bl cksort ; verify sort checksum is still good */ mem_data[30] = 32’hef00000c; /* 0x78 swi 12 ; done, trapped by simulator */ mem_data[31] = 32’h00000400; /* 0x7c array: .long 1024 ; &array[0], easy to change binary in simulator */ mem_data[32] = SORT_SIZE; /* 0x80 asize: .long 16 ; =10h, 256=100h */ mem_data[33] = 32’h00000001; /* 0x84 rseed: .long 1 ; random seed value */

/* rand: */ mem_data[34] = 32’he92d01f0; /* 0x88 stmfd sp!, {r4,r5,r6,r7,r8} ; push stack */ mem_data[35] = 32’he2003000; /* 0x8c and r3,r0,#0 ; =0 parity checksum, insensitive to order */ mem_data[36] = 32’he1c14001; /* 0x90 bic r4,r1,r1 ; =0 lower arithmetic checksum, insensitive to order */ mem_data[37] = 32’he1835004; /* 0x94 orr r5,r3,r4 ; =0 upper arithmetic checksum, insensitive to order */ mem_data[38] = 32’he59f6034; /* 0x98 ldr r6,rand_b ; =1103515245 */ mem_data[39] = 32’he59f7034; /* 0x9c ldr r7,rand_c ; =12345 */

/* rand1: */ mem_data[40] = 32’he0080692; /* 0xa0 mul r8,r2,r6 ; r = rseed * 1103515245 */ mem_data[41] = 32’he0882007; /* 0xa4 add r2,r8,r7 ; rseed = r + 12345 */ mem_data[42] = 32’he4802004; /* 0xa8 str r2,[r0],#sizeofint ; *p++ = rseed */ mem_data[43] = 32’he0233002; /* 0xac eor r3,r3,r2 ; parity checksum ^= rseed */ mem_data[44] = 32’he0944002; /* 0xb0 adds r4,r4,r2 ; arithmetic checksum += rseed */ mem_data[45] = 32’he2a55000; /* 0xb4 adc r5,r5,#0 */ mem_data[46] = 32’he2511001; /* 0xb8 subs r1,r1,#1 ; N-- != 0 */ mem_data[47] = 32’h1afffff7; /* 0xbc bne rand1 ; loop */ mem_data[48] = 32’he1a00003; /* 0xc0 mov r0,r3 ; return parity checksum */ mem_data[49] = 32’he1a01004; /* 0xc4 mov r1,r4 ; return lower arithmetic checksum */ mem_data[50] = 32’he1a02005; /* 0xc8 mov r2,r5 ; return upper arithmetic checksum */ mem_data[51] = 32’he8bd01f0; /* 0xcc ldmfd sp!, {r4,r5,r6,r7,r8} ; pop stack */ mem_data[52] = 32’he1a0f00e; /* 0xd0 mov pc,lr ; return */ mem_data[53] = 32’h41c64e6d; /* 0xd4 rand_b: .long 1103515245 ; -align on asm command line */ mem_data[54] = 32’h00003039; /* 0xd8 rand_c: .long 12345 */

/* bsort: */ mem_data[55] = 32’he92d03f0; /* 0x0dc stmfd sp!, {r4-r9} ; push stack */ mem_data[56] = 32’he0807101; /* 0x0e0 add r7,r0,r1,LSL #2 ; r7=&array + N*4 = &array[N]*/ mem_data[57] = 32’he2476004; /* 0x0e4 sub r6,r7,#sizeofint ; r6=&array[N-1]*/

302 CHAPTER 11. APPENDIX

mem_data[58] = 32’he2404004; /* 0x0e8 sub r4,r0,#sizeofint ; &array[i-1] => &array[-1]*/ /* bsortfori: */ mem_data[59] = 32’he2844004; /* 0x0ec add r4,r4,#sizeofint ; i++; &array[++i] => &array[0], &array[1], &array[2], ...*/ mem_data[60] = 32’he1540006; /* 0x0f0 cmp r4,r6 ; if i (N-1)-i => N-1-0, N-1-1, N-1-2, ...*/ mem_data[63] = 32’he2405004; /* 0x0fc sub r5,r0,#sizeofint ; j=-1; &array[j-1] */ /* bsortforj: */ mem_data[64] = 32’he2855004; /* 0x100 add r5,r5,#sizeofint ; j++; j=0, 1, 2, ... */ mem_data[65] = 32’he1550007; /* 0x104 cmp r5,r7 ; if (j < (N-1)-i) then */ mem_data[66] = 32’haafffff7; /* 0x108 bge bsortfori */ mem_data[67] = 32’he8950300; /* 0x10c ldmia r5, {r8, r9} ; array[j], array[j+1] */ mem_data[68] = 32’he1580009; /* 0x110 cmp r8,r9 ; if (array[j] > array[j+1]) then */ mem_data[69] = 32’h9AFFFFF9; /* 0x114 bls bsortforj ; unsigned => bls, signed sort => ble */ mem_data[70] = 32’he5859000; /* 0x118 str r9,[r5] ; swap array[j], array[j+1] */ mem_data[71] = 32’he5858004; /* 0x11c str r8,[r5, #sizeofint] */ mem_data[72] = 32’heafffff6; /* 0x120 b bsortforj */ /* bsortend: */ mem_data[73] = 32’he8bd03f0; /* 0x124 ldmfd sp!, {r4-r9} ; pop stack*/ mem_data[74] = 32’he1a0f00e; /* 0x128 mov pc,lr ; return */ mem_data[75] = 32’he1a00000; /* cksort: nop ; push stack */ mem_data[76] = 32’he1a05001; /* mov r5,r1 ; N */ mem_data[77] = 32’he3a01001; /* mov r1,#1 ; i=1 */ mem_data[78] = 32’he4909004; /* ldr r9,[r0],#sizeofint ; tmp = a[j] */ mem_data[79] = 32’he1a06009; /* mov r6,r9 ; initial parity checksum */ mem_data[80] = 32’he1a07009; /* mov r7,r9 ; initial lower arithmetic checksum */ mem_data[81] = 32’he3a08000; /* mov r8,#0 ; initial upper arithmetic checksum */ mem_data[82] = 32’he490a004; /* cksort1: ldr r10,[r0],#sizeofint ; a[j+1] */ mem_data[83] = 32’he159000a; /* cmp r9,r10 ; if (a[j] <= a[j+1]) */ mem_data[84] = 32’h8a00000c; /* bhi cksort2 ; unsigned => bhi, signed sort => bgt; not sorted, return address r0, r1 = nth word */ mem_data[85] = 32’he026600a; /* eor r6,r6,r10 ; parity checksum ^= a[i] */ mem_data[86] = 32’he097700a; /* adds r7,r7,r10 ; lower arithmetic checksum += a[i] */ mem_data[87] = 32’he2a88000; /* adc r8,r8,#0 ; upper arithmetic checksum += carry */ mem_data[88] = 32’he1a0900a; /* mov r9,r10 ; shift value, tmp = a[j+1] */ mem_data[89] = 32’he2811001; /* add r1,r1,#1 ; i++ */ mem_data[90] = 32’he1510005; /* cmp r1,r5 ; i+1 < N */ mem_data[91] = 32’hbafffff5; /* blt cksort1 ; */ mem_data[92] = 32’he3a00000; /* mov r0,#0 ; zero address => sorted, now checksum */ mem_data[93] = 32’he0229006; /* eor r9,r2,r6 ; mash parity checksum */ mem_data[94] = 32’he023a007; /* eor r10,r3,r7 ; mash lower arithmetic checksum new - old */ mem_data[95] = 32’he024b008; /* eor r11,r4,r8 ; mash upper arithmetic checksum new - old */ mem_data[96] = 32’he029c00a; /* eor r12,r9,r10 ; mash lower ^ upper */ mem_data[97] = 32’he02cc00b; /* eor r12,r12,r11 */ /* cksort2: */ mem_data[98] = 32’hE92DFFFF; /* stmfd sp!, {r0-r15} ; DEBUG: push stack for dc_netlist testbench to show registers*/ mem_data[99] = 32’he1a0f00e; /* mov pc,lr ; return, r0=address, r1=index, r2=parity r3=lower, r4=upper, r5=N, r6=parity, r7=lower */ mem_data[100]= MEM_DATA_SIZE; /* stack: .long 8192 ; stack address, don’t forget to set it in the test bench */

303 CHAPTER 11. APPENDIX

mem_data[101]= 32’hE51FD00C; /* 0x194 ldr sp,stack ; setup stack */ mem_data[102]= 32’hE3E00000; /* 0x198 mov r0, #0xffffffff ; */ mem_data[103]= 32’hEE030F10; /* 0x19c mcr p15,0,r0,c3,c0,0 ; cacheable area */ mem_data[104]= 32’hE3A00000 | CACHE_ON; /* 0x1a0 mov r0,#1 ; DEBUG HERE: cache =0 off, =1 on */ mem_data[105]= 32’hEE020F10; /* 0x1a4 mcr p15,0,r0,c2,c0,0 ; cache enable */ mem_data[106]= 32’hE1A0F00E; /* 0x1a8 mov pc,lr */ mem_data[107]= 32’he1a00000; /* 0x1ac nop - processor gets confused if it prefetches 32’hxxxxxxxx */ mem_data[108]= 32’he1a00000; /* 0x1b0 nop - processor gets confused if it prefetches 32’hxxxxxxxx */ mem_data[109]= 32’he1a00000; /* nop - processor gets confused if it prefetches 32’hxxxxxxxx */ mem_data[110]= 32’he1a00000; /* nop - processor gets confused if it prefetches 32’hxxxxxxxx */ mem_data[111]= 32’he1a00000; /* nop - processor gets confused if it prefetches 32’hxxxxxxxx */

tb_reset = 1’d1; mem_ack = 1’bx; mem_err = 1’bx; mem_state = 2’bxx; end assign tb_rdy = ~tb_reset; always @(posedge tb_clk) begin if (tb_rdy) begin if (mem_state == 2’b00) begin if (o_wb_stb) begin mem_state <= 2’b01; mem_addr <= o_wb_adr;

if (o_wb_adr < MEM_DATA_SIZE) begin // 1024 .. 2047 wordindx = o_wb_adr[31:2]; // o_wb_adr[31:0]=byte address! if (o_wb_we) begin $display("RAM store mem[%09d %032h]=%032h", o_wb_adr, o_wb_adr, o_wb_dat[31:0]); mem_data[wordindx] = o_wb_dat[31:0]; // o_wb_dat[127:0]=four words, 16 bytes! mem_read <= 128’hDDDDDDDD_CCCCCCCC_BBBBBBBB_AAAAAAAA; end else begin $display("RAM read mem[%09d %032h]=%032h", o_wb_adr, o_wb_adr, mem_data[wordindx]); wordindx = { o_wb_adr[31:4], 2’b00 }; //mask word //case (o_wb_adr[1:0]) //may cache the whole line of four words?! mem_read <= { mem_data[wordindx+3], mem_data[wordindx+2], mem_data[wordindx+1], mem_data[wordindx+0] }; end end else begin $display("illegal RAM data address = %032h", o_wb_adr); tb_done = 1’b1; end mem_ack <= 1’b0; end end else if (mem_state == 2’b01) begin mem_state <= 2’b10; mem_ack <= 1’b1; wordindx = 255; end else if (mem_state == 2’b10) begin mem_state <= 2’b00;

304 CHAPTER 11. APPENDIX

mem_ack <= 1’b0; wordindx = 255; end end else begin mem_state <= 2’b00; mem_ack <= 1’b0; mem_err <= 1’b0; end end

a25_core u_a25_core ( .i_clk(tb_clk), .i_irq(1’b0), .i_firq(1’b0), .i_system_rdy(tb_rdy), .o_wb_adr(o_wb_adr), .o_wb_sel(o_wb_sel), .o_wb_we(o_wb_we), .i_wb_dat(mem_read), .o_wb_dat(o_wb_dat), .o_wb_cyc(o_wb_cyc), .o_wb_stb(o_wb_stb), .i_wb_ack(mem_ack), .i_wb_err(mem_err) ); endmodule

305 CHAPTER 11. APPENDIX

11.3 ICC TCL reporting

The script below is an example of the .tcl command ﬁles that were created for ICC. The script was used to extract the parameters needed to generate the statistics used in Figure 7.6.

# # Steps to run # 1. reset_switching_activity # 3. report_saif -hier # 4. report_power # propagates switching_activity # 5. source 00_wire_stats # 6. 00_wire_stats > 00_wire_stats_default.csv # # 1. reset_switching_activity # 2. read_saif -verbose -input a25_tb_icc_vcs_128_cache_off.saif -instance_name tb/u_a25_core # 3. report_saif -hier # 4. report_power # propagates switching_activity # 5. source 00_wire_stats # 6. 00_wire_stats > 00_net_stats_clock_128_cache_off.csv # proc 00_wire_stats {} { # No Power, Ground, Tie Low, Tie High, Disconnected Nets set nets [get_flat_nets -filter "number_of_pins>=2 && (net_type==Signal || net_type==Clock)" ] set Process [get_attr saed32hvt_tt1p05v25c nom_process] set Vdd [get_attr saed32hvt_tt1p05v25c nom_voltage] set Temperature [get_attr saed32hvt_tt1p05v25c nom_temperature] set n 50 set j 0 for {set i 0} {$i < $n} {incr i} { set Length($i) $j; # microns, 1e-6 set NetCnt($i) 0 set SigCnt($i) 0 set ClkCnt($i) 0 set AvgStatic($i) 0.0 set MaxStatic($i) 0.0 set AvgToggle($i) 0.0; # toggle/ns, toggle/1e-9 set MaxToggle($i) 0.0 set SigAvgToggle($i) 0.0 set SigMaxToggle($i) 0.0 set ClkAvgToggle($i) 0.0 set ClkMaxToggle($i) 0.0 set AvgRes($i) 0.0; # ohms set MaxRes($i) 0.0 set SigAvgRes($i) 0.0 set SigMaxRes($i) 0.0 set ClkAvgRes($i) 0.0 set ClkMaxRes($i) 0.0 set AvgCap($i) 0.0; # femtofarads, 1e-15 set MaxCap($i) 0.0 set SigAvgCap($i) 0.0 set SigMaxCap($i) 0.0 set ClkAvgCap($i) 0.0

306 CHAPTER 11. APPENDIX

set ClkMaxCap($i) 0.0 set AvgRC($i) 0.0; # seconds set MaxRC($i) 0.0 set SigAvgRC($i) 0.0 set SigMaxRC($i) 0.0 set ClkAvgRC($i) 0.0 set ClkMaxRC($i) 0.0 set AvgMet($i) 0; # number of metal layers set MaxMet($i) 0; # example: {{M1 1.983} {M2 32.380} {M3 292.896} {M4 141.844}} set SigAvgMet($i) 0 set SigMaxMet($i) 0 set ClkAvgMet($i) 0 set ClkMaxMet($i) 0 set AvgPwr($i) 0.0; # Watts set MaxPwr($i) 0.0 set SigAvgPwr($i) 0.0 set SigMaxPwr($i) 0.0 set ClkAvgPwr($i) 0.0 set ClkMaxPwr($i) 0.0 set AvgVia($i) 0 set MaxVia($i) 0 set SigAvgVia($i) 0 set SigMaxVia($i) 0 set ClkAvgVia($i) 0 set ClkMaxVia($i) 0 set AvgFan($i) 0 set MaxFan($i) 0 set SigAvgFan($i) 0 set SigMaxFan($i) 0 set ClkAvgFan($i) 0 set ClkMaxFan($i) 0 set j [expr $j + 33] } set Length($n) 1000000 set ZeroRes 0 set TotalPwr 0.0 set MaxTiming 0.0 set MinTiming 1e10 foreach_in_collection net $nets { set L [get_attribute [get_nets $net] total_wire_length] for {set i 0} {$i < $n} {incr i} { set r [get_attribute -quiet $net ba_resistance_max] if [expr "{$r}" eq "{}"] { incr ZeroRes; break } if [expr $Length($i)<=$L && $L<$Length([expr $i+1])] { set NetCnt($i) [expr $NetCnt($i) + 1] set f [expr [get_attribute $net number_of_pins] - 1] set w [get_attribute $net route_length] set m [regsub -all M $w {} ignore] set v [sizeof [get_vias -of_objects $net]] set s [get_attribute $net switching_activity] set c [get_attribute $net total_capacitance_max] set rc [expr $r * $c * 1e-15] set p [expr $s * 1e9 * 0.5 * $c * 1e-15 * $Vdd * $Vdd ] set t [get_attribute $net net_type] if { $t eq "Signal"} { set SigCnt($i) [expr $SigCnt($i) + 1]

307 CHAPTER 11. APPENDIX

set SigAvgToggle($i) [expr $SigAvgToggle($i) + $s] set SigMaxToggle($i) [expr $SigMaxToggle($i)>$s? $SigMaxToggle($i):$s] set SigAvgRes($i) [expr $SigAvgRes($i) + $r] set SigMaxRes($i) [expr $SigMaxRes($i)>$r? $SigMaxRes($i):$r] set SigAvgCap($i) [expr $SigAvgCap($i) + $c] set SigMaxCap($i) [expr $SigMaxCap($i)>$c? $SigMaxCap($i):$c] set SigAvgRC($i) [expr $SigAvgRC($i) + $rc] set SigMaxRC($i) [expr $SigMaxRC($i)>$rc? $SigMaxRC($i):$rc] set SigAvgMet($i) [expr $SigAvgMet($i) + $m] set SigMaxMet($i) [expr $SigMaxMet($i)>$m? $SigMaxMet($i):$m] set SigAvgPwr($i) [expr $SigAvgPwr($i) + $p] set SigMaxPwr($i) [expr $SigMaxPwr($i)>$p? $SigMaxPwr($i):$p] set SigAvgVia($i) [expr $SigAvgVia($i) + $v] set SigMaxVia($i) [expr $SigMaxVia($i)>$v? $SigMaxVia($i):$v] set SigAvgFan($i) [expr $SigAvgFan($i) + $f] set SigMaxFan($i) [expr $SigMaxFan($i)>$f? $SigMaxFan($i):$f]

} elseif { $t eq "Clock" } { set ClkCnt($i) [expr $ClkCnt($i) + 1] set ClkAvgToggle($i) [expr $ClkAvgToggle($i) + $s] set ClkMaxToggle($i) [expr $ClkMaxToggle($i)>$s? $ClkMaxToggle($i):$s] set ClkAvgRes($i) [expr $ClkAvgRes($i) + $r] set ClkMaxRes($i) [expr $ClkMaxRes($i)>$r? $ClkMaxRes($i):$r] set ClkAvgCap($i) [expr $ClkAvgCap($i) + $c] set ClkMaxCap($i) [expr $ClkMaxCap($i)>$c? $ClkMaxCap($i):$c] set ClkAvgRC($i) [expr $ClkAvgRC($i) + $rc] set ClkMaxRC($i) [expr $ClkMaxRC($i)>$rc? $ClkMaxRC($i):$rc] set ClkAvgMet($i) [expr $ClkAvgMet($i) + $m] set ClkMaxMet($i) [expr $ClkMaxMet($i)>$m? $ClkMaxMet($i):$m] set ClkAvgPwr($i) [expr $ClkAvgPwr($i) + $p] set ClkMaxPwr($i) [expr $ClkMaxPwr($i)>$p? $ClkMaxPwr($i):$p] set ClkAvgVia($i) [expr $ClkAvgVia($i) + $v] set ClkMaxVia($i) [expr $ClkMaxVia($i)>$v? $ClkMaxVia($i):$v] set ClkAvgFan($i) [expr $ClkAvgFan($i) + $f] set ClkMaxFan($i) [expr $ClkMaxFan($i)>$f? $ClkMaxFan($i):$f] } set AvgToggle($i) [expr $AvgToggle($i) + $s] set MaxToggle($i) [expr $MaxToggle($i)>$s? $MaxToggle($i):$s] set AvgRes($i) [expr $AvgRes($i) + $r] set MaxRes($i) [expr $MaxRes($i)>$r? $MaxRes($i):$r] set AvgCap($i) [expr $AvgCap($i) + $c] set MaxCap($i) [expr $MaxCap($i)>$c? $MaxCap($i):$c] set AvgRC($i) [expr $AvgRC($i) + $rc] set MaxRC($i) [expr $MaxRC($i)>$rc? $MaxRC($i):$rc] set AvgMet($i) [expr $AvgMet($i) + $m] set MaxMet($i) [expr $MaxMet($i)>$m? $MaxMet($i):$m] set AvgPwr($i) [expr $AvgPwr($i) + $p] set MaxPwr($i) [expr $MaxPwr($i)>$p? $MaxPwr($i):$p] set AvgVia($i) [expr $AvgVia($i) + $v] set MaxVia($i) [expr $MaxVia($i)>$v? $MaxVia($i):$v] set AvgFan($i) [expr $AvgFan($i) + $f] set MaxFan($i) [expr $MaxFan($i)>$f? $MaxFan($i):$f] set s [get_attribute $net static_probability] set AvgStatic($i) [expr $AvgStatic($i) + $s] set MaxStatic($i) [expr $MaxStatic($i)>$s? $MaxStatic($i):$s] set TotalPwr [expr $TotalPwr + $p]

308 CHAPTER 11. APPENDIX

set MaxTiming [expr $MaxTiming>$rc? $MaxTiming:$rc] set MinTiming [expr $MinTiming<$rc? $MinTiming:$rc] } } } puts "Interconnect Length Distribution" puts "Copy output below into text file with filetype .csv, Read into spreadsheet Excel program" puts "======" puts -nonewline "n, LowLength, HighLength, " puts -nonewline "NetCnt, SigCnt, ClkCnt, " puts -nonewline "NetLog10, SigLog10, ClkLog10, " puts -nonewline "NetAvgStatic, NetMaxStatic, NetAvgToggle, SigAvgToggle, ClkAvgToggle, " puts -nonewline "NetMaxToggle, SigMaxToggle, ClkMaxToggle, " puts -nonewline "AvgRes, SigAvgRes, ClkAvgRes, MaxRes, SigMaxRes, ClkMaxRes, " puts -nonewline "AvgCap, SigAvgCap, ClkAvgCap, MaxCap, SigMaxCap, ClkMaxCap, " puts -nonewline "AvgRC, SigAvgRC, ClkAvgRC, MaxRC, SigMaxRC, ClkMaxRC, " puts -nonewline "AvgLayer, SigAvgLayer, ClkAvgLayer, MaxLayer, SigMaxLayer, ClkMaxLayer, " puts -nonewline "AvgPwr, SigAvgPwr, ClkAvgPwr, MaxPwr, SigMaxPwr, ClkMaxPwr, " puts -nonewline "AvgVia, SigAvgVia, ClkAvgVia, MaxVia, SigMaxVia, ClkMaxVia, " puts -nonewline "AvgFanOut, SigAvgFanOut, ClkAvgFanOut, MaxFanOut, SigMaxFanOut, ClkMaxFanOut, " puts "Process, Vdd, Temperature" set Total 0 for {set i 0} {$i < $n} {incr i} { set Total [expr $Total + $NetCnt($i)] set NetLog [expr $NetCnt($i) < 1 ? 0.0 : log10($NetCnt($i))] set SigLog [expr $SigCnt($i) < 1 ? 0.0 : log10($SigCnt($i))] set ClkLog [expr $ClkCnt($i) < 1 ? 0.0 : log10($ClkCnt($i))] set AvgS [expr $NetCnt($i) < 1 ? 0.0 : $AvgStatic($i) / $NetCnt($i)] set AvgT [expr $NetCnt($i) < 1 ? 0.0 : $AvgToggle($i) / $NetCnt($i)] set SigAvgT [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgToggle($i) / $SigCnt($i)] set ClkAvgT [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgToggle($i) / $ClkCnt($i)] set AvgR [expr $NetCnt($i) < 1 ? 0.0 : $AvgRes($i) / $NetCnt($i)] set SigAvgR [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgRes($i) / $SigCnt($i)] set ClkAvgR [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgRes($i) / $ClkCnt($i)] set AvgC [expr $NetCnt($i) < 1 ? 0.0 : $AvgCap($i) / $NetCnt($i)] set SigAvgC [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgCap($i) / $SigCnt($i)] set ClkAvgC [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgCap($i) / $ClkCnt($i)] set AvgRX [expr $NetCnt($i) < 1 ? 0.0 : $AvgRC($i) / $NetCnt($i)] set SigAvgRX [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgRC($i) / $SigCnt($i)] set ClkAvgRX [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgRC($i) / $ClkCnt($i)] set AvgM [expr $NetCnt($i) < 1 ? 0.0 : $AvgMet($i) / $NetCnt($i)] set SigAvgM [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgMet($i) / $SigCnt($i)] set ClkAvgM [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgMet($i) / $ClkCnt($i)] set AvgP [expr $NetCnt($i) < 1 ? 0.0 : $AvgPwr($i) / $NetCnt($i)] set SigAvgP [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgPwr($i) / $SigCnt($i)] set ClkAvgP [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgPwr($i) / $ClkCnt($i)] set AvgV [expr $NetCnt($i) < 1 ? 0.0 : $AvgVia($i) / $NetCnt($i)] set SigAvgV [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgVia($i) / $SigCnt($i)] set ClkAvgV [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgVia($i) / $ClkCnt($i)] set AvgF [expr $NetCnt($i) < 1 ? 0.0 : $AvgFan($i) / $NetCnt($i)] set SigAvgF [expr $SigCnt($i) < 1 ? 0.0 : $SigAvgFan($i) / $SigCnt($i)] set ClkAvgF [expr $ClkCnt($i) < 1 ? 0.0 : $ClkAvgFan($i) / $ClkCnt($i)] puts -nonewline "[expr $i+1], $Length($i), $Length([expr $i+1]), " puts -nonewline "$NetCnt($i), $SigCnt($i), $ClkCnt($i), " puts -nonewline "$NetLog, $SigLog, $ClkLog, "; #plotting puts -nonewline "$AvgS, $MaxStatic($i), $AvgT, $SigAvgT, $ClkAvgT, "

309 CHAPTER 11. APPENDIX

puts -nonewline "$MaxToggle($i), $SigMaxToggle($i), $ClkMaxToggle($i), "; # Toggle/ns puts -nonewline "$AvgR, $SigAvgR, $ClkAvgR, $MaxRes($i), $SigMaxRes($i), $ClkMaxRes($i), "; # Ohms puts -nonewline "$AvgC, $SigAvgC, $ClkAvgC, $MaxCap($i), $SigMaxCap($i), $ClkMaxCap($i), "; # femtofarads puts -nonewline "$AvgRX, $SigAvgRX, $ClkAvgRX, $MaxRC($i), $SigMaxRC($i), $ClkMaxRC($i), "; # Seconds puts -nonewline "$AvgM, $SigAvgM, $ClkAvgM, $MaxMet($i), $SigMaxMet($i), $ClkMaxMet($i), "; # Metal Layers used puts -nonewline "$AvgP, $SigAvgP, $ClkAvgP, $MaxPwr($i), $SigMaxPwr($i), $ClkMaxPwr($i), "; # Watts puts -nonewline "$AvgV, $SigAvgV, $ClkAvgV, $MaxVia($i), $SigMaxVia($i), $ClkMaxVia($i), "; # Watts puts -nonewline "$AvgF, $SigAvgF, $ClkAvgF, $MaxFan($i), $SigMaxFan($i), $ClkMaxFan($i), "; # Fanout puts "$Process, $Vdd, $Temperature"; # csv alignment marker } puts "======" puts "Total $ZeroRes Zero Resistance nets" puts -nonewline "Verify that Total original nets - ZeroRes nets => " puts "[sizeof $nets]-$ZeroRes=[expr [sizeof $nets]-$ZeroRes] equals $Total" puts "Total Net Switching Power = $TotalPwr Watts ([format {%.4e} [expr $TotalPwr * 1e6]] uW)" puts "Min Net Timing = $MinTiming seconds ([expr $MinTiming * 1e12] ps)" puts "Max Net Timing = $MaxTiming seconds ([expr $MaxTiming * 1e12] ps)" }

310 CHAPTER 11. APPENDIX

11.4 Python script to generate ALF ﬁle

The ALF (Advance Library File) is an IEEE 1603 and IEC 62265 standard format. The .alf contains the table information for EM needed by ICC to perform the EM analysis. Below is the python script created to generate the .alf for the explore methodology.

# # example: python 00_saed32nm_em_generate_alf.py -T 110 -F 0.01 -v -x 0 | more # example: python 00_saed32nm_em_generate_alf.py -0 0 > 00_saed32nm_em_zero.alf # synopsys does not like zeros # example: python 00_saed32nm_em_generate_alf.py -0 1e-4 > 00_saed32nm_em_zero.alf # python 00_saed32nm_em_generate_alf.py -0 1e-7 1e-2 1e-1 -1 "%.8f" > 00_saed32nm_em_test.alf # # icc_shell> report_signal_em_calculation n1763 # **************************************** # Units: Length unit: um, Current unit: uA, Switching activity unit: /ns, Time unit: ns # ************************************ # LAYER METAL LAYER CENTER WIDTH MODE CURRENT # NAME VIA ID COORDINATE VIA CUT Mean(Limit, Violated) RMS(Limit, Violated) Peak(Limit, Violated) # M6 Metal 21 [513.59, 783.90] 0.06 min 1.57e-03 (1.00e-01,-) 5.35e+00 (1.00e-01,v) 4.49e+00 (1.00e-01,v) # M6 Metal 21 [513.59, 783.90] 0.06 max 3.41e-04 (1.00e-01,-) 6.55e+00 (1.00e-01,v) 5.50e+00 (1.00e-01,v) # M1 Metal 11 [513.65, 771.78] 0.05 min 1.57e-03 (1.00e-01,-) 3.51e+00 (1.00e-01,v) 2.95e+00 (1.00e-01,v) # M1 Metal 11 [513.65, 771.78] 0.05 max 3.41e-04 (1.00e-01,-) 4.80e+00 (1.00e-01,v) 4.03e+00 (1.00e-01,v) # VIA1 Via 12 [513.59, 771.78] 1 min 1.57e-03 (1.00e-01,-) 3.56e+00 (1.00e-01,v) 2.99e+00 (1.00e-01,v) import os import sys import re import glob import argparse import math #from scipy.stats import norm Lop = 100000 # hours Fop = 0.001 # failure rate at lifetime, 0.1% Top = 110 # Kelvin, AF=1 for 110C

Jfab = 0.8147368 # MA/cm2, M1, 110C, 11.4 years, 0.1%, 20% Ohm change Lfab = float(100000)# hours Ffab = 0.001 # failure rate at lifetime, 0.1% Tfab = float(110) # Kelvin, AF=1 for 110C Ea = 0.8 # Activation energy nfab = 1 # electromigration current density exponent kB = 8.61733e-5 # Boltzmann constant Sfab = 0.5 # lognormal sigma em_slope = -0.0150000 # curve fit from 28nm PDK em_linear = 5.4955833 libname = ’saed32nm_em_1p9m’ nskip = 3 Temperature = ( -40, 0, 25, 70, 85, 95, 100, 105, 110, 120, 125, 130, 140, 150 ) #Celsius

311 CHAPTER 11. APPENDIX

metal_Layer = (’M1’, ’M2’, ’M3’, ’M4’, ’M5’, ’M6’, ’M7’, ’M8’, ’M9’, ’MRDL’) Scale = 0.001 # nm to um Thickness = (95, 95, 95, 95, 95, 95, 95, 95, 190, 280 ) #nm Wmin = (50, 56, 56, 56, 56, 56, 56, 56, 160, 2000 ) #nm Wmin_n = 8 metal_Irms_r = 0.02 metal_Ipeak_r = 0.05 metal_Javg_28nm = ( 0.8147368, 0.8187970, 0.8187970, 0.8187970, 0.8187970, 0.8187970, 0.8187970, 0.8187970, 0.4203947, 0.2889643) #MA/cm2 via_Layer = (’VIA1’, ’VIA2’, ’VIA3’, ’VIA4’, ’VIA5’, ’VIA6’, ’VIA7’, ’VIA8’, ’VIARDL’) via_scale = 0.001 via_Length = (50, 50, 50, 50, 50, 50, 50, 50, 130 ) #nm via_Wmin = (50, 50, 50, 50, 50, 50, 50, 50, 130 ) #nm via_Wmin_n = 2 via_Irms_r = 0.02 via_Ipeak_r = 0.05 via_Javg_28nm = ( 1.6000000, 1.6000000, 1.6000000, 1.6000000, 1.6000000, 1.6000000, 1.6000000, 1.6000000, 0.4733728 ) #MA/cm2 def AF(T): # acceleration factor if T <= 105: af = em_linear + em_slope*(T-110 + 273.15) else: af = math.exp((Ea/kB)*(1/(T+273.15) - 1/(Tfab+273.15))) return af def metal_header(current_type, measurement_type, temperature): print 3*3*’ ’, ’CURRENT ’ + current_type + ’ {’ print 4*3*’ ’, ’MEASUREMENT = ’ + measurement_type + ’;’ print 4*3*’ ’, ’MAX {’ print 5*3*’ ’, ’HEADER {’

if temperature: print 6*3*’ ’, ’TEMPERATURE { TABLE { ’, for T in Temperature: print T, print ’ } }’

print 6*3*’ ’, ’WIDTH { TABLE { ’, for W in range(1, Wmin_n+1): print Scale*Wmin[M]*W, print ’ } }’ print 5*3*’ ’, ’}’ print 5*3*’ ’, ’TABLE {’ def via_header(current_type, measurement_type, temperature): print 3*3*’ ’, ’CURRENT ’ + current_type + ’ {’ print 4*3*’ ’, ’MEASUREMENT = ’ + measurement_type + ’;’ print 4*3*’ ’, ’MAX {’ print 5*3*’ ’, ’HEADER {’

if temperature: print 6*3*’ ’, ’TEMPERATURE { TABLE { ’, for T in Temperature: print T,

312 CHAPTER 11. APPENDIX

print ’ } }’

print 6*3*’ ’, ’AREA { TABLE { ’, for W in range(1, via_Wmin_n+1): print via_scale*via_Length[V]*W*via_scale*via_Wmin[V]*W, print ’ } }’ print 5*3*’ ’, ’}’ print 5*3*’ ’, ’TABLE {’ def RatApprox(t): # www.johndcook.com/blog/cpp_phi_inverse/ # Abramowitz and Stegun formula 26.2.23. # The absolute value of the error should be less than 4.5 e-4. c = (2.515517, 0.802853, 0.010328) d = (1.432788, 0.189269, 0.001308) n = (c[2]*t + c[1])*t + c[0] m = ((d[2]*t + d[1])*t + d[0])*t + 1.0 return t - n/m def NORMSINV(p): if p <= 0.0 or p >= 1.0: print "NORMSINV error: must be 0.0 <= p="+str(p)+" <= 1.0" exit()

if p < 0.5: # F^-1(p) = - G^-1(p) return -RatApprox(math.sqrt(-2.0*math.log(p))) else: # F^-1(p) = G^-1(1-p) return RatApprox(math.sqrt(-2.0*math.log(1-p)) ); parser = argparse.ArgumentParser() parser.add_argument("-v", "--verbose", action="store_true", dest="verbose", default=False, help="Print status messages to stdout") parser.add_argument("-T", "--Top", action="store", dest="Top", default=110, help="Operating Temperature in Celsius, default=110") parser.add_argument("-L", "--Lop", action="store", dest="Lop", default=100000, help="Operating Lifetime in hours, default=100000=11.4 years") parser.add_argument("-F", "--Fop", action="store", dest="Fop", default=0.001, help="Operating Failure, default=0.001")

# -0 1e-5; -0 1e-5 1e-4; -1 1e-5 1e-4 1e-2 mA parser.add_argument("-0", action="store", nargs="+", dest="force", default=[-1, -1, -1], help="Force all the same Iavg Irms Ipeak mA values") parser.add_argument("-1", "--Prec", action="store", type=str, dest="Prec", default="%.4f", help=’ALF Table Precision, default="%%.4f"’)

# debug level x, -x 1 => (T,W,AF) -x 2 => stop on M1, -x 3 => 2 and 1 parser.add_argument("-x", action="store", dest="debug", default=0, help="Debug level, -x 1 (T,W,AF), -x 2 (stop on M1)") args = parser.parse_args()

313 CHAPTER 11. APPENDIX

Top = float(args.Top) Lop = float(args.Lop) Fop = float(args.Fop) if len(args.force) == 1: Favg = float(args.force[0]) Frms = Favg Fmax = Favg elif len(args.force) == 2: Favg = float(args.force[0]) Frms = float(args.force[1]) Fmax = Frms elif len(args.force) == 3: Favg = float(args.force[0]) Frms = float(args.force[1]) Fmax = float(args.force[2]) else: print "Error: too many force values" exit()

Prec = args.Prec debug = int(args.debug)

# operating conditions for application environmen LAop = Lfab/Lop TAop = AF(Top) # =math.exp((Ea/kB)*(1/(Top+273.15) - 1/(Tfab+273.15))) FAop = math.exp(Sfab *(NORMSINV(Fop) - NORMSINV(Ffab))) Jop = Jfab * (LAop * TAop * FAop) ** (1/nfab) metal_Javg = ( Jop, Jop, Jop, Jop, Jop, Jop, Jop, Jop, Jop/2, Jop/3) via_Javg = ( 2*Jop, 2*Jop, 2*Jop, 2*Jop, 2*Jop, 2*Jop, 2*Jop, 2*Jop, Jop/2) if args.verbose or True: print print ’// Lifetime Lop =’, Lop, ’hours’, Lop/(24*365.25), ’years’ print ’// Lifetime Lfab=’, Lfab, ’hours’, Lfab/(24*365.25), ’years’ print print ’// Operating Top =’, Top, ’Celsius’, Top+273.15, ’Kelvin’ print ’// Tfab=’, Tfab, ’Celsius’, Tfab+273.15, ’Kelvin’ print print ’// Failure Fop =’+str(Fop), ’Fop =’+str(Fop*100)+’%’, ’NORMSINV(Fop)=’, NORMSINV(Fop) print ’// Failure Ffab=’+str(Ffab), ’Ffab=’+str(Ffab*100)+’%’, ’NORMSINV(Ffab)=’, NORMSINV(Ffab) print print ’// nfab=(j^n)=’+str(nfab), ’Ea=’+str(Ea), ’eV’, ’kB=’+str(Ea), ’eV/Kelvin’, ’Sigma=’+str(Sfab)

print print ’// Lifetime acceration LAop=’, LAop, ’Temperature TAop=’, TAop, ’Failure FAop=’, FAop print ’// Jop =’+str(Jop), ’MA/cm2’, ’( Jop = Jfab * ( LAop * TAop * FAop ) ^ (1/nfab)’ print ’// Jfab=’+str(Jfab), ’MA/cm2’ M=0 #M1 print ’// Iavg,op (M1, Wmin=’+str(Wmin[M])+’nm, T=’+str(Top)+’C, F=’+str(Fop*100)+’%)=’, print AF(Top)*metal_Javg[M]*10*Scale*Thickness[M]*Scale*Wmin[M], ’mA’ print ’// Iavg,fab(M1, Wmin=’+str(Wmin[M])+’nm, T=’+str(Tfab)+’C, F=’+str(Ffab*100)+’%)=’, print AF(Tfab)*Jfab*10*Scale*Thickness[M]*Scale*Wmin[M], ’mA’ print print ’LIBRARY’, libname, ’{’

314 CHAPTER 11. APPENDIX

for M in range(len(metal_Layer)): print 1*3*’ ’, ’LAYER’, metal_Layer[M], ’{’ print 2*3*’ ’, ’PURPOSE = routing;’ print 2*3*’ ’, ’LIMIT {’ metal_header(’average_limit’, ’average’, True)

for W in range(1,Wmin_n+1): print 1*3*’ ’, for T in Temperature: if (debug & 1) > 0: print ’(’,Scale*Thickness[M],Scale*Wmin[M]*W,AF(T),’)’, elif (Favg >= 0): print Prec%Favg, else: print Prec%(AF(T)*metal_Javg[M]*10*Scale*Thickness[M]*Scale*Wmin[M]*W), print print 5*3*’ ’, ’}’ print 4*3*’ ’, ’}’ print 3*3*’ ’, ’}’

metal_header(’rms_limit’, ’rms’, True) for W in range(1,Wmin_n+1): print 1*3*’ ’, for T in Temperature: if (debug & 1) > 0: print "("+str(T)+","+str(Scale*Wmin[M]*W)+","+str(AF(T))+")", elif (Frms >= 0): print Prec%Frms, else: print Prec%(AF(T)*metal_Javg[M]*10*Scale*Thickness[M]*Scale*Wmin[M]*W/math.sqrt(metal_Irms_r)), print print 5*3*’ ’, ’}’ print 4*3*’ ’, ’}’ print 3*3*’ ’, ’}’

metal_header(’peak_limit’, ’peak’, True) for W in range(1,Wmin_n+1): print 1*3*’ ’, for T in Temperature: if (debug & 1) > 0: print "("+str(T)+","+str(Scale*Wmin[M]*W)+","+str(AF(T))+")", elif (Fmax >= 0): print Prec%Fmax, else: print Prec%(AF(T)*metal_Javg[M]*10*Scale*Thickness[M]*Scale*Wmin[M]*W/metal_Ipeak_r), print print 5*3*’ ’, ’}’ print 4*3*’ ’, ’}’ print 3*3*’ ’, ’}’ print 2*3*’ ’, ’}’ print 1*3*’ ’, ’}’ if (debug & 2) > 0: break for V in range(len(via_Layer)):

315 CHAPTER 11. APPENDIX

print 1*3*’ ’, ’LAYER’, via_Layer[V], ’{’ print 2*3*’ ’, ’PURPOSE = cut;’ print 2*3*’ ’, ’LIMIT {’ via_header(’average_limit’, ’average’, True)

for W in range(1,via_Wmin_n+1): print 1*3*’ ’, for T in Temperature: if (debug & 1) > 0: print "("+str(T)+","+str(via_scale*via_Wmin[V]*W)+","+str(AF(T))+")", elif (Favg >= 0): print Prec%Favg, else: print Prec%(AF(T)*via_Javg[V]*10*via_scale*via_Length[V]*via_scale*via_Wmin[V]*W), print print 5*3*’ ’, ’}’ print 4*3*’ ’, ’}’ print 3*3*’ ’, ’}’

via_header(’rms_limit’, ’rms’, True) for W in range(1,via_Wmin_n+1): print 1*3*’ ’, for T in Temperature: if (debug & 1) > 0: print "("+str(T)+","+str(via_scale*via_Wmin[V]*W)+","+str(AF(T))+")", elif (Frms >= 0): print Prec%Frms, else: print Prec%(AF(T)*via_Javg[V]*10*via_scale*via_Length[V]*via_scale*via_Wmin[V]*W/math.sqrt(via_Irms_r)), print print 5*3*’ ’, ’}’ print 4*3*’ ’, ’}’ print 3*3*’ ’, ’}’

via_header(’peak_limit’, ’peak’, True) for W in range(1,via_Wmin_n+1): print 1*3*’ ’, for T in Temperature: if (debug & 1) > 0: print "("+str(T)+","+str(via_scale*via_Wmin[V]*W)+","+str(AF(T))+")", elif (Fmax >= 0): print Prec%Fmax, else: print Prec%(AF(T)*via_Javg[V]*10*via_scale*via_Length[V]*via_scale*via_Wmin[V]*W/via_Ipeak_r), print print 5*3*’ ’, ’}’ print 4*3*’ ’, ’}’ print 3*3*’ ’, ’}’ print 2*3*’ ’, ’}’ print 1*3*’ ’, ’}’ if (debug & 2) > 0: break print 0*3*’ ’, ’}’

316 CHAPTER 11. APPENDIX

11.5 ITF (Interconnect Technology File)

The methodology requires 3 separate .itf to explore the design space. Python scripts were created to modify the PDK library .itf file shown in the Tool Flow (Figure 6.2) diagram as Modified Black’s Law. .itf files were generated for temperatures -40 ◦C, 25 ◦C and 125 ◦C and listed below.

.itf ﬁle for -40 ◦C

$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ $ ITF file: 00_saed32nm_1p9m_nominal_2018.itf $ STARRCXT process file for saed 32nm Logic 1p9m 1.05V/1.8V/2.5V $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ $ Revision History: $ Rev. Date What $ ------$ Rev.1 02/Feb/2011 Initial version. $ Rev.1.1 --/---/2011 Changed thickness and rpsq of some layers $ ------$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ $ Copyright (c), 2011 Synopsys, Inc. All rights reserved. $ This process description file and the associated documentation are confidential $ and proprietary to Synopsys, Inc. $ $ DISCLAIMER $ The information contained herein is provided by Synopsys, Inc. on $ an "AS IS" basis without any warranty, and Synopsys has no obligation $ to support or otherwise maintain the information. $ $ Synopsys, Inc. disclaims any representation that the information $ does not infringe any intellectual property rights or proprietary $ rights of any third parties. There are no other warranties given by $ Synopsys, whether express, implied or statutory, including, without $ limitation, implied warranties of merchantability and fitness for a $ particular purpose. $ $ Synopsys, Inc. reserves the right to make changes to the information $ at any time and without notice. $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ TECHNOLOGY=00_saed32nm_1p9m_n40c_2019

DIELECTRIC PASS1 { THICKNESS = 3.00 ER=3.9 }

$ MRDL Redistribution layer CONDUCTOR MRDL { THICKNESS = 0.28 WMIN=2 SMIN=2 RPSQ=0.0596 } DIELECTRIC PASS2 { THICKNESS = 3.00 ER=3.9 }

CONDUCTOR M9 { THICKNESS = 0.19 WMIN=0.16 SMIN=0.16 RPSQ=0.0886 } DIELECTRIC D9 { THICKNESS = 0.6 ER=3.9 }

317 CHAPTER 11. APPENDIX

CONDUCTOR M8 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D8 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M7 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D7 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M6 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D6 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M5 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D5 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M4 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D4 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M3 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D3 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M2 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.3623 } DIELECTRIC D2 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M1 { THICKNESS = 0.095 WMIN=0.050 SMIN=0.050 RPSQ=0.3623 } DIELECTRIC D1 { THICKNESS = 0.2 ER=3.9 }

CONDUCTOR POLY { THICKNESS = 0.071 WMIN=0.03 SMIN=0.086 RPSQ=15 } DIELECTRIC GOX { THICKNESS = 0.0015 ER=4 } CONDUCTOR DIFF {IS_DIFF THICKNESS=0.05 WMIN=0.044 SMIN=0.05 RPSQ=15} DIELECTRIC D0 { THICKNESS = 0.13 ER=4 }

VIA SUBCONT { FROM=SUBSTRATE TO=DIFF RPV=0.00001 AREA=0.0144} VIA DIFFCONT { FROM=DIFF TO=M1 AREA=0.001764 RPV=150 } VIA POLYCONT { FROM=POLY TO=M1 AREA=0.001764 RPV=135 } VIA VIA1 { FROM=M1 TO=M2 AREA=0.0025 RPV=0.8050 } VIA VIA1_BAR { FROM=M1 TO=M2 AREA=0.005 RPV=0.8050 } VIA VIA1_LRG { FROM=M1 TO=M2 AREA=0.01 RPV=0.4025 } VIA VIA2 { FROM=M2 TO=M3 AREA=0.0025 RPV=0.4025 } VIA VIA2_BAR { FROM=M2 TO=M3 AREA=0.005 RPV=0.4025 } VIA VIA2_LRG { FROM=M2 TO=M3 AREA=0.01 RPV=0.4025 } VIA VIA3 { FROM=M3 TO=M4 AREA=0.0025 RPV=0.4025 } VIA VIA3_BAR { FROM=M3 TO=M4 AREA=0.005 RPV=0.4025 } VIA VIA3_LRG { FROM=M3 TO=M4 AREA=0.01 RPV=0.4025 } VIA VIA4 { FROM=M4 TO=M5 AREA=0.0025 RPV=0.4025 } VIA VIA4_BAR { FROM=M4 TO=M5 AREA=0.005 RPV=0.4025 } VIA VIA4_LRG { FROM=M4 TO=M5 AREA=0.01 RPV=0.4025 } VIA VIA5 { FROM=M5 TO=M6 AREA=0.0025 RPV=0.4025 } VIA VIA5_BAR { FROM=M5 TO=M6 AREA=0.005 RPV=0.4025 } VIA VIA5_LRG { FROM=M5 TO=M6 AREA=0.01 RPV=0.4025 } VIA VIA6 { FROM=M6 TO=M7 AREA=0.0025 RPV=0.4025 } VIA VIA6_BAR { FROM=M6 TO=M7 AREA=0.005 RPV=0.4025 } VIA VIA6_LRG { FROM=M6 TO=M7 AREA=0.01 RPV=0.4025 } VIA VIA7 { FROM=M7 TO=M8 AREA=0.0025 RPV=0.4025 } VIA VIA7_BAR { FROM=M7 TO=M8 AREA=0.005 RPV=0.4025 } VIA VIA7_LRG { FROM=M7 TO=M8 AREA=0.01 RPV=0.4025 } VIA VIA8 { FROM=M8 TO=M9 AREA=0.0169 RPV=0.0805 } VIA VIARDL { FROM=M9 TO=MRDL AREA=4 RPV=0.0403 }

318 CHAPTER 11. APPENDIX

.itf ﬁle for 25 ◦C

DIELECTRIC PASS1 { THICKNESS = 3.00 ER=3.9 }

$ MRDL Redistribution layer CONDUCTOR MRDL { THICKNESS = 0.28 WMIN=2 SMIN=2 RPSQ=0.074 } DIELECTRIC PASS2 { THICKNESS = 3.00 ER=3.9 }

CONDUCTOR M9 { THICKNESS = 0.19 WMIN=0.16 SMIN=0.16 RPSQ=0.11 } DIELECTRIC D9 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M8 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 } DIELECTRIC D8 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M7 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 } DIELECTRIC D7 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M6 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 } DIELECTRIC D6 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M5 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 } DIELECTRIC D5 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M4 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 }

319 CHAPTER 11. APPENDIX

DIELECTRIC D4 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M3 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 } DIELECTRIC D3 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M2 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.45 } DIELECTRIC D2 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M1 { THICKNESS = 0.095 WMIN=0.050 SMIN=0.050 RPSQ=0.45 } DIELECTRIC D1 { THICKNESS = 0.2 ER=3.9 }

VIA SUBCONT { FROM=SUBSTRATE TO=DIFF RPV=0.00001 AREA=0.0144} VIA DIFFCONT { FROM=DIFF TO=M1 AREA=0.001764 RPV=150 } VIA POLYCONT { FROM=POLY TO=M1 AREA=0.001764 RPV=135 } VIA VIA1 { FROM=M1 TO=M2 AREA=0.0025 RPV=1 } VIA VIA1_BAR { FROM=M1 TO=M2 AREA=0.005 RPV=1 } VIA VIA1_LRG { FROM=M1 TO=M2 AREA=0.01 RPV=0.5 } VIA VIA2 { FROM=M2 TO=M3 AREA=0.0025 RPV=0.5 } VIA VIA2_BAR { FROM=M2 TO=M3 AREA=0.005 RPV=0.5 } VIA VIA2_LRG { FROM=M2 TO=M3 AREA=0.01 RPV=0.5 } VIA VIA3 { FROM=M3 TO=M4 AREA=0.0025 RPV=0.5 } VIA VIA3_BAR { FROM=M3 TO=M4 AREA=0.005 RPV=0.5 } VIA VIA3_LRG { FROM=M3 TO=M4 AREA=0.01 RPV=0.5 } VIA VIA4 { FROM=M4 TO=M5 AREA=0.0025 RPV=0.5 } VIA VIA4_BAR { FROM=M4 TO=M5 AREA=0.005 RPV=0.5 } VIA VIA4_LRG { FROM=M4 TO=M5 AREA=0.01 RPV=0.5 } VIA VIA5 { FROM=M5 TO=M6 AREA=0.0025 RPV=0.5 } VIA VIA5_BAR { FROM=M5 TO=M6 AREA=0.005 RPV=0.5 } VIA VIA5_LRG { FROM=M5 TO=M6 AREA=0.01 RPV=0.5 } VIA VIA6 { FROM=M6 TO=M7 AREA=0.0025 RPV=0.5 } VIA VIA6_BAR { FROM=M6 TO=M7 AREA=0.005 RPV=0.5 } VIA VIA6_LRG { FROM=M6 TO=M7 AREA=0.01 RPV=0.5 } VIA VIA7 { FROM=M7 TO=M8 AREA=0.0025 RPV=0.5 } VIA VIA7_BAR { FROM=M7 TO=M8 AREA=0.005 RPV=0.5 } VIA VIA7_LRG { FROM=M7 TO=M8 AREA=0.01 RPV=0.5 } VIA VIA8 { FROM=M8 TO=M9 AREA=0.0169 RPV=0.1 } VIA VIARDL { FROM=M9 TO=MRDL AREA=4 RPV=0.05 }

320 CHAPTER 11. APPENDIX

.itf ﬁle for 125 ◦C

DIELECTRIC PASS1 { THICKNESS = 3.00 ER=3.9 }

$ MRDL Redistribution layer CONDUCTOR MRDL { THICKNESS = 0.28 WMIN=2 SMIN=2 RPSQ=0.0962 } DIELECTRIC PASS2 { THICKNESS = 3.00 ER=3.9 }

CONDUCTOR M9 { THICKNESS = 0.19 WMIN=0.16 SMIN=0.16 RPSQ=0.1430 } DIELECTRIC D9 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M8 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 } DIELECTRIC D8 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M7 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 } DIELECTRIC D7 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M6 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 } DIELECTRIC D6 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M5 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 } DIELECTRIC D5 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M4 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 }

321 CHAPTER 11. APPENDIX

DIELECTRIC D4 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M3 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 } DIELECTRIC D3 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M2 { THICKNESS = 0.095 WMIN=0.056 SMIN=0.056 RPSQ=0.5850 } DIELECTRIC D2 { THICKNESS = 0.6 ER=3.9 }

CONDUCTOR M1 { THICKNESS = 0.095 WMIN=0.050 SMIN=0.050 RPSQ=0.5850 } DIELECTRIC D1 { THICKNESS = 0.2 ER=3.9 }

VIA SUBCONT { FROM=SUBSTRATE TO=DIFF RPV=0.00001 AREA=0.0144} VIA DIFFCONT { FROM=DIFF TO=M1 AREA=0.001764 RPV=150 } VIA POLYCONT { FROM=POLY TO=M1 AREA=0.001764 RPV=135 } VIA VIA1 { FROM=M1 TO=M2 AREA=0.0025 RPV=1.3 } VIA VIA1_BAR { FROM=M1 TO=M2 AREA=0.005 RPV=1.3 } VIA VIA1_LRG { FROM=M1 TO=M2 AREA=0.01 RPV=0.65 } VIA VIA2 { FROM=M2 TO=M3 AREA=0.0025 RPV=0.65 } VIA VIA2_BAR { FROM=M2 TO=M3 AREA=0.005 RPV=0.65 } VIA VIA2_LRG { FROM=M2 TO=M3 AREA=0.01 RPV=0.65 } VIA VIA3 { FROM=M3 TO=M4 AREA=0.0025 RPV=0.65 } VIA VIA3_BAR { FROM=M3 TO=M4 AREA=0.005 RPV=0.65 } VIA VIA3_LRG { FROM=M3 TO=M4 AREA=0.01 RPV=0.65 } VIA VIA4 { FROM=M4 TO=M5 AREA=0.0025 RPV=0.65 } VIA VIA4_BAR { FROM=M4 TO=M5 AREA=0.005 RPV=0.65 } VIA VIA4_LRG { FROM=M4 TO=M5 AREA=0.01 RPV=0.65 } VIA VIA5 { FROM=M5 TO=M6 AREA=0.0025 RPV=0.65 } VIA VIA5_BAR { FROM=M5 TO=M6 AREA=0.005 RPV=0.65 } VIA VIA5_LRG { FROM=M5 TO=M6 AREA=0.01 RPV=0.65 } VIA VIA6 { FROM=M6 TO=M7 AREA=0.0025 RPV=0.65 } VIA VIA6_BAR { FROM=M6 TO=M7 AREA=0.005 RPV=0.65 } VIA VIA6_LRG { FROM=M6 TO=M7 AREA=0.01 RPV=0.65 } VIA VIA7 { FROM=M7 TO=M8 AREA=0.0025 RPV=0.65 } VIA VIA7_BAR { FROM=M7 TO=M8 AREA=0.005 RPV=0.65 } VIA VIA7_LRG { FROM=M7 TO=M8 AREA=0.01 RPV=0.65 } VIA VIA8 { FROM=M8 TO=M9 AREA=0.0169 RPV=0.13 } VIA VIARDL { FROM=M9 TO=MRDL AREA=4 RPV=0.065 }

322 CHAPTER 11. APPENDIX

11.6 StarXtract

StarXtract is the Synopsys program that will extract the hspice model for a design. Below is an example of the hspice created by running StarXtract that was used in the methodology.

* Design file: 09_28nm_hspice_invx0_rvt_ff1p16v125c.sp * Transient Waveforms in file: 09_28nm_hspice_invx0_rvt_ff1p16v125c.tr0 .tr1 .tr2 .tr3 .tr4 .tr5 .tr6 * Measure output in text file: 09_28nm_hspice_invx0_rvt_ff1p16v125c.ms0 .ms1 .ms2 .ms3 .ms4 .ms5 .ms6 (Use Waveform, wv)

.lib ’saed32nm.lib’ TT

.include "saed32nm_lvt_TestOhms_V2.spf" * .SUBCKT paramters in the same order .include "saed32nm_svt_TestOhms_V2.spf" * .SUBCKT paramters in the same order .include "saed32nm_hvt_TestOhms_V2.spf" * .SUBCKT paramters in the same order .include "saed32nm_nonparasitic.spf" * .SUBCKT paramters in the same order .include "10_28nm_build_icc_starRC_Cnom.sp" * From ICC, StarRCi, python extract

*.TEMP -40 0 25 105 .TEMP 25

.options POST ACCURATE NUMDGT=16 MEASDGT=16 *.TEMP -55 -40 25 55 70 85 105 125

.param VddScale =0.0 * 0=zero percent .param gate_H =95e-9 * 28nm metal thickness (m), Hmin=230nm, Hmax=300nm .param gate_W =50e-9 * metal width (m)

.param M1_thickness =95e-9 .param M2_thickness =95e-9 .param M3_thickness =95e-9 .param M4_thickness =95e-9 .param M5_thickness =95e-9 .param M6_thickness =95e-9 .param M7_thickness =95e-9 .param M8_thickness =95e-9 .param M9_thickness =95e-9

.param EM_n = 1 * current density exponent, n, for copper .param EM_Ea = 0.8 * eV, activation energy, for copper .param EM_k = 8.61733e-5 * eV/K .param EM_T = ’273.15+125’ * Operating use temperature, 125 Celsius .param EM_sigma = 0.4 * failure deviation .param EM_failure = -3.09 * failute rate, 0.1% .param EM_A50 = 8.95e-6 * = 11.9494e-6 (for sigma 0.5) * hours/MA/cm2, see spreadsheet

323 CHAPTER 11. APPENDIX

.measure Param_EM_n PARAM=EM_n .measure Param_EM_k PARAM=EM_k .measure Param_EM_A50 PARAM=EM_A50 .measure Param_EM_T PARAM=EM_T .measure EM_t50_hours PARAM=’EM_A50*(EM_Javg_MAcm2**(-EM_n))*exp(EM_Ea/(EM_k*EM_T105C))’ .measure EM_t50_lifetime_hours PARAM=’EM_t50_hours’ .measure EM_t50_lifetime_years PARAM=’EM_t50_hours/(24*365.25)’ .measure EM_t_hours PARAM=’EM_A50*(EM_Javg_MAcm2**(-EM_n))*exp(EM_Ea/(EM_k*EM_T105C))*exp(EM_failure*EM_sigma)’ .measure EM_t_lifetime_hours PARAM=’EM_t_hours’ .measure EM_t_lifetime_years PARAM=’EM_t_hours/(24*365.25)’

.param FALLN = 3 * FALLN = 1 does nothickness give stable results .param RISEN = 3 * RISEN = 1 does not give stable results

.param TestRgate =0.0 .param TestOhms = ’(1+TestRgate)’

* set libfile saed32rvt_ff1p16v125c.db .param TestVdd = ’1.05*(1+VddScale)’ * Input pin D1 report_timing and report_power * R=28.5e7; C=2.9e-16; t=RC=82.649ns; * INVX0 8 fF max load * Wire Cap = 2.9933863e-15, Pin Load = 5 fF, Total = 7.9933863e-15 * .param R1value = 0 * 67.84217 * 28.5e7 * 28.5kohm * 15k ***warning** Capacitance value for element c1 device is 0.000. Capacitance should be a positive, non-zero value. .param C1value = 0.001fF * 2.9933863e-15 * 7.9933863e-15 * 2.9e-16 * 2.9fF * 4fF .param RC = ’R1value*C1value’

.param ClockRise = 0 * 50ps .param ClockFall = 0 * 50ps * 1 MHz = 1e6; period = 1000ns = 1e-6; 10 MHz = 100ns; * 1 GHz = 1e9; period = 1ns = 1e-9 = 1000ps = 1000ps * 5RC is required to fit above the 10% to 90% Vdd boundaries. * 1RC=63.2%, 2RC=86.5%, 3RC=95.0%, 4RC=98.2%, 5RC=99.3% * .param ClockPeriod = 1ns * ’10*RC’ * 100ns will not match Synopsys create_clock! must be long enough for signal to settle down .param ClockTop = ’ClockPeriod/2-ClockRise’ .param CLockOn = ’ClockRise+ClockPeriod/2’ .param CLockOff = ’ClockPeriod/2+ClockFall’ .param TestDelay = ’ClockPeriod*0.5’ .param ClockDelay = TestDelay

.param TestWidth = CLockOn .param TestWindow = ’ClockOn’ .param TestBegin1 = ’TestDelay+Clockoff’ * Rising edge of Clockon .param TestEnd1 = ’TestDelay+Clockoff+Clockon’ * Half clock cycle: Ends at falling edge of Clockon .param TestBegin2 = ’TestDelay+Clockoff+Clockon’ * falling edge of Clockon .param TestEnd2 = ’TestDelay+TestWindow+ClockPeriod’ * Full clock cycle

.param T63 = 0.632120558829 * One time constant = (1-e^-1); .param T10 = 0.105360515658 * = ln(1-0.10) .param T90 = 2.302585093 * = ln(1-0.90) .param T50 = 0.693147180560 * =ln(1-a) = ln(1-0.50) .param RC63 = ’1.0 - 1.0/exp(1.0)’ .param RC37 = ’1.0/exp(1.0)’

324 CHAPTER 11. APPENDIX

* Operating Condition Name: WCCOM * Library: 02_lsi10k_lc, Process: 1.50, Temperature: 70.00, Voltage: 4.75, Interconnect Model: worst_case_tree

* Operating Condition Name : BCCOM * Library: 02_lsi10k_lc, Process: 0.60, Temperature: 0.00, Voltage: 5.25, Interconnect Model : worst_case_tree

.param TestStop = ’ClockDelay+(max(RISEN,FALLN)+1)*ClockPeriod’ * ClockDelay+(must be greater than RISEN)+Guardband

.tran STEP=0.01fs STOP=TestStop

.measure Vdd PARAM=’TestVdd’

.measure param_M1_thickness PARAM=’M1_thickness’ .measure g_W PARAM=’gate_W’ .measure param_R PARAM=’R1value’ .measure param_C PARAM=’C1value’ .measure param_RC PARAM=’RC’ .measure param_ClockRise PARAM=’ClockRise’ .measure param_ClockFall PARAM=’ClockFall’

.measure tRC63_exact PARAM=’R1value*C1value’ .measure tClockPeriod PARAM=’ClockPeriod’ .measure tperiod trig v(C1node) RISE=RISEN val=’TestVdd/2’ targ v(C1node) RISE=RISEN+1 val=’TestVdd/2’ .measure frequency PARAM=’1/tperiod’

.measure vRC63low PARAM=’TestVdd*0.01’ .measure vRC63high PARAM=’TestVdd*RC63’ .measure tRC63rise TRIG v(C1node) RISE=RISEN val=’TestVdd*0.01’ TARG v(C1node) RISE=RISEN val=’TestVdd*RC63’ .measure tRC63fall TRIG v(C1node) FALL=FALLN val=’TestVdd*0.99’ TARG v(C1node) FALL=FALLN val=’TestVdd*RC37’

* complete path: Clk, INVX0, Q1, Cload .measure tpHL TRIG V(clock1node) RISE=RISEN VAL=’TestVdd/2’ TARG V(C1node) FALL=FALLN val=’TestVdd/2’ .measure tpLH TRIG V(clock1node) FALL=FALLN VAL=’TestVdd/2’ TARG V(C1node) RISE=RISEN val=’TestVdd/2’ .measure tp PARAM=’(tpHL+tpLH)/2’ .measure tRC50_exact PARAM=’R1value*C1value*T50’ * =RC*-ln(1/2)

.measure trise TRIG V(C1node) RISE=RISEN val=’TestVdd*0.1’ TARG V(C1node) RISE=RISEN val=’TestVdd*0.9’ .measure tfall TRIG V(C1node) FALL=FALLN val=’TestVdd*0.9’ TARG V(C1node) FALL=FALLN val=’TestVdd*0.1’ .measure ts PARAM=’(trise+tfall)/2’ .measure tRC1090_exact PARAM=’(T90-T10)*R1value*C1value’

.measure I_from PARAM=’TestBegin1’ .measure I_to PARAM=’TestEnd1’ .measure Twindow PARAM=’ClockPeriod/2’ * not used

* INVX0 only .measure TRAN Win_Vavg AVG V(vU1in) FROM=TestBegin1 TO=TestEnd2 .measure Win_Drise TRIG V(CLK1) RISE=RISEN VAL=’TestVdd/2’ TARG V(vU1in) RISE=RISEN val=’TestVdd/2’ .measure Win_Dfall TRIG V(CLK1) FALL=FALLN VAL=’TestVdd/2’ TARG V(vU1in) FALL=FALLN val=’TestVdd/2’ .measure Win_Delay PARAM=’(Win_Drise + Win_Dfall)/2’ .measure U1in_Trise TRIG V(vU1in) RISE=RISEN val=’TestVdd*0.1’ TARG V(vU1in) RISE=RISEN val=’TestVdd*0.9’ .measure U1in_Tfall TRIG V(vU1in) FALL=FALLN val=’TestVdd*0.9’ TARG V(vU1in) FALL=FALLN val=’TestVdd*0.1’ .measure U1in_Ts PARAM=’(U1in_trise + U1in_tfall)/2’

.measure TRAN U1_Vavg AVG V(vU1out) FROM=TestBegin1 TO=TestEnd2

325 CHAPTER 11. APPENDIX

.measure TRAN U1_Iavg AVG I(vU1outdevice) FROM=TestBegin1 TO=TestEnd2 * Average current during switch .measure U1_Pavg PARAM=’U1_Iavg*U1_Vavg’ .measure U1_Javg_Ampm2 PARAM=’U1_Iavg/(M1_thickness*gate_W)’ .measure U1_Javg_MAcm2 PARAM=’(1e-6/(100*100))*U1_Javg_Ampm2’ .measure U1_trise TRIG V(vU1out) RISE=RISEN val=’TestVdd*0.1’ TARG V(vU1out) RISE=RISEN val=’TestVdd*0.9’ .measure U1_tfall TRIG V(vU1out) FALL=FALLN val=’TestVdd*0.9’ TARG V(vU1out) FALL=FALLN val=’TestVdd*0.1’ .measure U1_ts PARAM=’(U1_trise+U1_tfall)/2’ .measure U1_tpHL TRIG V(vU1in) RISE=RISEN VAL=’TestVdd/2’ TARG V(vU1out) FALL=FALLN val=’TestVdd/2’ .measure U1_tpLH TRIG V(vU1in) FALL=FALLN VAL=’TestVdd/2’ TARG V(vU1out) RISE=RISEN val=’TestVdd/2’ .measure U1_tp PARAM=’(U1_tpHL+U1_tpLH)/2’

.measure TRAN U1_Ipos_integ INTEG ’max(I(vU1out),0)’ FROM=TestBegin1 TO=TestEnd2 .measure U1_Ipos PARAM=’U1_Ipos_integ/ClockPeriod’ .measure U1_Ppos PARAM=’U1_Ipos*U1_Vavg’ .measure U1_Ppos_clock PARAM=’C1value*TestVdd^2*(1/ClockPeriod)’ .measure U1_Jpos_Ampm2 PARAM=’U1_Ipos/(M1_thickness*gate_W)’ .measure U1_Jpos_MAcm2 PARAM=’(1e-6/(100*100))*U1_Jpos_Ampm2’

* CLK only .measure TRAN CLK_Vavg AVG V(Clock1node) from=TestBegin1 to=TestEnd2 .measure TRAN CLK_Iavg AVG I(vClock1) from=TestBegin1 to=TestEnd2 .measure CLK_Pavg PARAM=’CLK_Iavg*CLK_Vavg’ .measure CLK_Javg PARAM=’CLK_Iavg/(M1_thickness*gate_W)’ .measure CLK_Javg_Ampm2 PARAM=’CLK_Iavg/(M1_thickness*gate_W)’ .measure CLK_Javg_MAcm2 PARAM=’(1e-6/(100*100))*CLK_Javg_Ampm2’

.measure TRAN CLK_Ipos_integ INTEG ’max(I(vClock1),0)’ FROM=TestBegin1 TO=TestEnd2 .measure CLK_Ipos PARAM=’CLK_Ipos_integ/ClockPeriod’ .measure CLK_Ppos PARAM=’CLK_Ipos*CLK_Vavg’ .measure CLK_Ppos_clock PARAM=’C1value*TestVdd^2*(1/ClockPeriod)’ .measure CLK_Jpos_Ampm2 PARAM=’CLK_Ipos/(M1_thickness*gate_W)’ .measure CLK_Jpos_MAcm2 PARAM=’(1e-6/(100*100))*CLK_Jpos_Ampm2’

.measure TRAN CLK_Ineg INTEG ’min(I(vClock1),0)’ FROM=TestBegin1 TO=TestEnd1 .measure CLK_Pneg PARAM=’CLK_Ineg*TestVdd’ .measure CLK_Jneg_Ampm2 PARAM=’CLK_Ineg/(M1_thickness*gate_W)’ .measure CLK_Jneg_MAcm2 PARAM=’(1e-6/(100*100))*CLK_Jneg_Ampm2’

* Irms = Iavg + Istandard_deviation .measure TRAN CLK_Vrms RMS V(Clock1node) from=TestBegin1 to=TestEnd2 .measure TRAN CLK_Irms RMS I(vClock1) from=TestBegin1 to=TestEnd2 .measure CLK_Prms PARAM=’CLK_Irms*CLK_Vrms’ .measure CLK_Jrms_Ampm2 PARAM=’CLK_Irms/(M1_thickness*gate_W)’ .measure CLK_Jrms_MAcm2 PARAM=’(1e-6/(100*100))*CLK_Jrms_Ampm2’

* Depends on Rise Time .measure TRAN CLK_Imax MAX I(vClock1) from=TestBegin1 to=TestEnd2 * Same as Iopeak, Step-response .measure CLK_Imax_ClockZero_exact PARAM=’TestVdd/R1value’ * Ramp-response, have to know RC from ICC .measure CLK_Imax_ClockRise_exact PARAM=’(RC/ClockRise)*(1-exp(-ClockRise/RC))*(TestVdd/R1value)’ .measure CLK_Pmax PARAM=’CLK_Imax*TestVdd’ .measure CLK_Jmax_Ampm2 PARAM=’CLK_Imax/(M1_thickness*gate_W)’ .measure CLK_Jmax_MAcm2 PARAM=’(1e-6/(100*100))*CLK_Jmax_Ampm2’

326 CHAPTER 11. APPENDIX

.measure TRAN CLK_Imin MIN I(vClock1) from=TestBegin1 to=TestEnd2 .measure CLK_Pmin PARAM=’CLK_Imin*TestVdd’ .measure CLK_Jmin_Ampm2 PARAM=’CLK_Imin/(M1_thickness*gate_W)’

.probe TRAN R1watts =PAR(’I(R1device)*(V(R1node)-V(C1node))’) .probe TRAN C1watts =PAR(’I(C1device)*V(C1node)’) .probe TRAN C1watts2 =PAR(’P(C1device)’) .probe TRAN R1C1watts =PAR(’I(C1device)*V(C1node) + I(R1device)*(V(R1node)-V(C1node))’) .probe TRAN Clockwatts =PAR(’I(Vclock)*V(clock1node)’) * instantaneous power .probe TRAN Clockwatts2=PAR(’P(Vclock)’) .probe TRAN C1volts =PAR(’V(C1node)’) .probe TRAN R1volts =PAR(’V(R1node)-V(C1node)’)

* Vname N1 N2 PULSE(Voff Von Tdelay Trise Tfall Ton Tperiod) VClock Clock1node gnd PULSE(TestVdd 0V ClockDelay ClockRise ClockFall ClockTop ClockPeriod)

* output driver vClock1 Clock1node CLK1 0v vdd0 VDD0P1 gnd TestVdd vdd0Tap VDD0P1 VDD0 0 * Test TAP Point: correct direction of current xINV0 VSS0 VDD0 CLK1 C1node INVX0_SVT * INVX0_SVT_NP vss0Tap VSS0 gnd 0v * Test TAP Point vout0Tap Q1 C1node 0v * Test TAP Point C1device C1node gnd C1value * Cload

* Use two vertical cursors of wave viewer tool to find delay time at 50% point, tpHL, tpLH v50percent v50reference gnd ’TestVdd*0.50’ r50percent v50reference gnd 1e6

* Use two vertical cursors of wave viewer tool to find 10%/90%, rise/fall time v10percent v10reference gnd ’TestVdd*0.10’ r10percent v10reference gnd 1e6 v90percent v90reference gnd ’TestVdd*0.90’ r90percent v90reference gnd 1e6

* Use only for wave viewer to all to plot lines, 63% v63percent v63reference gnd ’TestVdd*0.63’ r63percent v63reference gnd 1e6

.end

327 CHAPTER 11. APPENDIX

11.7 Hspice Simulations

Hspice was use to validate the results of the design space exploration methodology using ICC, eﬀects of timing due to interconnect wire resistance change and to observe the currents in the interconnect wires.

11.7.1 Lifetime Comparisons

Hspice was use to validate the results of the design space exploration methodology using ICC. A ring oscillator was created to observe the eﬀects EM timing to ensure hspice simulation results matched the results generated by ICC. Below is the hspice used in the analysis.

.lib ’saed32nm.lib’ TT

*.TEMP -40 0 25 105 .TEMP 25

.options POST ACCURATE NUMDGT=16 MEASDGT=16 *.TEMP -55 -40 25 55 70 85 105 125

.param VddScale =0.0 * 0=zero percent .param gate_H =95e-9 * 28nm metal thickness (m), Hmin=230nm, Hmax=300nm .param gate_W =50e-9 * metal width (m)

.param EM_n = 1 * current density exponent, n, for copper .param EM_Ea = 0.8 * eV, activation energy, for copper

328 CHAPTER 11. APPENDIX

.param EM_k = 8.61733e-5 * eV/K .param EM_T = ’273.15+125’ * Operating use temperature, 125 Celsius .param EM_sigma = 0.4 * failure deviation .param EM_failure = -3.09 * failute rate, 0.1% .param EM_A50 = 8.95e-6 * = 11.9494e-6 (for sigma 0.5) * hours/MA/cm2, see spreadsheet

.measure EM_Javg_MAcm2 PARAM=’1.194’ .measure EM_T105C PARAM=’273.15+105’ .measure EM_A50_100k_hours PARAM=’100000*(EM_Javg_MAcm2**(EM_n))*exp(-EM_Ea/(EM_k*EM_T105C))*exp(-EM_failure*EM_sigma)’ * Sanity Check, Synopsys 28nm specification for 100k hours at 10 year lifetime .measure Param_EM_Ea PARAM=EM_Ea .measure Param_EM_failure PARAM=EM_failure .measure Param_sigma PARAM=EM_sigma .measure Param_EM_n PARAM=EM_n .measure Param_EM_k PARAM=EM_k .measure Param_EM_A50 PARAM=EM_A50 .measure Param_EM_T PARAM=EM_T .measure EM_t50_hours PARAM=’EM_A50*(EM_Javg_MAcm2**(-EM_n))*exp(EM_Ea/(EM_k*EM_T105C))’ .measure EM_t50_lifetime_hours PARAM=’EM_t50_hours’ .measure EM_t50_lifetime_years PARAM=’EM_t50_hours/(24*365.25)’ .measure EM_t_hours PARAM=’EM_A50*(EM_Javg_MAcm2**(-EM_n))*exp(EM_Ea/(EM_k*EM_T105C))*exp(EM_failure*EM_sigma)’ .measure EM_t_lifetime_hours PARAM=’EM_t_hours’ .measure EM_t_lifetime_years PARAM=’EM_t_hours/(24*365.25)’

.param FALLN = 3 * FALLN = 1 does nothickness give stable results .param RISEN = 3 * RISEN = 1 does not give stable results

.param TestRgate =0.0 .param TestOhms = ’(1+TestRgate)’

329 CHAPTER 11. APPENDIX

* Operating Condition Name: WCCOM * Library: 02_lsi10k_lc, Process: 1.50, Temperature: 70.00, Voltage: 4.75, Interconnect Model: worst_case_tree

* Operating Condition Name : BCCOM * Library: 02_lsi10k_lc, Process: 0.60, Temperature: 0.00, Voltage: 5.25, Interconnect Model : worst_case_tree

.param TestStop = ’ClockDelay+(max(RISEN,FALLN)+1)*ClockPeriod’ * ClockDelay+(must be greater than RISEN)+Guardband

.tran STEP=0.01fs STOP=TestStop

.measure Vdd PARAM=’TestVdd’

.measure I_from PARAM=’TestBegin1’

330 CHAPTER 11. APPENDIX

.measure I_to PARAM=’TestEnd1’ .measure Twindow PARAM=’ClockPeriod/2’ * not used

.measure TRAN U1_Vavg AVG V(vU1out) FROM=TestBegin1 TO=TestEnd2 .measure TRAN U1_Iavg AVG I(vU1outdevice) FROM=TestBegin1 TO=TestEnd2 * Average current during switch .measure U1_Pavg PARAM=’U1_Iavg*U1_Vavg’ .measure U1_Javg_Ampm2 PARAM=’U1_Iavg/(M1_thickness*gate_W)’ .measure U1_Javg_MAcm2 PARAM=’(1e-6/(100*100))*U1_Javg_Ampm2’ .measure U1_trise TRIG V(vU1out) RISE=RISEN val=’TestVdd*0.1’ TARG V(vU1out) RISE=RISEN val=’TestVdd*0.9’ .measure U1_tfall TRIG V(vU1out) FALL=FALLN val=’TestVdd*0.9’ TARG V(vU1out) FALL=FALLN val=’TestVdd*0.1’ .measure U1_ts PARAM=’(U1_trise+U1_tfall)/2’ .measure U1_tpHL TRIG V(vU1in) RISE=RISEN VAL=’TestVdd/2’ TARG V(vU1out) FALL=FALLN val=’TestVdd/2’ .measure U1_tpLH TRIG V(vU1in) FALL=FALLN VAL=’TestVdd/2’ TARG V(vU1out) RISE=RISEN val=’TestVdd/2’ .measure U1_tp PARAM=’(U1_tpHL+U1_tpLH)/2’

331 CHAPTER 11. APPENDIX

.measure CLK_Jrms_Ampm2 PARAM=’CLK_Irms/(M1_thickness*gate_W)’ .measure CLK_Jrms_MAcm2 PARAM=’(1e-6/(100*100))*CLK_Jrms_Ampm2’

.measure TRAN CLK_Imin MIN I(vClock1) from=TestBegin1 to=TestEnd2 .measure CLK_Pmin PARAM=’CLK_Imin*TestVdd’ .measure CLK_Jmin_Ampm2 PARAM=’CLK_Imin/(M1_thickness*gate_W)’

* Vname N1 N2 PULSE(Voff Von Tdelay Trise Tfall Ton Tperiod) VClock Clock1node gnd PULSE(TestVdd 0V ClockDelay ClockRise ClockFall ClockTop ClockPeriod)

* Use two vertical cursors of wave viewer tool to find delay time at 50% point, tpHL, tpLH v50percent v50reference gnd ’TestVdd*0.50’ r50percent v50reference gnd 1e6

* Use only for wave viewer to all to plot lines, 63% v63percent v63reference gnd ’TestVdd*0.63’ r63percent v63reference gnd 1e6

.end

332 CHAPTER 11. APPENDIX

Hspice Schematics

Figure 11.1 is the schematic for the 28/32nm inverter. Figure 11.2 and 11.3 show the schematics for the 90nm inverter. Figures 11.4 and 11.5 are the schematic for the NAND gate, and Figure 11.6 is the NOR gate for 90nm used in the simulations. The two libraries were used for comparisons in performance between 28/32nm and 90nm.

Figure 11.1: 28/32nm LVT Inverter 0.5 Drive Schematic

333 CHAPTER 11. APPENDIX

Figure 11.2: 90nm LVT Inverter Schematic

Figure 11.3: 90nm LVT Inverter Schematic with Capicitors

334 CHAPTER 11. APPENDIX

Figure 11.4: 28/32nm LVT NAND2 Schematic

335 CHAPTER 11. APPENDIX

Figure 11.5: 90nm LVT NAND2 Schematic

Figure 11.6: 90nm LVT NOR Schematic

336 CHAPTER 11. APPENDIX

11.7.2 Hspice Resistance Sweeps

The ring oscillator was created using the Synopsys PDK 28/32nm and 90nm Physical Design Kits (PDK) using inverters, NOR gates and NAND gates. Schematics were created from the hspice models in the PDK schematics to understand the gate models. These helped understand the affects the changes in resistance, capacitance and currents in the nets effect delays and lifetimes. An example hspice file used is listed below.

* Design file: hspice_32nm_Driver1_INVX0_Sweep_Vdd_Parasitic.spp * Transient Waveforms in file: hspice_32nm_Driver1_INVX0_Sweep_Vdd_Parasitic.tr0 .tr1 .tr2 .tr3 .tr4 .tr5 .tr6 * Measure output in file: hspice_32nm_Driver1_INVX0_Sweep_Vdd_Parasitic.ms0 .ms1 .ms2 .ms3 .ms4 .ms5 .ms6 (Use Waveform, wv)

.lib ’saed32nm.lib’ TT

*.options post relvar=.05 *.options POST ACCURATE NUMDGT=16 INGOLD=2 MEASDGT=16 *.options POST ACCURATE NUMDGT=16 MEASDGT=16 .options POST ACCURATE NUMDGT=16 MEASDGT=16

*.TEMP -40 0 25 105 *.TEMP -55 -40 25 55 70 85 105 125

.param TestVtp =0.0 .param TestVtn =0.0 .param TestRgate =0.0 .param VddScale =0.0 * 0=zero percent .param gate_node =32nm * Technology node .param gate_process =0 * 0=TT, 1=SS, 2=SF, 3=FS, 4=FF .param gate_netlist =1 * 1=parasitic, 2=nonparastic .param gate_threshold =1 * 1=LVT, 2=SVT, 3=HVT .param gate_type =1 * 1=INVERTER, 2=NAND, 3=NOR .param gate_drive =0.5 * 0.5x Drive Strength .param gate_input =1 * 1=A input, 2=B input, 12=AB input both driven .param gate_design =2 * 1=INTRINSIC, 2=RING, 3=RINGNOLOAD .param gate_base_cmp =5 * 0=use last run 1=within SWEEP .param gate_H =230e-9 * metal thickness (m), Hmin=230nm, Hmax=300nm .param gate_W =140e-9 * metal width (m)

.param TestVdd = ’1.05*(1+VddScale)’ .param TestOhms = ’(1+TestRgate)’

337 CHAPTER 11. APPENDIX

.param TestCaps = 1

.param FALLN = 3 * FALLN = 1 does not give stable results .param RISEN = 3 * RISEN = 1 does not give stable results .param RINGN = 11 * Must be ODD Number of Stages

.param TestDelay = 0.1ns .param TestStop = 20.0ns * invx0_hvt is slow needs 10ns at -0.15 volts

* .tran STEP=1p STOP=TestStop SWEEP TestRise POI 7 1fs 10fs 100fs 1000fs 10000fs 100000fs 1000000fs * 1fs gives 30 Amps for Idd of inverter! * 100fs gives 0.6mA for Idd *.tran STEP=1f STOP=TestStop SWEEP TestRgate POI 9 0.4 0.3 0.2 0.1 0.00 -0.10 -0.20 -0.30 -0.40 * femtofarad .tran STEP=1f STOP=TestStop SWEEP VddScale POI 9 0.2 0.15 0.1 0.05 0.0 -0.05 -0.10 -0.15 -0.20 .tran STEP=1p STOP=TestStop SWEEP VddScale POI 9 0.2 0.15 0.1 0.05 0.0 -0.05 -0.10 -0.15 -0.20

*.probe TRANS pmos_U0 = par(’valm(xINV0.mm1.u0)’) *.probe TRANS nmos_U0 = par(’valm(xINV0.mm2.u0)’) *.probe TRANS Ratio_U0p_U0n = par(’(valm(xINV0.mm1.u0)/(valm(xINV0.mm2.u0)))’) *.probe TRANS Ratio_Wp_Wn = par(’(valm(xINV0.mm1.W)/(valm(xINV0.mm2.W)))’) *.probe TRANS Beta_Wp_Wn = par(’(valm(xINV0.mm1.u0)/valm(xINV0.mm2.u0))*(valm(xINV0.mm1.W)/valm(xINV0.mm2.W))’)

.measure pmos_Leff_lv1 PARAM=’lv1(xinv0.xmp)’ * Leff .measure pmos_Weff_lv2 PARAM=’lv2(xinv0.xmp)’ * Weff .measure nmos_Leff_lv1 PARAM=’lv1(xinv0.xmn)’ * Leff .measure nmos_Weff_lv2 PARAM=’lv2(xinv0.xmn)’ * Weff

.measure pmos_Leff_lx63 PARAM=’lx65(xinv0.xmp)’ * Leff .measure pmos_Weff_lx62 PARAM=’lx64(xinv0.xmp)’ * Weff .measure nmos_Leff_lx63 PARAM=’lx65(xinv0.xmn)’ * Leff .measure nmos_Weff_lx62 PARAM=’lx64(xinv0.xmn)’ * Weff

.measure g_drive PARAM=’gate_drive’ .measure g_type PARAM=’gate_type’ .measure g_input PARAM=’gate_input’ .measure g_node PARAM=’gate_node’ .measure g_process PARAM=’gate_process’ .measure g_netlist PARAM=’gate_netlist’ .measure g_threshold PARAM=’gate_threshold’ .measure g_Vdd PARAM=’TestVdd’ .measure g_VddScale PARAM=’VddScale’ .measure g_VtpScale PARAM=’TestVtp’ .measure g_VtnScale PARAM=’TestVtn’ .measure g_Rgate PARAM=’TestRgate’ .measure g_design PARAM=’gate_design’ .measure g_base_cmp PARAM=’gate_base_cmp’ .measure g_H PARAM=’gate_H’ .measure g_W PARAM=’gate_W’

.measure v_testVdd PARAM=’TestVdd’ .measure v_testVdd2 PARAM=’TestVdd/2’

.measure tperiod0 trig v(out0) RISE=RISEN val=’TestVdd/2’ targ v(out0) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod1 trig v(out1) RISE=RISEN val=’TestVdd/2’ targ v(out1) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod2 trig v(out2) RISE=RISEN val=’TestVdd/2’ targ v(out2) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod3 trig v(out3) RISE=RISEN val=’TestVdd/2’ targ v(out3) RISE=RISEN+1 val=’TestVdd/2’

338 CHAPTER 11. APPENDIX

.measure tperiod4 trig v(out4) RISE=RISEN val=’TestVdd/2’ targ v(out4) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod5 trig v(out5) RISE=RISEN val=’TestVdd/2’ targ v(out5) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod6 trig v(out6) RISE=RISEN val=’TestVdd/2’ targ v(out6) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod7 trig v(out7) RISE=RISEN val=’TestVdd/2’ targ v(out7) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod8 trig v(out8) RISE=RISEN val=’TestVdd/2’ targ v(out8) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod9 trig v(out9) RISE=RISEN val=’TestVdd/2’ targ v(out9) RISE=RISEN+1 val=’TestVdd/2’ .measure tperiod_AVG PARAM=’(tperiod0+tperiod1+tperiod2+tperiod3+tperiod4+tperiod5+tperiod6+tperiod7+tperiod8+tperiod9)/10’ .measure f_period_AVG PARAM=’1/tperiod_AVG’

.measure tpHL0 trig v(in0) RISE=RISEN val=’TestVdd/2’ targ v(out0) FALL=FALLN val=’TestVdd/2’ .measure tpHL1 trig v(out0) RISE=RISEN val=’TestVdd/2’ targ v(out1) FALL=FALLN val=’TestVdd/2’ .measure tpHL2 trig v(out1) RISE=RISEN val=’TestVdd/2’ targ v(out2) FALL=FALLN val=’TestVdd/2’ .measure tpHL3 trig v(out2) RISE=RISEN val=’TestVdd/2’ targ v(out3) FALL=FALLN val=’TestVdd/2’ .measure tpHL4 trig v(out3) RISE=RISEN val=’TestVdd/2’ targ v(out4) FALL=FALLN val=’TestVdd/2’ .measure tpHL5 trig v(out4) RISE=RISEN val=’TestVdd/2’ targ v(out5) FALL=FALLN val=’TestVdd/2’ .measure tpHL6 trig v(out5) RISE=RISEN val=’TestVdd/2’ targ v(out6) FALL=FALLN val=’TestVdd/2’ .measure tpHL7 trig v(out6) RISE=RISEN val=’TestVdd/2’ targ v(out7) FALL=FALLN val=’TestVdd/2’ .measure tpHL8 trig v(out7) RISE=RISEN val=’TestVdd/2’ targ v(out8) FALL=FALLN val=’TestVdd/2’ .measure tpHL9 trig v(out8) RISE=RISEN val=’TestVdd/2’ targ v(out9) FALL=FALLN val=’TestVdd/2’ .measure tpHL_AVG PARAM=’(tpHL0+tpHL1+tpHL2+tpHL3+tpHL4+tpHL5+tpHL6+tpHL7+tpHL8+tpHL9)/10’

.measure tpLH0 trig v(in0) FALL=FALLN val=’TestVdd/2’ targ v(out0) RISE=RISEN val=’TestVdd/2’ .measure tpLH1 trig v(out0) FALL=FALLN val=’TestVdd/2’ targ v(out1) RISE=RISEN val=’TestVdd/2’ .measure tpLH2 trig v(out1) FALL=FALLN val=’TestVdd/2’ targ v(out2) RISE=RISEN val=’TestVdd/2’ .measure tpLH3 trig v(out2) FALL=FALLN val=’TestVdd/2’ targ v(out3) RISE=RISEN val=’TestVdd/2’ .measure tpLH4 trig v(out3) FALL=FALLN val=’TestVdd/2’ targ v(out4) RISE=RISEN val=’TestVdd/2’ .measure tpLH5 trig v(out4) FALL=FALLN val=’TestVdd/2’ targ v(out5) RISE=RISEN val=’TestVdd/2’ .measure tpLH6 trig v(out5) FALL=FALLN val=’TestVdd/2’ targ v(out6) RISE=RISEN val=’TestVdd/2’ .measure tpLH7 trig v(out6) FALL=FALLN val=’TestVdd/2’ targ v(out7) RISE=RISEN val=’TestVdd/2’ .measure tpLH8 trig v(out7) FALL=FALLN val=’TestVdd/2’ targ v(out8) RISE=RISEN val=’TestVdd/2’ .measure tpLH9 trig v(out8) FALL=FALLN val=’TestVdd/2’ targ v(out9) RISE=RISEN val=’TestVdd/2’ .measure tpLH_AVG PARAM=’(tpLH0+tpLH1+tpLH2+tpLH3+tpLH4+tpLH5+tpLH6+tpLH7+tpLH8+tpLH9)/10’ .measure tpBeta_np PARAM=’tpLH_AVG/tpHL_AVG’

.measure tp0 PARAM=’(tpHL0+tpLH0)/2’ .measure tp1 PARAM=’(tpHL1+tpLH1)/2’ .measure tp2 PARAM=’(tpHL2+tpLH2)/2’ .measure tp3 PARAM=’(tpHL3+tpLH3)/2’ .measure tp4 PARAM=’(tpHL4+tpLH4)/2’ .measure tp5 PARAM=’(tpHL5+tpLH5)/2’ .measure tp6 PARAM=’(tpHL6+tpLH6)/2’ .measure tp7 PARAM=’(tpHL7+tpLH7)/2’ .measure tp8 PARAM=’(tpHL8+tpLH8)/2’ .measure tp9 PARAM=’(tpHL9+tpLH9)/2’ *.measure tp_AVG PARAM=’(tp0+tp1+tp2+tp3+tp4+tp5+tp6+tp7+tp8+tp9)/10’ .measure tp_AVG PARAM=’(tpHL_AVG+tpLH_AVG)/2’

.measure tsrise0 TRIG V(out0) RISE=RISEN val=’TestVdd*0.1’ TARG V(out0) RISE=RISEN val=’TestVdd*0.9’ .measure tsrise1 TRIG V(out1) RISE=RISEN val=’TestVdd*0.1’ TARG V(out1) RISE=RISEN val=’TestVdd*0.9’ .measure tsrise2 TRIG V(out2) RISE=RISEN val=’TestVdd*0.1’ TARG V(out2) RISE=RISEN val=’TestVdd*0.9’ .measure tsrise3 TRIG V(out3) RISE=RISEN val=’TestVdd*0.1’ TARG V(out3) RISE=RISEN val=’TestVdd*0.9’ .measure tsrise4 TRIG V(out4) RISE=RISEN val=’TestVdd*0.1’ TARG V(out4) RISE=RISEN val=’TestVdd*0.9’ .measure tsrise5 TRIG V(out5) RISE=RISEN val=’TestVdd*0.1’ TARG V(out5) RISE=RISEN val=’TestVdd*0.9’ .measure tsrise_AVG PARAM=’(tsrise0+tsrise1+tsrise2+tsrise3+tsrise4+tsrise5)/6’

.measure tsfall0 TRIG V(out0) FALL=FALLN val=’TestVdd*0.9’ TARG V(out0) FALL=FALLN val=’TestVdd*0.1’

339 CHAPTER 11. APPENDIX

.measure tsfall1 TRIG V(out1) FALL=FALLN val=’TestVdd*0.9’ TARG V(out1) FALL=FALLN val=’TestVdd*0.1’ .measure tsfall2 TRIG V(out2) FALL=FALLN val=’TestVdd*0.9’ TARG V(out2) FALL=FALLN val=’TestVdd*0.1’ .measure tsfall3 TRIG V(out3) FALL=FALLN val=’TestVdd*0.9’ TARG V(out3) FALL=FALLN val=’TestVdd*0.1’ .measure tsfall4 TRIG V(out4) FALL=FALLN val=’TestVdd*0.9’ TARG V(out4) FALL=FALLN val=’TestVdd*0.1’ .measure tsfall5 TRIG V(out5) FALL=FALLN val=’TestVdd*0.9’ TARG V(out5) FALL=FALLN val=’TestVdd*0.1’ .measure tsfall_AVG PARAM=’(tsfall0+tsfall1+tsfall2+tsfall3+tsfall4+tsfall5)/6’ .measure tsBeta_np PARAM=’tsrise_AVG/tsfall_AVG’

.measure ts0 PARAM=’(tsrise0+tsfall0)/2’ .measure ts1 PARAM=’(tsrise1+tsfall1)/2’ .measure ts2 PARAM=’(tsrise2+tsfall2)/2’ .measure ts3 PARAM=’(tsrise2+tsfall2)/2’ .measure ts4 PARAM=’(tsrise2+tsfall2)/2’ .measure ts5 PARAM=’(tsrise2+tsfall2)/2’ *.measure ts_AVG PARAM=’(ts0+ts1+ts2+ts3+ts4+ts5)/6’ .measure ts_AVG PARAM=’(tsrise_AVG+tsfall_AVG)/2’

.measure TRAN Iomax0 MAX I(vwire0) from=TestDelay to=TestStop .measure TRAN Iomax1 MAX I(vwire1) from=TestDelay to=TestStop .measure TRAN Iomax2 MAX I(vwire2) from=TestDelay to=TestStop .measure TRAN Iomax3 MAX I(vwire3) from=TestDelay to=TestStop .measure TRAN Iomax4 MAX I(vwire4) from=TestDelay to=TestStop .measure TRAN Iomax5 MAX I(vwire5) from=TestDelay to=TestStop .measure Iomax_AVG PARAM=’(Iomax0+Iomax1+Iomax2+Iomax3+Iomax4+Iomax5)/6’ .measure Jomax_AVG PARAM=’Iomax_AVG/(gate_H*gate_W)’

.measure TRAN Iomin0 MIN I(vwire0) from=TestDelay to=TestStop .measure TRAN Iomin1 MIN I(vwire1) from=TestDelay to=TestStop .measure TRAN Iomin2 MIN I(vwire2) from=TestDelay to=TestStop .measure TRAN Iomin3 MIN I(vwire3) from=TestDelay to=TestStop .measure TRAN Iomin4 MIN I(vwire4) from=TestDelay to=TestStop .measure TRAN Iomin5 MIN I(vwire5) from=TestDelay to=TestStop .measure Iomin_AVG PARAM=’(Iomin0+Iomin1+Iomin2+Iomin3+Iomin4+Iomin5)/6’ .measure Jomin_AVG PARAM=’Iomin_AVG/(gate_H*gate_W)’

.measure TRAN Ioavg0 AVG I(vwire0) from=TestDelay to=TestStop .measure TRAN Ioavg1 AVG I(vwire1) from=TestDelay to=TestStop .measure TRAN Ioavg2 AVG I(vwire2) from=TestDelay to=TestStop .measure TRAN Ioavg3 AVG I(vwire3) from=TestDelay to=TestStop .measure TRAN Ioavg4 AVG I(vwire4) from=TestDelay to=TestStop .measure TRAN Ioavg5 AVG I(vwire5) from=TestDelay to=TestStop .measure Ioavg_AVG PARAM=’(Ioavg0+Ioavg1+Ioavg2+Ioavg3+Ioavg4+Ioavg5)/6’ .measure Joavg_AVG PARAM=’Ioavg_AVG/(gate_H*gate_W)’ *.measure TRAN Ioavg_AVG AVG I(vwire5) from=TestDelay to=TestStop *.measure TRAN Joavg_AVG1 INTEG I(vwire5) from=TestDelay to=TestStop *.measure Joavg_AVG PARAM=’Joavg_AVG1/(TestStop-TestDelay)’

.measure TRAN Iopos0 INTEG ’max(I(vwire0),0)’ from=TestDelay to=TestStop .measure TRAN Iopos1 INTEG ’max(I(vwire1),0)’ from=TestDelay to=TestStop .measure TRAN Iopos2 INTEG ’max(I(vwire2),0)’ from=TestDelay to=TestStop .measure TRAN Iopos3 INTEG ’max(I(vwire3),0)’ from=TestDelay to=TestStop .measure TRAN Iopos4 INTEG ’max(I(vwire4),0)’ from=TestDelay to=TestStop .measure TRAN Iopos5 INTEG ’max(I(vwire5),0)’ from=TestDelay to=TestStop .measure Iopos_AVG PARAM=’(Iopos0+Iopos1+Iopos2+Iopos3+Iopos4+Iopos5)/(6*(TestStop-TestDelay))’ .measure Jopos_AVG PARAM=’Iopos_AVG/(gate_H*gate_W)’

340 CHAPTER 11. APPENDIX

.measure TRAN Ioneg0 INTEG ’min(I(vwire0),0)’ from=TestDelay to=TestStop .measure TRAN Ioneg1 INTEG ’min(I(vwire1),0)’ from=TestDelay to=TestStop .measure TRAN Ioneg2 INTEG ’min(I(vwire2),0)’ from=TestDelay to=TestStop .measure TRAN Ioneg3 INTEG ’min(I(vwire3),0)’ from=TestDelay to=TestStop .measure TRAN Ioneg4 INTEG ’min(I(vwire4),0)’ from=TestDelay to=TestStop .measure TRAN Ioneg5 INTEG ’min(I(vwire5),0)’ from=TestDelay to=TestStop .measure Ioneg_AVG PARAM=’(Ioneg0+Ioneg1+Ioneg2+Ioneg3+Ioneg4+Ioneg5)/(6*(TestStop-TestDelay))’ .measure Joneg_AVG PARAM=’Ioneg_AVG/(gate_H*gate_W)’

.measure TRAN Iorms0 RMS I(vwire0) from=TestDelay to=TestStop .measure TRAN Iorms1 RMS I(vwire1) from=TestDelay to=TestStop .measure TRAN Iorms2 RMS I(vwire2) from=TestDelay to=TestStop .measure TRAN Iorms3 RMS I(vwire3) from=TestDelay to=TestStop .measure TRAN Iorms4 RMS I(vwire4) from=TestDelay to=TestStop .measure TRAN Iorms5 RMS I(vwire5) from=TestDelay to=TestStop .measure Iorms_AVG PARAM=’(Iorms0+Iorms1+Iorms2+Iorms3+Iorms4+Iorms5)/6’ .measure Jorms_AVG PARAM=’Iorms_AVG/(gate_H*gate_W)’

.measure TRAN Idmax0 MAX I(vdd0) from=TestDelay to=TestStop .measure TRAN Idmax1 MAX I(vdd1) from=TestDelay to=TestStop .measure TRAN Idmax2 MAX I(vdd2) from=TestDelay to=TestStop .measure TRAN Idmax3 MAX I(vdd3) from=TestDelay to=TestStop .measure TRAN Idmax4 MAX I(vdd4) from=TestDelay to=TestStop .measure TRAN Idmax5 MAX I(vdd5) from=TestDelay to=TestStop .measure Idmax_AVG PARAM=’(Idmax0+Idmax1+Idmax2+Idmax3+Idmax4+Idmax5)/6’ .measure Jdmax_AVG PARAM=’Idmax_AVG/(gate_H*gate_W)’

.measure TRAN Idmin0 MIN I(vdd0) from=TestDelay to=TestStop .measure TRAN Idmin1 MIN I(vdd1) from=TestDelay to=TestStop .measure TRAN Idmin2 MIN I(vdd2) from=TestDelay to=TestStop .measure TRAN Idmin3 MIN I(vdd3) from=TestDelay to=TestStop .measure TRAN Idmin4 MIN I(vdd4) from=TestDelay to=TestStop .measure TRAN Idmin5 MIN I(vdd5) from=TestDelay to=TestStop .measure Idmin_AVG PARAM=’(Idmin0+Idmin1+Idmin2+Idmin3+Idmin4+Idmin5)/6’ .measure Jdmin_AVG PARAM=’Idmin_AVG/(gate_H*gate_W)’

.measure TRAN Idavg0 AVG I(vdd0) from=TestDelay to=TestStop .measure TRAN Idavg1 AVG I(vdd1) from=TestDelay to=TestStop .measure TRAN Idavg2 AVG I(vdd2) from=TestDelay to=TestStop .measure TRAN Idavg3 AVG I(vdd3) from=TestDelay to=TestStop .measure TRAN Idavg4 AVG I(vdd4) from=TestDelay to=TestStop .measure TRAN Idavg5 AVG I(vdd5) from=TestDelay to=TestStop .measure Idavg_AVG PARAM=’(Idavg0+Idavg1+Idavg2+Idavg3+Idavg4+Idavg5)/6’ .measure Jdavg_AVG PARAM=’Idavg_AVG/(gate_H*gate_W)’

.measure TRAN Idrms0 RMS I(vdd0) from=TestDelay to=TestStop .measure TRAN Idrms1 RMS I(vdd1) from=TestDelay to=TestStop .measure TRAN Idrms2 RMS I(vdd2) from=TestDelay to=TestStop .measure TRAN Idrms3 RMS I(vdd3) from=TestDelay to=TestStop .measure TRAN Idrms4 RMS I(vdd4) from=TestDelay to=TestStop .measure TRAN Idrms5 RMS I(vdd5) from=TestDelay to=TestStop .measure Idrms_AVG PARAM=’(Idrms0+Idrms1+Idrms2+Idrms3+Idrms4+Idrms5)/6’ .measure Jdrms_AVG PARAM=’Idrms_AVG/(gate_H*gate_W)’

.measure TRAN Idpos0 INTEG ’max(I(vdd0),0)’ from=TestDelay to=TestStop .measure TRAN Idpos1 INTEG ’max(I(vdd1),0)’ from=TestDelay to=TestStop

341 CHAPTER 11. APPENDIX

.measure TRAN Idpos2 INTEG ’max(I(vdd2),0)’ from=TestDelay to=TestStop .measure TRAN Idpos3 INTEG ’max(I(vdd3),0)’ from=TestDelay to=TestStop .measure TRAN Idpos4 INTEG ’max(I(vdd4),0)’ from=TestDelay to=TestStop .measure TRAN Idpos5 INTEG ’max(I(vdd5),0)’ from=TestDelay to=TestStop .measure Idpos_AVG PARAM=’(Idpos0+Idpos1+Idpos2+Idpos3+Idpos4+Idpos5)/(6*(TestStop-TestDelay))’ .measure Jdpos_AVG PARAM=’Idpos_AVG/(gate_H*gate_W)’

.measure TRAN Idneg0 INTEG ’min(I(vdd0),0)’ from=TestDelay to=TestStop .measure TRAN Idneg1 INTEG ’min(I(vdd1),0)’ from=TestDelay to=TestStop .measure TRAN Idneg2 INTEG ’min(I(vdd2),0)’ from=TestDelay to=TestStop .measure TRAN Idneg3 INTEG ’min(I(vdd3),0)’ from=TestDelay to=TestStop .measure TRAN Idneg4 INTEG ’min(I(vdd4),0)’ from=TestDelay to=TestStop .measure TRAN Idneg5 INTEG ’min(I(vdd5),0)’ from=TestDelay to=TestStop .measure Idneg_AVG PARAM=’(Idneg0+Idneg1+Idneg2+Idneg3+Idneg4+Idneg5)/(6*(TestStop-TestDelay))’ .measure Jdneg_AVG PARAM=’Idneg_AVG/(gate_H*gate_W)’

.measure TRAN tLH_Beg0 WHEN v(in0)=’TestVdd*0.950’ FALL=FALLN .measure TRAN tLH_End0 WHEN v(out0)=’TestVdd/2’ RISE=RISEN .measure TRAN tLH_Beg1 WHEN v(out0)=’TestVdd*0.950’ FALL=FALLN .measure TRAN tLH_End1 WHEN v(out1)=’TestVdd/2’ RISE=RISEN .measure TRAN tLH_Beg2 WHEN v(out1)=’TestVdd*0.950’ FALL=FALLN .measure TRAN tLH_End2 WHEN v(out2)=’TestVdd/2’ RISE=RISEN .measure TRAN tLH_Beg3 WHEN v(out2)=’TestVdd*0.950’ FALL=FALLN .measure TRAN tLH_End3 WHEN v(out3)=’TestVdd/2’ RISE=RISEN .measure TRAN tLH_Beg4 WHEN v(out3)=’TestVdd*0.950’ FALL=FALLN .measure TRAN tLH_End4 WHEN v(out4)=’TestVdd/2’ RISE=RISEN .measure TRAN tLH_Beg5 WHEN v(out4)=’TestVdd*0.950’ FALL=FALLN .measure TRAN tLH_End5 WHEN v(out5)=’TestVdd/2’ RISE=RISEN

.measure TRAN ILH_avg0 AVG I(vdd0) from=tLH_Beg0 to=tLH_End0 .measure TRAN ILH_avg1 AVG I(vdd1) from=tLH_Beg1 to=tLH_End1 .measure TRAN ILH_avg2 AVG I(vdd2) from=tLH_Beg2 to=tLH_End2 .measure TRAN ILH_avg3 AVG I(vdd3) from=tLH_Beg3 to=tLH_End3 .measure TRAN ILH_avg4 AVG I(vdd4) from=tLH_Beg4 to=tLH_End4 .measure TRAN ILH_avg5 AVG I(vdd5) from=tLH_Beg5 to=tLH_End5

.measure ILH_AVG PARAM=’(ILH_avg3+ILH_avg4+ILH_avg5)/3’

.measure TRAN tHL_Beg0 WHEN v(in0)=’TestVdd*0.050’ RISE=RISEN .measure TRAN tHL_End0 WHEN v(out0)=’TestVdd/2’ FALL=FALLN .measure TRAN tHL_Beg1 WHEN v(out0)=’TestVdd*0.050’ RISE=RISEN .measure TRAN tHL_End1 WHEN v(out1)=’TestVdd/2’ FALL=FALLN .measure TRAN tHL_Beg2 WHEN v(out1)=’TestVdd*0.050’ RISE=RISEN .measure TRAN tHL_End2 WHEN v(out2)=’TestVdd/2’ FALL=FALLN .measure TRAN tHL_Beg3 WHEN v(out2)=’TestVdd*0.050’ RISE=RISEN .measure TRAN tHL_End3 WHEN v(out3)=’TestVdd/2’ FALL=FALLN .measure TRAN tHL_Beg4 WHEN v(out3)=’TestVdd*0.050’ RISE=RISEN .measure TRAN tHL_End4 WHEN v(out4)=’TestVdd/2’ FALL=FALLN .measure TRAN tHL_Beg5 WHEN v(out4)=’TestVdd*0.050’ RISE=RISEN .measure TRAN tHL_End5 WHEN v(out5)=’TestVdd/2’ FALL=FALLN

.measure TRAN IHL_avg0 AVG I(vdd0) from=tHL_Beg0 to=tHL_End0 .measure TRAN IHL_avg1 AVG I(vdd1) from=tHL_Beg1 to=tHL_End1 .measure TRAN IHL_avg2 AVG I(vdd2) from=tHL_Beg2 to=tHL_End2 .measure TRAN IHL_avg3 AVG I(vdd3) from=tHL_Beg3 to=tHL_End3 .measure TRAN IHL_avg4 AVG I(vdd4) from=tHL_Beg4 to=tHL_End4

342 CHAPTER 11. APPENDIX

.measure TRAN IHL_avg5 AVG I(vdd5) from=tHL_Beg5 to=tHL_End5

.measure IHL_AVG PARAM=’(IHL_avg3+IHL_avg4+IHL_avg5)/3’

.measure TRAN ILH_rms0 RMS I(vdd0) from=tLH_Beg0 to=tLH_End0 .measure TRAN ILH_rms1 RMS I(vdd1) from=tLH_Beg1 to=tLH_End1 .measure TRAN ILH_rms2 RMS I(vdd2) from=tLH_Beg2 to=tLH_End2 .measure TRAN ILH_rms3 RMS I(vdd3) from=tLH_Beg3 to=tLH_End3 .measure TRAN ILH_rms4 RMS I(vdd4) from=tLH_Beg4 to=tLH_End4 .measure TRAN ILH_rms5 RMS I(vdd5) from=tLH_Beg5 to=tLH_End5

.measure ILH_RMS PARAM=’(ILH_rms3+ILH_rms4+ILH_rms5)/3’

.measure TRAN IHL_rms0 RMS I(vdd0) from=tHL_Beg0 to=tHL_End0 .measure TRAN IHL_rms1 RMS I(vdd1) from=tHL_Beg1 to=tHL_End1 .measure TRAN IHL_rms2 RMS I(vdd2) from=tHL_Beg2 to=tHL_End2 .measure TRAN IHL_rms3 RMS I(vdd3) from=tHL_Beg3 to=tHL_End3 .measure TRAN IHL_rms4 RMS I(vdd4) from=tHL_Beg4 to=tHL_End4 .measure TRAN IHL_rms5 RMS I(vdd5) from=tHL_Beg5 to=tHL_End5

.measure IHL_RMS PARAM=’(IHL_rms3+IHL_rms4+IHL_rms5)/3’

.measure ILH_Cload PARAM=’ILH_AVG*tpLH_AVG/(TestVdd/2)’ .measure IHL_Cload PARAM=’IHL_AVG*tpHL_AVG/(TestVdd/2)’ .measure f_ring PARAM=’1/(2*RINGN*tp_AVG)’ .measure f_max PARAM=’1/(tsrise_AVG+tsfall_AVG)’

.IC V(in0) = 0 .IC V(in1) = TestVdd .IC V(in2) = 0v .IC V(in3) = TestVdd .IC V(in4) = 0v .IC V(in5) = TestVdd .IC V(in6) = 0v .IC V(in7) = TestVdd .IC V(in8) = 0v .IC V(in9) = TestVdd vHighP High gnd TestVdd

* output driver vdd0P VDD0P gnd TestVdd vdd0 VDD0P VDD0 0 * correct direction of current xINV0 VSS0 VDD0 in0 out0 INVX0_LVT vss0 VSS0 gnd 0v vwire0 out0 in1 0v vdd1P VDD1P gnd TestVdd vdd1 VDD1P VDD1 0 * correct direction of current xINV1 VSS1 VDD1 in1 out1 INVX0_LVT vss1 VSS1 gnd 0v vwire1 out1 in2 0v vdd2P VDD2P gnd TestVdd vdd2 VDD2P VDD2 0 * correct direction of current xINV2 VSS2 VDD2 in2 out2 INVX0_LVT

343 CHAPTER 11. APPENDIX

vss2 VSS2 gnd 0v vwire2 out2 in3 0v

vdd3P VDD3P gnd TestVdd vdd3 VDD3P VDD3 0 * correct direction of current xINV3 VSS3 VDD3 in3 out3 INVX0_LVT vss3 VSS3 gnd 0v vwire3 out3 in4 0v

vdd4P VDD4P gnd TestVdd vdd4 VDD4P VDD4 0 * correct direction of current xINV4 VSS4 VDD4 in4 out4 INVX0_LVT vss4 VSS4 gnd 0v vwire4 out4 in5 0v

vdd5P VDD5P gnd TestVdd vdd5 VDD5P VDD5 0 * correct direction of current xINV5 VSS5 VDD5 in5 out5 INVX0_LVT vss5 VSS5 gnd 0v vwire5 out5 in6 0v

vdd6P VDD6P gnd TestVdd vdd6 VDD6P VDD6 0 * correct direction of current xINV6 VSS6 VDD6 in6 out6 INVX0_LVT vss6 VSS6 gnd 0v vwire6 out6 in7 0v

vdd7P VDD7P gnd TestVdd vdd7 VDD7P VDD7 0 * correct direction of current xINV7 VSS7 VDD7 in7 out7 INVX0_LVT vss7 VSS7 gnd 0v vwire7 out7 in8 0v

vdd8P VDD8P gnd TestVdd vdd8 VDD8P VDD8 0 * correct direction of current xINV8 VSS8 VDD8 in8 out8 INVX0_LVT vss8 VSS8 gnd 0v vwire8 out8 in9 0v

vdd9P VDD9P gnd TestVdd vdd9 VDD9P VDD9 0 * correct direction of current xINV9 VSS9 VDD9 in9 out9 INVX0_LVT vss9 VSS9 gnd 0v vwireA out9 inA 0v

vddAP VDDAP gnd TestVdd vddA VDDAP VDDA 0 * correct direction of current xINVA VSSA VDDA inA outA INVX0_LVT vssA VSSA gnd 0v vwireB outA in0 0v

* measurement file: hspice_32nm_Ring_INVX0.mt1 .ALTER INVX0_LVT_NP .param gate_process =0 * 0=TT, 1=SS, 2=SF, 3=FS, 4=FF .param gate_netlist =2 * 1=parasitic, 2=nonparastic .param gate_threshold =1 * 1=LVT, 2=SVT, 3=HVT

344 CHAPTER 11. APPENDIX

.param VddScale =0.0 * 0=zero percent .param gate_type =1 * 1=INVERTER, 2=NAND, 3=NOR .param gate_drive =0.5 * 0.5x Drive Strength .param gate_input =1 * 1=A input, 2=B input, 12=AB input both driven .param gate_base_cmp =0 * 0=False 1=True

xINV0 VSS0 VDD0 in0 out0 INVX0_LVT_NP xINV1 VSS1 VDD1 in1 out1 INVX0_LVT_NP xINV2 VSS2 VDD2 in2 out2 INVX0_LVT_NP xINV3 VSS3 VDD3 in3 out3 INVX0_LVT_NP xINV4 VSS4 VDD4 in4 out4 INVX0_LVT_NP xINV5 VSS5 VDD5 in5 out5 INVX0_LVT_NP xINV6 VSS6 VDD6 in6 out6 INVX0_LVT_NP xINV7 VSS7 VDD7 in7 out7 INVX0_LVT_NP xINV8 VSS8 VDD8 in8 out8 INVX0_LVT_NP xINV9 VSS9 VDD9 in9 out9 INVX0_LVT_NP xINVA VSSA VDDA inA outA INVX0_LVT_NP

.ALTER INVX0_SVT .param gate_process =0 * 0=TT, 1=SS, 2=SF, 3=FS, 4=FF .param gate_netlist =1 * 1=parasitic, 2=nonparastic .param gate_threshold =2 * 1=LVT, 2=SVT, 3=HVT .param VddScale =0.0 * 0=zero percent .param gate_type =1 * 1=INVERTER, 2=NAND, 3=NOR .param gate_drive =0.5 * 0.5x Drive Strength .param gate_input =1 * 1=A input, 2=B input, 12=AB input both driven .param gate_base_cmp =5 * 0=False 1=True

xINV0 VSS0 VDD0 in0 out0 INVX0_SVT xINV1 VSS1 VDD1 in1 out1 INVX0_SVT xINV2 VSS2 VDD2 in2 out2 INVX0_SVT xINV3 VSS3 VDD3 in3 out3 INVX0_SVT xINV4 VSS4 VDD4 in4 out4 INVX0_SVT xINV5 VSS5 VDD5 in5 out5 INVX0_SVT xINV6 VSS6 VDD6 in6 out6 INVX0_SVT xINV7 VSS7 VDD7 in7 out7 INVX0_SVT xINV8 VSS8 VDD8 in8 out8 INVX0_SVT xINV9 VSS9 VDD9 in9 out9 INVX0_SVT xINVA VSSA VDDA inA outA INVX0_SVT

.ALTER INVX0_SVT_NP .param gate_process =0 * 0=TT, 1=SS, 2=SF, 3=FS, 4=FF .param gate_netlist =2 * 1=parasitic, 2=nonparastic .param gate_threshold =2 * 1=LVT, 2=SVT, 3=HVT .param VddScale =0.0 * 0=zero percent .param gate_type =1 * 1=INVERTER, 2=NAND, 3=NOR .param gate_drive =0.5 * 0.5x Drive Strength .param gate_input =1 * 1=A input, 2=B input, 12=AB input both driven .param gate_base_cmp =0 * 0=False 1=True

xINV0 VSS0 VDD0 in0 out0 INVX0_SVT_NP xINV1 VSS1 VDD1 in1 out1 INVX0_SVT_NP xINV2 VSS2 VDD2 in2 out2 INVX0_SVT_NP xINV3 VSS3 VDD3 in3 out3 INVX0_SVT_NP xINV4 VSS4 VDD4 in4 out4 INVX0_SVT_NP xINV5 VSS5 VDD5 in5 out5 INVX0_SVT_NP

345 CHAPTER 11. APPENDIX

xINV6 VSS6 VDD6 in6 out6 INVX0_SVT_NP xINV7 VSS7 VDD7 in7 out7 INVX0_SVT_NP xINV8 VSS8 VDD8 in8 out8 INVX0_SVT_NP xINV9 VSS9 VDD9 in9 out9 INVX0_SVT_NP xINVA VSSA VDDA inA outA INVX0_SVT_NP

.ALTER INVX0_HVT .param gate_process =0 * 0=TT, 1=SS, 2=SF, 3=FS, 4=FF .param gate_netlist =1 * 1=parasitic, 2=nonparastic .param gate_threshold =3 * 1=LVT, 2=SVT, 3=HVT .param VddScale =0.0 * 0=zero percent .param gate_type =1 * 1=INVERTER, 2=NAND, 3=NOR .param gate_drive =0.5 * 0.5x Drive Strength .param gate_input =1 * 1=A input, 2=B input, 12=AB input both driven .param gate_base_cmp =5 * 0=False 1=True

xINV0 VSS0 VDD0 in0 out0 INVX0_HVT xINV1 VSS1 VDD1 in1 out1 INVX0_HVT xINV2 VSS2 VDD2 in2 out2 INVX0_HVT xINV3 VSS3 VDD3 in3 out3 INVX0_HVT xINV4 VSS4 VDD4 in4 out4 INVX0_HVT xINV5 VSS5 VDD5 in5 out5 INVX0_HVT xINV6 VSS6 VDD6 in6 out6 INVX0_HVT xINV7 VSS7 VDD7 in7 out7 INVX0_HVT xINV8 VSS8 VDD8 in8 out8 INVX0_HVT xINV9 VSS9 VDD9 in9 out9 INVX0_HVT xINVA VSSA VDDA inA outA INVX0_HVT

.ALTER INVX0_HVT_NP .param gate_process =0 * 0=TT, 1=SS, 2=SF, 3=FS, 4=FF .param gate_netlist =2 * 1=parasitic, 2=nonparastic .param gate_threshold =3 * 1=LVT, 2=SVT, 3=HVT .param VddScale =0.0 * 0=zero percent .param gate_type =1 * 1=INVERTER, 2=NAND, 3=NOR .param gate_drive =0.5 * 0.5x Drive Strength .param gate_input =1 * 1=A input, 2=B input, 12=AB input both driven .param gate_base_cmp =0 * 0=False 1=True

xINV0 VSS0 VDD0 in0 out0 INVX0_HVT_NP xINV1 VSS1 VDD1 in1 out1 INVX0_HVT_NP xINV2 VSS2 VDD2 in2 out2 INVX0_HVT_NP xINV3 VSS3 VDD3 in3 out3 INVX0_HVT_NP xINV4 VSS4 VDD4 in4 out4 INVX0_HVT_NP xINV5 VSS5 VDD5 in5 out5 INVX0_HVT_NP xINV6 VSS6 VDD6 in6 out6 INVX0_HVT_NP xINV7 VSS7 VDD7 in7 out7 INVX0_HVT_NP xINV8 VSS8 VDD8 in8 out8 INVX0_HVT_NP xINV9 VSS9 VDD9 in9 out9 INVX0_HVT_NP xINVA VSSA VDDA inA outA INVX0_HVT_NP

.end

346 CHAPTER 11. APPENDIX

To illustrate the eﬀects of changing the interconnect wire resistance in the ring oscillator, hspice simulations were performed using the slow, typical and fast prop- agation delay (tp) for 0.5X, 1X, 2X and 4X drive gates in the 28/32nm and 90nm libraries. The current changes as a percent change in resistance are shown in Table 11.2 for the typical delays. The interconnect resistance was sweep from ±40%. Figure 11.7 is the graph. Table 11.3 and Figure 11.8 is the delay for the ±40% sweep.

Table 11.2: Percent change in tp for the 28/32nm inverter with ±40 change in interconnect resistance

R tp0.5X(TT) tp1X(TT) tp2X(TT) tp4X(TT)

40 % 1.20 % 1.53 % 1.60 % 1.88 %

30 % 0.90 % 1.13 % 1.20 % 1.42 %

20 % 0.60 % 0.74 % 0.80 % 0.95 %

10 % 0.30 % 0.38 % 0.40 % 0.47 %

0 % 0.00 % 0.00 % 0.00 % 0.00 %

-10 % -0.30 % -0.38 % -0.40 % -0.47 %

-20 % -0.60 % -0.75 % -0.82 % -0.95 %

-30 % -0.89 % -1.16 % -1.21 % -1.42 %

-40 % -1.19 % -1.53 % -1.58 % -1.90 %

347 CHAPTER 11. APPENDIX

Figure 11.7: Plot of the percent change in tp for a typical 28/32nm inverter

348 CHAPTER 11. APPENDIX

Table 11.3: Delay change in tp for a typical 28/32nm inverter with ±40 change in interconnect resistance

R tp0.5X(TT) tp1X(TT) tp2X(TT) tp4X(TT)

40 % 2.78 ps 2.65 ps 2.44 ps 2.25 ps

30 % 2.77 ps 2.64 ps 2.43 ps 2.24 ps

20 % 2.76 ps 2.63 ps 2.42 ps 2.23 ps

10 % 2.75 ps 2.62 ps 2.41 ps 2.22 ps

0 % 2.75 ps 2.61 ps 2.40 ps 2.21 ps

-10 % 2.74 ps 2.60 ps 2.39 ps 2.20 ps

-20 % 2.73 ps 2.59 ps 2.38 ps 2.19 ps

-30 % 2.72 ps 2.58 ps 2.37 ps 2.18 ps

-40 % 2.71 ps 2.57 ps 2.36 ps 2.17 ps

349 CHAPTER 11. APPENDIX

Figure 11.8: Plot of the delay change in tp for a typical 28/32nm inverter with ±40 change in interconnect resistance

350 CHAPTER 11. APPENDIX

The eﬀects on the typical output current of the inverters in the ring oscillator for the 28/32nm library with a ±40% is shown in Table 11.4, and plotted in Figure 11.9.

Table 11.4: Iomax change for a typical 28/32nm inverter with ±40 change in interconnect resistance

Rgate Iomax0.5X(TT) Iomax1X(TT) Iomax2X(TT) Iomax4X(TT)

40 % -0.86 % -1.18 % -1.27 % -1.62 %

30 % -0.62 % -0.89 % -0.95 % -1.21 %

20 % -0.47 % -0.59 % -0.64 % -0.82 %

10 % -0.23 % -0.28 % -0.32 % -0.41 %

0 % 0.00 % 0.00 % 0.00 % 0.00 %

-10 % 0.23 % 0.30 % 0.33 % 0.41 %

-20 % 0.47 % 0.62 % 0.64 % 0.82 %

-30 % 0.71 % 0.92 % 0.96 % 1.26 %

-40 % 1.01 % 1.22 % 1.27 % 1.68 %

351 CHAPTER 11. APPENDIX

Figure 11.9: Plot of the Iomax change for a typical 28/32nm inverter with ±40 change in interconnect resistance

352 CHAPTER 11. APPENDIX

Table 11.5 shows the eﬀect of a ±40% interconnect resistance change for the typical inverter oscillator. Note the eﬀects or the interconnect for 90nm is 1/2 the change of 28/32nm. Figure 11.7.2 is the plot of percent change.

Table 11.5: Percent change in tp for the 90nm inverter with ±40 change in interconnect resistance

Rgate tp0.5X(TT) tp1X(TT) tp2X(TT) tp4X(TT)

40 % 0.24 % 0.38 % 0.70 % 0.88 %

30 % 0.17 % 0.27 % 0.47 % 0.69 %

20 % 0.10 % 0.17 % 0.30 % 0.46 %

10 % 0.04 % 0.06 % 0.13 % 0.23 %

0 % 0.00 % 0.00 % 0.00 % 0.00 %

-10 % -0.10 % -0.10 % -0.21 % -0.21 %

-20 % -0.17 % -0.21 % -0.35 % -0.42 %

-30 % -0.22 % -0.31 % -0.53 % -0.64 %

-40 % -0.30 % -0.40 % -0.70 % -0.85 %

353 CHAPTER 11. APPENDIX

Figure 11.10: Plot of the percent change in tp for a typical 90nm inverter

354 CHAPTER 11. APPENDIX

Table 11.6 and Figure 11.11 is the delay for the ±40% sweep.

Table 11.6: Delay change in tp for a typical 90nm inverter with ±40 change in interconnect resistance

Rgate tp0.5X(TT) tp1X(TT) tp2X(TT) tp4X(TT)

40 % 16.00 ps 13.75 ps 13.80 ps 12.77 ps

30 % 15.99 ps 13.74 ps 13.77 ps 12.75 ps

20 % 15.98 ps 13.73 ps 13.75 ps 12.72 ps

10 % 15.97 ps 13.71 ps 13.73 ps 12.69 ps

0 % 15.97 ps 13.70 ps 13.71 ps 12.66 ps

-10 % 15.95 ps 13.69 ps 13.68 ps 12.63 ps

-20 % 15.94 ps 13.67 ps 13.66 ps 12.61 ps

-30 % 15.93 ps 13.66 ps 13.64 ps 12.58 ps

-40 % 15.92 ps 13.65 ps 13.61 ps 12.55 ps

355 CHAPTER 11. APPENDIX

Figure 11.11: Plot of the delay change in tp for a typical 90nm inverter with ±40 change in interconnect resistance

356 CHAPTER 11. APPENDIX

The eﬀects on the typical output current of the inverters in the ring oscillator for the 90nm library with a ±40% is shown in Table 11.7, and plotted in Figure 11.7.2.

Table 11.7: Iomax change for a typical 90nm inverter with ±40 change in interconnect resistance

Rgate Iomax0.5X(TT) Iomax1X(TT) Iomax2X(TT) Iomax4X(TT)

40 % -0.54 % -0.37 % -0.77 % -1.19 %

30 % -0.49 % -0.25 % -0.54 % -0.89 %

20 % -0.26 % -0.17 % -0.40 % -0.58 %

10 % -0.31 % -0.09 % -0.27 % -0.28 %

0 % 0.00 % 0.00 % 0.00 % 0.00 %

-10 % 0.24 % 0.29 % 0.42 % 0.17 %

-20 % 0.02 % 0.32 % 0.46 % 0.25 %

-30 % 0.08 % 0.44 % 0.59 % 0.56 %

-40 % 0.24 % 0.50 % 0.89 % 0.81 %

357 CHAPTER 11. APPENDIX

Figure 11.12: Plot of the Iomax change for a typical 90nm inverter with ±40 change in interconnect resistance

358 CHAPTER 11. APPENDIX

11.7.3 Clock Buﬀer hspice Simulations

The circuit consists of a clock connected to a resistor and capacitor. The waveforms are as follows:

90% Vdd = red liner

90% Vdd = blue liner

Vin = green line = Clock pulse

Vout = yellow = voltage across the capacitor

The hspice simulations requires T ≥ 5RC to have an accurate interconnect delay calculation. Figure 11.7.3 is the simulation for a time constant of 1 RC.

Figure 11.13: Interconnect delay calculation for Tperiod = 1RC

Figure 11.7.3 is the simulation for a time constant of 4 RC. Figure 11.7.3 is the simulation for a time constant of 5 RC. Figure 11.7.3 is the simulation for a time constant of 6 RC. Figure 11.7.3 is the simulation for a time constant of 10 RC.

Figure 11.7.3 is the simulation showing Idd with a time constant of 1 RC. Idd approaches zero before switching. Idd = brown line = capacitor.

359 CHAPTER 11. APPENDIX

Figure 11.14: Interconnect delay calculation for Tperiod = 4RC

Figure 11.15: Interconnect delay calculation for Tperiod = 5RC

Figure 11.7.3 is the simulation showing Idd with a time constant of 4 RC.

Figure 11.7.3 is the simulation showing Idd with a time constant of 5 RC.

Figure 11.7.3 is the simulation showing Idd with a time constant of 6 RC.

Figure 11.7.3 is the simulation showing Idd with a time constant of 10 RC.

360 CHAPTER 11. APPENDIX

Figure 11.16: Interconnect delay calculation for Tperiod = 6RC

Figure 11.17: Interconnect delay calculation for Tperiod = 10RC

Figure 11.18: Clock simulation with Idd for time constant of 1 RC

361 CHAPTER 11. APPENDIX

Figure 11.19: Clock simulation with Idd for time constant of 4 RC

Figure 11.20: Clock simulation with Idd for time constant of 5 RC

Figure 11.21: Clock simulation with Idd for time constant of 6 RC

362 CHAPTER 11. APPENDIX

Figure 11.22: Clock simulation with Idd for time constant of 10 RC

363 CHAPTER 11. APPENDIX

Capacitance eﬀect of Lifetime

An experiment was run in ICC and hspice to show the eﬀects of changing the capacitance load for an INVX0 inverter. The results are tabulated in Table 11.8.

Table 11.8: Capacitance load eﬀect on power, Jmax and Lifetime

Clock ICC hspice ICC hspice ICC hspice Temp Gate Period Freq Power Power J J Life Life (ns) (uW ) (uW ) (ua/cm2) (ua/cm2) (years) (years)

125 ◦C INVX0 1 1GHZ 10.7559 10.7501 0.195 0.195 27.142 27.158

5ﬂoad 0.5 2GHZ 21.512 21.500 0.3904 0.3902 13.571 13.579

5ﬂoad 0.25 4GHZ 43.0236 43.000 0.7808 0.7804 6.7857 6.7894

2.5ﬂoad 0.25 4GHZ 29.5676 29.5728 0.5366 0.5367 9.8739 9.8721

2.0ﬂoad 0.25 4GHZ 26.8764 26.9131 0.4878 0.4884 10.8626 10.8477

364 CHAPTER 11. APPENDIX

11.8 Semiconductor properties

Table 11.9 list the properties of NBTI an HCI.

365 CHAPTER 11. APPENDIX

Table 11.9: Semiconductor Properties Degradation Lifetime Critical Process factors that eﬀect Mechanisms Model Failures critical parameters

2/3 1/6 Negative- Nit = K · t + Nit0 Bias Tem- 1. critical 1. Nitrogen p perature K ∝ (ox/Tox)(Vgs − Vth) device concentra- V −V switching tion near Instability gs th Ea T E − (NBTI) . e ox 0 . e kT time delay Si/SiO2 interface, 2. non- responsive 2. Presence of device boron functionality 3. Water near Si/SiO2 interface

4. Gate dimensions

5. Gate oxide thickness

6. Oxide damage

7. Silicon starting material

8. Temperature

9. Bias/Stress Conditions

10. Other Pro- cess/Fab dependent materials like Hy- drogen, Deuterium, Fluorine

Hot n Carrier Ids −Eait,e n 1. critical 1. Drain dop- ∆Nit = C1 exp t device ing levels Injection W qλeEm (HCI) switching time delay 2. Channel lengths 2. non- responsive 3. Gate oxide device thickness functionality 4. Interface traps

5. Purity and quality of gate oxide

366 CHAPTER 11. APPENDIX

11.9 Nernst-Einstein relationship of drift velocity

D ~ −Ea ~νd = Fem and D = D0 exp (11.1) kBT kBT D −E = 0 qρZ∗~j exp a (11.2) kBT kbT

CvDv ~ F lux = J = −Dν 5 Cν + Fem (11.3) kBT

where: ∂σ F~ m = Z∗qρj − Ω (11.4) e ∂x

and Cv is the vacancy concentration and where:

∂σ Ω = Belch0s length (11.5) ∂x

. By Fick’s 2nd Law:

∂C CD ~ = − div J = −div −D 5 C + Fem (11.6) ∂t kBT CD ~ = − div (−D5) − div Fem (11.7) kBT ∂2C(x, t) ∂(x, t) = D − D α (11.8) ν ∂x2 ν ∂x

Clemens and Lloyd [Clement and Lloyd, 1992] develop a numeric evaluation for various conductor lengths as shown in Figure 11.23. From [Tan, 2010], [de Orio et al., 2009] and [Shatzkes and Lloyd, 1986] the boundary conditions (Table 11.10) can be calculated. Case1: D∂C J(0, t) = − νC = 0 or J(0, t) = 0 (11.9) ∂x

367 CHAPTER 11. APPENDIX

Figure 11.23: Ratio of vacancy concentration at the blocking barrier C(0, t) to the initial vacancy concentration C(x, 0) = C0) as a function of the normalized to τ = α2 × Dt for various conductor lengths for each boundary conditions of 11.6. Note that all solutions approximate the semi-inﬁnite case except near steady state. [Clement and Lloyd, 1992]

C(−∞, t) = C0 (11.10)

then the analytic solution is at x = 0

C (0, t) β ν = 1 + erfβ + 2 β2(1 + erfβ) + √ exp(−β2) (11.11) Cν0 π where √ √ √ ~ Dνt ∗ ~ Dνt ∗ Dνt β = Fem ⇒ Z qE ⇒ Z qpj (11.12) 2kBT 2kBT 2kBT

Deﬁne failure f(x) = Cν (0,t) > 10%: Cν0

2 ~ ! ∗ 2 Cν(0, t) Cνf 2 Fem Z qpj ⇒ ≈ 4β = DνTTF = DνTTF (11.13) Cν0 Cν0 kBT kBT

and −Ea Dν = Dν0 exp (11.14) kBT

368 CHAPTER 11. APPENDIX

Table 11.10: Boundry Conditions

Case Boundry Condition

for all cases J(0, t) = 0

case 1 C(−∞, t) = C0

case 2 J(−l, t) = C

case 3 C(−l, t) = C0

C k T 2 1 C k T 2 1 t = t = νf B = νf B (11.15) 10% F ∗ Cρ0 Fem Dρ Cρ0 Z qpj −Ea Dvρ0 exp kB T

t50% = MTTF = ttf (11.16)   C k T 2 1 E = νf B T 2 × j−2 exp a (11.17)  ∗  Cρ0 Z qpj −Ea kBT Dvρ0 exp kB T E = A AT 2 × j−2 exp a (11.18) kBT

= tgrowth + tnucleation (11.19) −2 −2 Ea = AkBT × j + BT × j exp (11.20) kBT

From [de Orio et al., 2009], [Hu et al., 1999]

369 CHAPTER 11. APPENDIX

11.10 Intel and Synopsys 90nm parameters

This information was collected when evaluating the methodology to compare the diﬀerences between the Synopsys 28/32nm PDK and 90nm PDK, and is included as refernece material. Table 11.11 is the table for the Intel 90nm metal layers.

Table 11.11: Intel:Metal Layers

H AR ρ ρ, R , R , H , Pitch, Pitch R , w Metal s typ In- AR In- µΩ- In- w Ω/µm Ω/sq nm nm Intel Ω/µm tel tel cm tel Intel

M1 0.09 280 150 280 220 1.9 1.4 2.52 2.03 2.00 1.23

M2 0.09 280 256 320 320 1.7 1.6 2.52 1.92 1.79 0.469

M3 0.09 280 256 320 320 1.7 1.6 2.52 1.92 1.79 0.469

M4 0.09 280 320 320 400 1.7 1.6 2.52 2.02 1.79

M5 0.09 280 384 320 480 1.7 1.6 2.52 1.92 1.79

M6 0.09 280 576 320 720 1.7 1.6 2.52 1.73 1.79

M7 0.09 280 972 320 1080 1.7 1.8 2.52 1.94 1.79

M8 0.09 280 320 1.7 2.52 1.79

M9 0.028 900 900 1.2 2.52 1.65

Table 11.12 is the table for the Synopsys 90nm PDK metal layers.

370 CHAPTER 11. APPENDIX

Table 11.12: Synopsy 90nm PDK Metal Layers

90nm Cmin Cmax

εr, W, D , R , Ω/sq, max1 D D , D H , Metal s min, min, nm max, H min1 min, max min, max µm min nm µm nm max max

Diﬀ 10 3.9 120 60 0.06 144.5 49 0.06 144.5

Poly 11 3.9 100 146.5 0.2065 800 146.5 0.1955 110

M1 0.09 3.9 140 1090 1.2965 230 800 0.9955 300

M2 0.09 3.9 160 1090 2.3865 230 800 1.7955 300

M3 0.09 3.9 160 1090 3.4765 230 800 2.5955 300

M4 0.09 3.9 160 1090 4.5665 230 800 3.3955 300

M5 0.09 3.9 160 1090 5.6565 230 800 4.1955 300

M6 0.09 3.9 160 1090 6.7465 230 800 4.9955 300

M7 0.09 3.9 160 1090 7.8365 230 800 5.7955 300

M8 0.09 3.9 160 1090 8.9265 230 800 6.5955 300

M9 0.028 3.9 450 1090 10.0165 750 800 7.3955 1100

371 CHAPTER 11. APPENDIX

Table 11.13 is a simpliﬁed table for the Synopsys 90nm PDK metal layers.

Table 11.13: Synopsy 90nm PDK simpliﬁed Metal Layers

Cmin Cmax

Rs, εr, W, Ω/sq, H , Metal min, min, D H D max min, max min min nm max max max

M1 0.09 3.9 140 1090 230 800 300

M2 0.09 3.9 160 1090 230 800 300

M3 0.09 3.9 160 1090 230 800 300

M4 0.09 3.9 160 1090 230 800 300

M5 0.09 3.9 160 1090 230 800 300

M6 0.09 3.9 160 1090 230 800 300

M7 0.09 3.9 160 1090 230 800 300

M8 0.09 3.9 160 1090 230 800 300

M9 0.028 3.9 450 1090 750 800 1100

372 CHAPTER 11. APPENDIX

Table 11.14 is a table for the Synopsys 90nm PDK capacitance for the metal layers.

Table 11.14: Synopsy 90nm PDK capacitance for Metal Layers

C , C , L, W, C , spef ppf C , % Metal R ,Ω spef max max C , fF ﬁnge µm µm spef min fF pp fF C fF fF fringe

M1 49.16 0.14 31.6028 4.0089 4.4259 4.1881 0.2969 3.8912 92%

M2 49.16 0.16 27.6525 3.7370 4.0657 4.2306 0.3393 3.8912 91%

M9 49.2 0.45 3.06133 3.7370 4.2135 6.6859 0.9552 5.7307 85%

M1 49.16 1.4 3.16028 6.5364 7.4062 6.8605 2.9693 3.8912 56%

M2 49.16 1.6 2.76525 5.6865 6.2902 7.2847 3.3935 3.8912 53%

M9 49.2 4.5 0.30613 5.2142 5.8409 15.2827 9.5520 5.7307 37%

373 Chapter 12

Published Papers

The author has collaborated and presented several papers at various conferences, exploring the issues of Hardware trojans and exploiting the aging eﬀects for HW trojans, and other topics related to ICs/ASICs.

1. Methodology for Tradeoﬀs between Performance and Lifetimes of Integrated Circuits

2. Road Pothole Detection System Based on Stereo Vision

3. System level self-healing for parametric yield and reliability improvement under power bound

4. Process reliability based trojans through NBTI and HCI eﬀects

5. Hardware Trojan by Hot Carrier Injection

6. Exploiting Semiconductor Properties for Hardware Trojans

7. Embedded system protection from software corruption

8. A robust authentication methodology using physically unclonable functions in DRAM arrays

374 CHAPTER 12. PUBLISHED PAPERS

9. An Adaptable Task Manager for Reconﬁgurable Architecture Kernel

10. Knowledge-Guided Methodology for Third-Party Soft IP Analysis

11. Cross-correlation of speciﬁcation and RTL for soft IP analysis

12. Knowledge-Guided Methodology for Speciﬁcation Analysis

13. A supply-demand model based scalable energy management system for improved energy utilization eﬃciency

14. A Dynamic Reconﬁgurable Fabric for Platform SoCs

15. A Technique for High Ratio LZW Compression

16. Using codesign techniques to support analog functionality

Below are the abstracts for the papers.

1. Paper accepted for 2019 IOLTS conference, “Methodology for Tradeoffs between Performance and Lifetimes of Integrated Circuits”, Integrated Circuit technology (IC) and ASIC in particular were always designed to tradeoff between Per- formance, Cost (Area) and Power. The Reliability of the ICs or ASICs was assumed to always exceed the expected lifetime of the product. Reliability cannot be ignored as the IC ndustry moves to nano-scale geometries. This paper describes a design methodology to perform tradeoffs between Lifetime, Perfor- mance, Cost (Area) and Power. The main objective of this paper is to develop a design space exploration method and tools for IC/ASICs driven by lifetime concerns due to Electromigration. Our method applies to both safety based products that require longer lifetime, and also to higher performance products that are frequently replaced. [Weyer et al., 2019]

2. Presented paper “Road Pothole Detection System Based on Stereo Vision”, we proposed a stereo vision system, which detects potholes during driving. The

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objective is to benefit drivers to react to potholes in advance. This system contains two USB cameras taking photo simultaneously. We use parameters obtained from camera calibration with checkerboard to calculate the disparity map. 2-dimensional image points can be projected to 3-dimensional world points using the disparity map. With all the 3-dimensional points, we use the bi- square weighted robust least-squares approximation for road surface fitting. All points below the road surface model can be detected as pothole region. The size and depth of each pothole can be obtained as well. The experiments we conducted show robust detection of potholes in different road and light conditions [Li et al., 2018].

3. The paper ‘’System level self-healing for parametric yield and reliability improvement under power bound”, we present a system level healing algorithm for compensating SoC chips for a specific output parameter under power constraint. We formulate the healing problem as an ordinal optimization problem, where individual cores need to be assigned the right amount of healing that sat- isfies the target system performance and power requirement. Next, we propose an efficient solution to the problem using a priori design-time information about the relative sensitivities of the cores to system performance and power. Simula- tion results for example systems show that the proposed healing approach can achieve higher parametric yield and better settling time compared to conven- tional healing approaches. [Narasimhan et al., 2010b]

4. The paper ‘’Process reliability based trojans through NBTI and HCI eﬀects”, describes possible process alterations for both NBTI and HCI mechanisms that might result in creation of process reliability trojans. The paper also explores some possible detection techniques that can help identify the hidden trojans and discusses the various scenarios when process reliability based trojans lead

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to severe damages. [Shiyanovskii et al., 2010]

5. The paper ‘’Hardware Trojan by Hot Carrier Injection”, discusses how hot carrier injection (HCI) can be exploited to create a trojan that will cause hardware failures. The trojan is produced not Via additional logic circuitry but by controlled scenarios that maximize and accelerate the HCI effect in transistors. These scenarios range from manipulating the manufacturing process to varying the internal voltage distribution. This new type of trojan is difficult to test due to its gradual hardware degradation mechanism. This paper describes the HCI effect, detection techniques and discusses the possibility for maliciously induced HCI trojans. [Shiyanovskii et al., 2009c]

6. The paper ‘’Exploiting Semiconductor Properties for Hardware Trojans”, discusses the possible introduction of hidden reliability defects during CMOS foundry fabrication processes that may lead to accelerated wearout of the devices. These hidden defects or hardware Trojans can be created by deviation from foundry design rules and processing parameters. The Trojans are produced by exploiting time-based wearing mechanisms (HCI, NBTI, TDDB and EM) and/or condition-basedt riggers (ESD, Latchup and Softerror). This class of latent damage is diﬃcult to test due to its gradual degradation nature. The paper describes life-time expectancy results for various Trojan induced scenarios. Semiconductor properties, processing and design parameters critical for device reliability and Trojan creation are discussed. [Shiyanovskii et al., 2009b]

7. The paper ‘’Embedded system protection from software corruption”, discusses how as Embedded Systems are being network enabled, allowing for remote updates and data sharing, software corruption has become a major concern. Security protection has mostly been overlooked. Software corruption can sim- plistically be considered as unauthorized instructions that are executed within

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the system. This can occur through behaviorally modified instruction code introduced Via new software installation, updates, or application input data (such as buffer overflows). We introduce a vault architecture that prevents the insertion of software corruptions for embedded systems that allow remote access. Simulation results for the vault architecture are provided. [Wolff et al., 2010]

8. The paper ‘’A robust authentication methodology using physically unclonable functions in DRAM arrays”, discusses with the high availability of DRAM in either embedded or stand-alone form make it a target for counterfeit attacks, we propose ar obust authentication methodologyagainst counterfeiting. The authentication is performed by exploiting the intrinsic process variation in write reliability of DRAM cells. Extensive Monte Carlo simulations performed inhspice show that the proposed authentication methodology provides high uniqueness of 50.01% average inter-die Hamming distance and good robustness under tempo- ral ﬂuctuations in supply voltage, temperature, and ageing eﬀect over a 10-year lifetime. [Hashemian et al., 2015]

9. The paper ‘’An Adaptable Task Manager for Reconfigurable Architecture Ker- nel”, discusses how as Self-reconfigurable hardware is a new emerging technology, which will enable adaptation of computing systems to changing en- vironments. This paper deals with the design of architecture kernels for an autonomous on-board system and the development of an adaptation manager for real-time scheduling of the reconfigurable hardware fabric. Our approach employs a reconfigurable computer architecture with two key layers: the adaptation manager and the real time configuration kernel. This provides significant advantages in terms of flexibility, scalability, cost, and compatibility with embedded technology. [Shiyanovskii et al., 2009a]

10. The paper ‘’Knowledge-Guided Methodology for Third-Party Soft IP Analysis”,

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discuss how in System-on-Chip designs, third party IP reuse is prevalent as it increases productivity and reduces time-to-market. These IPs can be classified as untrusted designs since the userhas no insight into IP verification or quality control process. Inpractice, it is generally assumed that the IP has been functionallyvalidated by developers and thorough verification at user end is not performed. In the current state-of-the-art, lint tools are primarily used todeter- mine IP design quality. These tools pinpoint design issues by performing static analysis of RTL code but have a limitation that they do not perform behavioral analysis. In this paper, we present a knowledge-guided methodology, which identifies RTL behavior by finding correspondences with a knowledge base of previously analysed trusted designs. In comparison to existing techniques, our approach uses combination of static and dynamic analysis techniques to better approximate design behavior. We tested our methodology by analysing several IEEE-754 floating point soft IPs. We define identification coverage and confidence factor metric to quantify our IP analysis results. [Singh et al., 2014b]

11. The paper ‘’Cross-correlation of specification and RTL for soft IP analysis”, discusses as Semiconductor companies often use 3rd party IPs in order to improve their design productivity. In practice, there are risks involved in using a 3rd party IP as bugs may creep in due to versioning issues, poor documentation, and mismatches between specification and RTL. As a result of this, 3rd party IP specification and RTL must be carefully evaluated. Our methodology addresses this issue, which cross-correlates specification and RTL to discover these discrepancies. The key innovative ideas in our approach are to use prior and trusted experience about designs, which include their specs and RTL code. Also, we have captured this trusted experience into two knowledge bases (KB), Spec-KB and RTL-KB. Finally, knowledge base rules are used to cross-correlate the RTL blocks to the specs. We have tested our approach by analyzing sev-

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eral 3rd party IPs. We have defined metrics for specification coverage and RTL identification coverage to quantify our results. [Singh et al., 2014a]

12. The paper ‘’Knowledge-Guided Methodology for Specification Analysis”, discusses as the number of Soft-IP vendors and designs becoming available on the global market is growing at a phenomenal rate. The current practice of evaluating Soft IPs using theirspecification is a time consuming manual process. A specification document is primarily written in English, which serves as a common language for internal product development teams as well as customers. Designers have a preference for writing specifications in an informal natural language using text and notations, including diagrams, charts and tables. The lack of formality of specification documents is a limiting factor in their analysis. The current state-of-the-art in hardwaredesign lacks any specification analysis technique. In this paper, we present a knowledge-guided methodology for specification analysis that can automatically analyze specification documents. Our approach avoids formal specification. Instead we rely on domain-based ontolo- gies to capture design behavior We tested our approach by analyzing floating point specification from several third party IP vendors. We define spec coverage and requirement coverage metrics to quantify our results. [Singh et al., 2013]

13. The paper‘’A supply-demand model based scalable energy management system for improved energy utilization efficiency”, we propose a scalable rule-based energy management system for managing the acquisition, mixing, delivery and storage of energy for arbitrary collection of energy sources and users, which are characterized with different energy generation and consumption parameters. The system uses economics inspired supply-demand model for efficiently managing energy distribution between a set of energy sources and users. The energy allocation procedure tries to maximize the energy utilization efficiency of the

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sources while satisfying the demand of the users in order of their associated pri- orities, without starving an already allocated user. [Narasimhan et al., 2010a]

14. The paper ‘’A Dynamic Reconfigurable Fabric for Platform SoCs”, proposes a dynamic coarse-grained reconfigurable architecture, which targets computa- tionally intensive applications like multimedia and wireless applications is presented. Fundamental features of the architecture are an interconnection matrix, switch buffers, functional units, and a controller. Important aspects of the architecture is dynamic datapath reconfiguration over each control step of the application. Simulations of several classes of applications with results are also presented. Results of Xilinx Virtex 4 Implementations are provided. [Papachristou et al., 2006]

15. The paper ‘’A Technique for High Ratio LZW Compression”, discusses the reduction of both the test suite size and the download time of test vectors is important in today’s System-On-a-Chip designs. In this paper, a method for compressing the scan test patterns using the LZW algorithm is presented. This method leverages the large number of Don’t-Cares in test vectors in order to improve the compression ratio signiﬁcantly. The hardware decompression architecture presented here uses existing on-chip embedded memories. Tests using the ISCAS89 and the ITC99 benchmarks show that this method achieves high compression ratios. [Knieser et al., 2003]

16. The paper ‘’Using codesign techniques to support analog functionality”, With the growth of System on a Chip (SoC), the functionality of analog components must also be considered in the design process. his paper describes some of the design implementation partitioning issues and experiences using analog and digital techniques for embedded systems. To achieve a quick turn around for new embedded system development, a design methodology was extended for

381 CHAPTER 12. PUBLISHED PAPERS analog codesign based on the specify-explore-refine paradigm and system-level design methodology. Many system-level issues were addressed including hardware/software codesign tradeoffs. [Wolff et al., 1999]

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